593 files changed, 14303 insertions, 7803 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7bab17ed2972..6d2f7f5c0036 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -16,6 +16,7 @@ config ARM
         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
         select HAVE_ARCH_KGDB
         select HAVE_ARCH_TRACEHOOK
+        select HAVE_SYSCALL_TRACEPOINTS
         select HAVE_KPROBES if !XIP_KERNEL
         select HAVE_KRETPROBES if (HAVE_KPROBES)
         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
@@ -529,10 +530,11 @@ config ARCH_IXP4XX
 config ARCH_DOVE
         bool "Marvell Dove"
         select CPU_V7
-        select PCI
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
-        select PLAT_ORION
+        select MIGHT_HAVE_PCI
+        select PLAT_ORION_LEGACY
+        select USB_ARCH_HAS_EHCI
         help
           Support for the Marvell Dove SoC 88AP510
 
@@ -542,7 +544,7 @@ config ARCH_KIRKWOOD
         select PCI
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
-        select PLAT_ORION
+        select PLAT_ORION_LEGACY
         help
           Support for the following Marvell Kirkwood series SoCs:
           88F6180, 88F6192 and 88F6281.
@@ -568,7 +570,7 @@ config ARCH_MV78XX0
         select PCI
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
-        select PLAT_ORION
+        select PLAT_ORION_LEGACY
         help
           Support for the following Marvell MV78xx0 series SoCs:
           MV781x0, MV782x0.
@@ -580,7 +582,7 @@ config ARCH_ORION5X
         select PCI
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
-        select PLAT_ORION
+        select PLAT_ORION_LEGACY
         help
           Support for the following Marvell Orion 5x series SoCs:
           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
@@ -1138,6 +1140,10 @@ config PLAT_ORION
         select IRQ_DOMAIN
         select COMMON_CLK
 
+config PLAT_ORION_LEGACY
+        bool
+        select PLAT_ORION
+
 config PLAT_PXA
         bool
 
@@ -1397,6 +1403,16 @@ config PL310_ERRATA_769419
           on systems with an outer cache, the store buffer is drained
           explicitly.
 
+config ARM_ERRATA_775420
+       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
+       depends on CPU_V7
+       help
+         This option enables the workaround for the 775420 Cortex-A9 (r2p2,
+         r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
+         operation aborts with MMU exception, it might cause the processor
+         to deadlock. This workaround puts DSB before executing ISB if
+         an abort may occur on cache maintenance.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -1781,8 +1797,8 @@ config ALIGNMENT_TRAP
           configuration it is safe to say N, otherwise say Y.
 
 config UACCESS_WITH_MEMCPY
-        bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
-        depends on MMU && EXPERIMENTAL
+        bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
+        depends on MMU
         default y if CPU_FEROCEON
         help
           Implement faster copy_to_user and clear_user methods for CPU
@@ -1823,11 +1839,15 @@ config CC_STACKPROTECTOR
           neutralized via a kernel panic.
           This feature requires gcc version 4.2 or above.
 
-config DEPRECATED_PARAM_STRUCT
-        bool "Provide old way to pass kernel parameters"
+config XEN_DOM0
+        def_bool y
+        depends on XEN
+
+config XEN
+        bool "Xen guest support on ARM (EXPERIMENTAL)"
+        depends on EXPERIMENTAL && ARM && OF
         help
-          This was deprecated in 2001 and announced to live on for 5 years.
-          Some old boot loaders still use this way.
+          Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
 
 endmenu
 
@@ -1841,6 +1861,23 @@ config USE_OF
         help
           Include support for flattened device tree machine descriptions.
 
+config ATAGS
+        bool "Support for the traditional ATAGS boot data passing" if USE_OF
+        default y
+        help
+          This is the traditional way of passing data to the kernel at boot
+          time. If you are solely relying on the flattened device tree (or
+          the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
+          to remove ATAGS support from your kernel binary.  If unsure,
+          leave this to y.
+
+config DEPRECATED_PARAM_STRUCT
+        bool "Provide old way to pass kernel parameters"
+        depends on ATAGS
+        help
+          This was deprecated in 2001 and announced to live on for 5 years.
+          Some old boot loaders still use this way.
+
 # Compressed boot loader in ROM.  Yes, we really want to ask about
 # TEXT and BSS so we preserve their values in the config files.
 config ZBOOT_ROM_TEXT
@@ -1967,6 +2004,7 @@ config CMDLINE
 choice
         prompt "Kernel command line type" if CMDLINE != ""
         default CMDLINE_FROM_BOOTLOADER
+        depends on ATAGS
 
 config CMDLINE_FROM_BOOTLOADER
         bool "Use bootloader kernel arguments if available"
@@ -2036,7 +2074,7 @@ config KEXEC
 
 config ATAGS_PROC
         bool "Export atags in procfs"
-        depends on KEXEC
+        depends on ATAGS && KEXEC
         default y
         help
           Should the atags used to boot the kernel be exported in an "atags"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index b86e57ef146b..f023e3acdfbd 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -250,6 +250,7 @@ endif
 core-$(CONFIG_FPE_NWFPE)        += arch/arm/nwfpe/
 core-$(CONFIG_FPE_FASTFPE)      += $(FASTFPE_OBJ)
 core-$(CONFIG_VFP)              += arch/arm/vfp/
+core-$(CONFIG_XEN)              += arch/arm/xen/
 
 # If we have a machine-specific directory, then include it in the build.
 core-y                          += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
@@ -268,7 +269,12 @@ else
 KBUILD_IMAGE := zImage
 endif
 
-all:    $(KBUILD_IMAGE)
+# Build the DT binary blobs if we have OF configured
+ifeq ($(CONFIG_USE_OF),y)
+KBUILD_DTBS := dtbs
+endif
+
+all:    $(KBUILD_IMAGE) $(KBUILD_DTBS)
 
 boot := arch/arm/boot
 
@@ -306,7 +312,7 @@ define archhelp
   echo  '  uImage        - U-Boot wrapped zImage'
   echo  '  bootpImage    - Combined zImage and initial RAM disk' 
   echo  '                  (supply initrd image via make variable INITRD=<path>)'
-  echo  '  dtbs          - Build device tree blobs for enabled boards'
+  echo  '* dtbs          - Build device tree blobs for enabled boards'
   echo  '  install       - Install uncompressed kernel'
   echo  '  zinstall      - Install compressed kernel'
   echo  '  uinstall      - Install U-Boot wrapped compressed kernel'
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index f41b38cafce8..9deb56a702ce 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
@@ -32,6 +32,9 @@ extern void error(char *);
 #  define Tracecv(c,x)
 #endif
 
+/* Not needed, but used in some headers pulled in by decompressors */
+extern char * strstr(const char * s1, const char *s2);
+
 #ifdef CONFIG_KERNEL_GZIP
 #include "../../../../lib/decompress_inflate.c"
 #endif
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 43c084c2cd66..29f541f0e653 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -17,6 +17,9 @@ dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \
         usb_a9263.dtb \
         usb_a9g20.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
+        dove-cubox.dtb \
+        dove-dove-db.dtb
 dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
         exynos4210-smdkv310.dtb \
         exynos4210-trats.dtb \
@@ -33,10 +36,13 @@ dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
         kirkwood-dns325.dtb \
+        kirkwood-dockstar.dtb \
         kirkwood-dreamplug.dtb \
         kirkwood-goflexnet.dtb \
         kirkwood-ib62x0.dtb \
         kirkwood-iconnect.dtb \
+        kirkwood-iomega_ix2_200.dtb \
+        kirkwood-km_kirkwood.dtb \
         kirkwood-lschlv2.dtb \
         kirkwood-lsxhl.dtb \
         kirkwood-ts219-6281.dtb \
@@ -96,6 +102,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
         vexpress-v2p-ca9.dtb \
         vexpress-v2p-ca15-tc1.dtb \
-        vexpress-v2p-ca15_a7.dtb
+        vexpress-v2p-ca15_a7.dtb \
+        xenvm-4.2.dtb
 
 endif
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 6b6b932a5a7d..16cc82cdaa81 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -63,6 +63,11 @@
                                reg = <0xd0020300 0x30>;
                                interrupts = <37>, <38>, <39>, <40>;
                 };
+
+                addr-decoding@d0020000 {
+                        compatible = "marvell,armada-addr-decoding-controller";
+                        reg = <0xd0020000 0x258>;
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 3228ccc83332..2069151afe01 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -21,6 +21,12 @@
         model = "Marvell Armada 370 family SoC";
         compatible = "marvell,armada370", "marvell,armada-370-xp";
 
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                gpio2 = &gpio2;
+        };
+
         mpic: interrupt-controller@d0020000 {
               reg = <0xd0020a00 0x1d0>,
                     <0xd0021870 0x58>;
@@ -31,5 +37,43 @@
                                 compatible = "marvell,armada-370-xp-system-controller";
                                 reg = <0xd0018200 0x100>;
                 };
+
+                pinctrl {
+                        compatible = "marvell,mv88f6710-pinctrl";
+                        reg = <0xd0018000 0x38>;
+                };
+
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,orion-gpio";
+                        reg = <0xd0018100 0x40>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <82>, <83>, <84>, <85>;
+                };
+
+                gpio1: gpio@d0018140 {
+                        compatible = "marvell,orion-gpio";
+                        reg = <0xd0018140 0x40>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <87>, <88>, <89>, <90>;
+                };
+
+                gpio2: gpio@d0018180 {
+                        compatible = "marvell,orion-gpio";
+                        reg = <0xd0018180 0x40>;
+                        ngpios = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <91>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index f97040d4258d..b1fc728515e9 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -14,11 +14,11 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp.dtsi"
+/include/ "armada-xp-mv78460.dtsi"
 
 / {
         model = "Marvell Armada XP Evaluation Board";
-        compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+        compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
 
         chosen {
                 bootargs = "console=ttyS0,115200 earlyprintk";
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
new file mode 100644
index 000000000000..ea355192be6f
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78230 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+        model = "Marvell Armada XP MV78230 SoC";
+        compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+        };
+
+        soc {
+                pinctrl {
+                        compatible = "marvell,mv78230-pinctrl";
+                        reg = <0xd0018000 0x38>;
+                };
+
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018100 0x40>,
+                            <0xd0018800 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <16>, <17>, <18>, <19>;
+                };
+
+                gpio1: gpio@d0018140 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018140 0x40>,
+                            <0xd0018840 0x30>;
+                        ngpios = <17>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <20>, <21>, <22>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
new file mode 100644
index 000000000000..2057863f3dfa
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -0,0 +1,70 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78260 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+        model = "Marvell Armada XP MV78260 SoC";
+        compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                gpio2 = &gpio2;
+        };
+
+        soc {
+                pinctrl {
+                        compatible = "marvell,mv78260-pinctrl";
+                        reg = <0xd0018000 0x38>;
+                };
+
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018100 0x40>,
+                            <0xd0018800 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <16>, <17>, <18>, <19>;
+                };
+
+                gpio1: gpio@d0018140 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018140 0x40>,
+                            <0xd0018840 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <20>, <21>, <22>, <23>;
+                };
+
+                gpio2: gpio@d0018180 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018180 0x40>,
+                            <0xd0018870 0x30>;
+                        ngpios = <3>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <24>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
new file mode 100644
index 000000000000..ffac98373792
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -0,0 +1,70 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78460 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+        model = "Marvell Armada XP MV78460 SoC";
+        compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                gpio2 = &gpio2;
+        };
+
+        soc {
+                pinctrl {
+                        compatible = "marvell,mv78460-pinctrl";
+                        reg = <0xd0018000 0x38>;
+                };
+
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018100 0x40>,
+                            <0xd0018800 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <16>, <17>, <18>, <19>;
+                };
+
+                gpio1: gpio@d0018140 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018140 0x40>,
+                            <0xd0018840 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <20>, <21>, <22>, <23>;
+                };
+
+                gpio2: gpio@d0018180 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018180 0x40>,
+                            <0xd0018870 0x30>;
+                        ngpios = <3>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <24>;
+                };
+        };
+ };
diff --git a/arch/arm/boot/dts/dove-cm-a510.dts b/arch/arm/boot/dts/dove-cm-a510.dts
new file mode 100644
index 000000000000..61a8062e56de
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cm-a510.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+        model = "Compulab CM-A510";
+        compatible = "compulab,cm-a510", "marvell,dove";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+};
+
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&spi0 {
+        status = "okay";
+
+        /* spi0.0: 4M Flash Winbond W25Q32BV */
+        spi-flash@0 {
+                compatible = "st,w25q32";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+
+&i2c0 {
+          status = "okay";
+};
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
new file mode 100644
index 000000000000..0adbd5a38095
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -0,0 +1,42 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+        model = "SolidRun CuBox";
+        compatible = "solidrun,cubox", "marvell,dove";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                power {
+                        label = "Power";
+                        gpios = <&gpio0 18 1>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+};
+
+&uart0 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sata0 { status = "okay"; };
+&i2c0 { status = "okay"; };
+
+&spi0 {
+        status = "okay";
+
+        /* spi0.0: 4M Flash Winbond W25Q32BV */
+        spi-flash@0 {
+                compatible = "st,w25q32";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts
new file mode 100644
index 000000000000..e5a920beab45
--- /dev/null
+++ b/arch/arm/boot/dts/dove-dove-db.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+        model = "Marvell DB-MV88AP510-BP Development Board";
+        compatible = "marvell,dove-db", "marvell,dove";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+};
+
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&spi0 {
+        status = "okay";
+
+        /* spi0.0: 4M Flash ST-M25P32-VMF6P */
+        spi-flash@0 {
+                compatible = "st,m25p32";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+
+&i2c0 {
+          status = "okay";
+};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
new file mode 100644
index 000000000000..96fb824b5e6e
--- /dev/null
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -0,0 +1,143 @@
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "marvell,dove";
+        model = "Marvell Armada 88AP510 SoC";
+
+        interrupt-parent = <&intc>;
+
+        intc: interrupt-controller {
+                compatible = "marvell,orion-intc";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0xf1020204 0x04>,
+                      <0xf1020214 0x04>;
+        };
+
+        mbus@f1000000 {
+                compatible = "simple-bus";
+                ranges = <0 0xf1000000 0x4000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                uart0: serial@12000 {
+                        compatible = "ns16550a";
+                        reg = <0x12000 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <7>;
+                        clock-frequency = <166666667>;
+                        status = "disabled";
+                };
+
+                uart1: serial@12100 {
+                        compatible = "ns16550a";
+                        reg = <0x12100 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <8>;
+                        clock-frequency = <166666667>;
+                        status = "disabled";
+                };
+
+                uart2: serial@12200 {
+                        compatible = "ns16550a";
+                        reg = <0x12000 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <9>;
+                        clock-frequency = <166666667>;
+                        status = "disabled";
+                };
+
+                uart3: serial@12300 {
+                        compatible = "ns16550a";
+                        reg = <0x12100 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <10>;
+                        clock-frequency = <166666667>;
+                        status = "disabled";
+                };
+
+                wdt: wdt@20300 {
+                        compatible = "marvell,orion-wdt";
+                        reg = <0x20300 0x28>;
+                };
+
+                gpio0: gpio@d0400 {
+                        compatible = "marvell,orion-gpio";
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        reg = <0xd0400 0x20>;
+                        ngpio = <32>;
+                        interrupts = <12>, <13>, <14>, <60>;
+                };
+
+                gpio1: gpio@d0420 {
+                        compatible = "marvell,orion-gpio";
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        reg = <0xd0420 0x20>;
+                        ngpio = <32>;
+                        interrupts = <61>;
+                };
+
+                gpio2: gpio@e8400 {
+                        compatible = "marvell,orion-gpio";
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        reg = <0xe8400 0x0c>;
+                        ngpio = <8>;
+                };
+
+                spi0: spi@10600 {
+                        compatible = "marvell,orion-spi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        interrupts = <6>;
+                        reg = <0x10600 0x28>;
+                        status = "disabled";
+                };
+
+                spi1: spi@14600 {
+                        compatible = "marvell,orion-spi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        interrupts = <5>;
+                        reg = <0x14600 0x28>;
+                        status = "disabled";
+                };
+
+                i2c0: i2c@11000 {
+                        compatible = "marvell,mv64xxx-i2c";
+                        reg = <0x11000 0x20>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <11>;
+                        clock-frequency = <400000>;
+                        timeout-ms = <1000>;
+                        status = "disabled";
+                };
+
+                sdio0: sdio@92000 {
+                        compatible = "marvell,dove-sdhci";
+                        reg = <0x92000 0x100>;
+                        interrupts = <35>, <37>;
+                        status = "disabled";
+                };
+
+                sdio1: sdio@90000 {
+                        compatible = "marvell,dove-sdhci";
+                        reg = <0x90000 0x100>;
+                        interrupts = <36>, <38>;
+                        status = "disabled";
+                };
+
+                sata0: sata@a0000 {
+                        compatible = "marvell,orion-sata";
+                        reg = <0xa0000 0x2400>;
+                        interrupts = <62>;
+                        nr-ports = <1>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 35e5895ba3df..f3990b04fecf 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -400,8 +400,8 @@
                                 #clock-cells = <1>;
                         };
 
-                        anatop@020c8000 {
-                                compatible = "fsl,imx6q-anatop";
+                        anatop: anatop@020c8000 {
+                                compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
                                 reg = <0x020c8000 0x1000>;
                                 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 
@@ -531,6 +531,11 @@
                                 interrupts = <0 89 0x04 0 90 0x04>;
                         };
 
+                        gpr: iomuxc-gpr@020e0000 {
+                                compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+                                reg = <0x020e0000 0x38>;
+                        };
+
                         iomuxc@020e0000 {
                                 compatible = "fsl,imx6q-iomuxc";
                                 reg = <0x020e0000 0x4000>;
diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi
new file mode 100644
index 000000000000..813b91d7bea2
--- /dev/null
+++ b/arch/arm/boot/dts/integrator.dtsi
@@ -0,0 +1,76 @@
+/*
+ * SoC core Device Tree for the ARM Integrator platforms
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        timer@13000000 {
+                reg = <0x13000000 0x100>;
+                interrupt-parent = <&pic>;
+                interrupts = <5>;
+        };
+
+        timer@13000100 {
+                reg = <0x13000100 0x100>;
+                interrupt-parent = <&pic>;
+                interrupts = <6>;
+        };
+
+        timer@13000200 {
+                reg = <0x13000200 0x100>;
+                interrupt-parent = <&pic>;
+                interrupts = <7>;
+        };
+
+        pic@14000000 {
+                compatible = "arm,versatile-fpga-irq";
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                reg = <0x14000000 0x100>;
+                clear-mask = <0xffffffff>;
+        };
+
+        flash@24000000 {
+                compatible = "cfi-flash";
+                reg = <0x24000000 0x02000000>;
+        };
+
+        fpga {
+                compatible = "arm,amba-bus", "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                interrupt-parent = <&pic>;
+
+                /*
+                 * These PrimeCells are in the same locations and using the
+                 * same interrupts in all Integrators, however the silicon
+                 * version deployed is different.
+                 */
+                rtc@15000000 {
+                        reg = <0x15000000 0x1000>;
+                        interrupts = <8>;
+                };
+
+                uart@16000000 {
+                        reg = <0x16000000 0x1000>;
+                        interrupts = <1>;
+                };
+
+                uart@17000000 {
+                        reg = <0x17000000 0x1000>;
+                        interrupts = <2>;
+                };
+
+                kmi@18000000 {
+                        reg = <0x18000000 0x1000>;
+                        interrupts = <3>;
+                };
+
+                kmi@19000000 {
+                        reg = <0x19000000 0x1000>;
+                        interrupts = <4>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
new file mode 100644
index 000000000000..61767757b50a
--- /dev/null
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -0,0 +1,68 @@
+/*
+ * Device Tree for the ARM Integrator/AP platform
+ */
+
+/dts-v1/;
+/include/ "integrator.dtsi"
+
+/ {
+        model = "ARM Integrator/AP";
+        compatible = "arm,integrator-ap";
+
+        aliases {
+                arm,timer-primary = &timer2;
+                arm,timer-secondary = &timer1;
+        };
+
+        chosen {
+                bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
+        };
+
+        timer0: timer@13000000 {
+                compatible = "arm,integrator-timer";
+        };
+
+        timer1: timer@13000100 {
+                compatible = "arm,integrator-timer";
+        };
+
+        timer2: timer@13000200 {
+                compatible = "arm,integrator-timer";
+        };
+
+        pic: pic@14000000 {
+                valid-mask = <0x003fffff>;
+        };
+
+        fpga {
+                /*
+                 * The Integator/AP predates the idea to have magic numbers
+                 * identifying the PrimeCell in hardware, thus we have to
+                 * supply these from the device tree.
+                 */
+                rtc: rtc@15000000 {
+                        compatible = "arm,pl030", "arm,primecell";
+                        arm,primecell-periphid = <0x00041030>;
+                };
+
+                uart0: uart@16000000 {
+                        compatible = "arm,pl010", "arm,primecell";
+                        arm,primecell-periphid = <0x00041010>;
+                };
+
+                uart1: uart@17000000 {
+                        compatible = "arm,pl010", "arm,primecell";
+                        arm,primecell-periphid = <0x00041010>;
+                };
+
+                kmi0: kmi@18000000 {
+                        compatible = "arm,pl050", "arm,primecell";
+                        arm,primecell-periphid = <0x00041050>;
+                };
+
+                kmi1: kmi@19000000 {
+                        compatible = "arm,pl050", "arm,primecell";
+                        arm,primecell-periphid = <0x00041050>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
new file mode 100644
index 000000000000..2dd5e4e48481
--- /dev/null
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -0,0 +1,110 @@
+/*
+ * Device Tree for the ARM Integrator/CP platform
+ */
+
+/dts-v1/;
+/include/ "integrator.dtsi"
+
+/ {
+        model = "ARM Integrator/CP";
+        compatible = "arm,integrator-cp";
+
+        aliases {
+                arm,timer-primary = &timer2;
+                arm,timer-secondary = &timer1;
+        };
+
+        chosen {
+                bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
+        };
+
+        timer0: timer@13000000 {
+                compatible = "arm,sp804", "arm,primecell";
+        };
+
+        timer1: timer@13000100 {
+                compatible = "arm,sp804", "arm,primecell";
+        };
+
+        timer2: timer@13000200 {
+                compatible = "arm,sp804", "arm,primecell";
+        };
+
+        pic: pic@14000000 {
+                valid-mask = <0x1fc003ff>;
+        };
+
+        cic: cic@10000040 {
+                compatible = "arm,versatile-fpga-irq";
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                reg = <0x10000040 0x100>;
+                clear-mask = <0xffffffff>;
+                valid-mask = <0x00000007>;
+        };
+
+        sic: sic@ca000000 {
+                compatible = "arm,versatile-fpga-irq";
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                reg = <0xca000000 0x100>;
+                clear-mask = <0x00000fff>;
+                valid-mask = <0x00000fff>;
+        };
+
+        ethernet@c8000000 {
+                compatible = "smsc,lan91c111";
+                reg = <0xc8000000 0x10>;
+                interrupt-parent = <&pic>;
+                interrupts = <27>;
+        };
+
+        fpga {
+                /*
+                 * These PrimeCells are at the same location and using
+                 * the same interrupts in all Integrators, but in the CP
+                 * slightly newer versions are deployed.
+                 */
+                rtc@15000000 {
+                        compatible = "arm,pl031", "arm,primecell";
+                };
+
+                uart@16000000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                };
+
+                uart@17000000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                };
+
+                kmi@18000000 {
+                        compatible = "arm,pl050", "arm,primecell";
+                };
+
+                kmi@19000000 {
+                        compatible = "arm,pl050", "arm,primecell";
+                };
+
+                /*
+                 * These PrimeCells are only available on the Integrator/CP
+                 */
+                mmc@1c000000 {
+                        compatible = "arm,pl180", "arm,primecell";
+                        reg = <0x1c000000 0x1000>;
+                        interrupts = <23 24>;
+                        max-frequency = <515633>;
+                };
+
+                aaci@1d000000 {
+                        compatible = "arm,pl041", "arm,primecell";
+                        reg = <0x1d000000 0x1000>;
+                        interrupts = <25>;
+                };
+
+                clcd@c0000000 {
+                        compatible = "arm,pl110", "arm,primecell";
+                        reg = <0xC0000000 0x1000>;
+                        interrupts = <22>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 7408655f91b5..9b32d0272825 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -25,6 +25,16 @@
                 };
         };
 
+        gpio_fan {
+                /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
+                compatible = "gpio-fan";
+                gpios = <&gpio1 14 1
+                         &gpio1 13 1>;
+                gpio-fan,speed-map = <0    0
+                                      3000 1
+                                      6000 2>;
+        };
+
         ocp@f1000000 {
                 sata@80000 {
                         status = "okay";
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
new file mode 100644
index 000000000000..08a582414b88
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -0,0 +1,57 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+        model = "Seagate FreeAgent Dockstar";
+        compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
+        };
+
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+
+                nand@3000000 {
+                        status = "okay";
+
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x100000>;
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x0100000 0x400000>;
+                        };
+
+                        partition@500000 {
+                                label = "data";
+                                reg = <0x0500000 0xfb00000>;
+                        };
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                health {
+                        label = "status:green:health";
+                        gpios = <&gpio1 14 1>;
+                        linux,default-trigger = "default-on";
+                };
+                fault {
+                        label = "status:orange:fault";
+                        gpios = <&gpio1 15 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index f8ca6fa88192..d97cd9d4753e 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -12,7 +12,7 @@
         };
 
         chosen {
-                bootargs = "console=ttyS0,115200n8 earlyprintk mtdparts=orion_nand:0xc0000@0x0(uboot),0x20000@0xa0000(env),0x300000@0x100000(zImage),0x300000@0x540000(initrd),0x1f400000@0x980000(boot)";
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
                 linux,initrd-start = <0x4500040>;
                 linux,initrd-end   = <0x4800000>;
         };
@@ -30,7 +30,37 @@
                         clock-frequency = <200000000>;
                         status = "ok";
                 };
+
+                nand@3000000 {
+                        status = "okay";
+
+                        partition@0 {
+                                label = "uboot";
+                                reg = <0x0000000 0xc0000>;
+                        };
+
+                        partition@a0000 {
+                                label = "env";
+                                reg = <0xa0000 0x20000>;
+                        };
+
+                        partition@100000 {
+                                label = "zImage";
+                                reg = <0x100000 0x300000>;
+                        };
+
+                        partition@540000 {
+                                label = "initrd";
+                                reg = <0x540000 0x300000>;
+                        };
+
+                        partition@980000 {
+                                label = "boot";
+                                reg = <0x980000 0x1f400000>;
+                        };
+                };
         };
+
         gpio-leds {
                 compatible = "gpio-leds";
 
@@ -69,4 +99,22 @@
                         gpios = <&gpio1 16 0>;
                 };
         };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "OTB Button";
+                        linux,code = <133>;
+                        gpios = <&gpio1 3 1>;
+                        debounce-interval = <100>;
+                };
+                button@2 {
+                        label = "Reset";
+                        linux,code = <0x198>;
+                        gpios = <&gpio0 12 1>;
+                        debounce-interval = <100>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
new file mode 100644
index 000000000000..865aeec40a26
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -0,0 +1,105 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+        model = "Iomega StorCenter ix2-200";
+        compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        ocp@f1000000 {
+                i2c@11000 {
+                        status = "okay";
+
+                        lm63: lm63@4c {
+                                compatible = "national,lm63";
+                                reg = <0x4c>;
+                        };
+                };
+
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+
+                nand@3000000 {
+                        status = "okay";
+
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x100000>;
+                                read-only;
+                        };
+
+                        partition@a0000 {
+                                label = "env";
+                                reg = <0xa0000 0x20000>;
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x100000 0x300000>;
+                        };
+
+                        partition@400000 {
+                                label = "uInitrd";
+                                reg = <0x540000 0x1000000>;
+                        };
+                };
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                power_led {
+                        label = "status:white:power_led";
+                        gpios = <&gpio0 16 0>;
+                        linux,default-trigger = "default-on";
+                };
+                health_led1 {
+                        label = "status:red:health_led";
+                        gpios = <&gpio1 5 0>;
+                };
+                health_led2 {
+                        label = "status:white:health_led";
+                        gpios = <&gpio1 4 0>;
+                };
+                backup_led {
+                        label = "status:blue:backup_led";
+                        gpios = <&gpio0 15 0>;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                Power {
+                        label = "Power Button";
+                        linux,code = <116>;
+                        gpios = <&gpio0 14 1>;
+                };
+                Reset {
+                        label = "Reset Button";
+                        linux,code = <0x198>;
+                        gpios = <&gpio0 12 1>;
+                };
+                OTB {
+                        label = "OTB Button";
+                        linux,code = <133>;
+                        gpios = <&gpio1 3 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
new file mode 100644
index 000000000000..75bdb93fed26
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -0,0 +1,29 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+        model = "Keymile Kirkwood Reference Design";
+        compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x08000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+
+                nand@3000000 {
+                        status = "ok";
+                        chip-delay = <25>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index cef9616f330a..4e5b8154a5be 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -14,7 +14,8 @@
 
         ocp@f1000000 {
                 compatible = "simple-bus";
-                ranges = <0 0xf1000000 0x4000000>;
+                ranges = <0x00000000 0xf1000000 0x4000000
+                          0xf5000000 0xf5000000 0x0000400>;
                 #address-cells = <1>;
                 #size-cells = <1>;
 
@@ -105,5 +106,14 @@
                         clock-frequency = <100000>;
                         status = "disabled";
                 };
+
+                crypto@30000 {
+                        compatible = "marvell,orion-crypto";
+                        reg = <0x30000 0x10000>,
+                              <0xf5000000 0x800>;
+                        reg-names = "regs", "sram";
+                        interrupts = <22>;
+                        status = "okay";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
index e92be5a474e7..595492aa5053 100644
--- a/arch/arm/boot/dts/pxa910-dkb.dts
+++ b/arch/arm/boot/dts/pxa910-dkb.dts
@@ -29,6 +29,143 @@
                         };
                         twsi1: i2c@d4011000 {
                                 status = "okay";
+
+                                pmic: 88pm860x@34 {
+                                        compatible = "marvell,88pm860x";
+                                        reg = <0x34>;
+                                        interrupts = <4>;
+                                        interrupt-parent = <&intc>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <1>;
+
+                                        marvell,88pm860x-irq-read-clr;
+                                        marvell,88pm860x-slave-addr = <0x11>;
+
+                                        regulators {
+                                                BUCK1 {
+                                                        regulator-min-microvolt = <1000000>;
+                                                        regulator-max-microvolt = <1500000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                BUCK2 {
+                                                        regulator-min-microvolt = <1000000>;
+                                                        regulator-max-microvolt = <1500000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                BUCK3 {
+                                                        regulator-min-microvolt = <1000000>;
+                                                        regulator-max-microvolt = <3000000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO1 {
+                                                        regulator-min-microvolt = <1200000>;
+                                                        regulator-max-microvolt = <2800000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO2 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO3 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO4 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-always-on;
+                                                };
+                                                LDO5 {
+                                                        regulator-min-microvolt = <2900000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO6 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO7 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <2900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO8 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <2900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO9 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO10 {
+                                                        regulator-min-microvolt = <1200000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO12 {
+                                                        regulator-min-microvolt = <1200000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-always-on;
+                                                };
+                                                LDO13 {
+                                                        regulator-min-microvolt = <1200000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-always-on;
+                                                };
+                                                LDO14 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-always-on;
+                                                };
+                                        };
+                                        rtc {
+                                                marvell,88pm860x-vrtc = <1>;
+                                        };
+                                        touch {
+                                                marvell,88pm860x-gpadc-prebias = <1>;
+                                                marvell,88pm860x-gpadc-slot-cycle = <1>;
+                                                marvell,88pm860x-tsi-prebias = <6>;
+                                                marvell,88pm860x-pen-prebias = <16>;
+                                                marvell,88pm860x-pen-prechg = <2>;
+                                                marvell,88pm860x-resistor-X = <300>;
+                                        };
+                                        backlights {
+                                                backlight-0 {
+                                                        marvell,88pm860x-iset = <4>;
+                                                        marvell,88pm860x-pwm = <3>;
+                                                };
+                                                backlight-2 {
+                                                };
+                                        };
+                                        leds {
+                                                led0-red {
+                                                        marvell,88pm860x-iset = <12>;
+                                                };
+                                                led0-green {
+                                                        marvell,88pm860x-iset = <12>;
+                                                };
+                                                led0-blue {
+                                                        marvell,88pm860x-iset = <12>;
+                                                };
+                                        };
+                                };
                         };
                         rtc: rtc@d4010000 {
                                 status = "okay";
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index a3be44d86bcd..825aaca33034 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -120,6 +120,8 @@
 
                         twsi1: i2c@d4011000 {
                                 compatible = "mrvl,mmp-twsi";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                 reg = <0xd4011000 0x1000>;
                                 interrupts = <7>;
                                 mrvl,i2c-fast-mode;
@@ -128,6 +130,8 @@
 
                         twsi2: i2c@d4037000 {
                                 compatible = "mrvl,mmp-twsi";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                 reg = <0xd4037000 0x1000>;
                                 interrupts = <54>;
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/xenvm-4.2.dts b/arch/arm/boot/dts/xenvm-4.2.dts
new file mode 100644
index 000000000000..ec3f9528e180
--- /dev/null
+++ b/arch/arm/boot/dts/xenvm-4.2.dts
@@ -0,0 +1,68 @@
+/*
+ * Xen Virtual Machine for unprivileged guests
+ *
+ * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU)
+ * Cortex-A15 MPCore (V2P-CA15)
+ *
+ */
+
+/dts-v1/;
+
+/ {
+        model = "XENVM-4.2";
+        compatible = "xen,xenvm-4.2", "xen,xenvm";
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        chosen {
+                /* this field is going to be adjusted by the hypervisor */
+                bootargs = "console=hvc0 root=/dev/xvda";
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                };
+        };
+
+        memory@80000000 {
+                device_type = "memory";
+                /* this field is going to be adjusted by the hypervisor */
+                reg = <0 0x80000000 0 0x08000000>;
+        };
+
+        gic: interrupt-controller@2c001000 {
+                compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0 0x2c001000 0 0x1000>,
+                      <0 0x2c002000 0 0x100>;
+        };
+
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0xf08>;
+        };
+
+        hypervisor {
+                compatible = "xen,xen-4.2", "xen,xen";
+                /* this field is going to be adjusted by the hypervisor */
+                reg = <0 0xb0000000 0 0x20000>;
+                /* this field is going to be adjusted by the hypervisor */
+                interrupts = <1 15 0xf08>;
+        };
+
+        motherboard {
+                arm,v2m-memory-map = "rs1";
+        };
+};
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 565132d02105..66aa7a6db884 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -40,7 +40,6 @@ CONFIG_VMSPLIT_2G=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
 CONFIG_VFP=y
 CONFIG_NEON=y
@@ -177,6 +176,9 @@ CONFIG_SND_SOC_IMX_MC13783=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_MXS_PHY=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index aeb3af541fed..74eee0c78f28 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -1,5 +1,7 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=19
 CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
@@ -15,9 +17,19 @@ CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
 CONFIG_MACH_ESATA_SHEEVAPLUG=y
 CONFIG_MACH_GURUPLUG=y
-CONFIG_MACH_DOCKSTAR=y
+CONFIG_MACH_DREAMPLUG_DT=y
+CONFIG_MACH_ICONNECT_DT=y
+CONFIG_MACH_DLINK_KIRKWOOD_DT=y
+CONFIG_MACH_IB62X0_DT=y
+CONFIG_MACH_TS219_DT=y
+CONFIG_MACH_DOCKSTAR_DT=y
+CONFIG_MACH_GOFLEXNET_DT=y
+CONFIG_MACH_LSXL_DT=y
+CONFIG_MACH_IOMEGA_IX2_200_DT=y
+CONFIG_MACH_KM_KIRKWOOD_DT=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
+CONFIG_MACH_DOCKSTAR=y
 CONFIG_MACH_OPENRD_BASE=y
 CONFIG_MACH_OPENRD_CLIENT=y
 CONFIG_MACH_OPENRD_ULTIMATE=y
@@ -29,8 +41,6 @@ CONFIG_MACH_NET2BIG_V2=y
 CONFIG_MACH_NET5BIG_V2=y
 CONFIG_MACH_T5325=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
@@ -47,13 +57,11 @@ CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IPV6 is not set
 CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MV88E6123_61_65=y
 CONFIG_NET_PKTGEN=m
 CONFIG_CFG80211=y
 CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -69,7 +77,6 @@ CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ORION=y
 CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=m
@@ -78,22 +85,21 @@ CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
-CONFIG_MARVELL_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
-CONFIG_NET_PCI=y
+CONFIG_NET_DSA_MV88E6123_61_65=y
 CONFIG_MV643XX_ETH=y
-# CONFIG_NETDEV_10000 is not set
+CONFIG_MARVELL_PHY=y
 CONFIG_LIBERTAS=y
 CONFIG_LIBERTAS_SDIO=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
+CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
@@ -103,7 +109,8 @@ CONFIG_SPI=y
 CONFIG_SPI_ORION=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
+CONFIG_WATCHDOG=y
+CONFIG_ORION_WATCHDOG=y
 CONFIG_HID_DRAGONRISE=y
 CONFIG_HID_GYRATION=y
 CONFIG_HID_TWINHAN=y
@@ -119,10 +126,8 @@ CONFIG_HID_TOPSEED=y
 CONFIG_HID_THRUSTMASTER=y
 CONFIG_HID_ZEROPLUS=y
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
 CONFIG_USB_PRINTER=m
 CONFIG_USB_STORAGE=y
 CONFIG_USB_STORAGE_DATAFAB=y
@@ -148,7 +153,6 @@ CONFIG_MV_XOR=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
 CONFIG_UDF_FS=m
@@ -158,7 +162,6 @@ CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
@@ -171,11 +174,8 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 CONFIG_CRYPTO_CBC=m
 CONFIG_CRYPTO_PCBC=m
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index e42a0e3d4c3a..92386b20bd09 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -133,7 +133,6 @@ CONFIG_SND_DEBUG_VERBOSE=y
 # CONFIG_SND_ARM is not set
 # CONFIG_SND_SPI is not set
 CONFIG_SND_SOC=y
-# CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
@@ -149,6 +148,7 @@ CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_PCA9532=y
 CONFIG_LEDS_PCA9532_GPIO=y
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
@@ -161,10 +161,13 @@ CONFIG_RTC_DRV_DS1374=y
 CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_LPC32XX=y
 CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
 CONFIG_STAGING=y
 CONFIG_LPC32XX_ADC=y
-CONFIG_MAX517=y
 CONFIG_IIO=y
+CONFIG_MAX517=y
+CONFIG_PWM=y
+CONFIG_PWM_LPC32XX=y
 CONFIG_EXT2_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_MSDOS_FS=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index f513acedc10a..53382b6c8bb4 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -1,13 +1,14 @@
 # CONFIG_ARM_PATCH_PHYS_VIRT is not set
 CONFIG_EXPERIMENTAL=y
 CONFIG_KERNEL_LZMA=y
+CONFIG_NO_HZ=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
-# CONFIG_BLOCK is not set
+# CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_SHMOBILE=y
 CONFIG_ARCH_R8A7779=y
 CONFIG_MACH_MARZEN=y
@@ -21,7 +22,6 @@ CONFIG_ARM_ERRATA_458693=y
 CONFIG_ARM_ERRATA_460075=y
 CONFIG_ARM_ERRATA_743622=y
 CONFIG_ARM_ERRATA_754322=y
-CONFIG_NO_HZ=y
 CONFIG_SMP=y
 # CONFIG_ARM_CPU_TOPOLOGY is not set
 CONFIG_AEABI=y
@@ -29,13 +29,16 @@ CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
+CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on"
 CONFIG_CMDLINE_FORCE=y
 CONFIG_KEXEC=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
+CONFIG_UNIX=y
 CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
 # CONFIG_IPV6 is not set
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
@@ -71,16 +74,18 @@ CONFIG_GPIO_SYSFS=y
 CONFIG_THERMAL=y
 CONFIG_RCAR_THERMAL=y
 CONFIG_SSB=y
-# CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
-# CONFIG_FILE_LOCKING is not set
 # CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY_USER is not set
 CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_INFO_REDUCED=y
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 2e86b31c33cf..7bcf850eddcd 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -21,6 +21,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 36d60dda310c..048aaca60814 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -53,6 +53,9 @@ CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 # CONFIG_BLK_DEV is not set
 CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_M25P80
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_GPMI_NAND=y
 CONFIG_NETDEVICES=y
@@ -82,13 +85,13 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MXS=y
 CONFIG_SPI=y
 CONFIG_SPI_GPIO=m
+CONFIG_SPI_MXS=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 # CONFIG_MFD_SUPPORT is not set
 CONFIG_DISPLAY_SUPPORT=m
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
@@ -103,14 +106,45 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
 CONFIG_SND_SOC_SGTL5000=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_FB=y
+CONFIG_FB_MXS=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FONTS=y
+CONFIG_LOGO=y
+CONFIG_USB=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
 CONFIG_MMC=y
 CONFIG_MMC_MXS=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_DS1307=m
 CONFIG_RTC_DRV_STMP=y
 CONFIG_DMADEVICES=y
 CONFIG_MXS_DMA=y
+CONFIG_STAGING=y
+CONFIG_MXS_LRADC=y
+CONFIG_IIO_SYSFS_TRIGGER=y
 CONFIG_COMMON_CLK_DEBUG=y
+CONFIG_IIO=y
+CONFIG_PWM=y
+CONFIG_PWM_MXS=y
 CONFIG_EXT3_FS=y
 # CONFIG_DNOTIFY is not set
 CONFIG_FSCACHE=m
diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig
index ba6a515086b5..3a186d653dac 100644
--- a/arch/arm/configs/s3c6400_defconfig
+++ b/arch/arm/configs/s3c6400_defconfig
@@ -9,11 +9,14 @@ CONFIG_ARCH_S3C64XX=y
 CONFIG_S3C_BOOT_ERROR_RESET=y
 CONFIG_MACH_SMDK6400=y
 CONFIG_MACH_ANW6410=y
+CONFIG_MACH_MINI6410=y
+CONFIG_MACH_REAL6410=y
 CONFIG_MACH_SMDK6410=y
 CONFIG_MACH_NCP=y
 CONFIG_MACH_HMT=y
 CONFIG_MACH_SMARTQ5=y
 CONFIG_MACH_SMARTQ7=y
+CONFIG_MACH_WLF_CRAGG_6410=y
 CONFIG_CPU_32v6K=y
 CONFIG_AEABI=y
 CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/linuxrc initrd=0x51000000,6M ramdisk_size=6144"
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 0d6bb738c6de..e2184f6c20b3 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -24,11 +24,11 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_TEGRA=y
+CONFIG_GPIO_PCA953X=y
 CONFIG_ARCH_TEGRA_2x_SOC=y
 CONFIG_ARCH_TEGRA_3x_SOC=y
-CONFIG_MACH_HARMONY=y
-CONFIG_MACH_PAZ00=y
-CONFIG_MACH_TRIMSLICE=y
+CONFIG_TEGRA_PCI=y
+CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA=y
 CONFIG_TEGRA_EMC_SCALING_ENABLE=y
 CONFIG_SMP=y
 CONFIG_PREEMPT=y
@@ -67,7 +67,18 @@ CONFIG_INET6_IPCOMP=y
 CONFIG_IPV6_MIP6=y
 CONFIG_IPV6_TUNNEL=y
 CONFIG_IPV6_MULTIPLE_TABLES=y
-# CONFIG_WIRELESS is not set
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HCIBTUSB=m
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_GPIO=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
@@ -87,7 +98,8 @@ CONFIG_USB_PEGASUS=y
 CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
 CONFIG_USB_NET_SMSC95XX=y
-# CONFIG_WLAN is not set
+CONFIG_RT2X00=y
+CONFIG_RT2800USB=m
 CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
@@ -105,25 +117,31 @@ CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
 CONFIG_SPI_TEGRA=y
-CONFIG_GPIO_TPS65910=y
+CONFIG_GPIO_PCA953X_IRQ=y
 CONFIG_GPIO_TPS6586X=y
+CONFIG_GPIO_TPS65910=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_BATTERY_SBS=y
 CONFIG_SENSORS_LM90=y
 CONFIG_MFD_TPS6586X=y
 CONFIG_MFD_TPS65910=y
+CONFIG_MFD_MAX8907=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
 CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MAX8907=y
 CONFIG_REGULATOR_TPS62360=y
 CONFIG_REGULATOR_TPS6586X=y
 CONFIG_REGULATOR_TPS65910=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
 CONFIG_SOUND=y
 CONFIG_SND=y
 # CONFIG_SND_SUPPORT_OLD_API is not set
 # CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_PCI is not set
 # CONFIG_SND_ARM is not set
 # CONFIG_SND_SPI is not set
 # CONFIG_SND_USB is not set
@@ -136,13 +154,25 @@ CONFIG_SND_SOC_TEGRA_ALC5632=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_ACM=y
+CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_DRV_MAX8907=y
+CONFIG_RTC_DRV_TPS65910=y
 CONFIG_RTC_DRV_EM3027=y
 CONFIG_RTC_DRV_TEGRA=y
 CONFIG_DMADEVICES=y
@@ -154,10 +184,14 @@ CONFIG_SENSORS_AK8975=y
 CONFIG_MFD_NVEC=y
 CONFIG_KEYBOARD_NVEC=y
 CONFIG_SERIO_NVEC_PS2=y
+CONFIG_NVEC_POWER=y
+CONFIG_NVEC_PAZ00=y
 CONFIG_TEGRA_IOMMU_GART=y
 CONFIG_TEGRA_IOMMU_SMMU=y
 CONFIG_MEMORY=y
 CONFIG_IIO=y
+CONFIG_PWM=y
+CONFIG_PWM_TEGRA=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
@@ -170,6 +204,7 @@ CONFIG_EXT4_FS=y
 # CONFIG_DNOTIFY is not set
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
@@ -188,8 +223,6 @@ CONFIG_DEBUG_VM=y
 CONFIG_DEBUG_SG=y
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ARC4=y
 CONFIG_CRYPTO_TWOFISH=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_DEV_TEGRA_AES=y
diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index 960abceb8e14..8a7196ca5106 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -5,16 +5,33 @@ header-y += hwcap.h
 generic-y += auxvec.h
 generic-y += bitsperlong.h
 generic-y += cputime.h
+generic-y += current.h
 generic-y += emergency-restart.h
 generic-y += errno.h
+generic-y += exec.h
 generic-y += ioctl.h
+generic-y += ipcbuf.h
 generic-y += irq_regs.h
 generic-y += kdebug.h
 generic-y += local.h
 generic-y += local64.h
+generic-y += msgbuf.h
+generic-y += param.h
+generic-y += parport.h
 generic-y += percpu.h
 generic-y += poll.h
 generic-y += resource.h
 generic-y += sections.h
+generic-y += segment.h
+generic-y += sembuf.h
+generic-y += serial.h
+generic-y += shmbuf.h
 generic-y += siginfo.h
 generic-y += sizes.h
+generic-y += socket.h
+generic-y += sockios.h
+generic-y += termbits.h
+generic-y += termios.h
+generic-y += timex.h
+generic-y += types.h
+generic-y += unaligned.h
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 62e75475e57e..d40229d9a1c9 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -2,11 +2,12 @@
 #define __ASMARM_ARCH_TIMER_H
 
 #include <asm/errno.h>
+#include <linux/clocksource.h>
 
 #ifdef CONFIG_ARM_ARCH_TIMER
-#define ARCH_HAS_READ_CURRENT_TIMER
 int arch_timer_of_register(void);
 int arch_timer_sched_clock_init(void);
+struct timecounter *arch_timer_get_timecounter(void);
 #else
 static inline int arch_timer_of_register(void)
 {
@@ -17,6 +18,11 @@ static inline int arch_timer_sched_clock_init(void)
 {
         return -ENXIO;
 }
+
+static inline struct timecounter *arch_timer_get_timecounter(void)
+{
+        return NULL;
+}
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/current.h b/arch/arm/include/asm/current.h
deleted file mode 100644
index 75d21e2a3ff7..000000000000
--- a/arch/arm/include/asm/current.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef _ASMARM_CURRENT_H
-#define _ASMARM_CURRENT_H
-
-#include <linux/thread_info.h>
-
-static inline struct task_struct *get_current(void) __attribute_const__;
-
-static inline struct task_struct *get_current(void)
-{
-        return current_thread_info()->task;
-}
-
-#define current (get_current())
-
-#endif /* _ASMARM_CURRENT_H */
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
index dc6145120de3..ab98fdd083bd 100644
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@@ -15,6 +15,11 @@
 
 #ifndef __ASSEMBLY__
 
+struct delay_timer {
+        unsigned long (*read_current_timer)(void);
+        unsigned long freq;
+};
+
 extern struct arm_delay_ops {
         void (*delay)(unsigned long);
         void (*const_udelay)(unsigned long);
@@ -56,6 +61,10 @@ extern void __loop_delay(unsigned long loops);
 extern void __loop_udelay(unsigned long usecs);
 extern void __loop_const_udelay(unsigned long);
 
+/* Delay-loop timer registration. */
+#define ARCH_HAS_READ_CURRENT_TIMER
+extern void register_current_timer_delay(const struct delay_timer *timer);
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* defined(_ARM_DELAY_H) */
diff --git a/arch/arm/include/asm/exec.h b/arch/arm/include/asm/exec.h
deleted file mode 100644
index 7c4fbef72b3a..000000000000
--- a/arch/arm/include/asm/exec.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_ARM_EXEC_H
-#define __ASM_ARM_EXEC_H
-
-#define arch_align_stack(x) (x)
-
-#endif /* __ASM_ARM_EXEC_H */
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index 7e30874377e6..4f8d2c0dc441 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -110,19 +110,19 @@
 #endif
 
 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
-//# ifdef _CACHE
+# ifdef _CACHE
 #  define MULTI_CACHE 1
-//# else
-//#  define _CACHE v6
-//# endif
+# else
+#  define _CACHE v6
+# endif
 #endif
 
 #if defined(CONFIG_CPU_V7)
-//# ifdef _CACHE
+# ifdef _CACHE
 #  define MULTI_CACHE 1
-//# else
-//#  define _CACHE v7
-//# endif
+# else
+#  define _CACHE v7
+# endif
 #endif
 
 #if !defined(_CACHE) && !defined(MULTI_CACHE)
diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h
index 436e60b2cf7a..2740c2a2df63 100644
--- a/arch/arm/include/asm/hardirq.h
+++ b/arch/arm/include/asm/hardirq.h
@@ -5,7 +5,7 @@
 #include <linux/threads.h>
 #include <asm/irq.h>
 
-#define NR_IPI  5
+#define NR_IPI  6
 
 typedef struct {
         unsigned int __softirq_pending;
diff --git a/arch/arm/include/asm/hardware/linkup-l1110.h b/arch/arm/include/asm/hardware/linkup-l1110.h
deleted file mode 100644
index 7ec91168a576..000000000000
--- a/arch/arm/include/asm/hardware/linkup-l1110.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
-*
-* Definitions for H3600 Handheld Computer
-*
-* Copyright 2001 Compaq Computer Corporation.
-*
-* Use consistent with the GNU GPL is permitted,
-* provided that this copyright notice is
-* preserved in its entirety in all copies and derived works.
-*
-* COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
-* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
-* FITNESS FOR ANY PARTICULAR PURPOSE.
-*
-* Author: Jamey Hicks.
-*
-*/
-
-/* LinkUp Systems PCCard/CompactFlash Interface for SA-1100 */
-
-/* PC Card Status Register */
-#define LINKUP_PRS_S1   (1 << 0) /* voltage control bits S1-S4 */
-#define LINKUP_PRS_S2   (1 << 1)
-#define LINKUP_PRS_S3   (1 << 2)
-#define LINKUP_PRS_S4   (1 << 3)
-#define LINKUP_PRS_BVD1 (1 << 4)
-#define LINKUP_PRS_BVD2 (1 << 5)
-#define LINKUP_PRS_VS1  (1 << 6)
-#define LINKUP_PRS_VS2  (1 << 7)
-#define LINKUP_PRS_RDY  (1 << 8)
-#define LINKUP_PRS_CD1  (1 << 9)
-#define LINKUP_PRS_CD2  (1 << 10)
-
-/* PC Card Command Register */
-#define LINKUP_PRC_S1   (1 << 0)
-#define LINKUP_PRC_S2   (1 << 1)
-#define LINKUP_PRC_S3   (1 << 2)
-#define LINKUP_PRC_S4   (1 << 3)
-#define LINKUP_PRC_RESET (1 << 4)
-#define LINKUP_PRC_APOE (1 << 5) /* Auto Power Off Enable: clears S1-S4 when either nCD goes high */
-#define LINKUP_PRC_CFE  (1 << 6) /* CompactFlash mode Enable: addresses A[10:0] only, A[25:11] high */
-#define LINKUP_PRC_SOE  (1 << 7) /* signal output driver enable */
-#define LINKUP_PRC_SSP  (1 << 8) /* sock select polarity: 0 for socket 0, 1 for socket 1 */
-#define LINKUP_PRC_MBZ  (1 << 15) /* must be zero */
-
-struct linkup_l1110 {
-        volatile short prc;
-};
diff --git a/arch/arm/include/asm/hypervisor.h b/arch/arm/include/asm/hypervisor.h
new file mode 100644
index 000000000000..b90d9e523d6f
--- /dev/null
+++ b/arch/arm/include/asm/hypervisor.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_ARM_HYPERVISOR_H
+#define _ASM_ARM_HYPERVISOR_H
+
+#include <asm/xen/hypervisor.h>
+
+#endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 8f4db67533e5..35c1ed89b936 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -47,13 +47,68 @@ extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
 
-#define __raw_writeb(v,a)       ((void)(__chk_io_ptr(a), *(volatile unsigned char __force  *)(a) = (v)))
-#define __raw_writew(v,a)       ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
-#define __raw_writel(v,a)       ((void)(__chk_io_ptr(a), *(volatile unsigned int __force   *)(a) = (v)))
+#if __LINUX_ARM_ARCH__ < 6
+/*
+ * Half-word accesses are problematic with RiscPC due to limitations of
+ * the bus. Rather than special-case the machine, just let the compiler
+ * generate the access for CPUs prior to ARMv6.
+ */
+#define __raw_readw(a)         (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
+#define __raw_writew(v,a)      ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
+#else
+/*
+ * When running under a hypervisor, we want to avoid I/O accesses with
+ * writeback addressing modes as these incur a significant performance
+ * overhead (the address generation must be emulated in software).
+ */
+static inline void __raw_writew(u16 val, volatile void __iomem *addr)
+{
+        asm volatile("strh %1, %0"
+                     : "+Qo" (*(volatile u16 __force *)addr)
+                     : "r" (val));
+}
+
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+        u16 val;
+        asm volatile("ldrh %1, %0"
+                     : "+Qo" (*(volatile u16 __force *)addr),
+                       "=r" (val));
+        return val;
+}
+#endif
 
-#define __raw_readb(a)          (__chk_io_ptr(a), *(volatile unsigned char __force  *)(a))
-#define __raw_readw(a)          (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
-#define __raw_readl(a)          (__chk_io_ptr(a), *(volatile unsigned int __force   *)(a))
+static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
+{
+        asm volatile("strb %1, %0"
+                     : "+Qo" (*(volatile u8 __force *)addr)
+                     : "r" (val));
+}
+
+static inline void __raw_writel(u32 val, volatile void __iomem *addr)
+{
+        asm volatile("str %1, %0"
+                     : "+Qo" (*(volatile u32 __force *)addr)
+                     : "r" (val));
+}
+
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+        u8 val;
+        asm volatile("ldrb %1, %0"
+                     : "+Qo" (*(volatile u8 __force *)addr),
+                       "=r" (val));
+        return val;
+}
+
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+        u32 val;
+        asm volatile("ldr %1, %0"
+                     : "+Qo" (*(volatile u32 __force *)addr),
+                       "=r" (val));
+        return val;
+}
 
 /*
  * Architecture ioremap implementation.
diff --git a/arch/arm/include/asm/ipcbuf.h b/arch/arm/include/asm/ipcbuf.h
deleted file mode 100644
index 84c7e51cb6d0..000000000000
--- a/arch/arm/include/asm/ipcbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ipcbuf.h>
diff --git a/arch/arm/include/asm/msgbuf.h b/arch/arm/include/asm/msgbuf.h
deleted file mode 100644
index 33b35b946eaa..000000000000
--- a/arch/arm/include/asm/msgbuf.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef _ASMARM_MSGBUF_H
-#define _ASMARM_MSGBUF_H
-
-/* 
- * The msqid64_ds structure for arm architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct msqid64_ds {
-        struct ipc64_perm msg_perm;
-        __kernel_time_t msg_stime;      /* last msgsnd time */
-        unsigned long   __unused1;
-        __kernel_time_t msg_rtime;      /* last msgrcv time */
-        unsigned long   __unused2;
-        __kernel_time_t msg_ctime;      /* last change time */
-        unsigned long   __unused3;
-        unsigned long  msg_cbytes;      /* current number of bytes on queue */
-        unsigned long  msg_qnum;        /* number of messages in queue */
-        unsigned long  msg_qbytes;      /* max number of bytes on queue */
-        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
-        __kernel_pid_t msg_lrpid;       /* last receive pid */
-        unsigned long  __unused4;
-        unsigned long  __unused5;
-};
-
-#endif /* _ASMARM_MSGBUF_H */
diff --git a/arch/arm/include/asm/mutex.h b/arch/arm/include/asm/mutex.h
index b1479fd04a95..87c044910fe0 100644
--- a/arch/arm/include/asm/mutex.h
+++ b/arch/arm/include/asm/mutex.h
@@ -9,8 +9,13 @@
 #define _ASM_MUTEX_H
 /*
  * On pre-ARMv6 hardware this results in a swp-based implementation,
- * which is the most efficient. For ARMv6+, we emit a pair of exclusive
- * accesses instead.
+ * which is the most efficient. For ARMv6+, we have exclusive memory
+ * accessors and use atomic_dec to avoid the extra xchg operations
+ * on the locking slowpaths.
  */
+#if __LINUX_ARM_ARCH__ < 6
 #include <asm-generic/mutex-xchg.h>
+#else
+#include <asm-generic/mutex-dec.h>
 #endif
+#endif  /* _ASM_MUTEX_H */
diff --git a/arch/arm/include/asm/opcodes-virt.h b/arch/arm/include/asm/opcodes-virt.h
new file mode 100644
index 000000000000..b85665a96f8e
--- /dev/null
+++ b/arch/arm/include/asm/opcodes-virt.h
@@ -0,0 +1,29 @@
+/*
+ * opcodes-virt.h: Opcode definitions for the ARM virtualization extensions
+ * Copyright (C) 2012  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARM_OPCODES_VIRT_H
+#define __ASM_ARM_OPCODES_VIRT_H
+
+#include <asm/opcodes.h>
+
+#define __HVC(imm16) __inst_arm_thumb32(                                \
+        0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F),    \
+        0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF)     \
+)
+
+#endif /* ! __ASM_ARM_OPCODES_VIRT_H */
diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index 19c48deda70f..74e211a6fb24 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -19,6 +19,33 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 
 
 /*
+ * Assembler opcode byteswap helpers.
+ * These are only intended for use by this header: don't use them directly,
+ * because they will be suboptimal in most cases.
+ */
+#define ___asm_opcode_swab32(x) (       \
+          (((x) << 24) & 0xFF000000)    \
+        | (((x) <<  8) & 0x00FF0000)    \
+        | (((x) >>  8) & 0x0000FF00)    \
+        | (((x) >> 24) & 0x000000FF)    \
+)
+#define ___asm_opcode_swab16(x) (       \
+          (((x) << 8) & 0xFF00)         \
+        | (((x) >> 8) & 0x00FF)         \
+)
+#define ___asm_opcode_swahb32(x) (      \
+          (((x) << 8) & 0xFF00FF00)     \
+        | (((x) >> 8) & 0x00FF00FF)     \
+)
+#define ___asm_opcode_swahw32(x) (      \
+          (((x) << 16) & 0xFFFF0000)    \
+        | (((x) >> 16) & 0x0000FFFF)    \
+)
+#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF)
+#define ___asm_opcode_identity16(x) ((x) & 0xFFFF)
+
+
+/*
  * Opcode byteswap helpers
  *
  * These macros help with converting instructions between a canonical integer
@@ -41,39 +68,163 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
  * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not
  * represent any valid Thumb-2 instruction.  For this range,
  * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false.
+ *
+ * The ___asm variants are intended only for use by this header, in situations
+ * involving inline assembler.  For .S files, the normal __opcode_*() macros
+ * should do the right thing.
  */
+#ifdef __ASSEMBLY__
 
-#ifndef __ASSEMBLY__
+#define ___opcode_swab32(x) ___asm_opcode_swab32(x)
+#define ___opcode_swab16(x) ___asm_opcode_swab16(x)
+#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x)
+#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x)
+#define ___opcode_identity32(x) ___asm_opcode_identity32(x)
+#define ___opcode_identity16(x) ___asm_opcode_identity16(x)
+
+#else /* ! __ASSEMBLY__ */
 
 #include <linux/types.h>
 #include <linux/swab.h>
 
+#define ___opcode_swab32(x) swab32(x)
+#define ___opcode_swab16(x) swab16(x)
+#define ___opcode_swahb32(x) swahb32(x)
+#define ___opcode_swahw32(x) swahw32(x)
+#define ___opcode_identity32(x) ((u32)(x))
+#define ___opcode_identity16(x) ((u16)(x))
+
+#endif /* ! __ASSEMBLY__ */
+
+
 #ifdef CONFIG_CPU_ENDIAN_BE8
-#define __opcode_to_mem_arm(x) swab32(x)
-#define __opcode_to_mem_thumb16(x) swab16(x)
-#define __opcode_to_mem_thumb32(x) swahb32(x)
-#else
-#define __opcode_to_mem_arm(x) ((u32)(x))
-#define __opcode_to_mem_thumb16(x) ((u16)(x))
-#define __opcode_to_mem_thumb32(x) swahw32(x)
+
+#define __opcode_to_mem_arm(x) ___opcode_swab32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x)
+#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x)
+
+#else /* ! CONFIG_CPU_ENDIAN_BE8 */
+
+#define __opcode_to_mem_arm(x) ___opcode_identity32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x)
+#ifndef CONFIG_CPU_ENDIAN_BE32
+/*
+ * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
+ * work in all cases, due to alignment constraints.  For now, a correct
+ * version is not provided for BE32.
+ */
+#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x)
 #endif
 
+#endif /* ! CONFIG_CPU_ENDIAN_BE8 */
+
 #define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x)
 #define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x)
+#ifndef CONFIG_CPU_ENDIAN_BE32
 #define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x)
+#endif
 
 /* Operations specific to Thumb opcodes */
 
 /* Instruction size checks: */
-#define __opcode_is_thumb32(x) ((u32)(x) >= 0xE8000000UL)
-#define __opcode_is_thumb16(x) ((u32)(x) < 0xE800UL)
+#define __opcode_is_thumb32(x) (                \
+           ((x) & 0xF8000000) == 0xE8000000     \
+        || ((x) & 0xF0000000) == 0xF0000000     \
+)
+#define __opcode_is_thumb16(x) (                                        \
+           ((x) & 0xFFFF0000) == 0                                      \
+        && !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000)      \
+)
 
 /* Operations to construct or split 32-bit Thumb instructions: */
-#define __opcode_thumb32_first(x) ((u16)((x) >> 16))
-#define __opcode_thumb32_second(x) ((u16)(x))
-#define __opcode_thumb32_compose(first, second) \
-        (((u32)(u16)(first) << 16) | (u32)(u16)(second))
+#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16))
+#define __opcode_thumb32_second(x) (___opcode_identity16(x))
+#define __opcode_thumb32_compose(first, second) (                       \
+          (___opcode_identity32(___opcode_identity16(first)) << 16)     \
+        | ___opcode_identity32(___opcode_identity16(second))            \
+)
+#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16))
+#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x))
+#define ___asm_opcode_thumb32_compose(first, second) (                      \
+          (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \
+        | ___asm_opcode_identity32(___asm_opcode_identity16(second))        \
+)
 
-#endif /* __ASSEMBLY__ */
+/*
+ * Opcode injection helpers
+ *
+ * In rare cases it is necessary to assemble an opcode which the
+ * assembler does not support directly, or which would normally be
+ * rejected because of the CFLAGS or AFLAGS used to build the affected
+ * file.
+ *
+ * Before using these macros, consider carefully whether it is feasible
+ * instead to change the build flags for your file, or whether it really
+ * makes sense to support old assembler versions when building that
+ * particular kernel feature.
+ *
+ * The macros defined here should only be used where there is no viable
+ * alternative.
+ *
+ *
+ * __inst_arm(x): emit the specified ARM opcode
+ * __inst_thumb16(x): emit the specified 16-bit Thumb opcode
+ * __inst_thumb32(x): emit the specified 32-bit Thumb opcode
+ *
+ * __inst_arm_thumb16(arm, thumb): emit either the specified arm or
+ *      16-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *      kernel is being built
+ *
+ * __inst_arm_thumb32(arm, thumb): emit either the specified arm or
+ *      32-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *      kernel is being built
+ *
+ *
+ * Note that using these macros directly is poor practice.  Instead, you
+ * should use them to define human-readable wrapper macros to encode the
+ * instructions that you care about.  In code which might run on ARMv7 or
+ * above, you can usually use the __inst_arm_thumb{16,32} macros to
+ * specify the ARM and Thumb alternatives at the same time.  This ensures
+ * that the correct opcode gets emitted depending on the instruction set
+ * used for the kernel build.
+ *
+ * Look at opcodes-virt.h for an example of how to use these macros.
+ */
+#include <linux/stringify.h>
+
+#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x))
+#define __inst_thumb32(x) ___inst_thumb32(                              \
+        ___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)),   \
+        ___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x))   \
+)
+#define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x))
+
+#ifdef CONFIG_THUMB2_KERNEL
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) \
+        __inst_thumb16(thumb_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) \
+        __inst_thumb32(thumb_opcode)
+#else
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#endif
+
+/* Helpers for the helpers.  Don't use these directly. */
+#ifdef __ASSEMBLY__
+#define ___inst_arm(x) .long x
+#define ___inst_thumb16(x) .short x
+#define ___inst_thumb32(first, second) .short first, second
+#else
+#define ___inst_arm(x) ".long " __stringify(x) "\n\t"
+#define ___inst_thumb16(x) ".short " __stringify(x) "\n\t"
+#define ___inst_thumb32(first, second) \
+        ".short " __stringify(first) ", " __stringify(second) "\n\t"
+#endif
 
 #endif /* __ASM_ARM_OPCODES_H */
diff --git a/arch/arm/include/asm/param.h b/arch/arm/include/asm/param.h
deleted file mode 100644
index 8b24bf94c06b..000000000000
--- a/arch/arm/include/asm/param.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- *  arch/arm/include/asm/param.h
- *
- *  Copyright (C) 1995-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_PARAM_H
-#define __ASM_PARAM_H
-
-#ifdef __KERNEL__
-# define HZ             CONFIG_HZ       /* Internal kernel timer frequency */
-# define USER_HZ        100             /* User interfaces are in "ticks" */
-# define CLOCKS_PER_SEC (USER_HZ)       /* like times() */
-#else
-# define HZ             100
-#endif
-
-#define EXEC_PAGESIZE   4096
-
-#ifndef NOGROUP
-#define NOGROUP         (-1)
-#endif
-
-/* max length of hostname */
-#define MAXHOSTNAMELEN  64
-
-#endif
-
diff --git a/arch/arm/include/asm/parport.h b/arch/arm/include/asm/parport.h
deleted file mode 100644
index 26e94b09035a..000000000000
--- a/arch/arm/include/asm/parport.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  arch/arm/include/asm/parport.h: ARM-specific parport initialisation
- *
- *  Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
- *
- * This file should only be included by drivers/parport/parport_pc.c.
- */
-
-#ifndef __ASMARM_PARPORT_H
-#define __ASMARM_PARPORT_H
-
-static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
-static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
-{
-        return parport_pc_find_isa_ports (autoirq, autodma);
-}
-
-#endif /* !(_ASMARM_PARPORT_H) */
diff --git a/arch/arm/include/asm/segment.h b/arch/arm/include/asm/segment.h
deleted file mode 100644
index 9e24c21f6304..000000000000
--- a/arch/arm/include/asm/segment.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __ASM_ARM_SEGMENT_H
-#define __ASM_ARM_SEGMENT_H
-
-#define __KERNEL_CS   0x0
-#define __KERNEL_DS   0x0
-
-#define __USER_CS     0x1
-#define __USER_DS     0x1
-
-#endif /* __ASM_ARM_SEGMENT_H */
-
diff --git a/arch/arm/include/asm/sembuf.h b/arch/arm/include/asm/sembuf.h
deleted file mode 100644
index 1c0283954289..000000000000
--- a/arch/arm/include/asm/sembuf.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _ASMARM_SEMBUF_H
-#define _ASMARM_SEMBUF_H
-
-/* 
- * The semid64_ds structure for arm architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct semid64_ds {
-        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
-        __kernel_time_t sem_otime;              /* last semop time */
-        unsigned long   __unused1;
-        __kernel_time_t sem_ctime;              /* last change time */
-        unsigned long   __unused2;
-        unsigned long   sem_nsems;              /* no. of semaphores in array */
-        unsigned long   __unused3;
-        unsigned long   __unused4;
-};
-
-#endif /* _ASMARM_SEMBUF_H */
diff --git a/arch/arm/include/asm/serial.h b/arch/arm/include/asm/serial.h
deleted file mode 100644
index ebb049091e26..000000000000
--- a/arch/arm/include/asm/serial.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *  arch/arm/include/asm/serial.h
- *
- *  Copyright (C) 1996 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Changelog:
- *   15-10-1996 RMK     Created
- */
-
-#ifndef __ASM_SERIAL_H
-#define __ASM_SERIAL_H
-
-#define BASE_BAUD       (1843200 / 16)
-
-#endif
diff --git a/arch/arm/include/asm/shmbuf.h b/arch/arm/include/asm/shmbuf.h
deleted file mode 100644
index 2e5c67ba1c97..000000000000
--- a/arch/arm/include/asm/shmbuf.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef _ASMARM_SHMBUF_H
-#define _ASMARM_SHMBUF_H
-
-/* 
- * The shmid64_ds structure for arm architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct shmid64_ds {
-        struct ipc64_perm       shm_perm;       /* operation perms */
-        size_t                  shm_segsz;      /* size of segment (bytes) */
-        __kernel_time_t         shm_atime;      /* last attach time */
-        unsigned long           __unused1;
-        __kernel_time_t         shm_dtime;      /* last detach time */
-        unsigned long           __unused2;
-        __kernel_time_t         shm_ctime;      /* last change time */
-        unsigned long           __unused3;
-        __kernel_pid_t          shm_cpid;       /* pid of creator */
-        __kernel_pid_t          shm_lpid;       /* pid of last operator */
-        unsigned long           shm_nattch;     /* no. of current attaches */
-        unsigned long           __unused4;
-        unsigned long           __unused5;
-};
-
-struct shminfo64 {
-        unsigned long   shmmax;
-        unsigned long   shmmin;
-        unsigned long   shmmni;
-        unsigned long   shmseg;
-        unsigned long   shmall;
-        unsigned long   __unused1;
-        unsigned long   __unused2;
-        unsigned long   __unused3;
-        unsigned long   __unused4;
-};
-
-#endif /* _ASMARM_SHMBUF_H */
diff --git a/arch/arm/include/asm/socket.h b/arch/arm/include/asm/socket.h
deleted file mode 100644
index 6433cadb6ed4..000000000000
--- a/arch/arm/include/asm/socket.h
+++ /dev/null
@@ -1,72 +0,0 @@
-#ifndef _ASMARM_SOCKET_H
-#define _ASMARM_SOCKET_H
-
-#include <asm/sockios.h>
-
-/* For setsockopt(2) */
-#define SOL_SOCKET      1
-
-#define SO_DEBUG        1
-#define SO_REUSEADDR    2
-#define SO_TYPE         3
-#define SO_ERROR        4
-#define SO_DONTROUTE    5
-#define SO_BROADCAST    6
-#define SO_SNDBUF       7
-#define SO_RCVBUF       8
-#define SO_SNDBUFFORCE  32
-#define SO_RCVBUFFORCE  33
-#define SO_KEEPALIVE    9
-#define SO_OOBINLINE    10
-#define SO_NO_CHECK     11
-#define SO_PRIORITY     12
-#define SO_LINGER       13
-#define SO_BSDCOMPAT    14
-/* To add :#define SO_REUSEPORT 15 */
-#define SO_PASSCRED     16
-#define SO_PEERCRED     17
-#define SO_RCVLOWAT     18
-#define SO_SNDLOWAT     19
-#define SO_RCVTIMEO     20
-#define SO_SNDTIMEO     21
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION              22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
-#define SO_SECURITY_ENCRYPTION_NETWORK          24
-
-#define SO_BINDTODEVICE 25
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER        26
-#define SO_DETACH_FILTER        27
-
-#define SO_PEERNAME             28
-#define SO_TIMESTAMP            29
-#define SCM_TIMESTAMP           SO_TIMESTAMP
-
-#define SO_ACCEPTCONN           30
-
-#define SO_PEERSEC              31
-#define SO_PASSSEC              34
-#define SO_TIMESTAMPNS          35
-#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
-
-#define SO_MARK                 36
-
-#define SO_TIMESTAMPING         37
-#define SCM_TIMESTAMPING        SO_TIMESTAMPING
-
-#define SO_PROTOCOL             38
-#define SO_DOMAIN               39
-
-#define SO_RXQ_OVFL             40
-
-#define SO_WIFI_STATUS          41
-#define SCM_WIFI_STATUS         SO_WIFI_STATUS
-#define SO_PEEK_OFF             42
-
-/* Instruct lower device to use last 4-bytes of skb data as FCS */
-#define SO_NOFCS                43
-
-#endif /* _ASM_SOCKET_H */
diff --git a/arch/arm/include/asm/sockios.h b/arch/arm/include/asm/sockios.h
deleted file mode 100644
index a2588a2512df..000000000000
--- a/arch/arm/include/asm/sockios.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ARCH_ARM_SOCKIOS_H
-#define __ARCH_ARM_SOCKIOS_H
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN       0x8901
-#define SIOCSPGRP       0x8902
-#define FIOGETOWN       0x8903
-#define SIOCGPGRP       0x8904
-#define SIOCATMARK      0x8905
-#define SIOCGSTAMP      0x8906          /* Get stamp (timeval) */
-#define SIOCGSTAMPNS    0x8907          /* Get stamp (timespec) */
-
-#endif
diff --git a/arch/arm/include/asm/sync_bitops.h b/arch/arm/include/asm/sync_bitops.h
new file mode 100644
index 000000000000..63479eecbf76
--- /dev/null
+++ b/arch/arm/include/asm/sync_bitops.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_SYNC_BITOPS_H__
+#define __ASM_SYNC_BITOPS_H__
+
+#include <asm/bitops.h>
+#include <asm/system.h>
+
+/* sync_bitops functions are equivalent to the SMP implementation of the
+ * original functions, independently from CONFIG_SMP being defined.
+ *
+ * We need them because _set_bit etc are not SMP safe if !CONFIG_SMP. But
+ * under Xen you might be communicating with a completely external entity
+ * who might be on another CPU (e.g. two uniprocessor guests communicating
+ * via event channels and grant tables). So we need a variant of the bit
+ * ops which are SMP safe even on a UP kernel.
+ */
+
+#define sync_set_bit(nr, p)             _set_bit(nr, p)
+#define sync_clear_bit(nr, p)           _clear_bit(nr, p)
+#define sync_change_bit(nr, p)          _change_bit(nr, p)
+#define sync_test_and_set_bit(nr, p)    _test_and_set_bit(nr, p)
+#define sync_test_and_clear_bit(nr, p)  _test_and_clear_bit(nr, p)
+#define sync_test_and_change_bit(nr, p) _test_and_change_bit(nr, p)
+#define sync_test_bit(nr, addr)         test_bit(nr, addr)
+#define sync_cmpxchg                    cmpxchg
+
+
+#endif
diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h
index c334a23ddf75..9fdded6b1089 100644
--- a/arch/arm/include/asm/syscall.h
+++ b/arch/arm/include/asm/syscall.h
@@ -8,6 +8,11 @@
 #define _ASM_ARM_SYSCALL_H
 
 #include <linux/err.h>
+#include <linux/sched.h>
+
+#include <asm/unistd.h>
+
+#define NR_syscalls (__NR_syscalls)
 
 extern const unsigned long sys_call_table[];
 
diff --git a/arch/arm/include/asm/termbits.h b/arch/arm/include/asm/termbits.h
deleted file mode 100644
index 704135d28d1d..000000000000
--- a/arch/arm/include/asm/termbits.h
+++ /dev/null
@@ -1,198 +0,0 @@
-#ifndef __ASM_ARM_TERMBITS_H
-#define __ASM_ARM_TERMBITS_H
-
-typedef unsigned char   cc_t;
-typedef unsigned int    speed_t;
-typedef unsigned int    tcflag_t;
-
-#define NCCS 19
-struct termios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-};
-
-struct termios2 {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-
-struct ktermios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-
-/* c_iflag bits */
-#define IGNBRK  0000001
-#define BRKINT  0000002
-#define IGNPAR  0000004
-#define PARMRK  0000010
-#define INPCK   0000020
-#define ISTRIP  0000040
-#define INLCR   0000100
-#define IGNCR   0000200
-#define ICRNL   0000400
-#define IUCLC   0001000
-#define IXON    0002000
-#define IXANY   0004000
-#define IXOFF   0010000
-#define IMAXBEL 0020000
-#define IUTF8   0040000
-
-/* c_oflag bits */
-#define OPOST   0000001
-#define OLCUC   0000002
-#define ONLCR   0000004
-#define OCRNL   0000010
-#define ONOCR   0000020
-#define ONLRET  0000040
-#define OFILL   0000100
-#define OFDEL   0000200
-#define NLDLY   0000400
-#define   NL0   0000000
-#define   NL1   0000400
-#define CRDLY   0003000
-#define   CR0   0000000
-#define   CR1   0001000
-#define   CR2   0002000
-#define   CR3   0003000
-#define TABDLY  0014000
-#define   TAB0  0000000
-#define   TAB1  0004000
-#define   TAB2  0010000
-#define   TAB3  0014000
-#define   XTABS 0014000
-#define BSDLY   0020000
-#define   BS0   0000000
-#define   BS1   0020000
-#define VTDLY   0040000
-#define   VT0   0000000
-#define   VT1   0040000
-#define FFDLY   0100000
-#define   FF0   0000000
-#define   FF1   0100000
-
-/* c_cflag bit meaning */
-#define CBAUD   0010017
-#define  B0     0000000         /* hang up */
-#define  B50    0000001
-#define  B75    0000002
-#define  B110   0000003
-#define  B134   0000004
-#define  B150   0000005
-#define  B200   0000006
-#define  B300   0000007
-#define  B600   0000010
-#define  B1200  0000011
-#define  B1800  0000012
-#define  B2400  0000013
-#define  B4800  0000014
-#define  B9600  0000015
-#define  B19200 0000016
-#define  B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE   0000060
-#define   CS5   0000000
-#define   CS6   0000020
-#define   CS7   0000040
-#define   CS8   0000060
-#define CSTOPB  0000100
-#define CREAD   0000200
-#define PARENB  0000400
-#define PARODD  0001000
-#define HUPCL   0002000
-#define CLOCAL  0004000
-#define CBAUDEX 0010000
-#define    BOTHER 0010000
-#define    B57600 0010001
-#define   B115200 0010002
-#define   B230400 0010003
-#define   B460800 0010004
-#define   B500000 0010005
-#define   B576000 0010006
-#define   B921600 0010007
-#define  B1000000 0010010
-#define  B1152000 0010011
-#define  B1500000 0010012
-#define  B2000000 0010013
-#define  B2500000 0010014
-#define  B3000000 0010015
-#define  B3500000 0010016
-#define  B4000000 0010017
-#define CIBAUD    002003600000          /* input baud rate */
-#define CMSPAR    010000000000          /* mark or space (stick) parity */
-#define CRTSCTS   020000000000          /* flow control */
-
-#define IBSHIFT    16
-
-/* c_lflag bits */
-#define ISIG    0000001
-#define ICANON  0000002
-#define XCASE   0000004
-#define ECHO    0000010
-#define ECHOE   0000020
-#define ECHOK   0000040
-#define ECHONL  0000100
-#define NOFLSH  0000200
-#define TOSTOP  0000400
-#define ECHOCTL 0001000
-#define ECHOPRT 0002000
-#define ECHOKE  0004000
-#define FLUSHO  0010000
-#define PENDIN  0040000
-#define IEXTEN  0100000
-#define EXTPROC 0200000
-
-/* tcflow() and TCXONC use these */
-#define TCOOFF          0
-#define TCOON           1
-#define TCIOFF          2
-#define TCION           3
-
-/* tcflush() and TCFLSH use these */
-#define TCIFLUSH        0
-#define TCOFLUSH        1
-#define TCIOFLUSH       2
-
-/* tcsetattr uses these */
-#define TCSANOW         0
-#define TCSADRAIN       1
-#define TCSAFLUSH       2
-
-#endif  /* __ASM_ARM_TERMBITS_H */
diff --git a/arch/arm/include/asm/termios.h b/arch/arm/include/asm/termios.h
deleted file mode 100644
index 293e3f1bc3f2..000000000000
--- a/arch/arm/include/asm/termios.h
+++ /dev/null
@@ -1,92 +0,0 @@
-#ifndef __ASM_ARM_TERMIOS_H
-#define __ASM_ARM_TERMIOS_H
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-
-struct winsize {
-        unsigned short ws_row;
-        unsigned short ws_col;
-        unsigned short ws_xpixel;
-        unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
-        unsigned short c_iflag;         /* input mode flags */
-        unsigned short c_oflag;         /* output mode flags */
-        unsigned short c_cflag;         /* control mode flags */
-        unsigned short c_lflag;         /* local mode flags */
-        unsigned char c_line;           /* line discipline */
-        unsigned char c_cc[NCC];        /* control characters */
-};
-
-#ifdef __KERNEL__
-/*      intr=^C         quit=^|         erase=del       kill=^U
-        eof=^D          vtime=\0        vmin=\1         sxtc=\0
-        start=^Q        stop=^S         susp=^Z         eol=\0
-        reprint=^R      discard=^U      werase=^W       lnext=^V
-        eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-#endif
-
-/* modem lines */
-#define TIOCM_LE        0x001
-#define TIOCM_DTR       0x002
-#define TIOCM_RTS       0x004
-#define TIOCM_ST        0x008
-#define TIOCM_SR        0x010
-#define TIOCM_CTS       0x020
-#define TIOCM_CAR       0x040
-#define TIOCM_RNG       0x080
-#define TIOCM_DSR       0x100
-#define TIOCM_CD        TIOCM_CAR
-#define TIOCM_RI        TIOCM_RNG
-#define TIOCM_OUT1      0x2000
-#define TIOCM_OUT2      0x4000
-#define TIOCM_LOOP      0x8000
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-
-#ifdef __KERNEL__
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) {              \
-        unsigned short __tmp;                                   \
-        get_user(__tmp,&(termio)->x);                           \
-        *(unsigned short *) &(termios)->x = __tmp;              \
-}
-
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
-        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
-        put_user((termios)->c_iflag, &(termio)->c_iflag); \
-        put_user((termios)->c_oflag, &(termio)->c_oflag); \
-        put_user((termios)->c_cflag, &(termio)->c_cflag); \
-        put_user((termios)->c_lflag, &(termio)->c_lflag); \
-        put_user((termios)->c_line,  &(termio)->c_line); \
-        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
-#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
-
-#endif  /* __KERNEL__ */
-
-#endif  /* __ASM_ARM_TERMIOS_H */
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index af7b0bda3355..f71cdab18b87 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -59,7 +59,9 @@ struct thread_info {
         __u32                   syscall;        /* syscall number */
         __u8                    used_cp[16];    /* thread used copro */
         unsigned long           tp_value;
+#ifdef CONFIG_CRUNCH
         struct crunch_state     crunchstate;
+#endif
         union fp_state          fpstate __attribute__((aligned(8)));
         union vfp_state         vfpstate;
 #ifdef CONFIG_ARM_THUMBEE
@@ -148,6 +150,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define TIF_NOTIFY_RESUME       2       /* callback before returning to user */
 #define TIF_SYSCALL_TRACE       8
 #define TIF_SYSCALL_AUDIT       9
+#define TIF_SYSCALL_TRACEPOINT  10
 #define TIF_POLLING_NRFLAG      16
 #define TIF_USING_IWMMXT        17
 #define TIF_MEMDIE              18      /* is terminating due to OOM killer */
@@ -160,12 +163,13 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
 #define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
 #define _TIF_SYSCALL_AUDIT      (1 << TIF_SYSCALL_AUDIT)
+#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT)
 #define _TIF_POLLING_NRFLAG     (1 << TIF_POLLING_NRFLAG)
 #define _TIF_USING_IWMMXT       (1 << TIF_USING_IWMMXT)
 #define _TIF_SECCOMP            (1 << TIF_SECCOMP)
 
 /* Checks for any syscall work in entry-common.S */
-#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
+#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
 
 /*
  * Change these and you break ASM code in entry-common.S
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
index 963342acebb7..83f2aa83899c 100644
--- a/arch/arm/include/asm/timex.h
+++ b/arch/arm/include/asm/timex.h
@@ -12,7 +12,6 @@
 #ifndef _ASMARM_TIMEX_H
 #define _ASMARM_TIMEX_H
 
-#include <asm/arch_timer.h>
 #ifdef CONFIG_ARCH_MULTIPLATFORM
 #define CLOCK_TICK_RATE 1000000
 #else
@@ -20,11 +19,6 @@
 #endif
 
 typedef unsigned long cycles_t;
-
-#ifdef ARCH_HAS_READ_CURRENT_TIMER
 #define get_cycles()    ({ cycles_t c; read_current_timer(&c) ? 0 : c; })
-#else
-#define get_cycles()    (0)
-#endif
 
 #endif
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
deleted file mode 100644
index 28beab917ffc..000000000000
--- a/arch/arm/include/asm/types.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __ASM_ARM_TYPES_H
-#define __ASM_ARM_TYPES_H
-
-#include <asm-generic/int-ll64.h>
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-#define BITS_PER_LONG 32
-
-#endif /* __KERNEL__ */
-
-#endif
-
diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h
deleted file mode 100644
index 44593a894903..000000000000
--- a/arch/arm/include/asm/unaligned.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _ASM_ARM_UNALIGNED_H
-#define _ASM_ARM_UNALIGNED_H
-
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-/*
- * Select endianness
- */
-#ifndef __ARMEB__
-#define get_unaligned   __get_unaligned_le
-#define put_unaligned   __put_unaligned_le
-#else
-#define get_unaligned   __get_unaligned_be
-#define put_unaligned   __put_unaligned_be
-#endif
-
-#endif /* _ASM_ARM_UNALIGNED_H */
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 2fde5fd1acce..d9ff5cc3a506 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -407,6 +407,14 @@
                                         /* 378 for kcmp */
 
 /*
+ * This may need to be greater than __NR_last_syscall+1 in order to
+ * account for the padding in the syscall table
+ */
+#ifdef __KERNEL__
+#define __NR_syscalls  (380)
+#endif /* __KERNEL__ */
+
+/*
  * The following SWIs are ARM private.
  */
 #define __ARM_NR_BASE                   (__NR_SYSCALL_BASE+0x0f0000)
diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h
new file mode 100644
index 000000000000..94b4e9020b02
--- /dev/null
+++ b/arch/arm/include/asm/xen/events.h
@@ -0,0 +1,18 @@
+#ifndef _ASM_ARM_XEN_EVENTS_H
+#define _ASM_ARM_XEN_EVENTS_H
+
+#include <asm/ptrace.h>
+
+enum ipi_vector {
+        XEN_PLACEHOLDER_VECTOR,
+
+        /* Xen IPIs go here */
+        XEN_NR_IPIS,
+};
+
+static inline int xen_irqs_disabled(struct pt_regs *regs)
+{
+        return raw_irqs_disabled_flags(regs->ARM_cpsr);
+}
+
+#endif /* _ASM_ARM_XEN_EVENTS_H */
diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h
new file mode 100644
index 000000000000..8a823253d775
--- /dev/null
+++ b/arch/arm/include/asm/xen/hypercall.h
@@ -0,0 +1,69 @@
+/******************************************************************************
+ * hypercall.h
+ *
+ * Linux-specific hypervisor handling.
+ *
+ * Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Citrix, 2012
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef _ASM_ARM_XEN_HYPERCALL_H
+#define _ASM_ARM_XEN_HYPERCALL_H
+
+#include <xen/interface/xen.h>
+
+long privcmd_call(unsigned call, unsigned long a1,
+                unsigned long a2, unsigned long a3,
+                unsigned long a4, unsigned long a5);
+int HYPERVISOR_xen_version(int cmd, void *arg);
+int HYPERVISOR_console_io(int cmd, int count, char *str);
+int HYPERVISOR_grant_table_op(unsigned int cmd, void *uop, unsigned int count);
+int HYPERVISOR_sched_op(int cmd, void *arg);
+int HYPERVISOR_event_channel_op(int cmd, void *arg);
+unsigned long HYPERVISOR_hvm_op(int op, void *arg);
+int HYPERVISOR_memory_op(unsigned int cmd, void *arg);
+int HYPERVISOR_physdev_op(int cmd, void *arg);
+
+static inline void
+MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va,
+                        unsigned int new_val, unsigned long flags)
+{
+        BUG();
+}
+
+static inline void
+MULTI_mmu_update(struct multicall_entry *mcl, struct mmu_update *req,
+                 int count, int *success_count, domid_t domid)
+{
+        BUG();
+}
+
+static inline int
+HYPERVISOR_multicall(void *call_list, int nr_calls)
+{
+        BUG();
+}
+#endif /* _ASM_ARM_XEN_HYPERCALL_H */
diff --git a/arch/arm/include/asm/xen/hypervisor.h b/arch/arm/include/asm/xen/hypervisor.h
new file mode 100644
index 000000000000..d7ab99a0c9eb
--- /dev/null
+++ b/arch/arm/include/asm/xen/hypervisor.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_ARM_XEN_HYPERVISOR_H
+#define _ASM_ARM_XEN_HYPERVISOR_H
+
+extern struct shared_info *HYPERVISOR_shared_info;
+extern struct start_info *xen_start_info;
+
+/* Lazy mode for batching updates / context switch */
+enum paravirt_lazy_mode {
+        PARAVIRT_LAZY_NONE,
+        PARAVIRT_LAZY_MMU,
+        PARAVIRT_LAZY_CPU,
+};
+
+static inline enum paravirt_lazy_mode paravirt_get_lazy_mode(void)
+{
+        return PARAVIRT_LAZY_NONE;
+}
+
+#endif /* _ASM_ARM_XEN_HYPERVISOR_H */
diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h
new file mode 100644
index 000000000000..ae05e56dd17d
--- /dev/null
+++ b/arch/arm/include/asm/xen/interface.h
@@ -0,0 +1,73 @@
+/******************************************************************************
+ * Guest OS interface to ARM Xen.
+ *
+ * Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Citrix, 2012
+ */
+
+#ifndef _ASM_ARM_XEN_INTERFACE_H
+#define _ASM_ARM_XEN_INTERFACE_H
+
+#include <linux/types.h>
+
+#define uint64_aligned_t uint64_t __attribute__((aligned(8)))
+
+#define __DEFINE_GUEST_HANDLE(name, type) \
+        typedef struct { union { type *p; uint64_aligned_t q; }; }  \
+        __guest_handle_ ## name
+
+#define DEFINE_GUEST_HANDLE_STRUCT(name) \
+        __DEFINE_GUEST_HANDLE(name, struct name)
+#define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name)
+#define GUEST_HANDLE(name)        __guest_handle_ ## name
+
+#define set_xen_guest_handle(hnd, val)                  \
+        do {                                            \
+                if (sizeof(hnd) == 8)                   \
+                        *(uint64_t *)&(hnd) = 0;        \
+                (hnd).p = val;                          \
+        } while (0)
+
+#ifndef __ASSEMBLY__
+/* Explicitly size integers that represent pfns in the interface with
+ * Xen so that we can have one ABI that works for 32 and 64 bit guests. */
+typedef uint64_t xen_pfn_t;
+typedef uint64_t xen_ulong_t;
+/* Guest handles for primitive C types. */
+__DEFINE_GUEST_HANDLE(uchar, unsigned char);
+__DEFINE_GUEST_HANDLE(uint,  unsigned int);
+__DEFINE_GUEST_HANDLE(ulong, unsigned long);
+DEFINE_GUEST_HANDLE(char);
+DEFINE_GUEST_HANDLE(int);
+DEFINE_GUEST_HANDLE(long);
+DEFINE_GUEST_HANDLE(void);
+DEFINE_GUEST_HANDLE(uint64_t);
+DEFINE_GUEST_HANDLE(uint32_t);
+DEFINE_GUEST_HANDLE(xen_pfn_t);
+
+/* Maximum number of virtual CPUs in multi-processor guests. */
+#define MAX_VIRT_CPUS 1
+
+struct arch_vcpu_info { };
+struct arch_shared_info { };
+
+/* TODO: Move pvclock definitions some place arch independent */
+struct pvclock_vcpu_time_info {
+        u32   version;
+        u32   pad0;
+        u64   tsc_timestamp;
+        u64   system_time;
+        u32   tsc_to_system_mul;
+        s8    tsc_shift;
+        u8    flags;
+        u8    pad[2];
+} __attribute__((__packed__)); /* 32 bytes */
+
+/* It is OK to have a 12 bytes struct with no padding because it is packed */
+struct pvclock_wall_clock {
+        u32   version;
+        u32   sec;
+        u32   nsec;
+} __attribute__((__packed__));
+#endif
+
+#endif /* _ASM_ARM_XEN_INTERFACE_H */
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
new file mode 100644
index 000000000000..174202318dff
--- /dev/null
+++ b/arch/arm/include/asm/xen/page.h
@@ -0,0 +1,82 @@
+#ifndef _ASM_ARM_XEN_PAGE_H
+#define _ASM_ARM_XEN_PAGE_H
+
+#include <asm/page.h>
+#include <asm/pgtable.h>
+
+#include <linux/pfn.h>
+#include <linux/types.h>
+
+#include <xen/interface/grant_table.h>
+
+#define pfn_to_mfn(pfn)                 (pfn)
+#define phys_to_machine_mapping_valid   (1)
+#define mfn_to_pfn(mfn)                 (mfn)
+#define mfn_to_virt(m)                  (__va(mfn_to_pfn(m) << PAGE_SHIFT))
+
+#define pte_mfn     pte_pfn
+#define mfn_pte     pfn_pte
+
+/* Xen machine address */
+typedef struct xmaddr {
+        phys_addr_t maddr;
+} xmaddr_t;
+
+/* Xen pseudo-physical address */
+typedef struct xpaddr {
+        phys_addr_t paddr;
+} xpaddr_t;
+
+#define XMADDR(x)       ((xmaddr_t) { .maddr = (x) })
+#define XPADDR(x)       ((xpaddr_t) { .paddr = (x) })
+
+static inline xmaddr_t phys_to_machine(xpaddr_t phys)
+{
+        unsigned offset = phys.paddr & ~PAGE_MASK;
+        return XMADDR(PFN_PHYS(pfn_to_mfn(PFN_DOWN(phys.paddr))) | offset);
+}
+
+static inline xpaddr_t machine_to_phys(xmaddr_t machine)
+{
+        unsigned offset = machine.maddr & ~PAGE_MASK;
+        return XPADDR(PFN_PHYS(mfn_to_pfn(PFN_DOWN(machine.maddr))) | offset);
+}
+/* VIRT <-> MACHINE conversion */
+#define virt_to_machine(v)      (phys_to_machine(XPADDR(__pa(v))))
+#define virt_to_pfn(v)          (PFN_DOWN(__pa(v)))
+#define virt_to_mfn(v)          (pfn_to_mfn(virt_to_pfn(v)))
+#define mfn_to_virt(m)          (__va(mfn_to_pfn(m) << PAGE_SHIFT))
+
+static inline xmaddr_t arbitrary_virt_to_machine(void *vaddr)
+{
+        /* TODO: assuming it is mapped in the kernel 1:1 */
+        return virt_to_machine(vaddr);
+}
+
+/* TODO: this shouldn't be here but it is because the frontend drivers
+ * are using it (its rolled in headers) even though we won't hit the code path.
+ * So for right now just punt with this.
+ */
+static inline pte_t *lookup_address(unsigned long address, unsigned int *level)
+{
+        BUG();
+        return NULL;
+}
+
+static inline int m2p_add_override(unsigned long mfn, struct page *page,
+                struct gnttab_map_grant_ref *kmap_op)
+{
+        return 0;
+}
+
+static inline int m2p_remove_override(struct page *page, bool clear_pte)
+{
+        return 0;
+}
+
+static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
+{
+        BUG();
+        return false;
+}
+#endif /* _ASM_ARM_XEN_PAGE_H */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index d81f3a6d9ad8..5dfef9d97ed9 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -19,7 +19,9 @@ obj-y		:= elf.o entry-armv.o entry-common.o irq.o opcodes.o \
                    process.o ptrace.o return_address.o sched_clock.o \
                    setup.o signal.o stacktrace.o sys_arm.o time.o traps.o
 
-obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
+obj-$(CONFIG_ATAGS)             += atags_parse.o
+obj-$(CONFIG_ATAGS_PROC)        += atags_proc.o
+obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o
 
 obj-$(CONFIG_OC_ETM)            += etm.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
@@ -51,7 +53,6 @@ test-kprobes-objs		+= kprobes-test-thumb.o
 else
 test-kprobes-objs               += kprobes-test-arm.o
 endif
-obj-$(CONFIG_ATAGS_PROC)        += atags.o
 obj-$(CONFIG_OABI_COMPAT)       += sys_oabi-compat.o
 obj-$(CONFIG_ARM_THUMBEE)       += thumbee.o
 obj-$(CONFIG_KGDB)              += kgdb.o
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index cf258807160d..c8ef20747ee7 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -21,18 +21,28 @@
 #include <linux/io.h>
 
 #include <asm/cputype.h>
+#include <asm/delay.h>
 #include <asm/localtimer.h>
 #include <asm/arch_timer.h>
 #include <asm/system_info.h>
 #include <asm/sched_clock.h>
 
 static unsigned long arch_timer_rate;
-static int arch_timer_ppi;
-static int arch_timer_ppi2;
+
+enum ppi_nr {
+        PHYS_SECURE_PPI,
+        PHYS_NONSECURE_PPI,
+        VIRT_PPI,
+        HYP_PPI,
+        MAX_TIMER_PPI
+};
+
+static int arch_timer_ppi[MAX_TIMER_PPI];
 
 static struct clock_event_device __percpu **arch_timer_evt;
+static struct delay_timer arch_delay_timer;
 
-extern void init_current_timer_delay(unsigned long freq);
+static bool arch_timer_use_virtual = true;
 
 /*
  * Architected system timer support.
@@ -46,50 +56,104 @@ extern void init_current_timer_delay(unsigned long freq);
 #define ARCH_TIMER_REG_FREQ             1
 #define ARCH_TIMER_REG_TVAL             2
 
-static void arch_timer_reg_write(int reg, u32 val)
+#define ARCH_TIMER_PHYS_ACCESS          0
+#define ARCH_TIMER_VIRT_ACCESS          1
+
+/*
+ * These register accessors are marked inline so the compiler can
+ * nicely work out which register we want, and chuck away the rest of
+ * the code. At least it does so with a recent GCC (4.6.3).
+ */
+static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
 {
-        switch (reg) {
-        case ARCH_TIMER_REG_CTRL:
-                asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
-                break;
-        case ARCH_TIMER_REG_TVAL:
-                asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
-                break;
+        if (access == ARCH_TIMER_PHYS_ACCESS) {
+                switch (reg) {
+                case ARCH_TIMER_REG_CTRL:
+                        asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+                        break;
+                case ARCH_TIMER_REG_TVAL:
+                        asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
+                        break;
+                }
+        }
+
+        if (access == ARCH_TIMER_VIRT_ACCESS) {
+                switch (reg) {
+                case ARCH_TIMER_REG_CTRL:
+                        asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
+                        break;
+                case ARCH_TIMER_REG_TVAL:
+                        asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
+                        break;
+                }
         }
 
         isb();
 }
 
-static u32 arch_timer_reg_read(int reg)
+static inline u32 arch_timer_reg_read(const int access, const int reg)
 {
-        u32 val;
+        u32 val = 0;
+
+        if (access == ARCH_TIMER_PHYS_ACCESS) {
+                switch (reg) {
+                case ARCH_TIMER_REG_CTRL:
+                        asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+                        break;
+                case ARCH_TIMER_REG_TVAL:
+                        asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
+                        break;
+                case ARCH_TIMER_REG_FREQ:
+                        asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
+                        break;
+                }
+        }
 
-        switch (reg) {
-        case ARCH_TIMER_REG_CTRL:
-                asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
-                break;
-        case ARCH_TIMER_REG_FREQ:
-                asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
-                break;
-        case ARCH_TIMER_REG_TVAL:
-                asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
-                break;
-        default:
-                BUG();
+        if (access == ARCH_TIMER_VIRT_ACCESS) {
+                switch (reg) {
+                case ARCH_TIMER_REG_CTRL:
+                        asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
+                        break;
+                case ARCH_TIMER_REG_TVAL:
+                        asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
+                        break;
+                }
         }
 
         return val;
 }
 
-static irqreturn_t arch_timer_handler(int irq, void *dev_id)
+static inline cycle_t arch_timer_counter_read(const int access)
 {
-        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
-        unsigned long ctrl;
+        cycle_t cval = 0;
+
+        if (access == ARCH_TIMER_PHYS_ACCESS)
+                asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
+
+        if (access == ARCH_TIMER_VIRT_ACCESS)
+                asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
+
+        return cval;
+}
+
+static inline cycle_t arch_counter_get_cntpct(void)
+{
+        return arch_timer_counter_read(ARCH_TIMER_PHYS_ACCESS);
+}
 
-        ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+static inline cycle_t arch_counter_get_cntvct(void)
+{
+        return arch_timer_counter_read(ARCH_TIMER_VIRT_ACCESS);
+}
+
+static irqreturn_t inline timer_handler(const int access,
+                                        struct clock_event_device *evt)
+{
+        unsigned long ctrl;
+        ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
         if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
                 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
-                arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+                arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
                 evt->event_handler(evt);
                 return IRQ_HANDLED;
         }
@@ -97,63 +161,100 @@ static irqreturn_t arch_timer_handler(int irq, void *dev_id)
         return IRQ_NONE;
 }
 
-static void arch_timer_disable(void)
+static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
 {
-        unsigned long ctrl;
+        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
 
-        ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
-        ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
-        arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+        return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
 }
 
-static void arch_timer_set_mode(enum clock_event_mode mode,
-                                struct clock_event_device *clk)
+static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
 {
+        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+
+        return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
+}
+
+static inline void timer_set_mode(const int access, int mode)
+{
+        unsigned long ctrl;
         switch (mode) {
         case CLOCK_EVT_MODE_UNUSED:
         case CLOCK_EVT_MODE_SHUTDOWN:
-                arch_timer_disable();
+                ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
+                ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
+                arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
                 break;
         default:
                 break;
         }
 }
 
-static int arch_timer_set_next_event(unsigned long evt,
-                                     struct clock_event_device *unused)
+static void arch_timer_set_mode_virt(enum clock_event_mode mode,
+                                     struct clock_event_device *clk)
 {
-        unsigned long ctrl;
+        timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode);
+}
 
-        ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+static void arch_timer_set_mode_phys(enum clock_event_mode mode,
+                                     struct clock_event_device *clk)
+{
+        timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode);
+}
+
+static inline void set_next_event(const int access, unsigned long evt)
+{
+        unsigned long ctrl;
+        ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
         ctrl |= ARCH_TIMER_CTRL_ENABLE;
         ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
+        arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
+        arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
+}
 
-        arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
-        arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+static int arch_timer_set_next_event_virt(unsigned long evt,
+                                          struct clock_event_device *unused)
+{
+        set_next_event(ARCH_TIMER_VIRT_ACCESS, evt);
+        return 0;
+}
 
+static int arch_timer_set_next_event_phys(unsigned long evt,
+                                          struct clock_event_device *unused)
+{
+        set_next_event(ARCH_TIMER_PHYS_ACCESS, evt);
         return 0;
 }
 
 static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
 {
-        /* Be safe... */
-        arch_timer_disable();
-
         clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
         clk->name = "arch_sys_timer";
         clk->rating = 450;
-        clk->set_mode = arch_timer_set_mode;
-        clk->set_next_event = arch_timer_set_next_event;
-        clk->irq = arch_timer_ppi;
+        if (arch_timer_use_virtual) {
+                clk->irq = arch_timer_ppi[VIRT_PPI];
+                clk->set_mode = arch_timer_set_mode_virt;
+                clk->set_next_event = arch_timer_set_next_event_virt;
+        } else {
+                clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
+                clk->set_mode = arch_timer_set_mode_phys;
+                clk->set_next_event = arch_timer_set_next_event_phys;
+        }
+
+        clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, NULL);
 
         clockevents_config_and_register(clk, arch_timer_rate,
                                         0xf, 0x7fffffff);
 
         *__this_cpu_ptr(arch_timer_evt) = clk;
 
-        enable_percpu_irq(clk->irq, 0);
-        if (arch_timer_ppi2)
-                enable_percpu_irq(arch_timer_ppi2, 0);
+        if (arch_timer_use_virtual)
+                enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
+        else {
+                enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
+                if (arch_timer_ppi[PHYS_NONSECURE_PPI])
+                        enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
+        }
 
         return 0;
 }
@@ -173,8 +274,8 @@ static int arch_timer_available(void)
                 return -ENXIO;
 
         if (arch_timer_rate == 0) {
-                arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0);
-                freq = arch_timer_reg_read(ARCH_TIMER_REG_FREQ);
+                freq = arch_timer_reg_read(ARCH_TIMER_PHYS_ACCESS,
+                                           ARCH_TIMER_REG_FREQ);
 
                 /* Check the timer frequency. */
                 if (freq == 0) {
@@ -185,52 +286,57 @@ static int arch_timer_available(void)
                 arch_timer_rate = freq;
         }
 
-        pr_info_once("Architected local timer running at %lu.%02luMHz.\n",
-                     arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100);
+        pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
+                     arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100,
+                     arch_timer_use_virtual ? "virt" : "phys");
         return 0;
 }
 
-static inline cycle_t arch_counter_get_cntpct(void)
+static u32 notrace arch_counter_get_cntpct32(void)
 {
-        u32 cvall, cvalh;
-
-        asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+        cycle_t cnt = arch_counter_get_cntpct();
 
-        return ((cycle_t) cvalh << 32) | cvall;
-}
-
-static inline cycle_t arch_counter_get_cntvct(void)
-{
-        u32 cvall, cvalh;
-
-        asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
-
-        return ((cycle_t) cvalh << 32) | cvall;
+        /*
+         * The sched_clock infrastructure only knows about counters
+         * with at most 32bits. Forget about the upper 24 bits for the
+         * time being...
+         */
+        return (u32)cnt;
 }
 
 static u32 notrace arch_counter_get_cntvct32(void)
 {
-        cycle_t cntvct = arch_counter_get_cntvct();
+        cycle_t cnt = arch_counter_get_cntvct();
 
         /*
          * The sched_clock infrastructure only knows about counters
          * with at most 32bits. Forget about the upper 24 bits for the
          * time being...
          */
-        return (u32)(cntvct & (u32)~0);
+        return (u32)cnt;
 }
 
 static cycle_t arch_counter_read(struct clocksource *cs)
 {
+        /*
+         * Always use the physical counter for the clocksource.
+         * CNTHCTL.PL1PCTEN must be set to 1.
+         */
         return arch_counter_get_cntpct();
 }
 
-int read_current_timer(unsigned long *timer_val)
+static unsigned long arch_timer_read_current_timer(void)
 {
-        if (!arch_timer_rate)
-                return -ENXIO;
-        *timer_val = arch_counter_get_cntpct();
-        return 0;
+        return arch_counter_get_cntpct();
+}
+
+static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
+{
+        /*
+         * Always use the physical counter for the clocksource.
+         * CNTHCTL.PL1PCTEN must be set to 1.
+         */
+        return arch_counter_get_cntpct();
 }
 
 static struct clocksource clocksource_counter = {
@@ -241,14 +347,32 @@ static struct clocksource clocksource_counter = {
         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static struct cyclecounter cyclecounter = {
+        .read   = arch_counter_read_cc,
+        .mask   = CLOCKSOURCE_MASK(56),
+};
+
+static struct timecounter timecounter;
+
+struct timecounter *arch_timer_get_timecounter(void)
+{
+        return &timecounter;
+}
+
 static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
 {
         pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
                  clk->irq, smp_processor_id());
-        disable_percpu_irq(clk->irq);
-        if (arch_timer_ppi2)
-                disable_percpu_irq(arch_timer_ppi2);
-        arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
+
+        if (arch_timer_use_virtual)
+                disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
+        else {
+                disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
+                if (arch_timer_ppi[PHYS_NONSECURE_PPI])
+                        disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
+        }
+
+        clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
 }
 
 static struct local_timer_ops arch_timer_ops __cpuinitdata = {
@@ -261,36 +385,48 @@ static struct clock_event_device arch_timer_global_evt;
 static int __init arch_timer_register(void)
 {
         int err;
+        int ppi;
 
         err = arch_timer_available();
         if (err)
-                return err;
+                goto out;
 
         arch_timer_evt = alloc_percpu(struct clock_event_device *);
-        if (!arch_timer_evt)
-                return -ENOMEM;
+        if (!arch_timer_evt) {
+                err = -ENOMEM;
+                goto out;
+        }
 
         clocksource_register_hz(&clocksource_counter, arch_timer_rate);
+        cyclecounter.mult = clocksource_counter.mult;
+        cyclecounter.shift = clocksource_counter.shift;
+        timecounter_init(&timecounter, &cyclecounter,
+                         arch_counter_get_cntpct());
+
+        if (arch_timer_use_virtual) {
+                ppi = arch_timer_ppi[VIRT_PPI];
+                err = request_percpu_irq(ppi, arch_timer_handler_virt,
+                                         "arch_timer", arch_timer_evt);
+        } else {
+                ppi = arch_timer_ppi[PHYS_SECURE_PPI];
+                err = request_percpu_irq(ppi, arch_timer_handler_phys,
+                                         "arch_timer", arch_timer_evt);
+                if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
+                        ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
+                        err = request_percpu_irq(ppi, arch_timer_handler_phys,
+                                                 "arch_timer", arch_timer_evt);
+                        if (err)
+                                free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
+                                                arch_timer_evt);
+                }
+        }
 
-        err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
-                                 "arch_timer", arch_timer_evt);
         if (err) {
                 pr_err("arch_timer: can't register interrupt %d (%d)\n",
-                       arch_timer_ppi, err);
+                       ppi, err);
                 goto out_free;
         }
 
-        if (arch_timer_ppi2) {
-                err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
-                                         "arch_timer", arch_timer_evt);
-                if (err) {
-                        pr_err("arch_timer: can't register interrupt %d (%d)\n",
-                               arch_timer_ppi2, err);
-                        arch_timer_ppi2 = 0;
-                        goto out_free_irq;
-                }
-        }
-
         err = local_timer_register(&arch_timer_ops);
         if (err) {
                 /*
@@ -302,21 +438,29 @@ static int __init arch_timer_register(void)
                 arch_timer_global_evt.cpumask = cpumask_of(0);
                 err = arch_timer_setup(&arch_timer_global_evt);
         }
-
         if (err)
                 goto out_free_irq;
 
-        init_current_timer_delay(arch_timer_rate);
+        /* Use the architected timer for the delay loop. */
+        arch_delay_timer.read_current_timer = &arch_timer_read_current_timer;
+        arch_delay_timer.freq = arch_timer_rate;
+        register_current_timer_delay(&arch_delay_timer);
         return 0;
 
 out_free_irq:
-        free_percpu_irq(arch_timer_ppi, arch_timer_evt);
-        if (arch_timer_ppi2)
-                free_percpu_irq(arch_timer_ppi2, arch_timer_evt);
+        if (arch_timer_use_virtual)
+                free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
+        else {
+                free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
+                                arch_timer_evt);
+                if (arch_timer_ppi[PHYS_NONSECURE_PPI])
+                        free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
+                                        arch_timer_evt);
+        }
 
 out_free:
         free_percpu(arch_timer_evt);
-
+out:
         return err;
 }
 
@@ -329,6 +473,7 @@ int __init arch_timer_of_register(void)
 {
         struct device_node *np;
         u32 freq;
+        int i;
 
         np = of_find_matching_node(NULL, arch_timer_of_match);
         if (!np) {
@@ -340,22 +485,40 @@ int __init arch_timer_of_register(void)
         if (!of_property_read_u32(np, "clock-frequency", &freq))
                 arch_timer_rate = freq;
 
-        arch_timer_ppi = irq_of_parse_and_map(np, 0);
-        arch_timer_ppi2 = irq_of_parse_and_map(np, 1);
-        pr_info("arch_timer: found %s irqs %d %d\n",
-                np->name, arch_timer_ppi, arch_timer_ppi2);
+        for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
+                arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
+
+        /*
+         * If no interrupt provided for virtual timer, we'll have to
+         * stick to the physical timer. It'd better be accessible...
+         */
+        if (!arch_timer_ppi[VIRT_PPI]) {
+                arch_timer_use_virtual = false;
+
+                if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
+                    !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
+                        pr_warn("arch_timer: No interrupt available, giving up\n");
+                        return -EINVAL;
+                }
+        }
 
         return arch_timer_register();
 }
 
 int __init arch_timer_sched_clock_init(void)
 {
+        u32 (*cnt32)(void);
         int err;
 
         err = arch_timer_available();
         if (err)
                 return err;
 
-        setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate);
+        if (arch_timer_use_virtual)
+                cnt32 = arch_counter_get_cntvct32;
+        else
+                cnt32 = arch_counter_get_cntpct32;
+
+        setup_sched_clock(cnt32, 32, arch_timer_rate);
         return 0;
 }
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 1429d8989fb9..c985b481192c 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -59,10 +59,12 @@ int main(void)
   DEFINE(TI_USED_CP,            offsetof(struct thread_info, used_cp));
   DEFINE(TI_TP_VALUE,           offsetof(struct thread_info, tp_value));
   DEFINE(TI_FPSTATE,            offsetof(struct thread_info, fpstate));
+#ifdef CONFIG_VFP
   DEFINE(TI_VFPSTATE,           offsetof(struct thread_info, vfpstate));
 #ifdef CONFIG_SMP
   DEFINE(VFP_CPU,               offsetof(union vfp_state, hard.cpu));
 #endif
+#endif
 #ifdef CONFIG_ARM_THUMBEE
   DEFINE(TI_THUMBEE_STATE,      offsetof(struct thread_info, thumbee_state));
 #endif
diff --git a/arch/arm/kernel/atags.h b/arch/arm/kernel/atags.h
index e5f028d214a1..9edc9692332d 100644
--- a/arch/arm/kernel/atags.h
+++ b/arch/arm/kernel/atags.h
@@ -3,3 +3,17 @@ extern void save_atags(struct tag *tags);
 #else
 static inline void save_atags(struct tag *tags) { }
 #endif
+
+void convert_to_tag_list(struct tag *tags);
+
+#ifdef CONFIG_ATAGS
+struct machine_desc *setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr);
+#else
+static inline struct machine_desc *
+setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr)
+{
+        early_print("no ATAGS support: can't continue\n");
+        while (true);
+        unreachable();
+}
+#endif
diff --git a/arch/arm/kernel/compat.c b/arch/arm/kernel/atags_compat.c
index 925652318b8b..5236ad38f417 100644
--- a/arch/arm/kernel/compat.c
+++ b/arch/arm/kernel/atags_compat.c
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/kernel/compat.c
+ *  linux/arch/arm/kernel/atags_compat.c
  *
  *  Copyright (C) 2001 Russell King
  *
@@ -26,7 +26,7 @@
 
 #include <asm/mach/arch.h>
 
-#include "compat.h"
+#include "atags.h"
 
 /*
  * Usage:
diff --git a/arch/arm/kernel/atags_parse.c b/arch/arm/kernel/atags_parse.c
new file mode 100644
index 000000000000..14512e6931d8
--- /dev/null
+++ b/arch/arm/kernel/atags_parse.c
@@ -0,0 +1,238 @@
+/*
+ * Tag parsing.
+ *
+ * Copyright (C) 1995-2001 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * This is the traditional way of passing data to the kernel at boot time.  Rather
+ * than passing a fixed inflexible structure to the kernel, we pass a list
+ * of variable-sized tags to the kernel.  The first tag must be a ATAG_CORE
+ * tag for the list to be recognised (to distinguish the tagged list from
+ * a param_struct).  The list is terminated with a zero-length tag (this tag
+ * is not parsed in any way).
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/root_dev.h>
+#include <linux/screen_info.h>
+
+#include <asm/setup.h>
+#include <asm/system_info.h>
+#include <asm/page.h>
+#include <asm/mach/arch.h>
+
+#include "atags.h"
+
+static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
+
+#ifndef MEM_SIZE
+#define MEM_SIZE        (16*1024*1024)
+#endif
+
+static struct {
+        struct tag_header hdr1;
+        struct tag_core   core;
+        struct tag_header hdr2;
+        struct tag_mem32  mem;
+        struct tag_header hdr3;
+} default_tags __initdata = {
+        { tag_size(tag_core), ATAG_CORE },
+        { 1, PAGE_SIZE, 0xff },
+        { tag_size(tag_mem32), ATAG_MEM },
+        { MEM_SIZE },
+        { 0, ATAG_NONE }
+};
+
+static int __init parse_tag_core(const struct tag *tag)
+{
+        if (tag->hdr.size > 2) {
+                if ((tag->u.core.flags & 1) == 0)
+                        root_mountflags &= ~MS_RDONLY;
+                ROOT_DEV = old_decode_dev(tag->u.core.rootdev);
+        }
+        return 0;
+}
+
+__tagtable(ATAG_CORE, parse_tag_core);
+
+static int __init parse_tag_mem32(const struct tag *tag)
+{
+        return arm_add_memory(tag->u.mem.start, tag->u.mem.size);
+}
+
+__tagtable(ATAG_MEM, parse_tag_mem32);
+
+#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
+static int __init parse_tag_videotext(const struct tag *tag)
+{
+        screen_info.orig_x            = tag->u.videotext.x;
+        screen_info.orig_y            = tag->u.videotext.y;
+        screen_info.orig_video_page   = tag->u.videotext.video_page;
+        screen_info.orig_video_mode   = tag->u.videotext.video_mode;
+        screen_info.orig_video_cols   = tag->u.videotext.video_cols;
+        screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx;
+        screen_info.orig_video_lines  = tag->u.videotext.video_lines;
+        screen_info.orig_video_isVGA  = tag->u.videotext.video_isvga;
+        screen_info.orig_video_points = tag->u.videotext.video_points;
+        return 0;
+}
+
+__tagtable(ATAG_VIDEOTEXT, parse_tag_videotext);
+#endif
+
+#ifdef CONFIG_BLK_DEV_RAM
+static int __init parse_tag_ramdisk(const struct tag *tag)
+{
+        extern int rd_size, rd_image_start, rd_prompt, rd_doload;
+
+        rd_image_start = tag->u.ramdisk.start;
+        rd_doload = (tag->u.ramdisk.flags & 1) == 0;
+        rd_prompt = (tag->u.ramdisk.flags & 2) == 0;
+
+        if (tag->u.ramdisk.size)
+                rd_size = tag->u.ramdisk.size;
+
+        return 0;
+}
+
+__tagtable(ATAG_RAMDISK, parse_tag_ramdisk);
+#endif
+
+static int __init parse_tag_serialnr(const struct tag *tag)
+{
+        system_serial_low = tag->u.serialnr.low;
+        system_serial_high = tag->u.serialnr.high;
+        return 0;
+}
+
+__tagtable(ATAG_SERIAL, parse_tag_serialnr);
+
+static int __init parse_tag_revision(const struct tag *tag)
+{
+        system_rev = tag->u.revision.rev;
+        return 0;
+}
+
+__tagtable(ATAG_REVISION, parse_tag_revision);
+
+static int __init parse_tag_cmdline(const struct tag *tag)
+{
+#if defined(CONFIG_CMDLINE_EXTEND)
+        strlcat(default_command_line, " ", COMMAND_LINE_SIZE);
+        strlcat(default_command_line, tag->u.cmdline.cmdline,
+                COMMAND_LINE_SIZE);
+#elif defined(CONFIG_CMDLINE_FORCE)
+        pr_warning("Ignoring tag cmdline (using the default kernel command line)\n");
+#else
+        strlcpy(default_command_line, tag->u.cmdline.cmdline,
+                COMMAND_LINE_SIZE);
+#endif
+        return 0;
+}
+
+__tagtable(ATAG_CMDLINE, parse_tag_cmdline);
+
+/*
+ * Scan the tag table for this tag, and call its parse function.
+ * The tag table is built by the linker from all the __tagtable
+ * declarations.
+ */
+static int __init parse_tag(const struct tag *tag)
+{
+        extern struct tagtable __tagtable_begin, __tagtable_end;
+        struct tagtable *t;
+
+        for (t = &__tagtable_begin; t < &__tagtable_end; t++)
+                if (tag->hdr.tag == t->tag) {
+                        t->parse(tag);
+                        break;
+                }
+
+        return t < &__tagtable_end;
+}
+
+/*
+ * Parse all tags in the list, checking both the global and architecture
+ * specific tag tables.
+ */
+static void __init parse_tags(const struct tag *t)
+{
+        for (; t->hdr.size; t = tag_next(t))
+                if (!parse_tag(t))
+                        printk(KERN_WARNING
+                                "Ignoring unrecognised tag 0x%08x\n",
+                                t->hdr.tag);
+}
+
+static void __init squash_mem_tags(struct tag *tag)
+{
+        for (; tag->hdr.size; tag = tag_next(tag))
+                if (tag->hdr.tag == ATAG_MEM)
+                        tag->hdr.tag = ATAG_NONE;
+}
+
+struct machine_desc * __init setup_machine_tags(phys_addr_t __atags_pointer,
+                                                unsigned int machine_nr)
+{
+        struct tag *tags = (struct tag *)&default_tags;
+        struct machine_desc *mdesc = NULL, *p;
+        char *from = default_command_line;
+
+        default_tags.mem.start = PHYS_OFFSET;
+
+        /*
+         * locate machine in the list of supported machines.
+         */
+        for_each_machine_desc(p)
+                if (machine_nr == p->nr) {
+                        printk("Machine: %s\n", p->name);
+                        mdesc = p;
+                        break;
+                }
+
+        if (!mdesc) {
+                early_print("\nError: unrecognized/unsupported machine ID"
+                            " (r1 = 0x%08x).\n\n", machine_nr);
+                dump_machine_table(); /* does not return */
+        }
+
+        if (__atags_pointer)
+                tags = phys_to_virt(__atags_pointer);
+        else if (mdesc->atag_offset)
+                tags = (void *)(PAGE_OFFSET + mdesc->atag_offset);
+
+#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
+        /*
+         * If we have the old style parameters, convert them to
+         * a tag list.
+         */
+        if (tags->hdr.tag != ATAG_CORE)
+                convert_to_tag_list(tags);
+#endif
+        if (tags->hdr.tag != ATAG_CORE) {
+                early_print("Warning: Neither atags nor dtb found\n");
+                tags = (struct tag *)&default_tags;
+        }
+
+        if (mdesc->fixup)
+                mdesc->fixup(tags, &from, &meminfo);
+
+        if (tags->hdr.tag == ATAG_CORE) {
+                if (meminfo.nr_banks != 0)
+                        squash_mem_tags(tags);
+                save_atags(tags);
+                parse_tags(tags);
+        }
+
+        /* parse_early_param needs a boot_command_line */
+        strlcpy(boot_command_line, from, COMMAND_LINE_SIZE);
+
+        return mdesc;
+}
diff --git a/arch/arm/kernel/atags.c b/arch/arm/kernel/atags_proc.c
index 42a1a1415fa6..42a1a1415fa6 100644
--- a/arch/arm/kernel/atags.c
+++ b/arch/arm/kernel/atags_proc.c
diff --git a/arch/arm/kernel/compat.h b/arch/arm/kernel/compat.h
deleted file mode 100644
index 39264ab1b9c6..000000000000
--- a/arch/arm/kernel/compat.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- *  linux/arch/arm/kernel/compat.h
- *
- *  Copyright (C) 2001 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-extern void convert_to_tag_list(struct tag *tags);
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 978eac57e04a..f45987037bf1 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -94,6 +94,15 @@ ENDPROC(ret_from_fork)
         .equ NR_syscalls,0
 #define CALL(x) .equ NR_syscalls,NR_syscalls+1
 #include "calls.S"
+
+/*
+ * Ensure that the system call table is equal to __NR_syscalls,
+ * which is the value the rest of the system sees
+ */
+.ifne NR_syscalls - __NR_syscalls
+.error "__NR_syscalls is not equal to the size of the syscall table"
+.endif
+
 #undef CALL
 #define CALL(x) .long x
 
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index dfcdb9f7c126..e29c3337ca81 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -8,7 +8,9 @@
 #include <linux/reboot.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/memblock.h>
 #include <asm/pgtable.h>
+#include <linux/of_fdt.h>
 #include <asm/pgalloc.h>
 #include <asm/mmu_context.h>
 #include <asm/cacheflush.h>
@@ -32,6 +34,29 @@ static atomic_t waiting_for_crash_ipi;
 
 int machine_kexec_prepare(struct kimage *image)
 {
+        struct kexec_segment *current_segment;
+        __be32 header;
+        int i, err;
+
+        /*
+         * No segment at default ATAGs address. try to locate
+         * a dtb using magic.
+         */
+        for (i = 0; i < image->nr_segments; i++) {
+                current_segment = &image->segment[i];
+
+                err = memblock_is_region_memory(current_segment->mem,
+                                                current_segment->memsz);
+                if (err)
+                        return - EINVAL;
+
+                err = get_user(header, (__be32*)current_segment->buf);
+                if (err)
+                        return err;
+
+                if (be32_to_cpu(header) == OF_DT_HEADER)
+                        kexec_boot_atags = current_segment->mem;
+        }
         return 0;
 }
 
@@ -122,7 +147,9 @@ void machine_kexec(struct kimage *image)
         kexec_start_address = image->start;
         kexec_indirection_page = page_list;
         kexec_mach_type = machine_arch_type;
-        kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET;
+        if (!kexec_boot_atags)
+                kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET;
+
 
         /* copy our kernel relocation code to the control code page */
         memcpy(reboot_code_buffer,
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 3e0fc5f7ed4b..739db3a1b2d2 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -30,6 +30,9 @@
 #include <asm/pgtable.h>
 #include <asm/traps.h>
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/syscalls.h>
+
 #define REG_PC  15
 #define REG_PSR 16
 /*
@@ -918,11 +921,11 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 {
         unsigned long ip;
 
+        current_thread_info()->syscall = scno;
+
         if (!test_thread_flag(TIF_SYSCALL_TRACE))
                 return scno;
 
-        current_thread_info()->syscall = scno;
-
         /*
          * IP is used to denote syscall entry/exit:
          * IP = 0 -> entry, =1 -> exit
@@ -941,15 +944,19 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 
 asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
 {
-        int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER);
+        scno = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER);
+        if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+                trace_sys_enter(regs, scno);
         audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0, regs->ARM_r1,
                             regs->ARM_r2, regs->ARM_r3);
-        return ret;
+        return scno;
 }
 
 asmlinkage int syscall_trace_exit(struct pt_regs *regs, int scno)
 {
-        int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT);
+        scno = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT);
+        if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+                trace_sys_exit(regs, scno);
         audit_syscall_exit(regs);
-        return ret;
+        return scno;
 }
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c
index f4515393248d..e21bac20d90d 100644
--- a/arch/arm/kernel/sched_clock.c
+++ b/arch/arm/kernel/sched_clock.c
@@ -9,6 +9,7 @@
 #include <linux/init.h>
 #include <linux/jiffies.h>
 #include <linux/kernel.h>
+#include <linux/moduleparam.h>
 #include <linux/sched.h>
 #include <linux/syscore_ops.h>
 #include <linux/timer.h>
@@ -27,6 +28,9 @@ struct clock_data {
 
 static void sched_clock_poll(unsigned long wrap_ticks);
 static DEFINE_TIMER(sched_clock_timer, sched_clock_poll, 0, 0);
+static int irqtime = -1;
+
+core_param(irqtime, irqtime, int, 0400);
 
 static struct clock_data cd = {
         .mult   = NSEC_PER_SEC / HZ,
@@ -157,6 +161,10 @@ void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate)
          */
         cd.epoch_ns = 0;
 
+        /* Enable IRQ time accounting if we have a fast enough sched_clock */
+        if (irqtime > 0 || (irqtime == -1 && rate >= 1000000))
+                enable_sched_clock_irqtime();
+
         pr_debug("Registered %pF as sched_clock source\n", read);
 }
 
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 725f9f2a9541..febafa0f552d 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -21,11 +21,9 @@
 #include <linux/init.h>
 #include <linux/kexec.h>
 #include <linux/of_fdt.h>
-#include <linux/root_dev.h>
 #include <linux/cpu.h>
 #include <linux/interrupt.h>
 #include <linux/smp.h>
-#include <linux/fs.h>
 #include <linux/proc_fs.h>
 #include <linux/memblock.h>
 #include <linux/bug.h>
@@ -56,15 +54,9 @@
 #include <asm/unwind.h>
 #include <asm/memblock.h>
 
-#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
-#include "compat.h"
-#endif
 #include "atags.h"
 #include "tcm.h"
 
-#ifndef MEM_SIZE
-#define MEM_SIZE        (16*1024*1024)
-#endif
 
 #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
 char fpe_type[8];
@@ -145,7 +137,6 @@ static const char *machine_name;
 static char __initdata cmd_line[COMMAND_LINE_SIZE];
 struct machine_desc *machine_desc __initdata;
 
-static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
 static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
 #define ENDIANNESS ((char)endian_test.l)
 
@@ -583,21 +574,6 @@ static int __init early_mem(char *p)
 }
 early_param("mem", early_mem);
 
-static void __init
-setup_ramdisk(int doload, int prompt, int image_start, unsigned int rd_sz)
-{
-#ifdef CONFIG_BLK_DEV_RAM
-        extern int rd_size, rd_image_start, rd_prompt, rd_doload;
-
-        rd_image_start = image_start;
-        rd_prompt = prompt;
-        rd_doload = doload;
-
-        if (rd_sz)
-                rd_size = rd_sz;
-#endif
-}
-
 static void __init request_standard_resources(struct machine_desc *mdesc)
 {
         struct memblock_region *region;
@@ -643,35 +619,6 @@ static void __init request_standard_resources(struct machine_desc *mdesc)
                 request_resource(&ioport_resource, &lp2);
 }
 
-/*
- *  Tag parsing.
- *
- * This is the new way of passing data to the kernel at boot time.  Rather
- * than passing a fixed inflexible structure to the kernel, we pass a list
- * of variable-sized tags to the kernel.  The first tag must be a ATAG_CORE
- * tag for the list to be recognised (to distinguish the tagged list from
- * a param_struct).  The list is terminated with a zero-length tag (this tag
- * is not parsed in any way).
- */
-static int __init parse_tag_core(const struct tag *tag)
-{
-        if (tag->hdr.size > 2) {
-                if ((tag->u.core.flags & 1) == 0)
-                        root_mountflags &= ~MS_RDONLY;
-                ROOT_DEV = old_decode_dev(tag->u.core.rootdev);
-        }
-        return 0;
-}
-
-__tagtable(ATAG_CORE, parse_tag_core);
-
-static int __init parse_tag_mem32(const struct tag *tag)
-{
-        return arm_add_memory(tag->u.mem.start, tag->u.mem.size);
-}
-
-__tagtable(ATAG_MEM, parse_tag_mem32);
-
 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
 struct screen_info screen_info = {
  .orig_video_lines      = 30,
@@ -681,117 +628,8 @@ struct screen_info screen_info = {
  .orig_video_isVGA      = 1,
  .orig_video_points     = 8
 };
-
-static int __init parse_tag_videotext(const struct tag *tag)
-{
-        screen_info.orig_x            = tag->u.videotext.x;
-        screen_info.orig_y            = tag->u.videotext.y;
-        screen_info.orig_video_page   = tag->u.videotext.video_page;
-        screen_info.orig_video_mode   = tag->u.videotext.video_mode;
-        screen_info.orig_video_cols   = tag->u.videotext.video_cols;
-        screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx;
-        screen_info.orig_video_lines  = tag->u.videotext.video_lines;
-        screen_info.orig_video_isVGA  = tag->u.videotext.video_isvga;
-        screen_info.orig_video_points = tag->u.videotext.video_points;
-        return 0;
-}
-
-__tagtable(ATAG_VIDEOTEXT, parse_tag_videotext);
 #endif
 
-static int __init parse_tag_ramdisk(const struct tag *tag)
-{
-        setup_ramdisk((tag->u.ramdisk.flags & 1) == 0,
-                      (tag->u.ramdisk.flags & 2) == 0,
-                      tag->u.ramdisk.start, tag->u.ramdisk.size);
-        return 0;
-}
-
-__tagtable(ATAG_RAMDISK, parse_tag_ramdisk);
-
-static int __init parse_tag_serialnr(const struct tag *tag)
-{
-        system_serial_low = tag->u.serialnr.low;
-        system_serial_high = tag->u.serialnr.high;
-        return 0;
-}
-
-__tagtable(ATAG_SERIAL, parse_tag_serialnr);
-
-static int __init parse_tag_revision(const struct tag *tag)
-{
-        system_rev = tag->u.revision.rev;
-        return 0;
-}
-
-__tagtable(ATAG_REVISION, parse_tag_revision);
-
-static int __init parse_tag_cmdline(const struct tag *tag)
-{
-#if defined(CONFIG_CMDLINE_EXTEND)
-        strlcat(default_command_line, " ", COMMAND_LINE_SIZE);
-        strlcat(default_command_line, tag->u.cmdline.cmdline,
-                COMMAND_LINE_SIZE);
-#elif defined(CONFIG_CMDLINE_FORCE)
-        pr_warning("Ignoring tag cmdline (using the default kernel command line)\n");
-#else
-        strlcpy(default_command_line, tag->u.cmdline.cmdline,
-                COMMAND_LINE_SIZE);
-#endif
-        return 0;
-}
-
-__tagtable(ATAG_CMDLINE, parse_tag_cmdline);
-
-/*
- * Scan the tag table for this tag, and call its parse function.
- * The tag table is built by the linker from all the __tagtable
- * declarations.
- */
-static int __init parse_tag(const struct tag *tag)
-{
-        extern struct tagtable __tagtable_begin, __tagtable_end;
-        struct tagtable *t;
-
-        for (t = &__tagtable_begin; t < &__tagtable_end; t++)
-                if (tag->hdr.tag == t->tag) {
-                        t->parse(tag);
-                        break;
-                }
-
-        return t < &__tagtable_end;
-}
-
-/*
- * Parse all tags in the list, checking both the global and architecture
- * specific tag tables.
- */
-static void __init parse_tags(const struct tag *t)
-{
-        for (; t->hdr.size; t = tag_next(t))
-                if (!parse_tag(t))
-                        printk(KERN_WARNING
-                                "Ignoring unrecognised tag 0x%08x\n",
-                                t->hdr.tag);
-}
-
-/*
- * This holds our defaults.
- */
-static struct init_tags {
-        struct tag_header hdr1;
-        struct tag_core   core;
-        struct tag_header hdr2;
-        struct tag_mem32  mem;
-        struct tag_header hdr3;
-} init_tags __initdata = {
-        { tag_size(tag_core), ATAG_CORE },
-        { 1, PAGE_SIZE, 0xff },
-        { tag_size(tag_mem32), ATAG_MEM },
-        { MEM_SIZE },
-        { 0, ATAG_NONE }
-};
-
 static int __init customize_machine(void)
 {
         /* customizes platform devices, or adds new ones */
@@ -858,78 +696,6 @@ static void __init reserve_crashkernel(void)
 static inline void reserve_crashkernel(void) {}
 #endif /* CONFIG_KEXEC */
 
-static void __init squash_mem_tags(struct tag *tag)
-{
-        for (; tag->hdr.size; tag = tag_next(tag))
-                if (tag->hdr.tag == ATAG_MEM)
-                        tag->hdr.tag = ATAG_NONE;
-}
-
-static struct machine_desc * __init setup_machine_tags(unsigned int nr)
-{
-        struct tag *tags = (struct tag *)&init_tags;
-        struct machine_desc *mdesc = NULL, *p;
-        char *from = default_command_line;
-
-        init_tags.mem.start = PHYS_OFFSET;
-
-        /*
-         * locate machine in the list of supported machines.
-         */
-        for_each_machine_desc(p)
-                if (nr == p->nr) {
-                        printk("Machine: %s\n", p->name);
-                        mdesc = p;
-                        break;
-                }
-
-        if (!mdesc) {
-                early_print("\nError: unrecognized/unsupported machine ID"
-                        " (r1 = 0x%08x).\n\n", nr);
-                dump_machine_table(); /* does not return */
-        }
-
-        if (__atags_pointer)
-                tags = phys_to_virt(__atags_pointer);
-        else if (mdesc->atag_offset)
-                tags = (void *)(PAGE_OFFSET + mdesc->atag_offset);
-
-#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
-        /*
-         * If we have the old style parameters, convert them to
-         * a tag list.
-         */
-        if (tags->hdr.tag != ATAG_CORE)
-                convert_to_tag_list(tags);
-#endif
-
-        if (tags->hdr.tag != ATAG_CORE) {
-#if defined(CONFIG_OF)
-                /*
-                 * If CONFIG_OF is set, then assume this is a reasonably
-                 * modern system that should pass boot parameters
-                 */
-                early_print("Warning: Neither atags nor dtb found\n");
-#endif
-                tags = (struct tag *)&init_tags;
-        }
-
-        if (mdesc->fixup)
-                mdesc->fixup(tags, &from, &meminfo);
-
-        if (tags->hdr.tag == ATAG_CORE) {
-                if (meminfo.nr_banks != 0)
-                        squash_mem_tags(tags);
-                save_atags(tags);
-                parse_tags(tags);
-        }
-
-        /* parse_early_param needs a boot_command_line */
-        strlcpy(boot_command_line, from, COMMAND_LINE_SIZE);
-
-        return mdesc;
-}
-
 static int __init meminfo_cmp(const void *_a, const void *_b)
 {
         const struct membank *a = _a, *b = _b;
@@ -944,7 +710,7 @@ void __init setup_arch(char **cmdline_p)
         setup_processor();
         mdesc = setup_machine_fdt(__atags_pointer);
         if (!mdesc)
-                mdesc = setup_machine_tags(machine_arch_type);
+                mdesc = setup_machine_tags(__atags_pointer, machine_arch_type);
         machine_desc = mdesc;
         machine_name = mdesc->name;
 
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index dea7a925c7e2..d100eacdb798 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -59,7 +59,8 @@ struct secondary_data secondary_data;
 volatile int __cpuinitdata pen_release = -1;
 
 enum ipi_msg_type {
-        IPI_TIMER = 2,
+        IPI_WAKEUP,
+        IPI_TIMER,
         IPI_RESCHEDULE,
         IPI_CALL_FUNC,
         IPI_CALL_FUNC_SINGLE,
@@ -414,7 +415,8 @@ void arch_send_call_function_single_ipi(int cpu)
 }
 
 static const char *ipi_types[NR_IPI] = {
-#define S(x,s)  [x - IPI_TIMER] = s
+#define S(x,s)  [x] = s
+        S(IPI_WAKEUP, "CPU wakeup interrupts"),
         S(IPI_TIMER, "Timer broadcast interrupts"),
         S(IPI_RESCHEDULE, "Rescheduling interrupts"),
         S(IPI_CALL_FUNC, "Function call interrupts"),
@@ -567,10 +569,13 @@ void handle_IPI(int ipinr, struct pt_regs *regs)
         unsigned int cpu = smp_processor_id();
         struct pt_regs *old_regs = set_irq_regs(regs);
 
-        if (ipinr >= IPI_TIMER && ipinr < IPI_TIMER + NR_IPI)
-                __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_TIMER]);
+        if (ipinr < NR_IPI)
+                __inc_irq_stat(cpu, ipi_irqs[ipinr]);
 
         switch (ipinr) {
+        case IPI_WAKEUP:
+                break;
+
         case IPI_TIMER:
                 irq_enter();
                 ipi_timer();
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
index 395d5fbb8fa2..9d0a30032d7f 100644
--- a/arch/arm/lib/delay.c
+++ b/arch/arm/lib/delay.c
@@ -34,7 +34,18 @@ struct arm_delay_ops arm_delay_ops = {
         .udelay         = __loop_udelay,
 };
 
-#ifdef ARCH_HAS_READ_CURRENT_TIMER
+static const struct delay_timer *delay_timer;
+static bool delay_calibrated;
+
+int read_current_timer(unsigned long *timer_val)
+{
+        if (!delay_timer)
+                return -ENXIO;
+
+        *timer_val = delay_timer->read_current_timer();
+        return 0;
+}
+
 static void __timer_delay(unsigned long cycles)
 {
         cycles_t start = get_cycles();
@@ -55,18 +66,24 @@ static void __timer_udelay(unsigned long usecs)
         __timer_const_udelay(usecs * UDELAY_MULT);
 }
 
-void __init init_current_timer_delay(unsigned long freq)
+void __init register_current_timer_delay(const struct delay_timer *timer)
 {
-        pr_info("Switching to timer-based delay loop\n");
-        lpj_fine                        = freq / HZ;
-        loops_per_jiffy                 = lpj_fine;
-        arm_delay_ops.delay             = __timer_delay;
-        arm_delay_ops.const_udelay      = __timer_const_udelay;
-        arm_delay_ops.udelay            = __timer_udelay;
+        if (!delay_calibrated) {
+                pr_info("Switching to timer-based delay loop\n");
+                delay_timer                     = timer;
+                lpj_fine                        = timer->freq / HZ;
+                loops_per_jiffy                 = lpj_fine;
+                arm_delay_ops.delay             = __timer_delay;
+                arm_delay_ops.const_udelay      = __timer_const_udelay;
+                arm_delay_ops.udelay            = __timer_udelay;
+                delay_calibrated                = true;
+        } else {
+                pr_info("Ignoring duplicate/late registration of read_current_timer delay\n");
+        }
 }
 
 unsigned long __cpuinit calibrate_delay_is_known(void)
 {
+        delay_calibrated = true;
         return lpj_fine;
 }
-#endif
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 188c82971ebd..33361505c0cd 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -625,7 +625,7 @@ fail:
         return 0;
 }
 
-static struct clk *const standard_pmc_clocks[] __initdata = {
+static struct clk *const standard_pmc_clocks[] __initconst = {
         /* four primary clocks */
         &clk32k,
         &main_clk,
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index ac4e003ad863..be3099733b1f 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -88,7 +88,7 @@ static struct davinci_mmc_config mmc_config = {
         .version        = MMC_CTLR_VERSION_1,
 };
 
-static const short sdio1_pins[] __initdata = {
+static const short sdio1_pins[] __initconst = {
         TNETV107X_SDIO1_CLK_1,          TNETV107X_SDIO1_CMD_1,
         TNETV107X_SDIO1_DATA0_1,        TNETV107X_SDIO1_DATA1_1,
         TNETV107X_SDIO1_DATA2_1,        TNETV107X_SDIO1_DATA3_1,
@@ -96,12 +96,12 @@ static const short sdio1_pins[] __initdata = {
         -1
 };
 
-static const short uart1_pins[] __initdata = {
+static const short uart1_pins[] __initconst = {
         TNETV107X_UART1_RD,             TNETV107X_UART1_TD,
         -1
 };
 
-static const short ssp_pins[] __initdata = {
+static const short ssp_pins[] __initconst = {
         TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2,
         TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2,
         TNETV107X_SSP1_3, -1
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index deee5c2da754..510648e0394b 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -838,7 +838,7 @@ static const struct mux_config da830_pins[] = {
 #endif
 };
 
-const short da830_emif25_pins[] __initdata = {
+const short da830_emif25_pins[] __initconst = {
         DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
         DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
         DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11,
@@ -853,19 +853,19 @@ const short da830_emif25_pins[] __initdata = {
         -1
 };
 
-const short da830_spi0_pins[] __initdata = {
+const short da830_spi0_pins[] __initconst = {
         DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA,
         DA830_NSPI0_SCS_0,
         -1
 };
 
-const short da830_spi1_pins[] __initdata = {
+const short da830_spi1_pins[] __initconst = {
         DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA,
         DA830_NSPI1_SCS_0,
         -1
 };
 
-const short da830_mmc_sd_pins[] __initdata = {
+const short da830_mmc_sd_pins[] __initconst = {
         DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
         DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
         DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
@@ -873,32 +873,32 @@ const short da830_mmc_sd_pins[] __initdata = {
         -1
 };
 
-const short da830_uart0_pins[] __initdata = {
+const short da830_uart0_pins[] __initconst = {
         DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD,
         -1
 };
 
-const short da830_uart1_pins[] __initdata = {
+const short da830_uart1_pins[] __initconst = {
         DA830_UART1_RXD, DA830_UART1_TXD,
         -1
 };
 
-const short da830_uart2_pins[] __initdata = {
+const short da830_uart2_pins[] __initconst = {
         DA830_UART2_RXD, DA830_UART2_TXD,
         -1
 };
 
-const short da830_usb20_pins[] __initdata = {
+const short da830_usb20_pins[] __initconst = {
         DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN,
         -1
 };
 
-const short da830_usb11_pins[] __initdata = {
+const short da830_usb11_pins[] __initconst = {
         DA830_USB_REFCLKIN,
         -1
 };
 
-const short da830_uhpi_pins[] __initdata = {
+const short da830_uhpi_pins[] __initconst = {
         DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3,
         DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7,
         DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11,
@@ -909,14 +909,14 @@ const short da830_uhpi_pins[] __initdata = {
         -1
 };
 
-const short da830_cpgmac_pins[] __initdata = {
+const short da830_cpgmac_pins[] __initconst = {
         DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV,
         DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK,
         DA830_MDIO_D,
         -1
 };
 
-const short da830_emif3c_pins[] __initdata = {
+const short da830_emif3c_pins[] __initconst = {
         DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0,
         DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1,
         DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2,
@@ -935,7 +935,7 @@ const short da830_emif3c_pins[] __initdata = {
         -1
 };
 
-const short da830_mcasp0_pins[] __initdata = {
+const short da830_mcasp0_pins[] __initconst = {
         DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0,
         DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0,
         DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3,
@@ -945,7 +945,7 @@ const short da830_mcasp0_pins[] __initdata = {
         -1
 };
 
-const short da830_mcasp1_pins[] __initdata = {
+const short da830_mcasp1_pins[] __initconst = {
         DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1,
         DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1,
         DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3,
@@ -954,24 +954,24 @@ const short da830_mcasp1_pins[] __initdata = {
         -1
 };
 
-const short da830_mcasp2_pins[] __initdata = {
+const short da830_mcasp2_pins[] __initconst = {
         DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2,
         DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2,
         DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3,
         -1
 };
 
-const short da830_i2c0_pins[] __initdata = {
+const short da830_i2c0_pins[] __initconst = {
         DA830_I2C0_SDA, DA830_I2C0_SCL,
         -1
 };
 
-const short da830_i2c1_pins[] __initdata = {
+const short da830_i2c1_pins[] __initconst = {
         DA830_I2C1_SCL, DA830_I2C1_SDA,
         -1
 };
 
-const short da830_lcdcntl_pins[] __initdata = {
+const short da830_lcdcntl_pins[] __initconst = {
         DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3,
         DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7,
         DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11,
@@ -981,34 +981,34 @@ const short da830_lcdcntl_pins[] __initdata = {
         -1
 };
 
-const short da830_pwm_pins[] __initdata = {
+const short da830_pwm_pins[] __initconst = {
         DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A,
         DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ,
         DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A,
         -1
 };
 
-const short da830_ecap0_pins[] __initdata = {
+const short da830_ecap0_pins[] __initconst = {
         DA830_ECAP0_APWM0,
         -1
 };
 
-const short da830_ecap1_pins[] __initdata = {
+const short da830_ecap1_pins[] __initconst = {
         DA830_ECAP1_APWM1,
         -1
 };
 
-const short da830_ecap2_pins[] __initdata = {
+const short da830_ecap2_pins[] __initconst = {
         DA830_ECAP2_APWM2,
         -1
 };
 
-const short da830_eqep0_pins[] __initdata = {
+const short da830_eqep0_pins[] __initconst = {
         DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B,
         -1
 };
 
-const short da830_eqep1_pins[] __initdata = {
+const short da830_eqep1_pins[] __initconst = {
         DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B,
         -1
 };
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index b44dc844e15e..6676dee7104e 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -576,17 +576,17 @@ static const struct mux_config da850_pins[] = {
 #endif
 };
 
-const short da850_i2c0_pins[] __initdata = {
+const short da850_i2c0_pins[] __initconst = {
         DA850_I2C0_SDA, DA850_I2C0_SCL,
         -1
 };
 
-const short da850_i2c1_pins[] __initdata = {
+const short da850_i2c1_pins[] __initconst = {
         DA850_I2C1_SCL, DA850_I2C1_SDA,
         -1
 };
 
-const short da850_lcdcntl_pins[] __initdata = {
+const short da850_lcdcntl_pins[] __initconst = {
         DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
         DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
         DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index dd937c526a45..00154e74ce6b 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -15,6 +15,13 @@ config MACH_CM_A510
           Say 'Y' here if you want your kernel to support the
           CompuLab CM-A510 Board.
 
+config MACH_DOVE_DT
+        bool "Marvell Dove Flattened Device Tree"
+        select USE_OF
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell Dove using flattened device tree.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index fa0f01856060..5e683baf96cf 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,4 +1,4 @@
-obj-y                           += common.o addr-map.o irq.o pcie.o mpp.o
-
+obj-y                           += common.o addr-map.o irq.o mpp.o
+obj-$(CONFIG_PCI)               += pcie.o
 obj-$(CONFIG_MACH_DOVE_DB)      += dove-db-setup.o
 obj-$(CONFIG_MACH_CM_A510)      += cm-a510.o
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 950ad9533d19..b37bef1d5ffa 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -16,6 +16,8 @@
 #include <linux/clk-provider.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/timex.h>
@@ -24,6 +26,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/pci.h>
 #include <mach/dove.h>
+#include <mach/pm.h>
 #include <mach/bridge-regs.h>
 #include <asm/mach/arch.h>
 #include <linux/irq.h>
@@ -33,19 +36,17 @@
 #include <plat/addr-map.h>
 #include "common.h"
 
-static int get_tclk(void);
-
 /*****************************************************************************
  * I/O Address Mapping
  ****************************************************************************/
 static struct map_desc dove_io_desc[] __initdata = {
         {
-                .virtual        = DOVE_SB_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
                 .length         = DOVE_SB_REGS_SIZE,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = DOVE_NB_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
                 .length         = DOVE_NB_REGS_SIZE,
                 .type           = MT_DEVICE,
@@ -60,14 +61,69 @@ void __init dove_map_io(void)
 /*****************************************************************************
  * CLK tree
  ****************************************************************************/
+static int dove_tclk;
+
+static DEFINE_SPINLOCK(gating_lock);
 static struct clk *tclk;
 
-static void __init clk_init(void)
+static struct clk __init *dove_register_gate(const char *name,
+                                             const char *parent, u8 bit_idx)
 {
-        tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
-                                       get_tclk());
+        return clk_register_gate(NULL, name, parent, 0,
+                                 (void __iomem *)CLOCK_GATING_CONTROL,
+                                 bit_idx, 0, &gating_lock);
+}
+
+static void __init dove_clk_init(void)
+{
+        struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
+        struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
+        struct clk *xor0, *xor1, *ge, *gephy;
 
-        orion_clkdev_init(tclk);
+        tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
+                                       dove_tclk);
+
+        usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
+        usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
+        sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
+        pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
+        pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
+        sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
+        sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
+        nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
+        camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
+        i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
+        i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
+        crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
+        ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
+        pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
+        xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
+        xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
+        gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
+        ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
+
+        orion_clkdev_add(NULL, "orion_spi.0", tclk);
+        orion_clkdev_add(NULL, "orion_spi.1", tclk);
+        orion_clkdev_add(NULL, "orion_wdt", tclk);
+        orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
+
+        orion_clkdev_add(NULL, "orion-ehci.0", usb0);
+        orion_clkdev_add(NULL, "orion-ehci.1", usb1);
+        orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
+        orion_clkdev_add("0", "sata_mv.0", sata);
+        orion_clkdev_add("0", "pcie", pex0);
+        orion_clkdev_add("1", "pcie", pex1);
+        orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
+        orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
+        orion_clkdev_add(NULL, "orion_nand", nand);
+        orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
+        orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
+        orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
+        orion_clkdev_add(NULL, "mv_crypto", crypto);
+        orion_clkdev_add(NULL, "dove-ac97", ac97);
+        orion_clkdev_add(NULL, "dove-pdma", pdma);
+        orion_clkdev_add(NULL, "mv_xor_shared.0", xor0);
+        orion_clkdev_add(NULL, "mv_xor_shared.1", xor1);
 }
 
 /*****************************************************************************
@@ -178,16 +234,16 @@ void __init dove_init_early(void)
         orion_time_set_base(TIMER_VIRT_BASE);
 }
 
-static int get_tclk(void)
+static int __init dove_find_tclk(void)
 {
-        /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
         return 166666667;
 }
 
 static void __init dove_timer_init(void)
 {
+        dove_tclk = dove_find_tclk();
         orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
-                        IRQ_DOVE_BRIDGE, get_tclk());
+                        IRQ_DOVE_BRIDGE, dove_tclk);
 }
 
 struct sys_timer dove_timer = {
@@ -195,6 +251,15 @@ struct sys_timer dove_timer = {
 };
 
 /*****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+ ****************************************************************************/
+void __init dove_crypto_init(void)
+{
+        orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
+                          DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
+}
+
+/*****************************************************************************
  * XOR 0
  ****************************************************************************/
 void __init dove_xor0_init(void)
@@ -275,8 +340,8 @@ void __init dove_sdio1_init(void)
 
 void __init dove_init(void)
 {
-        printk(KERN_INFO "Dove 88AP510 SoC, ");
-        printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
+        pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
+                (dove_tclk + 499999) / 1000000);
 
 #ifdef CONFIG_CACHE_TAUROS2
         tauros2_init(0);
@@ -284,7 +349,7 @@ void __init dove_init(void)
         dove_setup_cpu_mbus();
 
         /* Setup root of clk tree */
-        clk_init();
+        dove_clk_init();
 
         /* internal devices that every board has */
         dove_rtc_init();
@@ -307,3 +372,67 @@ void dove_restart(char mode, const char *cmd)
         while (1)
                 ;
 }
+
+#if defined(CONFIG_MACH_DOVE_DT)
+/*
+ * Auxdata required until real OF clock provider
+ */
+struct of_dev_auxdata dove_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
+        OF_DEV_AUXDATA("marvell,orion-spi", 0xf1014600, "orion_spi.1", NULL),
+        OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
+        OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
+                       NULL),
+        OF_DEV_AUXDATA("marvell,orion-sata", 0xf10a0000, "sata_mv.0", NULL),
+        OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1092000, "sdhci-dove.0", NULL),
+        OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1090000, "sdhci-dove.1", NULL),
+        {},
+};
+
+static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
+        .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
+};
+
+static void __init dove_dt_init(void)
+{
+        pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
+                (dove_tclk + 499999) / 1000000);
+
+#ifdef CONFIG_CACHE_TAUROS2
+        tauros2_init();
+#endif
+        dove_setup_cpu_mbus();
+
+        /* Setup root of clk tree */
+        dove_clk_init();
+
+        /* Internal devices not ported to DT yet */
+        dove_rtc_init();
+        dove_xor0_init();
+        dove_xor1_init();
+
+        dove_ge00_init(&dove_dt_ge00_data);
+        dove_ehci0_init();
+        dove_ehci1_init();
+        dove_pcie_init(1, 1);
+        dove_crypto_init();
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             dove_auxdata_lookup, NULL);
+}
+
+static const char * const dove_dt_board_compat[] = {
+        "marvell,dove",
+        NULL
+};
+
+DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
+        .map_io         = dove_map_io,
+        .init_early     = dove_init_early,
+        .init_irq       = orion_dt_init_irq,
+        .timer          = &dove_timer,
+        .init_machine   = dove_dt_init,
+        .restart        = dove_restart,
+        .dt_compat      = dove_dt_board_compat,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index 6432a3ba864b..1a233404b735 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -26,7 +26,11 @@ void dove_init_irq(void);
 void dove_setup_cpu_mbus(void);
 void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void dove_sata_init(struct mv_sata_platform_data *sata_data);
+#ifdef CONFIG_PCI
 void dove_pcie_init(int init_port0, int init_port1);
+#else
+static inline void dove_pcie_init(int init_port0, int init_port1) { }
+#endif
 void dove_ehci0_init(void);
 void dove_ehci1_init(void);
 void dove_uart0_init(void);
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
index f953bb54aa9d..99f259e8cf33 100644
--- a/arch/arm/mach-dove/include/mach/bridge-regs.h
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -13,22 +13,22 @@
 
 #include <mach/dove.h>
 
-#define CPU_CONFIG              (BRIDGE_VIRT_BASE | 0x0000)
+#define CPU_CONFIG              (BRIDGE_VIRT_BASE + 0x0000)
 
-#define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
 #define  CPU_CTRL_PCIE0_LINK    0x00000001
 #define  CPU_RESET              0x00000002
 #define  CPU_CTRL_PCIE1_LINK    0x00000008
 
-#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
 #define  SOFT_RESET_OUT_EN      0x00000004
 
-#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
 #define  SOFT_RESET             0x00000001
 
 #define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
 
-#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_LOW_OFF       0x0000
 #define IRQ_MASK_LOW_OFF        0x0004
 #define FIQ_MASK_LOW_OFF        0x0008
@@ -47,9 +47,9 @@
 #define ENDPOINT_MASK_HIGH      (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
 #define PCIE_INTERRUPT_MASK     (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
 
-#define POWER_MANAGEMENT        (BRIDGE_VIRT_BASE | 0x011c)
+#define POWER_MANAGEMENT        (BRIDGE_VIRT_BASE + 0x011c)
 
-#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
-#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE + 0x0300)
+#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
 
 #endif
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index c91e3004a47b..661725e3115a 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -25,7 +25,7 @@
  */
 
 #define DOVE_CESA_PHYS_BASE             0xc8000000
-#define DOVE_CESA_VIRT_BASE             0xfdb00000
+#define DOVE_CESA_VIRT_BASE             IOMEM(0xfdb00000)
 #define DOVE_CESA_SIZE                  SZ_1M
 
 #define DOVE_PCIE0_MEM_PHYS_BASE        0xe0000000
@@ -38,15 +38,15 @@
 #define DOVE_BOOTROM_SIZE               SZ_128M
 
 #define DOVE_SCRATCHPAD_PHYS_BASE       0xf0000000
-#define DOVE_SCRATCHPAD_VIRT_BASE       0xfdd00000
+#define DOVE_SCRATCHPAD_VIRT_BASE       IOMEM(0xfdd00000)
 #define DOVE_SCRATCHPAD_SIZE            SZ_1M
 
 #define DOVE_SB_REGS_PHYS_BASE          0xf1000000
-#define DOVE_SB_REGS_VIRT_BASE          0xfde00000
+#define DOVE_SB_REGS_VIRT_BASE          IOMEM(0xfde00000)
 #define DOVE_SB_REGS_SIZE               SZ_8M
 
 #define DOVE_NB_REGS_PHYS_BASE          0xf1800000
-#define DOVE_NB_REGS_VIRT_BASE          0xfe600000
+#define DOVE_NB_REGS_VIRT_BASE          IOMEM(0xfe600000)
 #define DOVE_NB_REGS_SIZE               SZ_8M
 
 #define DOVE_PCIE0_IO_PHYS_BASE         0xf2000000
@@ -62,75 +62,75 @@
  */
 
 /* SPI, I2C, UART */
-#define DOVE_I2C_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0x11000)
-#define DOVE_UART0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12000)
-#define DOVE_UART0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12000)
-#define DOVE_UART1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12100)
-#define DOVE_UART1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12100)
-#define DOVE_UART2_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12200)
-#define DOVE_UART2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12200)
-#define DOVE_UART3_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12300)
-#define DOVE_UART3_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12300)
-#define DOVE_SPI0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x10600)
-#define DOVE_SPI1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x14600)
+#define DOVE_I2C_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0x11000)
+#define DOVE_UART0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12000)
+#define DOVE_UART0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12000)
+#define DOVE_UART1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12100)
+#define DOVE_UART1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12100)
+#define DOVE_UART2_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12200)
+#define DOVE_UART2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12200)
+#define DOVE_UART3_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12300)
+#define DOVE_UART3_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12300)
+#define DOVE_SPI0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x10600)
+#define DOVE_SPI1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x14600)
 
 /* North-South Bridge */
-#define BRIDGE_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x20000)
-#define BRIDGE_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x20000)
+#define BRIDGE_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE + 0x20000)
+#define BRIDGE_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE + 0x20000)
 
 /* Cryptographic Engine */
-#define DOVE_CRYPT_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x30000)
+#define DOVE_CRYPT_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x30000)
 
 /* PCIe 0 */
-#define DOVE_PCIE0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x40000)
+#define DOVE_PCIE0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x40000)
 
 /* USB */
-#define DOVE_USB0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x50000)
-#define DOVE_USB1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x51000)
+#define DOVE_USB0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x50000)
+#define DOVE_USB1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x51000)
 
 /* XOR 0 Engine */
-#define DOVE_XOR0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x60800)
-#define DOVE_XOR0_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0x60800)
-#define DOVE_XOR0_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x60A00)
-#define DOVE_XOR0_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x60A00)
+#define DOVE_XOR0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x60800)
+#define DOVE_XOR0_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0x60800)
+#define DOVE_XOR0_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE + 0x60A00)
+#define DOVE_XOR0_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE + 0x60A00)
 
 /* XOR 1 Engine */
-#define DOVE_XOR1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x60900)
-#define DOVE_XOR1_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0x60900)
-#define DOVE_XOR1_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x60B00)
-#define DOVE_XOR1_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x60B00)
+#define DOVE_XOR1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x60900)
+#define DOVE_XOR1_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0x60900)
+#define DOVE_XOR1_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE + 0x60B00)
+#define DOVE_XOR1_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE + 0x60B00)
 
 /* Gigabit Ethernet */
-#define DOVE_GE00_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x70000)
+#define DOVE_GE00_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x70000)
 
 /* PCIe 1 */
-#define DOVE_PCIE1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x80000)
+#define DOVE_PCIE1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x80000)
 
 /* CAFE */
-#define DOVE_SDIO0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x92000)
-#define DOVE_SDIO1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x90000)
-#define DOVE_CAM_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0x94000)
-#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000)
+#define DOVE_SDIO0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x92000)
+#define DOVE_SDIO1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x90000)
+#define DOVE_CAM_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0x94000)
+#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000)
 
 /* SATA */
-#define DOVE_SATA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xa0000)
+#define DOVE_SATA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xa0000)
 
 /* I2S/SPDIF */
-#define DOVE_AUD0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xb0000)
-#define DOVE_AUD1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xb4000)
+#define DOVE_AUD0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xb0000)
+#define DOVE_AUD1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xb4000)
 
 /* NAND Flash Controller */
-#define DOVE_NFC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xc0000)
+#define DOVE_NFC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0xc0000)
 
 /* MPP, GPIO, Reset Sampling */
-#define DOVE_MPP_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
+#define DOVE_MPP_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
 #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
-#define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE | 0x014)
-#define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE | 0x018)
-#define DOVE_GPIO_LO_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
-#define DOVE_GPIO_HI_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE | 0xd0420)
-#define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
-#define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
+#define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE + 0x014)
+#define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE + 0x018)
+#define DOVE_GPIO_LO_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
+#define DOVE_GPIO_HI_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE + 0xd0420)
+#define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
+#define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
 #define  DOVE_AU1_SPDIFO_GPIO_EN        (1 << 1)
 #define  DOVE_NAND_GPIO_EN              (1 << 0)
 #define DOVE_MPP_CTRL4_VIRT_BASE        (DOVE_GPIO_LO_VIRT_BASE + 0x40)
@@ -142,44 +142,44 @@
 #define  DOVE_SD0_GPIO_SEL              (1 << 0)
 
 /* Power Management */
-#define DOVE_PMU_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
+#define DOVE_PMU_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE + 0xd0000)
 #define DOVE_PMU_SIG_CTRL       (DOVE_PMU_VIRT_BASE + 0x802c)
 
 /* Real Time Clock */
-#define DOVE_RTC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xd8500)
+#define DOVE_RTC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0xd8500)
 
 /* AC97 */
-#define DOVE_AC97_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xe0000)
-#define DOVE_AC97_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xe0000)
+#define DOVE_AC97_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xe0000)
+#define DOVE_AC97_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0xe0000)
 
 /* Peripheral DMA */
-#define DOVE_PDMA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xe4000)
-#define DOVE_PDMA_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xe4000)
+#define DOVE_PDMA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xe4000)
+#define DOVE_PDMA_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0xe4000)
 
-#define DOVE_GLOBAL_CONFIG_1    (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
+#define DOVE_GLOBAL_CONFIG_1    (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
 #define  DOVE_TWSI_ENABLE_OPTION1       (1 << 7)
-#define DOVE_GLOBAL_CONFIG_2    (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
+#define DOVE_GLOBAL_CONFIG_2    (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
 #define  DOVE_TWSI_ENABLE_OPTION2       (1 << 20)
 #define  DOVE_TWSI_ENABLE_OPTION3       (1 << 21)
 #define  DOVE_TWSI_OPTION3_GPIO         (1 << 22)
-#define DOVE_SSP_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xec000)
-#define DOVE_SSP_CTRL_STATUS_1  (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
+#define DOVE_SSP_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0xec000)
+#define DOVE_SSP_CTRL_STATUS_1  (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
 #define  DOVE_SSP_ON_AU1                (1 << 0)
 #define  DOVE_SSP_CLOCK_ENABLE          (1 << 1)
 #define  DOVE_SSP_BPB_CLOCK_SRC_SSP     (1 << 11)
 /* Memory Controller */
-#define DOVE_MC_VIRT_BASE       (DOVE_NB_REGS_VIRT_BASE | 0x00000)
+#define DOVE_MC_VIRT_BASE       (DOVE_NB_REGS_VIRT_BASE + 0x00000)
 
 /* LCD Controller */
-#define DOVE_LCD_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x10000)
-#define DOVE_LCD1_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE | 0x20000)
-#define DOVE_LCD2_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE | 0x10000)
-#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000)
+#define DOVE_LCD_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE + 0x10000)
+#define DOVE_LCD1_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE + 0x20000)
+#define DOVE_LCD2_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE + 0x10000)
+#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000)
 
 /* Graphic Engine */
-#define DOVE_GPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x40000)
+#define DOVE_GPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE + 0x40000)
 
 /* Video Engine */
-#define DOVE_VPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x400000)
+#define DOVE_VPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE + 0x400000)
 
 #endif
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
index 3ad9f946a9e8..7bcd0dfce4b1 100644
--- a/arch/arm/mach-dove/include/mach/pm.h
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -13,24 +13,42 @@
 #include <mach/irqs.h>
 
 #define CLOCK_GATING_CONTROL    (DOVE_PMU_VIRT_BASE + 0x38)
-#define  CLOCK_GATING_USB0_MASK         (1 << 0)
-#define  CLOCK_GATING_USB1_MASK         (1 << 1)
-#define  CLOCK_GATING_GBE_MASK          (1 << 2)
-#define  CLOCK_GATING_SATA_MASK         (1 << 3)
-#define  CLOCK_GATING_PCIE0_MASK        (1 << 4)
-#define  CLOCK_GATING_PCIE1_MASK        (1 << 5)
-#define  CLOCK_GATING_SDIO0_MASK        (1 << 8)
-#define  CLOCK_GATING_SDIO1_MASK        (1 << 9)
-#define  CLOCK_GATING_NAND_MASK         (1 << 10)
-#define  CLOCK_GATING_CAMERA_MASK       (1 << 11)
-#define  CLOCK_GATING_I2S0_MASK         (1 << 12)
-#define  CLOCK_GATING_I2S1_MASK         (1 << 13)
-#define  CLOCK_GATING_CRYPTO_MASK       (1 << 15)
-#define  CLOCK_GATING_AC97_MASK         (1 << 21)
-#define  CLOCK_GATING_PDMA_MASK         (1 << 22)
-#define  CLOCK_GATING_XOR0_MASK         (1 << 23)
-#define  CLOCK_GATING_XOR1_MASK         (1 << 24)
-#define  CLOCK_GATING_GIGA_PHY_MASK     (1 << 30)
+#define  CLOCK_GATING_BIT_USB0          0
+#define  CLOCK_GATING_BIT_USB1          1
+#define  CLOCK_GATING_BIT_GBE           2
+#define  CLOCK_GATING_BIT_SATA          3
+#define  CLOCK_GATING_BIT_PCIE0         4
+#define  CLOCK_GATING_BIT_PCIE1         5
+#define  CLOCK_GATING_BIT_SDIO0         8
+#define  CLOCK_GATING_BIT_SDIO1         9
+#define  CLOCK_GATING_BIT_NAND          10
+#define  CLOCK_GATING_BIT_CAMERA        11
+#define  CLOCK_GATING_BIT_I2S0          12
+#define  CLOCK_GATING_BIT_I2S1          13
+#define  CLOCK_GATING_BIT_CRYPTO        15
+#define  CLOCK_GATING_BIT_AC97          21
+#define  CLOCK_GATING_BIT_PDMA          22
+#define  CLOCK_GATING_BIT_XOR0          23
+#define  CLOCK_GATING_BIT_XOR1          24
+#define  CLOCK_GATING_BIT_GIGA_PHY      30
+#define  CLOCK_GATING_USB0_MASK         (1 << CLOCK_GATING_BIT_USB0)
+#define  CLOCK_GATING_USB1_MASK         (1 << CLOCK_GATING_BIT_USB1)
+#define  CLOCK_GATING_GBE_MASK          (1 << CLOCK_GATING_BIT_GBE)
+#define  CLOCK_GATING_SATA_MASK         (1 << CLOCK_GATING_BIT_SATA)
+#define  CLOCK_GATING_PCIE0_MASK        (1 << CLOCK_GATING_BIT_PCIE0)
+#define  CLOCK_GATING_PCIE1_MASK        (1 << CLOCK_GATING_BIT_PCIE1)
+#define  CLOCK_GATING_SDIO0_MASK        (1 << CLOCK_GATING_BIT_SDIO0)
+#define  CLOCK_GATING_SDIO1_MASK        (1 << CLOCK_GATING_BIT_SDIO1)
+#define  CLOCK_GATING_NAND_MASK         (1 << CLOCK_GATING_BIT_NAND)
+#define  CLOCK_GATING_CAMERA_MASK       (1 << CLOCK_GATING_BIT_CAMERA)
+#define  CLOCK_GATING_I2S0_MASK         (1 << CLOCK_GATING_BIT_I2S0)
+#define  CLOCK_GATING_I2S1_MASK         (1 << CLOCK_GATING_BIT_I2S1)
+#define  CLOCK_GATING_CRYPTO_MASK       (1 << CLOCK_GATING_BIT_CRYPTO)
+#define  CLOCK_GATING_AC97_MASK         (1 << CLOCK_GATING_BIT_AC97)
+#define  CLOCK_GATING_PDMA_MASK         (1 << CLOCK_GATING_BIT_PDMA)
+#define  CLOCK_GATING_XOR0_MASK         (1 << CLOCK_GATING_BIT_XOR0)
+#define  CLOCK_GATING_XOR1_MASK         (1 << CLOCK_GATING_BIT_XOR1)
+#define  CLOCK_GATING_GIGA_PHY_MASK     (1 << CLOCK_GATING_BIT_GIGA_PHY)
 
 #define PMU_INTERRUPT_CAUSE     (DOVE_PMU_VIRT_BASE + 0x50)
 #define PMU_INTERRUPT_MASK      (DOVE_PMU_VIRT_BASE + 0x54)
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 186357f3b4db..087711524e8a 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -100,19 +100,19 @@ void __init dove_init_irq(void)
 {
         int i;
 
-        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
-        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+        orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
+        orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
 
         /*
          * Initialize gpiolib for GPIOs 0-71.
          */
-        orion_gpio_init(NULL, 0, 32, (void __iomem *)DOVE_GPIO_LO_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
                         IRQ_DOVE_GPIO_START, gpio0_irqs);
 
-        orion_gpio_init(NULL, 32, 32, (void __iomem *)DOVE_GPIO_HI_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
                         IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
 
-        orion_gpio_init(NULL, 64, 8, (void __iomem *)DOVE_GPIO2_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
                         IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
 
         /*
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 355332d502cb..bb15b26041cb 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -182,18 +182,18 @@ static struct hw_pci dove_pci __initdata = {
         .map_irq        = dove_pcie_map_irq,
 };
 
-static void __init add_pcie_port(int index, unsigned long base)
+static void __init add_pcie_port(int index, void __iomem *base)
 {
         printk(KERN_INFO "Dove PCIe port %d: ", index);
 
-        if (orion_pcie_link_up((void __iomem *)base)) {
+        if (orion_pcie_link_up(base)) {
                 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
 
                 printk(KERN_INFO "link up\n");
 
                 pp->index = index;
                 pp->root_bus_nr = -1;
-                pp->base = (void __iomem *)base;
+                pp->base = base;
                 spin_lock_init(&pp->conf_lock);
                 memset(&pp->res, 0, sizeof(pp->res));
         } else {
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 8d57e4223bdb..f93d820ecab5 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -134,7 +134,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
 
                 __raw_writel(virt_to_phys(exynos4_secondary_startup),
                         CPU1_BOOT_REG);
-                gic_raise_softirq(cpumask_of(cpu), 1);
+                gic_raise_softirq(cpumask_of(cpu), 0);
 
                 if (pen_release == -1)
                         break;
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3a2042fb9712..32197c117afe 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -758,7 +758,7 @@ config SOC_IMX6Q
         select HAVE_IMX_MMDC
         select HAVE_IMX_SRC
         select HAVE_SMP
-        select MFD_ANATOP
+        select MFD_SYSCON
         select PINCTRL
         select PINCTRL_IMX6Q
 
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index f69ca4680049..3b6b640eed24 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -239,8 +239,8 @@ int __init mx27_clocks_init(unsigned long fref)
         clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
         clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
         clk_register_clkdev(clk[nfc_baud_gate], NULL, "mxc_nand.0");
-        clk_register_clkdev(clk[vpu_baud_gate], "per", "imx-vpu");
-        clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "imx-vpu");
+        clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
+        clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
         clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx-dma");
         clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx-dma");
         clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 436c5720fe6a..04822932cdd1 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -17,6 +17,10 @@ extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data;
 #define imx27_add_fsl_usb2_udc(pdata)   \
         imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
 
+extern const struct imx_imx27_coda_data imx27_coda_data;
+#define imx27_add_coda()        \
+        imx_add_imx27_coda(&imx27_coda_data)
+
 extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data;
 #define imx27_add_imx2_wdt()    \
         imx_add_imx2_wdt(&imx27_imx2_wdt_data)
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index f264ddddd47c..821d6aac411c 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -32,13 +32,13 @@
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/leds.h>
-#include <linux/memblock.h>
 #include <media/soc_camera.h>
 #include <sound/tlv320aic32x4.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/system_info.h>
+#include <asm/memblock.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
@@ -233,10 +233,8 @@ static void __init visstrim_camera_init(void)
 static void __init visstrim_reserve(void)
 {
         /* reserve 4 MiB for mx2-camera */
-        mx2_camera_base = memblock_alloc(MX2_CAMERA_BUF_SIZE,
+        mx2_camera_base = arm_memblock_steal(3 * MX2_CAMERA_BUF_SIZE,
                         MX2_CAMERA_BUF_SIZE);
-        memblock_free(mx2_camera_base, MX2_CAMERA_BUF_SIZE);
-        memblock_remove(mx2_camera_base, MX2_CAMERA_BUF_SIZE);
 }
 
 /* GPIOs used as events for applications */
@@ -405,6 +403,47 @@ static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = {
         .flags                  = IMX_SSI_DMA | IMX_SSI_SYN,
 };
 
+/* coda */
+
+static void __init visstrim_coda_init(void)
+{
+        struct platform_device *pdev;
+        int dma;
+
+        pdev = imx27_add_coda();
+        dma = dma_declare_coherent_memory(&pdev->dev,
+                                          mx2_camera_base + MX2_CAMERA_BUF_SIZE,
+                                          mx2_camera_base + MX2_CAMERA_BUF_SIZE,
+                                          MX2_CAMERA_BUF_SIZE,
+                                          DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+        if (!(dma & DMA_MEMORY_MAP))
+                return;
+}
+
+/* DMA deinterlace */
+static struct platform_device visstrim_deinterlace = {
+        .name = "m2m-deinterlace",
+        .id = 0,
+};
+
+static void __init visstrim_deinterlace_init(void)
+{
+        int ret = -ENOMEM;
+        struct platform_device *pdev = &visstrim_deinterlace;
+        int dma;
+
+        ret = platform_device_register(pdev);
+
+        dma = dma_declare_coherent_memory(&pdev->dev,
+                                          mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
+                                          mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
+                                          MX2_CAMERA_BUF_SIZE,
+                                          DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+        if (!(dma & DMA_MEMORY_MAP))
+                return;
+}
+
+
 static void __init visstrim_m10_revision(void)
 {
         int exp_version = 0;
@@ -467,7 +506,9 @@ static void __init visstrim_m10_board_init(void)
         platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0,
                                       &iclink_tvp5150, sizeof(iclink_tvp5150));
         gpio_led_register_device(0, &visstrim_m10_led_data);
+        visstrim_deinterlace_init();
         visstrim_camera_init();
+        visstrim_coda_init();
 }
 
 static void __init visstrim_m10_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 36979d3dfe34..47c91f7185d2 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -23,8 +23,9 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/phy.h>
+#include <linux/regmap.h>
 #include <linux/micrel_phy.h>
-#include <linux/mfd/anatop.h>
+#include <linux/mfd/syscon.h>
 #include <asm/cpuidle.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -118,20 +119,7 @@ static void __init imx6q_sabrelite_init(void)
 
 static void __init imx6q_usb_init(void)
 {
-        struct device_node *np;
-        struct platform_device *pdev = NULL;
-        struct anatop *adata = NULL;
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
-        if (np)
-                pdev = of_find_device_by_node(np);
-        if (pdev)
-                adata = platform_get_drvdata(pdev);
-        if (!adata) {
-                if (np)
-                        of_node_put(np);
-                return;
-        }
+        struct regmap *anatop;
 
 #define HW_ANADIG_USB1_CHRG_DETECT              0x000001b0
 #define HW_ANADIG_USB2_CHRG_DETECT              0x00000210
@@ -139,20 +127,21 @@ static void __init imx6q_usb_init(void)
 #define BM_ANADIG_USB_CHRG_DETECT_EN_B          0x00100000
 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B    0x00080000
 
-        /*
-         * The external charger detector needs to be disabled,
-         * or the signal at DP will be poor
-         */
-        anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT,
-                        BM_ANADIG_USB_CHRG_DETECT_EN_B
-                        | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
-                        ~0);
-        anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT,
-                        BM_ANADIG_USB_CHRG_DETECT_EN_B |
-                        BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
-                        ~0);
-
-        of_node_put(np);
+        anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
+        if (!IS_ERR(anatop)) {
+                /*
+                 * The external charger detector needs to be disabled,
+                 * or the signal at DP will be poor
+                 */
+                regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT,
+                                BM_ANADIG_USB_CHRG_DETECT_EN_B
+                                | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
+                regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT,
+                                BM_ANADIG_USB_CHRG_DETECT_EN_B |
+                                BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
+        } else {
+                pr_warn("failed to find fsl,imx6q-anatop regmap\n");
+        }
 }
 
 static void __init imx6q_init_machine(void)
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index 899561d8db28..c3ff21b5ea24 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,3 +1,6 @@
+#include <linux/amba/serial.h>
+extern struct amba_pl010_data integrator_uart_data;
 void integrator_init_early(void);
+int integrator_init(bool is_cp);
 void integrator_reserve(void);
 void integrator_restart(char, const char *);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index dad3cb74ed31..ea22a17246d7 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -32,7 +32,9 @@
 #include <asm/mach/time.h>
 #include <asm/pgtable.h>
 
-static struct amba_pl010_data integrator_uart_data;
+#include "common.h"
+
+#ifdef CONFIG_ATAGS
 
 #define INTEGRATOR_RTC_IRQ      { IRQ_RTCINT }
 #define INTEGRATOR_UART0_IRQ    { IRQ_UARTINT0 }
@@ -60,7 +62,7 @@ static struct amba_device *amba_devs[] __initdata = {
         &kmi1_device,
 };
 
-static int __init integrator_init(void)
+int __init integrator_init(bool is_cp)
 {
         int i;
 
@@ -69,7 +71,7 @@ static int __init integrator_init(void)
          * hard-code them. The Integator/CP and forward have proper cell IDs.
          * Else we leave them undefined to the bus driver can autoprobe them.
          */
-        if (machine_is_integrator()) {
+        if (!is_cp) {
                 rtc_device.periphid     = 0x00041030;
                 uart0_device.periphid   = 0x00041010;
                 uart1_device.periphid   = 0x00041010;
@@ -85,7 +87,7 @@ static int __init integrator_init(void)
         return 0;
 }
 
-arch_initcall(integrator_init);
+#endif
 
 /*
  * On the Integrator platform, the port RTS and DTR are provided by
@@ -100,11 +102,14 @@ arch_initcall(integrator_init);
 static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
 {
         unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
+        u32 phybase = dev->res.start;
 
-        if (dev == &uart0_device) {
+        if (phybase == INTEGRATOR_UART0_BASE) {
+                /* UART0 */
                 rts_mask = 1 << 4;
                 dtr_mask = 1 << 5;
         } else {
+                /* UART1 */
                 rts_mask = 1 << 6;
                 dtr_mask = 1 << 7;
         }
@@ -123,7 +128,7 @@ static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *bas
         __raw_writel(ctrlc, SC_CTRLC);
 }
 
-static struct amba_pl010_data integrator_uart_data = {
+struct amba_pl010_data integrator_uart_data = {
         .set_mctrl = integrator_uart_set_mctrl,
 };
 
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 2215d96cd735..d5b5435a09ae 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -34,6 +34,9 @@
 #include <linux/mtd/physmap.h>
 #include <linux/clk.h>
 #include <linux/platform_data/clk-integrator.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
 #include <video/vga.h>
 
 #include <mach/hardware.h>
@@ -158,23 +161,6 @@ static void __init ap_map_io(void)
         pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
 }
 
-#define INTEGRATOR_SC_VALID_INT 0x003fffff
-
-static void __init ap_init_irq(void)
-{
-        /* Disable all interrupts initially. */
-        /* Do the core module ones */
-        writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
-
-        /* do the header card stuff next */
-        writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
-        writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
-
-        fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
-                -1, INTEGRATOR_SC_VALID_INT, NULL);
-        integrator_clk_init(false);
-}
-
 #ifdef CONFIG_PM
 static unsigned long ic_irq_enable;
 
@@ -267,50 +253,6 @@ static struct physmap_flash_data ap_flash_data = {
         .set_vpp        = ap_flash_set_vpp,
 };
 
-static struct resource cfi_flash_resource = {
-        .start          = INTEGRATOR_FLASH_BASE,
-        .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device cfi_flash_device = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &ap_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &cfi_flash_resource,
-};
-
-static void __init ap_init(void)
-{
-        unsigned long sc_dec;
-        int i;
-
-        platform_device_register(&cfi_flash_device);
-
-        sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
-        for (i = 0; i < 4; i++) {
-                struct lm_device *lmdev;
-
-                if ((sc_dec & (16 << i)) == 0)
-                        continue;
-
-                lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
-                if (!lmdev)
-                        continue;
-
-                lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
-                lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
-                lmdev->resource.flags = IORESOURCE_MEM;
-                lmdev->irq = IRQ_AP_EXPINT0 + i;
-                lmdev->id = i;
-
-                lm_device_register(lmdev);
-        }
-}
-
 /*
  * Where is the timer (VA)?
  */
@@ -325,9 +267,9 @@ static u32 notrace integrator_read_sched_clock(void)
         return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
 }
 
-static void integrator_clocksource_init(unsigned long inrate)
+static void integrator_clocksource_init(unsigned long inrate,
+                                        void __iomem *base)
 {
-        void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
         u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
         unsigned long rate = inrate;
 
@@ -344,7 +286,7 @@ static void integrator_clocksource_init(unsigned long inrate)
         setup_sched_clock(integrator_read_sched_clock, 16, rate);
 }
 
-static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
+static void __iomem * clkevt_base;
 
 /*
  * IRQ handler for the timer
@@ -416,11 +358,13 @@ static struct irqaction integrator_timer_irq = {
         .dev_id         = &integrator_clockevent,
 };
 
-static void integrator_clockevent_init(unsigned long inrate)
+static void integrator_clockevent_init(unsigned long inrate,
+                                void __iomem *base, int irq)
 {
         unsigned long rate = inrate;
         unsigned int ctrl = 0;
 
+        clkevt_base = base;
         /* Calculate and program a divisor */
         if (rate > 0x100000 * HZ) {
                 rate /= 256;
@@ -432,7 +376,7 @@ static void integrator_clockevent_init(unsigned long inrate)
         timer_reload = rate / HZ;
         writel(ctrl, clkevt_base + TIMER_CTRL);
 
-        setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
+        setup_irq(irq, &integrator_timer_irq);
         clockevents_config_and_register(&integrator_clockevent,
                                         rate,
                                         1,
@@ -443,9 +387,153 @@ void __init ap_init_early(void)
 {
 }
 
+#ifdef CONFIG_OF
+
+static void __init ap_init_timer_of(void)
+{
+        struct device_node *node;
+        const char *path;
+        void __iomem *base;
+        int err;
+        int irq;
+        struct clk *clk;
+        unsigned long rate;
+
+        clk = clk_get_sys("ap_timer", NULL);
+        BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
+        rate = clk_get_rate(clk);
+
+        err = of_property_read_string(of_aliases,
+                                "arm,timer-primary", &path);
+        if (WARN_ON(err))
+                return;
+        node = of_find_node_by_path(path);
+        base = of_iomap(node, 0);
+        if (WARN_ON(!base))
+                return;
+        writel(0, base + TIMER_CTRL);
+        integrator_clocksource_init(rate, base);
+
+        err = of_property_read_string(of_aliases,
+                                "arm,timer-secondary", &path);
+        if (WARN_ON(err))
+                return;
+        node = of_find_node_by_path(path);
+        base = of_iomap(node, 0);
+        if (WARN_ON(!base))
+                return;
+        irq = irq_of_parse_and_map(node, 0);
+        writel(0, base + TIMER_CTRL);
+        integrator_clockevent_init(rate, base, irq);
+}
+
+static struct sys_timer ap_of_timer = {
+        .init           = ap_init_timer_of,
+};
+
+static const struct of_device_id fpga_irq_of_match[] __initconst = {
+        { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
+        { /* Sentinel */ }
+};
+
+static void __init ap_init_irq_of(void)
+{
+        /* disable core module IRQs */
+        writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
+        of_irq_init(fpga_irq_of_match);
+        integrator_clk_init(false);
+}
+
+/* For the Device Tree, add in the UART callbacks as AUXDATA */
+static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
+                "rtc", NULL),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
+                "uart0", &integrator_uart_data),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
+                "uart1", &integrator_uart_data),
+        OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
+                "kmi0", NULL),
+        OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
+                "kmi1", NULL),
+        OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
+                "physmap-flash", &ap_flash_data),
+        { /* sentinel */ },
+};
+
+static void __init ap_init_of(void)
+{
+        unsigned long sc_dec;
+        int i;
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        ap_auxdata_lookup, NULL);
+
+        sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
+        for (i = 0; i < 4; i++) {
+                struct lm_device *lmdev;
+
+                if ((sc_dec & (16 << i)) == 0)
+                        continue;
+
+                lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
+                if (!lmdev)
+                        continue;
+
+                lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
+                lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
+                lmdev->resource.flags = IORESOURCE_MEM;
+                lmdev->irq = IRQ_AP_EXPINT0 + i;
+                lmdev->id = i;
+
+                lm_device_register(lmdev);
+        }
+}
+
+static const char * ap_dt_board_compat[] = {
+        "arm,integrator-ap",
+        NULL,
+};
+
+DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
+        .reserve        = integrator_reserve,
+        .map_io         = ap_map_io,
+        .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
+        .init_early     = ap_init_early,
+        .init_irq       = ap_init_irq_of,
+        .handle_irq     = fpga_handle_irq,
+        .timer          = &ap_of_timer,
+        .init_machine   = ap_init_of,
+        .restart        = integrator_restart,
+        .dt_compat      = ap_dt_board_compat,
+MACHINE_END
+
+#endif
+
+#ifdef CONFIG_ATAGS
+
 /*
- * Set up timer(s).
+ * This is where non-devicetree initialization code is collected and stashed
+ * for eventual deletion.
  */
+
+static struct resource cfi_flash_resource = {
+        .start          = INTEGRATOR_FLASH_BASE,
+        .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device cfi_flash_device = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &ap_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &cfi_flash_resource,
+};
+
 static void __init ap_init_timer(void)
 {
         struct clk *clk;
@@ -460,14 +548,62 @@ static void __init ap_init_timer(void)
         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 
-        integrator_clocksource_init(rate);
-        integrator_clockevent_init(rate);
+        integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
+        integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
+                                IRQ_TIMERINT1);
 }
 
 static struct sys_timer ap_timer = {
         .init           = ap_init_timer,
 };
 
+#define INTEGRATOR_SC_VALID_INT 0x003fffff
+
+static void __init ap_init_irq(void)
+{
+        /* Disable all interrupts initially. */
+        /* Do the core module ones */
+        writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
+
+        /* do the header card stuff next */
+        writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
+        writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
+
+        fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
+                -1, INTEGRATOR_SC_VALID_INT, NULL);
+        integrator_clk_init(false);
+}
+
+static void __init ap_init(void)
+{
+        unsigned long sc_dec;
+        int i;
+
+        platform_device_register(&cfi_flash_device);
+
+        sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
+        for (i = 0; i < 4; i++) {
+                struct lm_device *lmdev;
+
+                if ((sc_dec & (16 << i)) == 0)
+                        continue;
+
+                lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
+                if (!lmdev)
+                        continue;
+
+                lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
+                lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
+                lmdev->resource.flags = IORESOURCE_MEM;
+                lmdev->irq = IRQ_AP_EXPINT0 + i;
+                lmdev->id = i;
+
+                lm_device_register(lmdev);
+        }
+
+        integrator_init(false);
+}
+
 MACHINE_START(INTEGRATOR, "ARM-Integrator")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
         .atag_offset    = 0x100,
@@ -481,3 +617,5 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
         .init_machine   = ap_init,
         .restart        = integrator_restart,
 MACHINE_END
+
+#endif
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 3df5fc369361..6870a1fbcd78 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -23,6 +23,9 @@
 #include <linux/gfp.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_data/clk-integrator.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -49,16 +52,9 @@
 #include "common.h"
 
 #define INTCP_PA_FLASH_BASE             0x24000000
-#define INTCP_FLASH_SIZE                SZ_32M
 
 #define INTCP_PA_CLCD_BASE              0xc0000000
 
-#define INTCP_VA_CIC_BASE               __io_address(INTEGRATOR_HDR_BASE + 0x40)
-#define INTCP_VA_PIC_BASE               __io_address(INTEGRATOR_IC_BASE)
-#define INTCP_VA_SIC_BASE               __io_address(INTEGRATOR_CP_SIC_BASE)
-
-#define INTCP_ETH_SIZE                  0x10
-
 #define INTCP_VA_CTRL_BASE              __io_address(INTEGRATOR_CP_CTL_BASE)
 #define INTCP_FLASHPROG                 0x04
 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
@@ -143,37 +139,6 @@ static void __init intcp_map_io(void)
         iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
 }
 
-static void __init intcp_init_irq(void)
-{
-        u32 pic_mask, cic_mask, sic_mask;
-
-        /* These masks are for the HW IRQ registers */
-        pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
-        pic_mask |= (~((~0u) << (29 - 22))) << 22;
-        cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
-        sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
-
-        /*
-         * Disable all interrupt sources
-         */
-        writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
-        writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
-        writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
-        writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
-        writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
-        writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
-
-        fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
-                      -1, pic_mask, NULL);
-
-        fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
-                      -1, cic_mask, NULL);
-
-        fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
-                      IRQ_CP_CPPLDINT, sic_mask, NULL);
-        integrator_clk_init(true);
-}
-
 /*
  * Flash handling.
  */
@@ -216,47 +181,6 @@ static struct physmap_flash_data intcp_flash_data = {
         .set_vpp        = intcp_flash_set_vpp,
 };
 
-static struct resource intcp_flash_resource = {
-        .start          = INTCP_PA_FLASH_BASE,
-        .end            = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device intcp_flash_device = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &intcp_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &intcp_flash_resource,
-};
-
-static struct resource smc91x_resources[] = {
-        [0] = {
-                .start  = INTEGRATOR_CP_ETH_BASE,
-                .end    = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_CP_ETHINT,
-                .end    = IRQ_CP_ETHINT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device smc91x_device = {
-        .name           = "smc91x",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(smc91x_resources),
-        .resource       = smc91x_resources,
-};
-
-static struct platform_device *intcp_devs[] __initdata = {
-        &intcp_flash_device,
-        &smc91x_device,
-};
-
 /*
  * It seems that the card insertion interrupt remains active after
  * we've acknowledged it.  We therefore ignore the interrupt, and
@@ -278,16 +202,6 @@ static struct mmci_platform_data mmc_data = {
         .gpio_cd        = -1,
 };
 
-#define INTEGRATOR_CP_MMC_IRQS  { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
-#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
-
-static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
-        INTEGRATOR_CP_MMC_IRQS, &mmc_data);
-
-static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
-        INTEGRATOR_CP_AACI_IRQS, NULL);
-
-
 /*
  * CLCD support
  */
@@ -338,15 +252,6 @@ static struct clcd_board clcd_data = {
         .remove         = versatile_clcd_remove_dma,
 };
 
-static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
-        { IRQ_CP_CLCDCINT }, &clcd_data);
-
-static struct amba_device *amba_devs[] __initdata = {
-        &mmc_device,
-        &aaci_device,
-        &clcd_device,
-};
-
 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
 
 static void __init intcp_init_early(void)
@@ -356,16 +261,193 @@ static void __init intcp_init_early(void)
 #endif
 }
 
-static void __init intcp_init(void)
+static void __init intcp_timer_init_of(void)
 {
-        int i;
+        struct device_node *node;
+        const char *path;
+        void __iomem *base;
+        int err;
+        int irq;
+
+        err = of_property_read_string(of_aliases,
+                                "arm,timer-primary", &path);
+        if (WARN_ON(err))
+                return;
+        node = of_find_node_by_path(path);
+        base = of_iomap(node, 0);
+        if (WARN_ON(!base))
+                return;
+        writel(0, base + TIMER_CTRL);
+        sp804_clocksource_init(base, node->name);
+
+        err = of_property_read_string(of_aliases,
+                                "arm,timer-secondary", &path);
+        if (WARN_ON(err))
+                return;
+        node = of_find_node_by_path(path);
+        base = of_iomap(node, 0);
+        if (WARN_ON(!base))
+                return;
+        irq = irq_of_parse_and_map(node, 0);
+        writel(0, base + TIMER_CTRL);
+        sp804_clockevents_init(base, irq, node->name);
+}
 
-        platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
+static struct sys_timer cp_of_timer = {
+        .init           = intcp_timer_init_of,
+};
 
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-                struct amba_device *d = amba_devs[i];
-                amba_device_register(d, &iomem_resource);
-        }
+#ifdef CONFIG_OF
+
+static const struct of_device_id fpga_irq_of_match[] __initconst = {
+        { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
+        { /* Sentinel */ }
+};
+
+static void __init intcp_init_irq_of(void)
+{
+        of_irq_init(fpga_irq_of_match);
+        integrator_clk_init(true);
+}
+
+/*
+ * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
+ * and enforce the bus names since these are used for clock lookups.
+ */
+static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
+                "rtc", NULL),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
+                "uart0", &integrator_uart_data),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
+                "uart1", &integrator_uart_data),
+        OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
+                "kmi0", NULL),
+        OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
+                "kmi1", NULL),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
+                "mmci", &mmc_data),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
+                "aaci", &mmc_data),
+        OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
+                "clcd", &clcd_data),
+        OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
+                "physmap-flash", &intcp_flash_data),
+        { /* sentinel */ },
+};
+
+static void __init intcp_init_of(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        intcp_auxdata_lookup, NULL);
+}
+
+static const char * intcp_dt_board_compat[] = {
+        "arm,integrator-cp",
+        NULL,
+};
+
+DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
+        .reserve        = integrator_reserve,
+        .map_io         = intcp_map_io,
+        .nr_irqs        = NR_IRQS_INTEGRATOR_CP,
+        .init_early     = intcp_init_early,
+        .init_irq       = intcp_init_irq_of,
+        .handle_irq     = fpga_handle_irq,
+        .timer          = &cp_of_timer,
+        .init_machine   = intcp_init_of,
+        .restart        = integrator_restart,
+        .dt_compat      = intcp_dt_board_compat,
+MACHINE_END
+
+#endif
+
+#ifdef CONFIG_ATAGS
+
+/*
+ * This is where non-devicetree initialization code is collected and stashed
+ * for eventual deletion.
+ */
+
+#define INTCP_FLASH_SIZE                SZ_32M
+
+static struct resource intcp_flash_resource = {
+        .start          = INTCP_PA_FLASH_BASE,
+        .end            = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device intcp_flash_device = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &intcp_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &intcp_flash_resource,
+};
+
+#define INTCP_ETH_SIZE                  0x10
+
+static struct resource smc91x_resources[] = {
+        [0] = {
+                .start  = INTEGRATOR_CP_ETH_BASE,
+                .end    = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_CP_ETHINT,
+                .end    = IRQ_CP_ETHINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device smc91x_device = {
+        .name           = "smc91x",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(smc91x_resources),
+        .resource       = smc91x_resources,
+};
+
+static struct platform_device *intcp_devs[] __initdata = {
+        &intcp_flash_device,
+        &smc91x_device,
+};
+
+#define INTCP_VA_CIC_BASE               __io_address(INTEGRATOR_HDR_BASE + 0x40)
+#define INTCP_VA_PIC_BASE               __io_address(INTEGRATOR_IC_BASE)
+#define INTCP_VA_SIC_BASE               __io_address(INTEGRATOR_CP_SIC_BASE)
+
+static void __init intcp_init_irq(void)
+{
+        u32 pic_mask, cic_mask, sic_mask;
+
+        /* These masks are for the HW IRQ registers */
+        pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
+        pic_mask |= (~((~0u) << (29 - 22))) << 22;
+        cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
+        sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
+
+        /*
+         * Disable all interrupt sources
+         */
+        writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
+        writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
+        writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
+        writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
+        writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
+        writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
+
+        fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
+                      -1, pic_mask, NULL);
+
+        fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
+                      -1, cic_mask, NULL);
+
+        fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
+                      IRQ_CP_CPPLDINT, sic_mask, NULL);
+
+        integrator_clk_init(true);
 }
 
 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
@@ -386,6 +468,37 @@ static struct sys_timer cp_timer = {
         .init           = intcp_timer_init,
 };
 
+#define INTEGRATOR_CP_MMC_IRQS  { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
+#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
+
+static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
+        INTEGRATOR_CP_MMC_IRQS, &mmc_data);
+
+static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
+        INTEGRATOR_CP_AACI_IRQS, NULL);
+
+static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
+        { IRQ_CP_CLCDCINT }, &clcd_data);
+
+static struct amba_device *amba_devs[] __initdata = {
+        &mmc_device,
+        &aaci_device,
+        &clcd_device,
+};
+
+static void __init intcp_init(void)
+{
+        int i;
+
+        platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
+
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+                struct amba_device *d = amba_devs[i];
+                amba_device_register(d, &iomem_resource);
+        }
+        integrator_init(true);
+}
+
 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
         .atag_offset    = 0x100,
@@ -399,3 +512,5 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
         .init_machine   = intcp_init,
         .restart        = integrator_restart,
 MACHINE_END
+
+#endif
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index ca5c15a4e626..50bca5032b7e 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -94,6 +94,13 @@ config MACH_TS219_DT
           or MV6282. If you have the wrong one, the buttons will not
           work.
 
+config MACH_DOCKSTAR_DT
+        bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Seagate FreeAgent Dockstar (Flattened Device Tree).
+
 config MACH_GOFLEXNET_DT
         bool "Seagate GoFlex Net (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
@@ -109,6 +116,20 @@ config MACH_LSXL_DT
           Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
           Flattened Device Tree.
 
+config MACH_IOMEGA_IX2_200_DT
+        bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Iomega StorCenter ix2-200 (Flattened Device Tree).
+
+config MACH_KM_KIRKWOOD_DT
+        bool "Keymile Kirkwood Reference Design (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
+
 config MACH_TS219
         bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
         help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 055c85a1cc46..294779f892d9 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -26,5 +26,8 @@ obj-$(CONFIG_MACH_ICONNECT_DT)		+= board-iconnect.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)    += board-dnskw.o
 obj-$(CONFIG_MACH_IB62X0_DT)            += board-ib62x0.o
 obj-$(CONFIG_MACH_TS219_DT)             += board-ts219.o tsx1x-common.o
+obj-$(CONFIG_MACH_DOCKSTAR_DT)          += board-dockstar.o
 obj-$(CONFIG_MACH_GOFLEXNET_DT)         += board-goflexnet.o
 obj-$(CONFIG_MACH_LSXL_DT)              += board-lsxl.o
+obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)    += board-iomega_ix2_200.o
+obj-$(CONFIG_MACH_KM_KIRKWOOD_DT)       += board-km_kirkwood.o
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index e9a7180863d9..8f0d162a1e1d 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -86,5 +86,6 @@ void __init kirkwood_setup_cpu_mbus(void)
         /*
          * Setup MBUS dram target info.
          */
-        orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
+        orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                    (void __iomem *) DDR_WINDOW_CPU_BASE);
 }
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index 4ab35065a144..43d16d6714b8 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -14,18 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/of.h>
 #include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/gpio-fan.h>
-#include <linux/leds.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/kirkwood.h>
-#include <mach/bridge-regs.h>
 #include "common.h"
 #include "mpp.h"
 
@@ -67,29 +57,6 @@ static unsigned int dnskw_mpp_config[] __initdata = {
         0
 };
 
-/* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
-static struct gpio_fan_speed dnskw_fan_speed[] = {
-        {    0,  0 },
-        { 3000,  1 },
-        { 6000,  2 },
-};
-static unsigned dnskw_fan_pins[] = {46, 45};
-
-static struct gpio_fan_platform_data dnskw_fan_data = {
-        .num_ctrl       = ARRAY_SIZE(dnskw_fan_pins),
-        .ctrl           = dnskw_fan_pins,
-        .num_speed      = ARRAY_SIZE(dnskw_fan_speed),
-        .speed          = dnskw_fan_speed,
-};
-
-static struct platform_device dnskw_fan_device = {
-        .name   = "gpio-fan",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &dnskw_fan_data,
-        },
-};
-
 static void dnskw_power_off(void)
 {
         gpio_set_value(36, 1);
@@ -114,8 +81,6 @@ void __init dnskw_init(void)
         kirkwood_ehci_init();
         kirkwood_ge00_init(&dnskw_ge00_data);
 
-        platform_device_register(&dnskw_fan_device);
-
         /* Register power-off GPIO. */
         if (gpio_request(36, "dnskw:power:off") == 0
             && gpio_direction_output(36, 0) == 0)
diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c
new file mode 100644
index 000000000000..f2fbb023e679
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-dockstar.c
@@ -0,0 +1,61 @@
+/*
+ * arch/arm/mach-kirkwood/board-dockstar.c
+ *
+ * Seagate FreeAgent Dockstar Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Copied and modified for Seagate GoFlex Net support by
+ * Joshua Coombs <josh.coombs@gmail.com> based on ArchLinux ARM's
+ * GoFlex kernel patches.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
+#include <linux/platform_data/mmc-mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data dockstar_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static unsigned int dockstar_mpp_config[] __initdata = {
+        MPP29_GPIO,     /* USB Power Enable */
+        MPP46_GPIO,     /* LED green */
+        MPP47_GPIO,     /* LED orange */
+        0
+};
+
+void __init dockstar_dt_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(dockstar_mpp_config);
+
+        if (gpio_request(29, "USB Power Enable") != 0 ||
+            gpio_direction_output(29, 1) != 0)
+                pr_err("can't setup GPIO 29 (USB Power Enable)\n");
+        kirkwood_ehci_init();
+
+        kirkwood_ge00_init(&dockstar_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e4eb450de301..70c5a2882409 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -33,6 +33,7 @@ struct of_dev_auxdata kirkwood_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
         OF_DEV_AUXDATA("marvell,orion-sata", 0xf1080000, "sata_mv.0", NULL),
         OF_DEV_AUXDATA("marvell,orion-nand", 0xf4000000, "orion_nand", NULL),
+        OF_DEV_AUXDATA("marvell,orion-crypto", 0xf1030000, "mv_crypto", NULL),
         {},
 };
 
@@ -60,7 +61,6 @@ static void __init kirkwood_dt_init(void)
         /* internal devices that every board has */
         kirkwood_xor0_init();
         kirkwood_xor1_init();
-        kirkwood_crypto_init();
 
 #ifdef CONFIG_KEXEC
         kexec_reinit = kirkwood_enable_pcie;
@@ -81,12 +81,21 @@ static void __init kirkwood_dt_init(void)
         if (of_machine_is_compatible("qnap,ts219"))
                 qnap_dt_ts219_init();
 
+        if (of_machine_is_compatible("seagate,dockstar"))
+                dockstar_dt_init();
+
         if (of_machine_is_compatible("seagate,goflexnet"))
                 goflexnet_init();
 
         if (of_machine_is_compatible("buffalo,lsxl"))
                 lsxl_init();
 
+        if (of_machine_is_compatible("iom,ix2-200"))
+                iomega_ix2_200_init();
+
+        if (of_machine_is_compatible("keymile,km_kirkwood"))
+                km_kirkwood_init();
+
         of_platform_populate(NULL, kirkwood_dt_match_table,
                              kirkwood_auxdata_lookup, NULL);
 }
@@ -98,8 +107,11 @@ static const char *kirkwood_dt_board_compat[] = {
         "iom,iconnect",
         "raidsonic,ib-nas62x0",
         "qnap,ts219",
+        "seagate,dockstar",
         "seagate,goflexnet",
         "buffalo,lsxl",
+        "iom,ix2-200",
+        "keymile,km_kirkwood",
         NULL
 };
 
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index d7a9198ed300..d084b1e2943a 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -16,11 +16,8 @@
 #include <linux/of_fdt.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/mtd/partitions.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
 #include "common.h"
@@ -44,57 +41,12 @@ static unsigned int iconnect_mpp_config[] __initdata = {
         0
 };
 
-static struct mtd_partition iconnect_nand_parts[] = {
-        {
-                .name = "flash",
-                .offset = 0,
-                .size = MTDPART_SIZ_FULL,
-        },
-};
-
-/* yikes... theses are the original input buttons */
-/* but I'm not convinced by the sw event choices  */
-static struct gpio_keys_button iconnect_buttons[] = {
-        {
-                .type           = EV_SW,
-                .code           = SW_LID,
-                .gpio           = 12,
-                .desc           = "Reset Button",
-                .active_low     = 1,
-                .debounce_interval = 100,
-        }, {
-                .type           = EV_SW,
-                .code           = SW_TABLET_MODE,
-                .gpio           = 35,
-                .desc           = "OTB Button",
-                .active_low     = 1,
-                .debounce_interval = 100,
-        },
-};
-
-static struct gpio_keys_platform_data iconnect_button_data = {
-        .buttons        = iconnect_buttons,
-        .nbuttons       = ARRAY_SIZE(iconnect_buttons),
-};
-
-static struct platform_device iconnect_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev        = {
-                .platform_data  = &iconnect_button_data,
-        },
-};
-
 void __init iconnect_init(void)
 {
         kirkwood_mpp_conf(iconnect_mpp_config);
-        kirkwood_nand_init(ARRAY_AND_SIZE(iconnect_nand_parts), 25);
 
         kirkwood_ehci_init();
         kirkwood_ge00_init(&iconnect_ge00_data);
-
-        platform_device_register(&iconnect_button_device);
 }
 
 static int __init iconnect_pci_init(void)
diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
new file mode 100644
index 000000000000..158fb97d0397
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+ *
+ * Iomega StorCenter ix2-200
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_NONE,
+        .speed          = SPEED_1000,
+        .duplex         = DUPLEX_FULL,
+};
+
+static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
+        MPP12_GPIO,                     /* Reset Button */
+        MPP14_GPIO,                     /* Power Button */
+        MPP15_GPIO,                     /* Backup LED (blue) */
+        MPP16_GPIO,                     /* Power LED (white) */
+        MPP35_GPIO,                     /* OTB Button */
+        MPP36_GPIO,                     /* Rebuild LED (white) */
+        MPP37_GPIO,                     /* Health LED (red) */
+        MPP38_GPIO,                     /* SATA LED brightness control 1 */
+        MPP39_GPIO,                     /* SATA LED brightness control 2 */
+        MPP40_GPIO,                     /* Backup LED brightness control 1 */
+        MPP41_GPIO,                     /* Backup LED brightness control 2 */
+        MPP42_GPIO,                     /* Power LED brightness control 1 */
+        MPP43_GPIO,                     /* Power LED brightness control 2 */
+        MPP44_GPIO,                     /* Health LED brightness control 1 */
+        MPP45_GPIO,                     /* Health LED brightness control 2 */
+        MPP46_GPIO,                     /* Rebuild LED brightness control 1 */
+        MPP47_GPIO,                     /* Rebuild LED brightness control 2 */
+        0
+};
+
+void __init iomega_ix2_200_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
+
+        kirkwood_ehci_init();
+
+        kirkwood_ge01_init(&iomega_ix2_200_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c
new file mode 100644
index 000000000000..f7d32834b757
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-km_kirkwood.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2012 2012 KEYMILE AG, CH-3097 Bern
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * arch/arm/mach-kirkwood/board-km_kirkwood.c
+ *
+ * Keymile km_kirkwood Reference Desing Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static unsigned int km_kirkwood_mpp_config[] __initdata = {
+        MPP8_GPIO,      /* I2C SDA */
+        MPP9_GPIO,      /* I2C SCL */
+        0
+};
+
+void __init km_kirkwood_init(void)
+{
+        struct clk *sata_clk;
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(km_kirkwood_mpp_config);
+
+        /*
+         * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
+         * SATA bits (14-15) of the Clock Gating Control Register. Since these
+         * devices are also not present in this variant, their clocks get
+         * disabled because unused when clk_disable_unused() gets called.
+         * That's why we change the flags to these clocks to CLK_IGNORE_UNUSED
+         */
+        sata_clk = clk_get_sys("sata_mv.0", "0");
+        if (!IS_ERR(sata_clk))
+                sata_clk->flags |= CLK_IGNORE_UNUSED;
+        sata_clk = clk_get_sys("sata_mv.0", "1");
+        if (!IS_ERR(sata_clk))
+                sata_clk->flags |= CLK_IGNORE_UNUSED;
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&km_kirkwood_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 5c38c94b79a2..3991077f58a2 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -42,7 +42,7 @@
  ****************************************************************************/
 static struct map_desc kirkwood_io_desc[] __initdata = {
         {
-                .virtual        = KIRKWOOD_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) KIRKWOOD_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
                 .length         = KIRKWOOD_REGS_SIZE,
                 .type           = MT_DEVICE,
@@ -205,8 +205,7 @@ static struct clk *tclk;
 
 static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
 {
-        return clk_register_gate(NULL, name, "tclk", 0,
-                                 (void __iomem *)CLOCK_GATING_CTRL,
+        return clk_register_gate(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
                                  bit_idx, 0, &gating_lock);
 }
 
@@ -215,8 +214,7 @@ static struct clk __init *kirkwood_register_gate_fn(const char *name,
                                                     void (*fn_en)(void),
                                                     void (*fn_dis)(void))
 {
-        return clk_register_gate_fn(NULL, name, "tclk", 0,
-                                    (void __iomem *)CLOCK_GATING_CTRL,
+        return clk_register_gate_fn(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
                                     bit_idx, 0, &gating_lock, fn_en, fn_dis);
 }
 
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 304dd1abfdca..bcffd7ca1ca2 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -82,6 +82,12 @@ void ib62x0_init(void);
 static inline void ib62x0_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_DOCKSTAR_DT
+void dockstar_dt_init(void);
+#else
+static inline void dockstar_dt_init(void) {};
+#endif
+
 #ifdef CONFIG_MACH_GOFLEXNET_DT
 void goflexnet_init(void);
 #else
@@ -94,6 +100,18 @@ void lsxl_init(void);
 static inline void lsxl_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
+void iomega_ix2_200_init(void);
+#else
+static inline void iomega_ix2_200_init(void) {};
+#endif
+
+#ifdef CONFIG_MACH_KM_KIRKWOOD_DT
+void km_kirkwood_init(void);
+#else
+static inline void km_kirkwood_init(void) {};
+#endif
+
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index a115142f8690..5c82b7dce4e2 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -13,37 +13,37 @@
 
 #include <mach/kirkwood.h>
 
-#define CPU_CONFIG              (BRIDGE_VIRT_BASE | 0x0100)
+#define CPU_CONFIG              (BRIDGE_VIRT_BASE + 0x0100)
 #define CPU_CONFIG_ERROR_PROP   0x00000004
 
-#define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
 #define CPU_RESET               0x00000002
 
-#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
 #define WDT_RESET_OUT_EN        0x00000002
 #define SOFT_RESET_OUT_EN       0x00000004
 
-#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
 #define SOFT_RESET              0x00000001
 
-#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
+#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE + 0x0110)
 #define WDT_INT_REQ             0x0008
 
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 
-#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_LOW_OFF       0x0000
 #define IRQ_MASK_LOW_OFF        0x0004
 #define IRQ_CAUSE_HIGH_OFF      0x0010
 #define IRQ_MASK_HIGH_OFF       0x0014
 
-#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
-#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE + 0x0300)
+#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
 
-#define L2_CONFIG_REG           (BRIDGE_VIRT_BASE | 0x0128)
+#define L2_CONFIG_REG           (BRIDGE_VIRT_BASE + 0x0128)
 #define L2_WRITETHROUGH         0x00000010
 
-#define CLOCK_GATING_CTRL       (BRIDGE_VIRT_BASE | 0x11c)
+#define CLOCK_GATING_CTRL       (BRIDGE_VIRT_BASE + 0x11c)
 #define CGC_BIT_GE0             (0)
 #define CGC_BIT_PEX0            (2)
 #define CGC_BIT_USB0            (3)
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index af4f0000dcef..041653a04a9c 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -45,7 +45,7 @@
 #define KIRKWOOD_PCIE_IO_SIZE           SZ_64K
 
 #define KIRKWOOD_REGS_PHYS_BASE         0xf1000000
-#define KIRKWOOD_REGS_VIRT_BASE         0xfed00000
+#define KIRKWOOD_REGS_VIRT_BASE         IOMEM(0xfed00000)
 #define KIRKWOOD_REGS_SIZE              SZ_1M
 
 #define KIRKWOOD_PCIE_MEM_PHYS_BASE     0xe0000000
@@ -59,61 +59,61 @@
 /*
  * Register Map
  */
-#define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
-#define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE | 0x1500)
-#define DDR_OPERATION_BASE      (DDR_VIRT_BASE | 0x1418)
-
-#define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
-#define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
-#define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE | 0x0030)
-#define  DEVICE_ID              (DEV_BUS_VIRT_BASE | 0x0034)
-#define  GPIO_LOW_VIRT_BASE     (DEV_BUS_VIRT_BASE | 0x0100)
-#define  GPIO_HIGH_VIRT_BASE    (DEV_BUS_VIRT_BASE | 0x0140)
-#define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0300)
-#define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0600)
-#define  I2C_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x1000)
-#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
-
-#define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
-#define BRIDGE_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE | 0x20000)
-
-#define CRYPTO_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE | 0x30000)
-
-#define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
-#define PCIE_LINK_CTRL          (PCIE_VIRT_BASE | 0x70)
-#define PCIE_STATUS             (PCIE_VIRT_BASE | 0x1a04)
-#define PCIE1_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x44000)
-#define PCIE1_LINK_CTRL         (PCIE1_VIRT_BASE | 0x70)
-#define PCIE1_STATUS            (PCIE1_VIRT_BASE | 0x1a04)
-
-#define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
-
-#define XOR0_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x60800)
-#define XOR0_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x60800)
-#define XOR1_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x60900)
-#define XOR1_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x60900)
-#define XOR0_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE | 0x60A00)
-#define XOR0_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE | 0x60A00)
-#define XOR1_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE | 0x60B00)
-#define XOR1_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE | 0x60B00)
-
-#define GE00_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
-#define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
-
-#define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
-#define SATA_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x80000)
-#define SATA0_IF_CTRL           (SATA_VIRT_BASE | 0x2050)
-#define SATA0_PHY_MODE_2        (SATA_VIRT_BASE | 0x2330)
-#define SATA1_IF_CTRL           (SATA_VIRT_BASE | 0x4050)
-#define SATA1_PHY_MODE_2        (SATA_VIRT_BASE | 0x4330)
-
-#define SDIO_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
-
-#define AUDIO_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0xA0000)
-#define AUDIO_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0xA0000)
+#define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
+#define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE + 0x1500)
+#define DDR_OPERATION_BASE      (DDR_VIRT_BASE + 0x1418)
+
+#define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
+#define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE + 0x10000)
+#define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE + 0x0030)
+#define  DEVICE_ID              (DEV_BUS_VIRT_BASE + 0x0034)
+#define  GPIO_LOW_VIRT_BASE     (DEV_BUS_VIRT_BASE + 0x0100)
+#define  GPIO_HIGH_VIRT_BASE    (DEV_BUS_VIRT_BASE + 0x0140)
+#define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x0300)
+#define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x0600)
+#define  I2C_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x1000)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2100)
+
+#define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE + 0x20000)
+#define BRIDGE_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
+
+#define CRYPTO_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE + 0x30000)
+
+#define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x40000)
+#define PCIE_LINK_CTRL          (PCIE_VIRT_BASE + 0x70)
+#define PCIE_STATUS             (PCIE_VIRT_BASE + 0x1a04)
+#define PCIE1_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE + 0x44000)
+#define PCIE1_LINK_CTRL         (PCIE1_VIRT_BASE + 0x70)
+#define PCIE1_STATUS            (PCIE1_VIRT_BASE + 0x1a04)
+
+#define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE + 0x50000)
+
+#define XOR0_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x60800)
+#define XOR0_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x60800)
+#define XOR1_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x60900)
+#define XOR1_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x60900)
+#define XOR0_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE + 0x60A00)
+#define XOR0_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE + 0x60A00)
+#define XOR1_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE + 0x60B00)
+#define XOR1_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE + 0x60B00)
+
+#define GE00_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x70000)
+#define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x74000)
+
+#define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x80000)
+#define SATA_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x80000)
+#define SATA0_IF_CTRL           (SATA_VIRT_BASE + 0x2050)
+#define SATA0_PHY_MODE_2        (SATA_VIRT_BASE + 0x2330)
+#define SATA1_IF_CTRL           (SATA_VIRT_BASE + 0x4050)
+#define SATA1_PHY_MODE_2        (SATA_VIRT_BASE + 0x4330)
+
+#define SDIO_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x90000)
+
+#define AUDIO_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE + 0xA0000)
+#define AUDIO_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE + 0xA0000)
 
 /*
  * Supported devices and revisions.
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index 20149a7fd280..884703535a0a 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -10,6 +10,7 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <mach/bridge-regs.h>
 #include <plat/orion-gpio.h>
 #include <plat/irq.h>
@@ -30,14 +31,14 @@ static int __initdata gpio1_irqs[4] = {
 
 void __init kirkwood_init_irq(void)
 {
-        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
-        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+        orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
+        orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
 
         /*
          * Initialize gpiolib for GPIOs 0-49.
          */
-        orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_LOW_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 0, 32, GPIO_LOW_VIRT_BASE, 0,
                         IRQ_KIRKWOOD_GPIO_START, gpio0_irqs);
-        orion_gpio_init(NULL, 32, 18, (void __iomem *)GPIO_HIGH_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 32, 18, GPIO_HIGH_VIRT_BASE, 0,
                         IRQ_KIRKWOOD_GPIO_START + 32, gpio1_irqs);
 }
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 532d8acb38f9..ec544918b12c 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -47,8 +47,8 @@ void kirkwood_enable_pcie(void)
 void kirkwood_pcie_id(u32 *dev, u32 *rev)
 {
         kirkwood_enable_pcie();
-        *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
-        *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
+        *dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
+        *rev = orion_pcie_rev(PCIE_VIRT_BASE);
 }
 
 struct pcie_port {
@@ -133,7 +133,7 @@ static struct pci_ops pcie_ops = {
 
 static void __init pcie0_ioresources_init(struct pcie_port *pp)
 {
-        pp->base = (void __iomem *)PCIE_VIRT_BASE;
+        pp->base = PCIE_VIRT_BASE;
         pp->irq = IRQ_KIRKWOOD_PCIE;
 
         /*
@@ -147,7 +147,7 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp)
 
 static void __init pcie1_ioresources_init(struct pcie_port *pp)
 {
-        pp->base = (void __iomem *)PCIE1_VIRT_BASE;
+        pp->base = PCIE1_VIRT_BASE;
         pp->irq = IRQ_KIRKWOOD_PCIE1;
 
         /*
@@ -255,11 +255,11 @@ static struct hw_pci kirkwood_pci __initdata = {
         .map_irq        = kirkwood_pcie_map_irq,
 };
 
-static void __init add_pcie_port(int index, unsigned long base)
+static void __init add_pcie_port(int index, void __iomem *base)
 {
         printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
 
-        if (orion_pcie_link_up((void __iomem *)base)) {
+        if (orion_pcie_link_up(base)) {
                 printk(KERN_INFO "link up\n");
                 pcie_port_map[num_pcie_ports++] = index;
         } else
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 5bbca2680442..367a9400f532 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -20,6 +20,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/io.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
@@ -161,7 +162,7 @@ static int __init ts41x_pci_init(void)
                  * (Marvell 88sx7042/sata_mv) is known to stop working
                  * after a few minutes.
                  */
-                orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
+                orion_pcie_reset(PCIE_VIRT_BASE);
 
                 kirkwood_pcie_id(&dev, &rev);
                 if (dev == MV88F6282_DEV_ID)
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index a344a373928b..2448fcf09eb1 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -37,8 +37,8 @@
 #include "devices.h"
 #include "common.h"
 
-static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
-static const unsigned        qsd8x50_surf_smc91x_gpio __initdata = 156;
+static const resource_size_t qsd8x50_surf_smc91x_base __initconst = 0x70000300;
+static const unsigned        qsd8x50_surf_smc91x_gpio __initconst = 156;
 
 /* Leave smc91x resources empty here, as we'll fill them in
  * at run-time: they vary from board to board, and the true
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 137e479d15a0..343c435b4176 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -48,7 +48,7 @@ static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, i
          * so we don't need to take that into account here.
          */
 
-        return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
+        return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);
 }
 
 /*
@@ -72,10 +72,10 @@ void __init mv78xx0_setup_cpu_mbus(void)
          */
         if (mv78xx0_core_index() == 0)
                 orion_setup_cpu_mbus_target(&addr_map_cfg,
-                                            DDR_WINDOW_CPU0_BASE);
+                                            (void __iomem *) DDR_WINDOW_CPU0_BASE);
         else
                 orion_setup_cpu_mbus_target(&addr_map_cfg,
-                                            DDR_WINDOW_CPU1_BASE);
+                                            (void __iomem *) DDR_WINDOW_CPU1_BASE);
 }
 
 void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index a6f3cd21e8c2..131cd4883f3d 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -130,12 +130,12 @@ static int get_tclk(void)
  ****************************************************************************/
 static struct map_desc mv78xx0_io_desc[] __initdata = {
         {
-                .virtual        = MV78XX0_CORE_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
                 .pfn            = 0,
                 .length         = MV78XX0_CORE_REGS_SIZE,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = MV78XX0_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) MV78XX0_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
                 .length         = MV78XX0_REGS_SIZE,
                 .type           = MT_DEVICE,
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
index eb187e0e059b..5f03484584d4 100644
--- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
@@ -11,18 +11,18 @@
 
 #include <mach/mv78xx0.h>
 
-#define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
 #define L2_WRITETHROUGH         0x00020000
 
-#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
 #define SOFT_RESET_OUT_EN       0x00000004
 
-#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
 #define SOFT_RESET              0x00000001
 
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 
-#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_ERR_OFF       0x0000
 #define IRQ_CAUSE_LOW_OFF       0x0004
 #define IRQ_CAUSE_HIGH_OFF      0x0008
@@ -30,7 +30,7 @@
 #define IRQ_MASK_LOW_OFF        0x0010
 #define IRQ_MASK_HIGH_OFF       0x0014
 
-#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
-#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE + 0x0300)
+#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
 
 #endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index bd03fed1128e..46200a183cf2 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -41,7 +41,7 @@
  */
 #define MV78XX0_CORE0_REGS_PHYS_BASE    0xf1020000
 #define MV78XX0_CORE1_REGS_PHYS_BASE    0xf1024000
-#define MV78XX0_CORE_REGS_VIRT_BASE     0xfe400000
+#define MV78XX0_CORE_REGS_VIRT_BASE     IOMEM(0xfe400000)
 #define MV78XX0_CORE_REGS_PHYS_BASE     0xfe400000
 #define MV78XX0_CORE_REGS_SIZE          SZ_16K
 
@@ -49,7 +49,7 @@
 #define MV78XX0_PCIE_IO_SIZE            SZ_1M
 
 #define MV78XX0_REGS_PHYS_BASE          0xf1000000
-#define MV78XX0_REGS_VIRT_BASE          0xfd000000
+#define MV78XX0_REGS_VIRT_BASE          IOMEM(0xfd000000)
 #define MV78XX0_REGS_SIZE               SZ_1M
 
 #define MV78XX0_PCIE_MEM_PHYS_BASE      0xc0000000
@@ -64,47 +64,47 @@
 /*
  * Register Map
  */
-#define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE | 0x00000)
-#define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE | 0x1500)
-#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE | 0x1570)
-
-#define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE | 0x10000)
-#define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x10000)
-#define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE | 0x0030)
-#define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE | 0x0034)
-#define  GPIO_VIRT_BASE         (DEV_BUS_VIRT_BASE | 0x0100)
-#define  I2C_0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1000)
-#define  I2C_1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1100)
-#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
-#define  UART2_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2200)
-#define  UART2_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2200)
-#define  UART3_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2300)
-#define  UART3_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2300)
-
-#define GE10_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x30000)
-#define GE11_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x34000)
-
-#define PCIE00_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x40000)
-#define PCIE01_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x44000)
-#define PCIE02_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x48000)
-#define PCIE03_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x4c000)
-
-#define USB0_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x50000)
-#define USB1_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x51000)
-#define USB2_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x52000)
-
-#define GE00_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x70000)
-#define GE01_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x74000)
-
-#define PCIE10_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x80000)
-#define PCIE11_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x84000)
-#define PCIE12_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x88000)
-#define PCIE13_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x8c000)
-
-#define SATA_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0xa0000)
+#define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE + 0x00000)
+#define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE + 0x1500)
+#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE + 0x1570)
+
+#define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE + 0x10000)
+#define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE + 0x10000)
+#define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE + 0x0030)
+#define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE + 0x0034)
+#define  GPIO_VIRT_BASE         (DEV_BUS_VIRT_BASE + 0x0100)
+#define  I2C_0_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x1000)
+#define  I2C_1_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x1100)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2100)
+#define  UART2_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2200)
+#define  UART2_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2200)
+#define  UART3_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2300)
+#define  UART3_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2300)
+
+#define GE10_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x30000)
+#define GE11_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x34000)
+
+#define PCIE00_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x40000)
+#define PCIE01_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x44000)
+#define PCIE02_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x48000)
+#define PCIE03_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x4c000)
+
+#define USB0_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x50000)
+#define USB1_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x51000)
+#define USB2_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x52000)
+
+#define GE00_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x70000)
+#define GE01_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x74000)
+
+#define PCIE10_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x80000)
+#define PCIE11_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x84000)
+#define PCIE12_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x88000)
+#define PCIE13_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x8c000)
+
+#define SATA_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0xa0000)
 
 /*
  * Supported devices and revisions.
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index 4d720f2aedba..32073444024b 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -10,6 +10,7 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <mach/bridge-regs.h>
 #include <plat/orion-gpio.h>
 #include <plat/irq.h>
@@ -24,16 +25,16 @@ static int __initdata gpio0_irqs[4] = {
 
 void __init mv78xx0_init_irq(void)
 {
-        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
-        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
-        orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
+        orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
+        orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
+        orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
 
         /*
          * Initialize gpiolib for GPIOs 0-31.  (The GPIO interrupt mask
          * registers for core #1 are at an offset of 0x18 from those of
          * core #0.)
          */
-        orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE,
+        orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE,
                         mv78xx0_core_index() ? 0x18 : 0,
                         IRQ_MV78XX0_GPIO_START, gpio0_irqs);
 }
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index 26a059b4f472..a9a154a646dd 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -34,8 +34,8 @@ static struct resource pcie_io_space;
 
 void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
 {
-        *dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE);
-        *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE);
+        *dev = orion_pcie_dev_id(PCIE00_VIRT_BASE);
+        *rev = orion_pcie_rev(PCIE00_VIRT_BASE);
 }
 
 u32 pcie_port_size[8] = {
@@ -223,11 +223,11 @@ static struct hw_pci mv78xx0_pci __initdata = {
         .map_irq        = mv78xx0_pcie_map_irq,
 };
 
-static void __init add_pcie_port(int maj, int min, unsigned long base)
+static void __init add_pcie_port(int maj, int min, void __iomem *base)
 {
         printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
 
-        if (orion_pcie_link_up((void __iomem *)base)) {
+        if (orion_pcie_link_up(base)) {
                 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
 
                 printk("link up\n");
@@ -235,7 +235,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base)
                 pp->maj = maj;
                 pp->min = min;
                 pp->root_bus_nr = -1;
-                pp->base = (void __iomem *)base;
+                pp->base = base;
                 spin_lock_init(&pp->conf_lock);
                 memset(&pp->res, 0, sizeof(pp->res));
         } else {
@@ -249,7 +249,7 @@ void __init mv78xx0_pcie_init(int init_port0, int init_port1)
 
         if (init_port0) {
                 add_pcie_port(0, 0, PCIE00_VIRT_BASE);
-                if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
+                if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) {
                         add_pcie_port(0, 1, PCIE01_VIRT_BASE);
                         add_pcie_port(0, 2, PCIE02_VIRT_BASE);
                         add_pcie_port(0, 3, PCIE03_VIRT_BASE);
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 7b270358536e..416d46ef7ebd 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -6,6 +6,8 @@ config ARCH_MVEBU
         select GENERIC_IRQ_CHIP
         select IRQ_DOMAIN
         select MULTI_IRQ_HANDLER
+        select PINCTRL
+        select PLAT_ORION
         select SPARSE_IRQ
 
 if ARCH_MVEBU
@@ -13,13 +15,25 @@ if ARCH_MVEBU
 menu "Marvell SOC with device tree"
 
 config MACH_ARMADA_370_XP
-        bool "Marvell Armada 370 and Aramada XP boards"
+        bool
         select ARMADA_370_XP_TIMER
         select CPU_V7
+
+config MACH_ARMADA_370
+        bool "Marvell Armada 370 boards"
+        select MACH_ARMADA_370_XP
+        select PINCTRL_ARMADA_370
         help
+          Say 'Y' here if you want your kernel to support boards based
+          on the Marvell Armada 370 SoC with device tree.
 
-          Say 'Y' here if you want your kernel to support boards based on
-          Marvell Armada 370 or Armada XP with device tree.
+config MACH_ARMADA_XP
+        bool "Marvell Armada XP boards"
+        select MACH_ARMADA_370_XP
+        select PINCTRL_ARMADA_XP
+        help
+          Say 'Y' here if you want your kernel to support boards based
+          on the Marvell Armada XP SoC with device tree.
 
 endmenu
 
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 6ea8998ab8f1..57f996b6aa0e 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,4 +1,5 @@
-ccflags-$(ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+        -I$(srctree)/arch/arm/plat-orion/include
 
 obj-y += system-controller.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o
diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c
new file mode 100644
index 000000000000..fe454a4430be
--- /dev/null
+++ b/arch/arm/mach-mvebu/addr-map.c
@@ -0,0 +1,134 @@
+/*
+ * Address map functions for Marvell 370 / XP SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <plat/addr-map.h>
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define ARMADA_XP_TARGET_DEV_BUS        1
+#define   ARMADA_XP_ATTR_DEV_BOOTROM    0x1D
+#define ARMADA_XP_TARGET_ETH1           3
+#define ARMADA_XP_TARGET_PCIE_0_2       4
+#define ARMADA_XP_TARGET_ETH0           7
+#define ARMADA_XP_TARGET_PCIE_1_3       8
+
+#define ARMADA_370_TARGET_DEV_BUS       1
+#define   ARMADA_370_ATTR_DEV_BOOTROM   0x1D
+#define ARMADA_370_TARGET_PCIE_0        4
+#define ARMADA_370_TARGET_PCIE_1        8
+
+#define ARMADA_WINDOW_8_PLUS_OFFSET       0x90
+#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180
+
+static const struct __initdata orion_addr_map_info
+armada_xp_addr_map_info[] = {
+        /*
+         * Window for the BootROM, needed for SMP on Armada XP
+         */
+        { 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS,
+          ARMADA_XP_ATTR_DEV_BOOTROM, -1 },
+        /* End marker */
+        { -1, 0, 0, 0, 0, 0 },
+};
+
+static const struct __initdata orion_addr_map_info
+armada_370_addr_map_info[] = {
+        /* End marker */
+        { -1, 0, 0, 0, 0, 0 },
+};
+
+static struct of_device_id of_addr_decoding_controller_table[] = {
+        { .compatible = "marvell,armada-addr-decoding-controller" },
+        { /* end of list */ },
+};
+
+static void __iomem *
+armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
+{
+        unsigned int offset;
+
+        /* The register layout is a bit annoying and the below code
+         * tries to cope with it.
+         * - At offset 0x0, there are the registers for the first 8
+         *   windows, with 4 registers of 32 bits per window (ctrl,
+         *   base, remap low, remap high)
+         * - Then at offset 0x80, there is a hole of 0x10 bytes for
+         *   the internal registers base address and internal units
+         *   sync barrier register.
+         * - Then at offset 0x90, there the registers for 12
+         *   windows, with only 2 registers of 32 bits per window
+         *   (ctrl, base).
+         */
+        if (win < 8)
+                offset = (win << 4);
+        else
+                offset = ARMADA_WINDOW_8_PLUS_OFFSET + (win << 3);
+
+        return cfg->bridge_virt_base + offset;
+}
+
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+        .num_wins = 20,
+        .remappable_wins = 8,
+        .win_cfg_base = armada_cfg_base,
+};
+
+static int __init armada_setup_cpu_mbus(void)
+{
+        struct device_node *np;
+        void __iomem *mbus_unit_addr_decoding_base;
+        void __iomem *sdram_addr_decoding_base;
+
+        np = of_find_matching_node(NULL, of_addr_decoding_controller_table);
+        if (!np)
+                return -ENODEV;
+
+        mbus_unit_addr_decoding_base = of_iomap(np, 0);
+        BUG_ON(!mbus_unit_addr_decoding_base);
+
+        sdram_addr_decoding_base =
+                mbus_unit_addr_decoding_base +
+                ARMADA_SDRAM_ADDR_DECODING_OFFSET;
+
+        addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base;
+
+        /*
+         * Disable, clear and configure windows.
+         */
+        if (of_machine_is_compatible("marvell,armadaxp"))
+                orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info);
+        else if (of_machine_is_compatible("marvell,armada370"))
+                orion_config_wins(&addr_map_cfg, armada_370_addr_map_info);
+        else {
+                pr_err("Unsupported SoC\n");
+                return -EINVAL;
+        }
+
+        /*
+         * Setup MBUS dram target info.
+         */
+        orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                    sdram_addr_decoding_base);
+        return 0;
+}
+
+/* Using a early_initcall is needed so that this initialization gets
+ * done before the SMP initialization, which requires the BootROM to
+ * be remapped. */
+early_initcall(armada_setup_cpu_mbus);
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index b46418a8b352..49d791548ad6 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -25,7 +25,7 @@
 
 static struct map_desc armada_370_xp_io_desc[] __initdata = {
         {
-                .virtual        = ARMADA_370_XP_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
                 .length         = ARMADA_370_XP_REGS_SIZE,
                 .type           = MT_DEVICE,
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 25f0ca8d7820..aac9bebc6b03 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -16,7 +16,7 @@
 #define __MACH_ARMADA_370_XP_H
 
 #define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE    0xfeb00000
+#define ARMADA_370_XP_REGS_VIRT_BASE    IOMEM(0xfeb00000)
 #define ARMADA_370_XP_REGS_SIZE         SZ_1M
 
 #endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-mvebu/include/mach/gpio.h b/arch/arm/mach-mvebu/include/mach/gpio.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/gpio.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 0cc54dd553e3..726c02c9c0cd 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -357,6 +357,33 @@ static inline void omap_init_uwire(void) {}
 #endif
 
 
+#define OMAP1_RNG_BASE          0xfffe5000
+
+static struct resource omap1_rng_resources[] = {
+        {
+                .start          = OMAP1_RNG_BASE,
+                .end            = OMAP1_RNG_BASE + 0x4f,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device omap1_rng_device = {
+        .name           = "omap_rng",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(omap1_rng_resources),
+        .resource       = omap1_rng_resources,
+};
+
+static void omap1_init_rng(void)
+{
+        if (!cpu_is_omap16xx())
+                return;
+
+        (void) platform_device_register(&omap1_rng_device);
+}
+
+/*-------------------------------------------------------------------------*/
+
 /*
  * This gets called after board-specific INIT_MACHINE, and initializes most
  * on-chip peripherals accessible on this board (except for few like USB):
@@ -395,6 +422,7 @@ static int __init omap1_init_devices(void)
         omap_init_spi100k();
         omap_init_sti();
         omap_init_uwire();
+        omap1_init_rng();
 
         return 0;
 }
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index aa81593db1af..cdeb9d3ef640 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -141,7 +141,7 @@ static int __init omap1_dm_timer_init(void)
 
                 pdata->set_timer_src = omap1_dm_timer_set_src;
                 pdata->timer_capability = OMAP_TIMER_ALWON |
-                                OMAP_TIMER_NEEDS_RESET;
+                                OMAP_TIMER_NEEDS_RESET | OMAP_TIMER_HAS_DSP_IRQ;
 
                 ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
                 if (ret) {
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 7d6abda3b74e..fe40d9e488c9 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -179,6 +179,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= omap_hwmod_44xx_data.o
 
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)                 += emu.o
+obj-$(CONFIG_HW_PERF_EVENTS)            += pmu.o
 
 obj-$(CONFIG_OMAP_MBOX_FWK)             += mailbox_mach.o
 mailbox_mach-objs                       := mailbox.o
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 3e2d76f05af4..cea3abace815 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -202,7 +202,7 @@ static inline void __init apollon_init_smc91x(void)
                 return;
         }
 
-        clk_enable(gpmc_fck);
+        clk_prepare_enable(gpmc_fck);
         rate = clk_get_rate(gpmc_fck);
 
         eth_cs = APOLLON_ETH_CS;
@@ -246,7 +246,7 @@ static inline void __init apollon_init_smc91x(void)
                 gpmc_cs_free(APOLLON_ETH_CS);
         }
 out:
-        clk_disable(gpmc_fck);
+        clk_disable_unprepare(gpmc_fck);
         clk_put(gpmc_fck);
 }
 
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index f6c48dd764fe..8d04bf851af4 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -265,9 +265,9 @@ static inline void __init h4_init_debug(void)
                 return;
         }
 
-        clk_enable(gpmc_fck);
+        clk_prepare_enable(gpmc_fck);
         rate = clk_get_rate(gpmc_fck);
-        clk_disable(gpmc_fck);
+        clk_disable_unprepare(gpmc_fck);
         clk_put(gpmc_fck);
 
         if (is_gpmc_muxed())
@@ -311,7 +311,7 @@ static inline void __init h4_init_debug(void)
                 gpmc_cs_free(eth_cs);
 
 out:
-        clk_disable(gpmc_fck);
+        clk_disable_unprepare(gpmc_fck);
         clk_put(gpmc_fck);
 }
 
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index e0dd70b9d917..2b012f9d6925 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -171,7 +171,7 @@ static void __init omap4_ehci_init(void)
                 return;
         }
         clk_set_rate(phy_ref_clk, 19200000);
-        clk_enable(phy_ref_clk);
+        clk_prepare_enable(phy_ref_clk);
 
         /* disable the power to the usb hub prior to init and reset phy+hub */
         ret = gpio_request_array(panda_ehci_gpios,
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 3945c5017085..ed85fb898c7f 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -33,6 +33,7 @@
 #include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
+#include <plat/omap-pm.h>
 #include "gpmc-smc91x.h"
 
 #include "board-rx51.h"
@@ -46,6 +47,10 @@
 #include <../drivers/staging/iio/light/tsl2563.h>
 #include <linux/lis3lv02d.h>
 
+#if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE)
+#include <media/ir-rx51.h>
+#endif
+
 #include "mux.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
@@ -1217,6 +1222,30 @@ static void __init rx51_init_tsc2005(void)
                                 gpio_to_irq(RX51_TSC2005_IRQ_GPIO);
 }
 
+#if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE)
+static struct lirc_rx51_platform_data rx51_lirc_data = {
+        .set_max_mpu_wakeup_lat = omap_pm_set_max_mpu_wakeup_lat,
+        .pwm_timer = 9, /* Use GPT 9 for CIR */
+};
+
+static struct platform_device rx51_lirc_device = {
+        .name           = "lirc_rx51",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &rx51_lirc_data,
+        },
+};
+
+static void __init rx51_init_lirc(void)
+{
+        platform_device_register(&rx51_lirc_device);
+}
+#else
+static void __init rx51_init_lirc(void)
+{
+}
+#endif
+
 void __init rx51_peripherals_init(void)
 {
         rx51_i2c_init();
@@ -1227,6 +1256,7 @@ void __init rx51_peripherals_init(void)
         rx51_init_wl1251();
         rx51_init_tsc2005();
         rx51_init_si4713();
+        rx51_init_lirc();
         spi_register_board_info(rx51_peripherals_spi_board_info,
                                 ARRAY_SIZE(rx51_peripherals_spi_board_info));
 
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index b19a1f7234ae..c2d15212d64d 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
         omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 
         omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
-                             OMAP24XX_CM_IDLEST_VAL, clk->name);
+                             OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
 
         /*
          * REVISIT: Should we return an error code if omap2_wait_clock_ready()
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index cabcfdba5246..3524f0e7b6d5 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
 long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
 {
         const struct prcm_config *ptr;
-        long highest_rate;
+        long highest_rate, sys_clk_rate;
 
         highest_rate = -EINVAL;
+        sys_clk_rate = __clk_get_rate(sclk);
 
         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
                 if (!(ptr->flags & cpu_mask))
                         continue;
-                if (ptr->xtal_speed != sclk->rate)
+                if (ptr->xtal_speed != sys_clk_rate)
                         continue;
 
                 highest_rate = ptr->mpu_speed;
@@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
         const struct prcm_config *prcm;
         unsigned long found_speed = 0;
         unsigned long flags;
+        long sys_clk_rate;
+
+        sys_clk_rate = __clk_get_rate(sclk);
 
         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
                 if (!(prcm->flags & cpu_mask))
                         continue;
 
-                if (prcm->xtal_speed != sclk->rate)
+                if (prcm->xtal_speed != sys_clk_rate)
                         continue;
 
                 if (prcm->mpu_speed <= rate) {
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index 298887b5bf66..7c6da2f731dc 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         struct omap_sdrc_params *sdrc_cs0;
         struct omap_sdrc_params *sdrc_cs1;
         int ret;
+        unsigned long clkrate;
 
         if (!clk || !rate)
                 return -EINVAL;
@@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         if (validrate != rate)
                 return -EINVAL;
 
-        sdrcrate = sdrc_ick_p->rate;
-        if (rate > clk->rate)
-                sdrcrate <<= ((rate / clk->rate) >> 1);
+        sdrcrate = __clk_get_rate(sdrc_ick_p);
+        clkrate = __clk_get_rate(clk);
+        if (rate > clkrate)
+                sdrcrate <<= ((rate / clkrate) >> 1);
         else
-                sdrcrate >>= ((clk->rate / rate) >> 1);
+                sdrcrate >>= ((clkrate / rate) >> 1);
 
         ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
         if (ret)
@@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         /*
          * XXX This only needs to be done when the CPU frequency changes
          */
-        _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
+        _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
         c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
         c += 1;  /* for safety */
         c *= SDRC_MPURATE_LOOPS;
@@ -90,8 +92,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         if (c == 0)
                 c = 1;
 
-        pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
-                 validrate);
+        pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
+                 clkrate, validrate);
         pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
@@ -102,14 +104,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 
         if (sdrc_cs1)
                 omap3_configure_core_dpll(
-                                  new_div, unlock_dll, c, rate > clk->rate,
+                                  new_div, unlock_dll, c, rate > clkrate,
                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
                                   sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
                                   sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
         else
                 omap3_configure_core_dpll(
-                                  new_div, unlock_dll, c, rate > clk->rate,
+                                  new_div, unlock_dll, c, rate > clkrate,
                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
                                   0, 0, 0, 0);
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 19a980956d44..eaed3900a83c 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -72,7 +72,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
         if (!clks->parent) {
                 /* This indicates a data problem */
                 WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
-                     clk->name, src_clk->name);
+                     __clk_get_name(clk), __clk_get_name(src_clk));
                 return NULL;
         }
 
@@ -127,7 +127,8 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
         if (max_div == 0) {
                 /* This indicates an error in the clksel data */
                 WARN(1, "clock: %s: could not find divisor for parent %s\n",
-                     clk->name, src_clk->parent->name);
+                     __clk_get_name(clk),
+                     __clk_get_name(__clk_get_parent(src_clk)));
                 return 0;
         }
 
@@ -176,8 +177,10 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
 {
         const struct clksel *clks;
         const struct clksel_rate *clkr;
+        struct clk *parent;
 
-        clks = _get_clksel_by_parent(clk, clk->parent);
+        parent = __clk_get_parent(clk);
+        clks = _get_clksel_by_parent(clk, parent);
         if (!clks)
                 return 0;
 
@@ -191,8 +194,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
 
         if (!clkr->div) {
                 /* This indicates a data error */
-                WARN(1, "clock: %s: could not find fieldval %d parent %s\n",
-                     clk->name, field_val, clk->parent->name);
+                WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
+                     __clk_get_name(clk), field_val, __clk_get_name(parent));
                 return 0;
         }
 
@@ -213,11 +216,13 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
 {
         const struct clksel *clks;
         const struct clksel_rate *clkr;
+        struct clk *parent;
 
         /* should never happen */
         WARN_ON(div == 0);
 
-        clks = _get_clksel_by_parent(clk, clk->parent);
+        parent = __clk_get_parent(clk);
+        clks = _get_clksel_by_parent(clk, parent);
         if (!clks)
                 return ~0;
 
@@ -230,8 +235,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
         }
 
         if (!clkr->div) {
-                pr_err("clock: %s: could not find divisor %d parent %s\n",
-                       clk->name, div, clk->parent->name);
+                pr_err("clock: %s: could not find divisor %d for parent %s\n",
+                       __clk_get_name(clk), div, __clk_get_name(parent));
                 return ~0;
         }
 
@@ -281,16 +286,23 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
         const struct clksel *clks;
         const struct clksel_rate *clkr;
         u32 last_div = 0;
+        struct clk *parent;
+        unsigned long parent_rate;
+        const char *clk_name;
+
+        parent = __clk_get_parent(clk);
+        parent_rate = __clk_get_rate(parent);
+        clk_name = __clk_get_name(clk);
 
         if (!clk->clksel || !clk->clksel_mask)
                 return ~0;
 
         pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
-                 clk->name, target_rate);
+                 clk_name, target_rate);
 
         *new_div = 1;
 
-        clks = _get_clksel_by_parent(clk, clk->parent);
+        clks = _get_clksel_by_parent(clk, parent);
         if (!clks)
                 return ~0;
 
@@ -300,29 +312,29 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
 
                 /* Sanity check */
                 if (clkr->div <= last_div)
-                        pr_err("clock: %s: clksel_rate table not sorted",
-                               clk->name);
+                        pr_err("clock: %s: clksel_rate table not sorted\n",
+                               clk_name);
 
                 last_div = clkr->div;
 
-                test_rate = clk->parent->rate / clkr->div;
+                test_rate = parent_rate / clkr->div;
 
                 if (test_rate <= target_rate)
                         break; /* found it */
         }
 
         if (!clkr->div) {
-                pr_err("clock: %s: could not find divisor for target rate %ld parent %s\n",
-                       clk->name, target_rate, clk->parent->name);
+                pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
+                       clk_name, target_rate, __clk_get_name(parent));
                 return ~0;
         }
 
         *new_div = clkr->div;
 
         pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
-                 (clk->parent->rate / clkr->div));
+                 (parent_rate / clkr->div));
 
-        return clk->parent->rate / clkr->div;
+        return parent_rate / clkr->div;
 }
 
 /*
@@ -344,10 +356,15 @@ void omap2_init_clksel_parent(struct clk *clk)
         const struct clksel *clks;
         const struct clksel_rate *clkr;
         u32 r, found = 0;
+        struct clk *parent;
+        const char *clk_name;
 
         if (!clk->clksel || !clk->clksel_mask)
                 return;
 
+        parent = __clk_get_parent(clk);
+        clk_name = __clk_get_name(clk);
+
         r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
         r >>= __ffs(clk->clksel_mask);
 
@@ -357,11 +374,13 @@ void omap2_init_clksel_parent(struct clk *clk)
                                 continue;
 
                         if (clkr->val == r) {
-                                if (clk->parent != clks->parent) {
+                                if (parent != clks->parent) {
                                         pr_debug("clock: %s: inited parent to %s (was %s)\n",
-                                                 clk->name, clks->parent->name,
-                                                 ((clk->parent) ?
-                                                  clk->parent->name : "NULL"));
+                                                 clk_name,
+                                                 __clk_get_name(clks->parent),
+                                                 ((parent) ?
+                                                  __clk_get_name(parent) :
+                                                 "NULL"));
                                         clk_reparent(clk, clks->parent);
                                 };
                                 found = 1;
@@ -371,7 +390,7 @@ void omap2_init_clksel_parent(struct clk *clk)
 
         /* This indicates a data error */
         WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
-             clk->name, r);
+             clk_name, r);
 
         return;
 }
@@ -389,15 +408,17 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
 {
         unsigned long rate;
         u32 div = 0;
+        struct clk *parent;
 
         div = _read_divisor(clk);
         if (div == 0)
-                return clk->rate;
+                return __clk_get_rate(clk);
 
-        rate = clk->parent->rate / div;
+        parent = __clk_get_parent(clk);
+        rate = __clk_get_rate(parent) / div;
 
-        pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
-                 rate, div);
+        pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
+                 __clk_get_name(clk), rate, div);
 
         return rate;
 }
@@ -452,9 +473,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 
         _write_clksel_reg(clk, field_val);
 
-        clk->rate = clk->parent->rate / new_div;
+        clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
 
-        pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
+        pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
+                 __clk_get_rate(clk));
 
         return 0;
 }
@@ -496,13 +518,15 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
         clk_reparent(clk, new_parent);
 
         /* CLKSEL clocks follow their parents' rates, divided by a divisor */
-        clk->rate = new_parent->rate;
+        clk->rate = __clk_get_rate(new_parent);
 
         if (parent_div > 0)
-                clk->rate /= parent_div;
+                __clk_get_rate(clk) /= parent_div;
 
         pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
-                 clk->name, clk->parent->name, clk->rate);
+                 __clk_get_name(clk),
+                 __clk_get_name(__clk_get_parent(clk)),
+                 __clk_get_rate(clk));
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 83b658bf385a..80411142f482 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
         dd = clk->dpll_data;
 
         /* DPLL divider must result in a valid jitter correction val */
-        fint = clk->parent->rate / n;
+        fint = __clk_get_rate(__clk_get_parent(clk)) / n;
 
         if (cpu_is_omap24xx()) {
                 /* Should not be called for OMAP2, so warn if it is called */
@@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)
         if (cpu_is_omap24xx()) {
                 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP2XXX_EN_DPLL_FRBYPASS)
-                        return dd->clk_bypass->rate;
+                        return __clk_get_rate(dd->clk_bypass);
         } else if (cpu_is_omap34xx()) {
                 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP3XXX_EN_DPLL_FRBYPASS)
-                        return dd->clk_bypass->rate;
+                        return __clk_get_rate(dd->clk_bypass);
         } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
                 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP4XXX_EN_DPLL_FRBYPASS ||
                     v == OMAP4XXX_EN_DPLL_MNBYPASS)
-                        return dd->clk_bypass->rate;
+                        return __clk_get_rate(dd->clk_bypass);
         }
 
         v = __raw_readl(dd->mult_div1_reg);
@@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
         dpll_div = v & dd->div1_mask;
         dpll_div >>= __ffs(dd->div1_mask);
 
-        dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
+        dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
         do_div(dpll_clk, dpll_div + 1);
 
         return dpll_clk;
@@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
         unsigned long scaled_rt_rp;
         unsigned long new_rate = 0;
         struct dpll_data *dd;
+        unsigned long ref_rate;
+        const char *clk_name;
 
         if (!clk || !clk->dpll_data)
                 return ~0;
 
         dd = clk->dpll_data;
 
+        ref_rate = __clk_get_rate(dd->clk_ref);
+        clk_name = __clk_get_name(clk);
         pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
-                 clk->name, target_rate);
+                 clk_name, target_rate);
 
-        scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
+        scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
         scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
 
         dd->last_rounded_rate = 0;
@@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
                         break;
 
                 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
-                                    dd->clk_ref->rate);
+                                    ref_rate);
 
                 /* m can't be set low enough for this n - try with a larger n */
                 if (r == DPLL_MULT_UNDERFLOW)
                         continue;
 
                 pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
-                         clk->name, m, n, new_rate);
+                         clk_name, m, n, new_rate);
 
                 if (target_rate == new_rate) {
                         dd->last_rounded_m = m;
@@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
         }
 
         if (target_rate != new_rate) {
-                pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
-                         target_rate);
+                pr_debug("clock: %s: cannot round to rate %ld\n",
+                         clk_name, target_rate);
                 return ~0;
         }
 
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e97f98ffe8b2..961ac8f7e13d 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -78,7 +78,7 @@ static void _omap2_module_wait_ready(struct clk *clk)
         clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
 
         omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
-                             clk->name);
+                             __clk_get_name(clk));
 }
 
 /* Public functions */
@@ -94,18 +94,21 @@ static void _omap2_module_wait_ready(struct clk *clk)
 void omap2_init_clk_clkdm(struct clk *clk)
 {
         struct clockdomain *clkdm;
+        const char *clk_name;
 
         if (!clk->clkdm_name)
                 return;
 
+        clk_name = __clk_get_name(clk);
+
         clkdm = clkdm_lookup(clk->clkdm_name);
         if (clkdm) {
                 pr_debug("clock: associated clk %s to clkdm %s\n",
-                         clk->name, clk->clkdm_name);
+                         clk_name, clk->clkdm_name);
                 clk->clkdm = clkdm;
         } else {
                 pr_debug("clock: could not associate clk %s to clkdm %s\n",
-                         clk->name, clk->clkdm_name);
+                         clk_name, clk->clkdm_name);
         }
 }
 
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 12c178dbc9f5..c3cde1a2b6de 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1804,6 +1804,7 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_242X),
         /* DSS domain clocks */
         CLK("omapdss_dss",      "ick",          &dss_ick,       CK_242X),
+        CLK(NULL,       "dss_ick",              &dss_ick,       CK_242X),
         CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_242X),
         CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_242X),
         CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_242X),
@@ -1843,12 +1844,16 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_242X),
         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_242X),
         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_242X),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_242X),
         CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_242X),
         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_242X),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_242X),
         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_242X),
         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_242X),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_242X),
         CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_242X),
         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_242X),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_242X),
         CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_242X),
         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_242X),
         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_242X),
@@ -1859,12 +1864,15 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_242X),
         CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_242X),
         CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_242X),
+        CLK(NULL,       "mpu_wdt_ick",          &mpu_wdt_ick,   CK_242X),
         CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_242X),
         CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_242X),
         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_242X),
         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_242X),
         CLK("omap24xxcam", "fck",       &cam_fck,       CK_242X),
+        CLK(NULL,       "cam_fck",      &cam_fck,       CK_242X),
         CLK("omap24xxcam", "ick",       &cam_ick,       CK_242X),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_242X),
         CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_242X),
         CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_242X),
         CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_242X),
@@ -1873,16 +1881,22 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_242X),
         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_242X),
         CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
+        CLK(NULL,       "mmc_ick",      &mmc_ick,       CK_242X),
         CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
+        CLK(NULL,       "mmc_fck",      &mmc_fck,       CK_242X),
         CLK(NULL,       "fac_ick",      &fac_ick,       CK_242X),
         CLK(NULL,       "fac_fck",      &fac_fck,       CK_242X),
         CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
         CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_242X),
+        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_242X),
         CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_242X),
+        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_242X),
         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_242X),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_242X),
         CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_242X),
         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_242X),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_242X),
         CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_242X),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
@@ -1892,14 +1906,18 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
         CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
         CLK("omap-sham",        "ick",  &sha_ick,       CK_242X),
+        CLK(NULL,       "sha_ick",      &sha_ick,       CK_242X),
         CLK("omap_rng", "ick",          &rng_ick,       CK_242X),
+        CLK(NULL,       "rng_ick",              &rng_ick,       CK_242X),
         CLK("omap-aes", "ick",  &aes_ick,       CK_242X),
+        CLK(NULL,       "aes_ick",      &aes_ick,       CK_242X),
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
         CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
         CLK("musb-hdrc",        "fck",  &osc_ck,        CK_242X),
-        CLK(NULL,       "timer_32k_ck", &func_32k_ck,   CK_243X),
-        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_243X),
-        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_243X),
+        CLK(NULL,       "timer_32k_ck", &func_32k_ck,   CK_242X),
+        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_242X),
+        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_242X),
+        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_242X),
 };
 
 /*
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 7ea91398217a..22404fe435e7 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1888,6 +1888,7 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
         /* DSS domain clocks */
         CLK("omapdss_dss",      "ick",          &dss_ick,       CK_243X),
+        CLK(NULL,       "dss_ick",              &dss_ick,       CK_243X),
         CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_243X),
         CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_243X),
         CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_243X),
@@ -1927,20 +1928,28 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X),
         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X),
         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_243X),
         CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_243X),
         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_243X),
         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_243X),
         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
+        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_243X),
         CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_243X),
         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
+        CLK(NULL,       "mcbsp4_ick",   &mcbsp4_ick,    CK_243X),
         CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_243X),
         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
+        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_243X),
         CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_243X),
         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_243X),
         CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_243X),
         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_243X),
         CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_243X),
         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
+        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_243X),
         CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_243X),
         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X),
         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X),
@@ -1951,13 +1960,16 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X),
         CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X),
         CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X),
+        CLK(NULL,       "mpu_wdt_ick",  &mpu_wdt_ick,   CK_243X),
         CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_243X),
         CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X),
         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X),
         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X),
         CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
         CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X),
+        CLK(NULL,       "cam_fck",      &cam_fck,       CK_243X),
         CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_243X),
         CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X),
         CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X),
         CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X),
@@ -1966,10 +1978,14 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X),
         CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X),
+        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_243X),
         CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X),
+        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_243X),
         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_243X),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_243X),
         CLK(NULL,       "i2chs1_fck",   &i2chs1_fck,    CK_243X),
         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_243X),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_243X),
         CLK(NULL,       "i2chs2_fck",   &i2chs2_fck,    CK_243X),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X),
         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X),
@@ -1978,22 +1994,29 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "des_ick",      &des_ick,       CK_243X),
         CLK("omap-sham",        "ick",  &sha_ick,       CK_243X),
         CLK("omap_rng", "ick",          &rng_ick,       CK_243X),
+        CLK(NULL,       "rng_ick",      &rng_ick,       CK_243X),
         CLK("omap-aes", "ick",  &aes_ick,       CK_243X),
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X),
         CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X),
         CLK("musb-omap2430",    "ick",  &usbhs_ick,     CK_243X),
+        CLK(NULL,       "usbhs_ick",    &usbhs_ick,     CK_243X),
         CLK("omap_hsmmc.0", "ick",      &mmchs1_ick,    CK_243X),
+        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_243X),
         CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_243X),
         CLK("omap_hsmmc.1", "ick",      &mmchs2_ick,    CK_243X),
+        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_243X),
         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_243X),
         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
         CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
         CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
         CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck,  CK_243X),
+        CLK(NULL,       "mmchsdb1_fck",         &mmchsdb1_fck,  CK_243X),
         CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck,  CK_243X),
+        CLK(NULL,       "mmchsdb2_fck",         &mmchsdb2_fck,  CK_243X),
         CLK(NULL,       "timer_32k_ck",  &func_32k_ck,   CK_243X),
         CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_243X),
         CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_243X),
+        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_243X),
 };
 
 /*
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index 2026311a4ff6..b87b88c2638b 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -1013,6 +1013,7 @@ static struct omap_clk am33xx_clks[] = {
         CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck,       CK_AM33XX),
         CLK(NULL,       "dpll_core_m6_ck",      &dpll_core_m6_ck,       CK_AM33XX),
         CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck,   CK_AM33XX),
+        CLK("cpu0",     NULL,                   &dpll_mpu_ck,           CK_AM33XX),
         CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck,        CK_AM33XX),
         CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck,   CK_AM33XX),
         CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck,        CK_AM33XX),
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 15cdc6471737..83bb01427d40 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -63,15 +63,15 @@ void __init omap3_clk_lock_dpll5(void)
 
         dpll5_clk = clk_get(NULL, "dpll5_ck");
         clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
-        clk_enable(dpll5_clk);
+        clk_prepare_enable(dpll5_clk);
 
         /* Program dpll5_m2_clk divider for no division */
         dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
-        clk_enable(dpll5_m2_clk);
+        clk_prepare_enable(dpll5_m2_clk);
         clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
 
-        clk_disable(dpll5_m2_clk);
-        clk_disable(dpll5_clk);
+        clk_disable_unprepare(dpll5_m2_clk);
+        clk_disable_unprepare(dpll5_clk);
         return;
 }
 
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 700317a1bd16..1f42c9d5ecf3 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3215,7 +3215,6 @@ static struct clk dummy_apb_pclk = {
  * clkdev
  */
 
-/* XXX At some point we should rename this file to clock3xxx_data.c */
 static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
@@ -3243,11 +3242,13 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
+        CLK(NULL,       "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
         CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
         CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
         CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
+        CLK(NULL,       "omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_36XX),
         CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
         CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
@@ -3263,6 +3264,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
+        CLK(NULL,       "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
         CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
         CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
@@ -3272,6 +3274,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
         CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
+        CLK(NULL,       "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
         CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
         CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_34XX | CK_36XX),
         CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_34XX | CK_36XX),
@@ -3295,6 +3298,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_tll",        "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
         CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
@@ -3315,6 +3319,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
         CLK("omap_hdq.0",       "fck",  &hdq_fck,       CK_3XXX),
+        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_3XXX),
         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
@@ -3322,6 +3327,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
+        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es1,  CK_3430ES1),
+        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
@@ -3329,28 +3336,42 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_tll",        "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "mmchs3_ick",   &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
         CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
         CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
         CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
         CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick,    CK_3XXX),
         CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick,    CK_3XXX),
+        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_3XXX),
+        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_3XXX),
         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
+        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_3XXX),
         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi4_ick",   &mcspi4_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_3XXX),
         CLK("omap_i2c.3", "ick",        &i2c3_ick,      CK_3XXX),
         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_3XXX),
         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_3XXX),
+        CLK(NULL,       "i2c3_ick",     &i2c3_ick,      CK_3XXX),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_3XXX),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_3XXX),
         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_3XXX),
         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
@@ -3369,7 +3390,9 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_3XXX),
         CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck, CK_3XXX),
         CLK("omapdss_dss",      "ick",          &dss_ick_3430es1,       CK_3430ES1),
+        CLK(NULL,       "dss_ick",              &dss_ick_3430es1,       CK_3430ES1),
         CLK("omapdss_dss",      "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "dss_ick",              &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
         CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
@@ -3385,6 +3408,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
         CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
         CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_tll",        "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
         CLK(NULL,       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
@@ -3394,6 +3419,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
+        CLK(NULL,       "wdt2_ick",     &wdt2_ick,      CK_3XXX),
         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
         CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
@@ -3439,9 +3465,13 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp4_ick",   &mcbsp2_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp4_ick,    CK_3XXX),
         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_3XXX),
         CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_3XXX),
         CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_3XXX),
+        CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_3XXX),
         CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
         CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
@@ -3457,8 +3487,12 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
         CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
         CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
+        CLK(NULL,       "emac_ick",     &emac_ick,      CK_AM35XX),
+        CLK(NULL,       "emac_fck",     &emac_fck,      CK_AM35XX),
         CLK("davinci_emac.0",   NULL,   &emac_ick,      CK_AM35XX),
         CLK("davinci_mdio.0",   NULL,   &emac_fck,      CK_AM35XX),
+        CLK(NULL,       "vpfe_ick",     &emac_ick,      CK_AM35XX),
+        CLK(NULL,       "vpfe_fck",     &emac_fck,      CK_AM35XX),
         CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
         CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
         CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx,   CK_AM35XX),
@@ -3467,6 +3501,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
         CLK(NULL,       "timer_32k_ck", &omap_32k_fck,  CK_3XXX),
         CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_3XXX),
+        CLK(NULL,       "cpufreq_ck",   &dpll1_ck,      CK_3XXX),
 };
 
 
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 500682c051c1..d661d138f270 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
         CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
         CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
+        CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
         CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
@@ -3212,6 +3213,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
         CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
         CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
+        CLK(NULL,       "rng_ick",                      &rng_ick,       CK_443X),
         CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
         CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
@@ -3243,6 +3245,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
         CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
+        CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
         CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
@@ -3253,15 +3256,19 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
+        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
         CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck,       CK_443X),
         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
+        CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick,        CK_443X),
         CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
         CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
         CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
+        CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
@@ -3312,8 +3319,10 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
         CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
         CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
+        CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck,      CK_443X),
         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
         CLK(NULL,       "timer_32k_ck", &sys_32k_ck,    CK_443X),
+        /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
         CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
         CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
         CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
@@ -3325,6 +3334,18 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
         CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
         CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("49038000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4903a000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4903c000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4903e000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck,   CK_443X),
 };
 
 int __init omap4xxx_clk_init(void)
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index a1555627ad97..cbb879139c51 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -899,6 +899,23 @@ bool clkdm_in_hwsup(struct clockdomain *clkdm)
         return ret;
 }
 
+/**
+ * clkdm_missing_idle_reporting - can @clkdm enter autoidle even if in use?
+ * @clkdm: struct clockdomain *
+ *
+ * Returns true if clockdomain @clkdm has the
+ * CLKDM_MISSING_IDLE_REPORTING flag set, or false if not or @clkdm is
+ * null.  More information is available in the documentation for the
+ * CLKDM_MISSING_IDLE_REPORTING macro.
+ */
+bool clkdm_missing_idle_reporting(struct clockdomain *clkdm)
+{
+        if (!clkdm)
+                return false;
+
+        return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false;
+}
+
 /* Clockdomain-to-clock/hwmod framework interface code */
 
 static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 5601dc13785e..629576be7444 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -1,9 +1,7 @@
 /*
- * arch/arm/plat-omap/include/mach/clockdomain.h
- *
  * OMAP2/3 clockdomain framework functions
  *
- * Copyright (C) 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008, 2012 Texas Instruments, Inc.
  * Copyright (C) 2008-2011 Nokia Corporation
  *
  * Paul Walmsley
@@ -34,6 +32,20 @@
  * CLKDM_ACTIVE_WITH_MPU: The PRCM guarantees that this clockdomain is
  *     active whenever the MPU is active.  True for interconnects and
  *     the WKUP clockdomains.
+ * CLKDM_MISSING_IDLE_REPORTING: The idle status of the IP blocks and
+ *     clocks inside this clockdomain are not taken into account by
+ *     the PRCM when determining whether the clockdomain is idle.
+ *     Without this flag, if the clockdomain is set to
+ *     hardware-supervised idle mode, the PRCM may transition the
+ *     enclosing powerdomain to a low power state, even when devices
+ *     inside the clockdomain and powerdomain are in use.  (An example
+ *     of such a clockdomain is the EMU clockdomain on OMAP3/4.)  If
+ *     this flag is set, and the clockdomain does not support the
+ *     force-sleep mode, then the HW_AUTO mode will be used to put the
+ *     clockdomain to sleep.  Similarly, if the clockdomain supports
+ *     the force-wakeup mode, then it will be used whenever a clock or
+ *     IP block inside the clockdomain is active, rather than the
+ *     HW_AUTO mode.
  */
 #define CLKDM_CAN_FORCE_SLEEP                   (1 << 0)
 #define CLKDM_CAN_FORCE_WAKEUP                  (1 << 1)
@@ -41,6 +53,7 @@
 #define CLKDM_CAN_DISABLE_AUTO                  (1 << 3)
 #define CLKDM_NO_AUTODEPS                       (1 << 4)
 #define CLKDM_ACTIVE_WITH_MPU                   (1 << 5)
+#define CLKDM_MISSING_IDLE_REPORTING            (1 << 6)
 
 #define CLKDM_CAN_HWSUP         (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
 #define CLKDM_CAN_SWSUP         (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
@@ -187,6 +200,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
 void clkdm_allow_idle(struct clockdomain *clkdm);
 void clkdm_deny_idle(struct clockdomain *clkdm);
 bool clkdm_in_hwsup(struct clockdomain *clkdm);
+bool clkdm_missing_idle_reporting(struct clockdomain *clkdm);
 
 int clkdm_wakeup(struct clockdomain *clkdm);
 int clkdm_sleep(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
index f99e65cfb862..9a7792aec673 100644
--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -162,6 +162,19 @@ static void _disable_hwsup(struct clockdomain *clkdm)
                                                 clkdm->clktrctrl_mask);
 }
 
+static int omap3_clkdm_sleep(struct clockdomain *clkdm)
+{
+        omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+        return 0;
+}
+
+static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+        return 0;
+}
 
 static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
 {
@@ -170,6 +183,17 @@ static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
         if (!clkdm->clktrctrl_mask)
                 return 0;
 
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
+            !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
+                _enable_hwsup(clkdm);
+                return 0;
+        }
+
         hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                 clkdm->clktrctrl_mask);
 
@@ -193,6 +217,17 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
         if (!clkdm->clktrctrl_mask)
                 return 0;
 
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
+            (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
+                omap3_clkdm_wakeup(clkdm);
+                return 0;
+        }
+
         hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                 clkdm->clktrctrl_mask);
 
@@ -209,20 +244,6 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
         return 0;
 }
 
-static int omap3_clkdm_sleep(struct clockdomain *clkdm)
-{
-        omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-        return 0;
-}
-
-static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
-{
-        omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-        return 0;
-}
-
 static void omap3_clkdm_allow_idle(struct clockdomain *clkdm)
 {
         if (atomic_read(&clkdm->usecount) > 0)
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index 762f2cc542ce..6fc6155625bc 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -113,6 +113,17 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
         if (!clkdm->prcm_partition)
                 return 0;
 
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
+            !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
+                omap4_clkdm_allow_idle(clkdm);
+                return 0;
+        }
+
         hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
                                         clkdm->cm_inst, clkdm->clkdm_offs);
 
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index 56089c49142a..933a35cd124a 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -387,14 +387,11 @@ static struct clockdomain per_am35x_clkdm = {
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
 };
 
-/*
- * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
- * switched of even if sdti is in use
- */
 static struct clockdomain emu_clkdm = {
         .name           = "emu_clkdm",
         .pwrdm          = { .name = "emu_pwrdm" },
-        .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
+        .flags          = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP |
+                           CLKDM_MISSING_IDLE_REPORTING),
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
 };
 
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index 63d60a773d3b..b56d06b48782 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -390,7 +390,8 @@ static struct clockdomain emu_sys_44xx_clkdm = {
         .prcm_partition   = OMAP4430_PRM_PARTITION,
         .cm_inst          = OMAP4430_PRM_EMU_CM_INST,
         .clkdm_offs       = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
-        .flags            = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP,
+        .flags            = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP |
+                             CLKDM_MISSING_IDLE_REPORTING),
 };
 
 static struct clockdomain l3_dma_44xx_clkdm = {
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h
index 532027ee3d8d..adf7bb79b18f 100644
--- a/arch/arm/mach-omap2/cm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-33xx.h
@@ -25,263 +25,328 @@
  * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
  */
 #define AM33XX_AUTO_DPLL_MODE_SHIFT                     0
+#define AM33XX_AUTO_DPLL_MODE_WIDTH                     3
 #define AM33XX_AUTO_DPLL_MODE_MASK                      (0x7 << 0)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT               14
+#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK                (1 << 16)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT                11
+#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH                1
 #define AM33XX_CLKACTIVITY_CAN_CLK_MASK                 (1 << 11)
 
 /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT         4
+#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH         1
 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK          (1 << 4)
 
 /* Used by CM_PER_CPSW_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK        (1 << 4)
 
 /* Used by CM_PER_L4HS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK        (1 << 4)
 
 /* Used by CM_PER_L4HS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT        5
+#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH        1
 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK         (1 << 5)
 
 /* Used by CM_PER_L4HS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT         6
+#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH         1
 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK          (1 << 6)
 
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT          6
+#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK           (1 << 6)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT     9
+#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH     1
 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK      (1 << 9)
 
 /* Used by CM_L3_AON_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT              2
+#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK               (1 << 2)
 
 /* Used by CM_L3_AON_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT             4
+#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH             1
 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK              (1 << 4)
 
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT              2
+#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK               (1 << 2)
 
 /* Used by CM_GFX_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT               9
+#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK                (1 << 9)
 
 /* Used by CM_GFX_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT            8
+#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK             (1 << 8)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT           8
+#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH           1
 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK            (1 << 8)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT          19
+#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK           (1 << 19)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT          20
+#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK           (1 << 20)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT          21
+#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK           (1 << 21)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT          22
+#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK           (1 << 22)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT          26
+#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK           (1 << 26)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT          18
+#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK           (1 << 18)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT             11
+#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH             1
 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK              (1 << 11)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT               24
+#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK                (1 << 24)
 
 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT         5
+#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH         1
 #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK          (1 << 5)
 
 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT         4
+#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH         1
 #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK          (1 << 4)
 
 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT        6
+#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH        1
 #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK         (1 << 6)
 
 /* Used by CM_PER_L3S_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT               3
+#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK                (1 << 3)
 
 /* Used by CM_L3_AON_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT            3
+#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK             (1 << 3)
 
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT                4
+#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH                1
 #define AM33XX_CLKACTIVITY_L3_GCLK_MASK                 (1 << 4)
 
 /* Used by CM_PER_L4FW_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT              8
+#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK               (1 << 8)
 
 /* Used by CM_PER_L4HS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT              3
+#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK               (1 << 3)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT              8
+#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK               (1 << 8)
 
 /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT          8
+#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK           (1 << 8)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT        8
+#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH        1
 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK         (1 << 8)
 
 /* Used by CM_RTC_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT            8
+#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK             (1 << 8)
 
 /* Used by CM_L4_WKUP_AON_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT       2
+#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK        (1 << 2)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT           2
+#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH           1
 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK            (1 << 2)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT              17
+#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK               (1 << 17)
 
 /* Used by CM_PER_LCDC_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK        (1 << 4)
 
 /* Used by CM_PER_LCDC_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT       5
+#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK        (1 << 5)
 
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT             7
+#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH             1
 #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK              (1 << 7)
 
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT               3
+#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK                (1 << 3)
 
 /* Used by CM_MPU_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT                2
+#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH                1
 #define AM33XX_CLKACTIVITY_MPU_CLK_MASK                 (1 << 2)
 
 /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT          4
+#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK           (1 << 4)
 
 /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT          5
+#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK           (1 << 5)
 
 /* Used by CM_RTC_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT             9
+#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH             1
 #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK              (1 << 9)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT               25
+#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK                (1 << 25)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT              3
+#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK               (1 << 3)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT            10
+#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK             (1 << 10)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT            13
+#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK             (1 << 13)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT            14
+#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK             (1 << 14)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT            15
+#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK             (1 << 15)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT            16
+#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK             (1 << 16)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT            27
+#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK             (1 << 27)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT            28
+#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK             (1 << 28)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT            13
+#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK             (1 << 13)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT            12
+#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK             (1 << 12)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT             10
+#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH             1
 #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK              (1 << 10)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT              9
+#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK               (1 << 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT              4
+#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK               (1 << 4)
 
 /* Used by CLKSEL_GFX_FCLK */
 #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT                0
+#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH                1
 #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK                 (1 << 0)
 
 /* Used by CM_CLKOUT_CTRL */
 #define AM33XX_CLKOUT2DIV_SHIFT                         3
-#define AM33XX_CLKOUT2DIV_MASK                          (0x05 << 3)
+#define AM33XX_CLKOUT2DIV_WIDTH                         3
+#define AM33XX_CLKOUT2DIV_MASK                          (0x7 << 3)
 
 /* Used by CM_CLKOUT_CTRL */
 #define AM33XX_CLKOUT2EN_SHIFT                          7
+#define AM33XX_CLKOUT2EN_WIDTH                          1
 #define AM33XX_CLKOUT2EN_MASK                           (1 << 7)
 
 /* Used by CM_CLKOUT_CTRL */
 #define AM33XX_CLKOUT2SOURCE_SHIFT                      0
-#define AM33XX_CLKOUT2SOURCE_MASK                       (0x02 << 0)
+#define AM33XX_CLKOUT2SOURCE_WIDTH                      3
+#define AM33XX_CLKOUT2SOURCE_MASK                       (0x7 << 0)
 
 /*
  * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
@@ -289,6 +354,7 @@
  * CLKSEL_TIMER7_CLK
  */
 #define AM33XX_CLKSEL_SHIFT                             0
+#define AM33XX_CLKSEL_WIDTH                             1
 #define AM33XX_CLKSEL_MASK                              (0x01 << 0)
 
 /*
@@ -296,17 +362,21 @@
  * CM_CPTS_RFT_CLKSEL
  */
 #define AM33XX_CLKSEL_0_0_SHIFT                         0
+#define AM33XX_CLKSEL_0_0_WIDTH                         1
 #define AM33XX_CLKSEL_0_0_MASK                          (1 << 0)
 
 #define AM33XX_CLKSEL_0_1_SHIFT                         0
+#define AM33XX_CLKSEL_0_1_WIDTH                         2
 #define AM33XX_CLKSEL_0_1_MASK                          (3 << 0)
 
 /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
 #define AM33XX_CLKSEL_0_2_SHIFT                         0
+#define AM33XX_CLKSEL_0_2_WIDTH                         3
 #define AM33XX_CLKSEL_0_2_MASK                          (7 << 0)
 
 /* Used by CLKSEL_GFX_FCLK */
 #define AM33XX_CLKSEL_GFX_FCLK_SHIFT                    1
+#define AM33XX_CLKSEL_GFX_FCLK_WIDTH                    1
 #define AM33XX_CLKSEL_GFX_FCLK_MASK                     (1 << 1)
 
 /*
@@ -318,6 +388,7 @@
  * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
  */
 #define AM33XX_CLKTRCTRL_SHIFT                          0
+#define AM33XX_CLKTRCTRL_WIDTH                          2
 #define AM33XX_CLKTRCTRL_MASK                           (0x3 << 0)
 
 /*
@@ -326,34 +397,42 @@
  * CM_SSC_DELTAMSTEP_DPLL_PER
  */
 #define AM33XX_DELTAMSTEP_SHIFT                         0
-#define AM33XX_DELTAMSTEP_MASK                          (0x19 << 0)
+#define AM33XX_DELTAMSTEP_WIDTH                         20
+#define AM33XX_DELTAMSTEP_MASK                          (0xfffff << 0)
 
 /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
 #define AM33XX_DPLL_BYP_CLKSEL_SHIFT                    23
+#define AM33XX_DPLL_BYP_CLKSEL_WIDTH                    1
 #define AM33XX_DPLL_BYP_CLKSEL_MASK                     (1 << 23)
 
 /* Used by CM_CLKDCOLDO_DPLL_PER */
 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT           8
+#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH           1
 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK            (1 << 8)
 
 /* Used by CM_CLKDCOLDO_DPLL_PER */
 #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT                12
+#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH                1
 #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK                 (1 << 12)
 
 /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
 #define AM33XX_DPLL_CLKOUT_DIV_SHIFT                    0
+#define AM33XX_DPLL_CLKOUT_DIV_WIDTH                    5
 #define AM33XX_DPLL_CLKOUT_DIV_MASK                     (0x1f << 0)
 
 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
 #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT                0
-#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK                 (0x06 << 0)
+#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH                7
+#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK                 (0x7f << 0)
 
 /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
 #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT               5
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH               1
 #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK                (1 << 5)
 
 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT        7
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH        1
 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK         (1 << 7)
 
 /*
@@ -361,6 +440,7 @@
  * CM_DIV_M2_DPLL_PER
  */
 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT              8
+#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH              1
 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK               (1 << 8)
 
 /*
@@ -368,19 +448,22 @@
  * CM_CLKSEL_DPLL_MPU
  */
 #define AM33XX_DPLL_DIV_SHIFT                           0
+#define AM33XX_DPLL_DIV_WIDTH                           7
 #define AM33XX_DPLL_DIV_MASK                            (0x7f << 0)
 
 #define AM33XX_DPLL_PER_DIV_MASK                        (0xff << 0)
 
 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
 #define AM33XX_DPLL_DIV_0_7_SHIFT                       0
-#define AM33XX_DPLL_DIV_0_7_MASK                        (0x07 << 0)
+#define AM33XX_DPLL_DIV_0_7_WIDTH                       8
+#define AM33XX_DPLL_DIV_0_7_MASK                        (0xff << 0)
 
 /*
  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
  * CM_CLKMODE_DPLL_MPU
  */
 #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT                 8
+#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH                 1
 #define AM33XX_DPLL_DRIFTGUARD_EN_MASK                  (1 << 8)
 
 /*
@@ -388,6 +471,7 @@
  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define AM33XX_DPLL_EN_SHIFT                            0
+#define AM33XX_DPLL_EN_WIDTH                            3
 #define AM33XX_DPLL_EN_MASK                             (0x7 << 0)
 
 /*
@@ -395,6 +479,7 @@
  * CM_CLKMODE_DPLL_MPU
  */
 #define AM33XX_DPLL_LPMODE_EN_SHIFT                     10
+#define AM33XX_DPLL_LPMODE_EN_WIDTH                     1
 #define AM33XX_DPLL_LPMODE_EN_MASK                      (1 << 10)
 
 /*
@@ -402,10 +487,12 @@
  * CM_CLKSEL_DPLL_MPU
  */
 #define AM33XX_DPLL_MULT_SHIFT                          8
+#define AM33XX_DPLL_MULT_WIDTH                          11
 #define AM33XX_DPLL_MULT_MASK                           (0x7ff << 8)
 
 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
 #define AM33XX_DPLL_MULT_PERIPH_SHIFT                   8
+#define AM33XX_DPLL_MULT_PERIPH_WIDTH                   12
 #define AM33XX_DPLL_MULT_PERIPH_MASK                    (0xfff << 8)
 
 /*
@@ -413,17 +500,20 @@
  * CM_CLKMODE_DPLL_MPU
  */
 #define AM33XX_DPLL_REGM4XEN_SHIFT                      11
+#define AM33XX_DPLL_REGM4XEN_WIDTH                      1
 #define AM33XX_DPLL_REGM4XEN_MASK                       (1 << 11)
 
 /* Used by CM_CLKSEL_DPLL_PERIPH */
 #define AM33XX_DPLL_SD_DIV_SHIFT                        24
-#define AM33XX_DPLL_SD_DIV_MASK                         (24, 31)
+#define AM33XX_DPLL_SD_DIV_WIDTH                        8
+#define AM33XX_DPLL_SD_DIV_MASK                         (0xff << 24)
 
 /*
  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define AM33XX_DPLL_SSC_ACK_SHIFT                       13
+#define AM33XX_DPLL_SSC_ACK_WIDTH                       1
 #define AM33XX_DPLL_SSC_ACK_MASK                        (1 << 13)
 
 /*
@@ -431,6 +521,7 @@
  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT                14
+#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH                1
 #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK                 (1 << 14)
 
 /*
@@ -438,54 +529,67 @@
  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define AM33XX_DPLL_SSC_EN_SHIFT                        12
+#define AM33XX_DPLL_SSC_EN_WIDTH                        1
 #define AM33XX_DPLL_SSC_EN_MASK                         (1 << 12)
 
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT              0
+#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH              5
 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK               (0x1f << 0)
 
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH         1
 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK          (1 << 5)
 
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH        1
 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK         (1 << 8)
 
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH             1
 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK              (1 << 12)
 
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT              0
+#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH              5
 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK               (0x1f << 0)
 
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH         1
 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK          (1 << 5)
 
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH        1
 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK         (1 << 8)
 
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH             1
 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK              (1 << 12)
 
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT              0
-#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK               (0x04 << 0)
+#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH              5
+#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK               (0x1f << 0)
 
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH         1
 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK          (1 << 5)
 
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH        1
 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK         (1 << 8)
 
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH             1
 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK              (1 << 12)
 
 /*
@@ -522,11 +626,12 @@
  * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
  */
 #define AM33XX_IDLEST_SHIFT                             16
+#define AM33XX_IDLEST_WIDTH                             2
 #define AM33XX_IDLEST_MASK                              (0x3 << 16)
-#define AM33XX_IDLEST_VAL                               0x3
 
 /* Used by CM_MAC_CLKSEL */
 #define AM33XX_MII_CLK_SEL_SHIFT                        2
+#define AM33XX_MII_CLK_SEL_WIDTH                        1
 #define AM33XX_MII_CLK_SEL_MASK                         (1 << 2)
 
 /*
@@ -535,7 +640,8 @@
  * CM_SSC_MODFREQDIV_DPLL_PER
  */
 #define AM33XX_MODFREQDIV_EXPONENT_SHIFT                8
-#define AM33XX_MODFREQDIV_EXPONENT_MASK                 (0x10 << 8)
+#define AM33XX_MODFREQDIV_EXPONENT_WIDTH                3
+#define AM33XX_MODFREQDIV_EXPONENT_MASK                 (0x7 << 8)
 
 /*
  * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
@@ -543,7 +649,8 @@
  * CM_SSC_MODFREQDIV_DPLL_PER
  */
 #define AM33XX_MODFREQDIV_MANTISSA_SHIFT                0
-#define AM33XX_MODFREQDIV_MANTISSA_MASK                 (0x06 << 0)
+#define AM33XX_MODFREQDIV_MANTISSA_WIDTH                7
+#define AM33XX_MODFREQDIV_MANTISSA_MASK                 (0x7f << 0)
 
 /*
  * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
@@ -580,42 +687,52 @@
  * CM_CEFUSE_CEFUSE_CLKCTRL
  */
 #define AM33XX_MODULEMODE_SHIFT                         0
+#define AM33XX_MODULEMODE_WIDTH                         2
 #define AM33XX_MODULEMODE_MASK                          (0x3 << 0)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT                  30
+#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH                  1
 #define AM33XX_OPTCLK_DEBUG_CLKA_MASK                   (1 << 30)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT                19
+#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH                1
 #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK                 (1 << 19)
 
 /* Used by CM_WKUP_GPIO0_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT             18
+#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH             1
 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK              (1 << 18)
 
 /* Used by CM_PER_GPIO1_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK             (1 << 18)
 
 /* Used by CM_PER_GPIO2_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK             (1 << 18)
 
 /* Used by CM_PER_GPIO3_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK             (1 << 18)
 
 /* Used by CM_PER_GPIO4_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK             (1 << 18)
 
 /* Used by CM_PER_GPIO5_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK             (1 << 18)
 
 /* Used by CM_PER_GPIO6_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK             (1 << 18)
 
 /*
@@ -627,25 +744,30 @@
  * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
  */
 #define AM33XX_STBYST_SHIFT                             18
+#define AM33XX_STBYST_WIDTH                             1
 #define AM33XX_STBYST_MASK                              (1 << 18)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT                  27
-#define AM33XX_STM_PMD_CLKDIVSEL_MASK                   (0x29 << 27)
+#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH                  3
+#define AM33XX_STM_PMD_CLKDIVSEL_MASK                   (0x7 << 27)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_STM_PMD_CLKSEL_SHIFT                     22
-#define AM33XX_STM_PMD_CLKSEL_MASK                      (0x23 << 22)
+#define AM33XX_STM_PMD_CLKSEL_WIDTH                     2
+#define AM33XX_STM_PMD_CLKSEL_MASK                      (0x3 << 22)
 
 /*
  * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
  * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
  */
 #define AM33XX_ST_DPLL_CLK_SHIFT                        0
+#define AM33XX_ST_DPLL_CLK_WIDTH                        1
 #define AM33XX_ST_DPLL_CLK_MASK                         (1 << 0)
 
 /* Used by CM_CLKDCOLDO_DPLL_PER */
 #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT                  8
+#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH                  1
 #define AM33XX_ST_DPLL_CLKDCOLDO_MASK                   (1 << 8)
 
 /*
@@ -653,18 +775,22 @@
  * CM_DIV_M2_DPLL_PER
  */
 #define AM33XX_ST_DPLL_CLKOUT_SHIFT                     9
+#define AM33XX_ST_DPLL_CLKOUT_WIDTH                     1
 #define AM33XX_ST_DPLL_CLKOUT_MASK                      (1 << 9)
 
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH               1
 #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK                (1 << 9)
 
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH               1
 #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK                (1 << 9)
 
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH               1
 #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK                (1 << 9)
 
 /*
@@ -672,16 +798,20 @@
  * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
  */
 #define AM33XX_ST_MN_BYPASS_SHIFT                       8
+#define AM33XX_ST_MN_BYPASS_WIDTH                       1
 #define AM33XX_ST_MN_BYPASS_MASK                        (1 << 8)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT                  24
-#define AM33XX_TRC_PMD_CLKDIVSEL_MASK                   (0x26 << 24)
+#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH                  3
+#define AM33XX_TRC_PMD_CLKDIVSEL_MASK                   (0x7 << 24)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_TRC_PMD_CLKSEL_SHIFT                     20
-#define AM33XX_TRC_PMD_CLKSEL_MASK                      (0x21 << 20)
+#define AM33XX_TRC_PMD_CLKSEL_WIDTH                     2
+#define AM33XX_TRC_PMD_CLKSEL_MASK                      (0x3 << 20)
 
 /* Used by CONTROL_SEC_CLK_CTRL */
+#define AM33XX_TIMER0_CLKSEL_WIDTH                      2
 #define AM33XX_TIMER0_CLKSEL_MASK                       (0x3 << 4)
 #endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 975f6bda0e0b..59598ffd8783 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -218,6 +218,8 @@
 #define OMAP3430_ST_MAILBOXES_MASK                      (1 << 7)
 #define OMAP3430_ST_OMAPCTRL_SHIFT                      6
 #define OMAP3430_ST_OMAPCTRL_MASK                       (1 << 6)
+#define OMAP3430_ST_SAD2D_SHIFT                         3
+#define OMAP3430_ST_SAD2D_MASK                          (1 << 3)
 #define OMAP3430_ST_SDMA_SHIFT                          2
 #define OMAP3430_ST_SDMA_MASK                           (1 << 2)
 #define OMAP3430_ST_SDRC_SHIFT                          1
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 65597a745638..4c6c2f7de65b 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -1,7 +1,7 @@
 /*
  * OMAP44xx Clock Management register bits
  *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
  * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley (paul@pwsan.com)
@@ -24,6 +24,7 @@
 
 /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
 #define OMAP4430_ABE_DYNDEP_SHIFT                               3
+#define OMAP4430_ABE_DYNDEP_WIDTH                               0x1
 #define OMAP4430_ABE_DYNDEP_MASK                                (1 << 3)
 
 /*
@@ -31,14 +32,17 @@
  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_ABE_STATDEP_SHIFT                              3
+#define OMAP4430_ABE_STATDEP_WIDTH                              0x1
 #define OMAP4430_ABE_STATDEP_MASK                               (1 << 3)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_ALWONCORE_DYNDEP_SHIFT                         16
+#define OMAP4430_ALWONCORE_DYNDEP_WIDTH                         0x1
 #define OMAP4430_ALWONCORE_DYNDEP_MASK                          (1 << 16)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
 #define OMAP4430_ALWONCORE_STATDEP_SHIFT                        16
+#define OMAP4430_ALWONCORE_STATDEP_WIDTH                        0x1
 #define OMAP4430_ALWONCORE_STATDEP_MASK                         (1 << 16)
 
 /*
@@ -47,294 +51,367 @@
  * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
  */
 #define OMAP4430_AUTO_DPLL_MODE_SHIFT                           0
+#define OMAP4430_AUTO_DPLL_MODE_WIDTH                           0x3
 #define OMAP4430_AUTO_DPLL_MODE_MASK                            (0x7 << 0)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_CEFUSE_DYNDEP_SHIFT                            17
+#define OMAP4430_CEFUSE_DYNDEP_WIDTH                            0x1
 #define OMAP4430_CEFUSE_DYNDEP_MASK                             (1 << 17)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
 #define OMAP4430_CEFUSE_STATDEP_SHIFT                           17
+#define OMAP4430_CEFUSE_STATDEP_WIDTH                           0x1
 #define OMAP4430_CEFUSE_STATDEP_MASK                            (1 << 17)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                13
+#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 (1 << 13)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT            12
+#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             (1 << 12)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT                   9
+#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    (1 << 9)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT                   11
+#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    (1 << 11)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                   8
+#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    (1 << 8)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT                11
+#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 (1 << 11)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT               12
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                (1 << 12)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT               13
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                (1 << 13)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT            9
+#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             (1 << 9)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT         12
+#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH         0x1
 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK          (1 << 12)
 
 /* Used by CM_EMU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT            9
+#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             (1 << 9)
 
 /* Used by CM_L4CFG_CLKSTCTRL */
 #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT                9
+#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH                0x1
 #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK                 (1 << 9)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT           9
+#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH           0x1
 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            (1 << 9)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                      9
+#define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH                      0x1
 #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                  9
+#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH                  0x1
 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                  10
+#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH                  0x1
 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   (1 << 10)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                   11
+#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    (1 << 11)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                   12
+#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    (1 << 12)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                   13
+#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    (1 << 13)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                   14
+#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    (1 << 14)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT            10
+#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             (1 << 10)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT                     9
+#define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH                     0x1
 #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      (1 << 9)
 
 /* Used by CM_DUCATI_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT                  8
+#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH                  0x1
 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   (1 << 8)
 
 /* Used by CM_EMU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT                  8
+#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH                  0x1
 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   (1 << 8)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                   10
+#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    (1 << 10)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT               15
+#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                (1 << 15)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT               10
+#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                (1 << 10)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT         11
+#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH         0x1
 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          (1 << 11)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT           20
+#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH           0x1
 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            (1 << 20)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                26
+#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 (1 << 26)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT           21
+#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH           0x1
 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            (1 << 21)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                27
+#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 (1 << 27)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT              13
+#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               (1 << 13)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT               12
+#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                (1 << 12)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT            28
+#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             (1 << 28)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT            29
+#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             (1 << 29)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT               11
+#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                (1 << 11)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT               16
+#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                (1 << 16)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT            17
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             (1 << 17)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT            18
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             (1 << 18)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT            19
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             (1 << 19)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT                     8
+#define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH                     0x1
 #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      (1 << 8)
 
 /* Used by CM_IVAHD_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT               8
+#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                (1 << 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT               10
+#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK                (1 << 10)
 
 /* Used by CM_L3_1_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                   8
+#define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    (1 << 8)
 
 /* Used by CM_L3_2_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                   8
+#define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    (1 << 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_SDMA_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT                8
+#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 (1 << 8)
 
 /* Used by CM_GFX_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT                8
+#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 (1 << 8)
 
 /* Used by CM_L3INSTR_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT               8
+#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                (1 << 8)
 
 /* Used by CM_L4SEC_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT              8
+#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               (1 << 8)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT                   8
+#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    (1 << 8)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT              8
+#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               (1 << 8)
 
 /* Used by CM_L4CFG_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                 9
+#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  (1 << 9)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT                9
+#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_L4SEC_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT              9
+#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               (1 << 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT                12
+#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 (1 << 12)
 
 /* Used by CM_MPU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  (1 << 8)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT                9
+#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT               16
+#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                (1 << 16)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT                17
+#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 (1 << 17)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT                18
+#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 (1 << 18)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT                19
+#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 (1 << 19)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT            25
+#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             (1 << 25)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT             20
+#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH             0x1
 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              (1 << 20)
 
 /* Used by CM_L4PER_CLKSTCTRL */
@@ -343,94 +420,114 @@
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT             22
+#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH             0x1
 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              (1 << 22)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT                24
+#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 (1 << 24)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                 10
+#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  (1 << 10)
 
 /* Used by CM_GFX_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT                    9
+#define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH                    0x1
 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     (1 << 9)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT               11
+#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                (1 << 11)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT                10
+#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 (1 << 10)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT                9
+#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 (1 << 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT                      8
+#define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH                      0x1
 #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       (1 << 8)
 
 /* Used by CM_TESLA_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT               8
+#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                (1 << 8)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                22
+#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 (1 << 22)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                23
+#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 (1 << 23)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                24
+#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 (1 << 24)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT              10
+#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK               (1 << 10)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT                 14
+#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK                  (1 << 14)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT              15
+#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               (1 << 15)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                   10
+#define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    (1 << 10)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                30
+#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 (1 << 30)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT              25
+#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               (1 << 25)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT               11
+#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                (1 << 11)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT                13
+#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH                0x1
 #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK                 (1 << 13)
 
 /*
  * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
  * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
- * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
  * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
  * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
- * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
- * CM_WKUP_TIMER1_CLKCTRL
+ * CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL
  */
 #define OMAP4430_CLKSEL_SHIFT                                   24
+#define OMAP4430_CLKSEL_WIDTH                                   0x1
 #define OMAP4430_CLKSEL_MASK                                    (1 << 24)
 
 /*
@@ -438,50 +535,62 @@
  * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
  */
 #define OMAP4430_CLKSEL_0_0_SHIFT                               0
+#define OMAP4430_CLKSEL_0_0_WIDTH                               0x1
 #define OMAP4430_CLKSEL_0_0_MASK                                (1 << 0)
 
 /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
 #define OMAP4430_CLKSEL_0_1_SHIFT                               0
+#define OMAP4430_CLKSEL_0_1_WIDTH                               0x2
 #define OMAP4430_CLKSEL_0_1_MASK                                (0x3 << 0)
 
 /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
 #define OMAP4430_CLKSEL_24_25_SHIFT                             24
+#define OMAP4430_CLKSEL_24_25_WIDTH                             0x2
 #define OMAP4430_CLKSEL_24_25_MASK                              (0x3 << 24)
 
 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 #define OMAP4430_CLKSEL_60M_SHIFT                               24
+#define OMAP4430_CLKSEL_60M_WIDTH                               0x1
 #define OMAP4430_CLKSEL_60M_MASK                                (1 << 24)
 
 /* Used by CM_MPU_MPU_CLKCTRL */
 #define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT                      25
+#define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH                      0x1
 #define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK                       (1 << 25)
 
 /* Used by CM1_ABE_AESS_CLKCTRL */
 #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                         24
+#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH                         0x1
 #define OMAP4430_CLKSEL_AESS_FCLK_MASK                          (1 << 24)
 
 /* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_CORE_SHIFT                              0
+#define OMAP4430_CLKSEL_CORE_WIDTH                              0x1
 #define OMAP4430_CLKSEL_CORE_MASK                               (1 << 0)
 
 /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_CLKSEL_CORE_1_1_SHIFT                          1
+#define OMAP4430_CLKSEL_CORE_1_1_WIDTH                          0x1
 #define OMAP4430_CLKSEL_CORE_1_1_MASK                           (1 << 1)
 
 /* Used by CM_WKUP_USIM_CLKCTRL */
 #define OMAP4430_CLKSEL_DIV_SHIFT                               24
+#define OMAP4430_CLKSEL_DIV_WIDTH                               0x1
 #define OMAP4430_CLKSEL_DIV_MASK                                (1 << 24)
 
 /* Used by CM_MPU_MPU_CLKCTRL */
 #define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT                     24
+#define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH                     0x1
 #define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK                      (1 << 24)
 
 /* Used by CM_CAM_FDIF_CLKCTRL */
 #define OMAP4430_CLKSEL_FCLK_SHIFT                              24
+#define OMAP4430_CLKSEL_FCLK_WIDTH                              0x2
 #define OMAP4430_CLKSEL_FCLK_MASK                               (0x3 << 24)
 
 /* Used by CM_L4PER_MCBSP4_CLKCTRL */
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT                   25
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH                   0x1
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    (1 << 25)
 
 /*
@@ -490,34 +599,42 @@
  * CM1_ABE_MCBSP3_CLKCTRL
  */
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT      26
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH      0x2
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       (0x3 << 26)
 
 /* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_L3_SHIFT                                4
+#define OMAP4430_CLKSEL_L3_WIDTH                                0x1
 #define OMAP4430_CLKSEL_L3_MASK                                 (1 << 4)
 
 /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                         2
+#define OMAP4430_CLKSEL_L3_SHADOW_WIDTH                         0x1
 #define OMAP4430_CLKSEL_L3_SHADOW_MASK                          (1 << 2)
 
 /* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_L4_SHIFT                                8
+#define OMAP4430_CLKSEL_L4_WIDTH                                0x1
 #define OMAP4430_CLKSEL_L4_MASK                                 (1 << 8)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_CLKSEL_OPP_SHIFT                               0
+#define OMAP4430_CLKSEL_OPP_WIDTH                               0x2
 #define OMAP4430_CLKSEL_OPP_MASK                                (0x3 << 0)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT                       27
+#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH                       0x3
 #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        (0x7 << 27)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT                     24
+#define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH                     0x3
 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      (0x7 << 24)
 
 /* Used by CM_GFX_GFX_CLKCTRL */
 #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT                          24
+#define OMAP4430_CLKSEL_SGX_FCLK_WIDTH                          0x1
 #define OMAP4430_CLKSEL_SGX_FCLK_MASK                           (1 << 24)
 
 /*
@@ -525,18 +642,22 @@
  * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
  */
 #define OMAP4430_CLKSEL_SOURCE_SHIFT                            24
+#define OMAP4430_CLKSEL_SOURCE_WIDTH                            0x2
 #define OMAP4430_CLKSEL_SOURCE_MASK                             (0x3 << 24)
 
 /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
 #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                      24
+#define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH                      0x1
 #define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       (1 << 24)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_CLKSEL_UTMI_P1_SHIFT                           24
+#define OMAP4430_CLKSEL_UTMI_P1_WIDTH                           0x1
 #define OMAP4430_CLKSEL_UTMI_P1_MASK                            (1 << 24)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_CLKSEL_UTMI_P2_SHIFT                           25
+#define OMAP4430_CLKSEL_UTMI_P2_WIDTH                           0x1
 #define OMAP4430_CLKSEL_UTMI_P2_MASK                            (1 << 25)
 
 /*
@@ -549,30 +670,37 @@
  * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
  */
 #define OMAP4430_CLKTRCTRL_SHIFT                                0
+#define OMAP4430_CLKTRCTRL_WIDTH                                0x2
 #define OMAP4430_CLKTRCTRL_MASK                                 (0x3 << 0)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT                        0
+#define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH                        0x7
 #define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         (0x7f << 0)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT                       8
+#define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH                       0xb
 #define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        (0x7ff << 8)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_CUSTOM_SHIFT                                   6
+#define OMAP4430_CUSTOM_WIDTH                                   0x2
 #define OMAP4430_CUSTOM_MASK                                    (0x3 << 6)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_D2D_DYNDEP_SHIFT                               18
+#define OMAP4430_D2D_DYNDEP_WIDTH                               0x1
 #define OMAP4430_D2D_DYNDEP_MASK                                (1 << 18)
 
 /* Used by CM_MPU_STATICDEP */
 #define OMAP4430_D2D_STATDEP_SHIFT                              18
+#define OMAP4430_D2D_STATDEP_WIDTH                              0x1
 #define OMAP4430_D2D_STATDEP_MASK                               (1 << 18)
 
 /* Used by CM_CLKSEL_DPLL_MPU */
 #define OMAP4460_DCC_COUNT_MAX_SHIFT                            24
+#define OMAP4460_DCC_COUNT_MAX_WIDTH                            0x8
 #define OMAP4460_DCC_COUNT_MAX_MASK                             (0xff << 24)
 
 /* Used by CM_CLKSEL_DPLL_MPU */
@@ -586,22 +714,27 @@
  * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
  */
 #define OMAP4430_DELTAMSTEP_SHIFT                               0
+#define OMAP4430_DELTAMSTEP_WIDTH                               0x14
 #define OMAP4430_DELTAMSTEP_MASK                                (0xfffff << 0)
 
 /* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
 #define OMAP4460_DELTAMSTEP_0_20_SHIFT                          0
+#define OMAP4460_DELTAMSTEP_0_20_WIDTH                          0x15
 #define OMAP4460_DELTAMSTEP_0_20_MASK                           (0x1fffff << 0)
 
 /* Used by CM_DLL_CTRL */
 #define OMAP4430_DLL_OVERRIDE_SHIFT                             0
+#define OMAP4430_DLL_OVERRIDE_WIDTH                             0x1
 #define OMAP4430_DLL_OVERRIDE_MASK                              (1 << 0)
 
 /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DLL_OVERRIDE_2_2_SHIFT                         2
+#define OMAP4430_DLL_OVERRIDE_2_2_WIDTH                         0x1
 #define OMAP4430_DLL_OVERRIDE_2_2_MASK                          (1 << 2)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DLL_RESET_SHIFT                                3
+#define OMAP4430_DLL_RESET_WIDTH                                0x1
 #define OMAP4430_DLL_RESET_MASK                                 (1 << 3)
 
 /*
@@ -610,30 +743,37 @@
  * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
  */
 #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                          23
+#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH                          0x1
 #define OMAP4430_DPLL_BYP_CLKSEL_MASK                           (1 << 23)
 
 /* Used by CM_CLKDCOLDO_DPLL_USB */
 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                 8
+#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH                 0x1
 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  (1 << 8)
 
 /* Used by CM_CLKSEL_DPLL_CORE */
 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                    20
+#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH                    0x1
 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     (1 << 20)
 
 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                       0
+#define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH                       0x5
 #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        (0x1f << 0)
 
 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                  5
+#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH                  0x1
 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   (1 << 5)
 
 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                 8
+#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH                 0x1
 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  (1 << 8)
 
 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT                  10
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH                  0x1
 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   (1 << 10)
 
 /*
@@ -641,10 +781,12 @@
  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                          0
+#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH                          0x5
 #define OMAP4430_DPLL_CLKOUT_DIV_MASK                           (0x1f << 0)
 
 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT                      0
+#define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH                      0x7
 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       (0x7f << 0)
 
 /*
@@ -652,10 +794,12 @@
  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                     5
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH                     0x1
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      (1 << 5)
 
 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT              7
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH              0x1
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               (1 << 7)
 
 /*
@@ -663,18 +807,22 @@
  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
  */
 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                    8
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH                    0x1
 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     (1 << 8)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                        8
+#define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH                        0x3
 #define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         (0x7 << 8)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                         11
+#define OMAP4430_DPLL_CORE_M2_DIV_WIDTH                         0x5
 #define OMAP4430_DPLL_CORE_M2_DIV_MASK                          (0x1f << 11)
 
 /* Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                         3
+#define OMAP4430_DPLL_CORE_M5_DIV_WIDTH                         0x5
 #define OMAP4430_DPLL_CORE_M5_DIV_MASK                          (0x1f << 3)
 
 /*
@@ -683,10 +831,12 @@
  * CM_CLKSEL_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_DIV_SHIFT                                 0
+#define OMAP4430_DPLL_DIV_WIDTH                                 0x7
 #define OMAP4430_DPLL_DIV_MASK                                  (0x7f << 0)
 
 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_DIV_0_7_SHIFT                             0
+#define OMAP4430_DPLL_DIV_0_7_WIDTH                             0x8
 #define OMAP4430_DPLL_DIV_0_7_MASK                              (0xff << 0)
 
 /*
@@ -694,10 +844,12 @@
  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                       8
+#define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH                       0x1
 #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        (1 << 8)
 
 /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT                   3
+#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH                   0x1
 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    (1 << 3)
 
 /*
@@ -706,6 +858,7 @@
  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_EN_SHIFT                                  0
+#define OMAP4430_DPLL_EN_WIDTH                                  0x3
 #define OMAP4430_DPLL_EN_MASK                                   (0x7 << 0)
 
 /*
@@ -714,6 +867,7 @@
  * CM_CLKMODE_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_LPMODE_EN_SHIFT                           10
+#define OMAP4430_DPLL_LPMODE_EN_WIDTH                           0x1
 #define OMAP4430_DPLL_LPMODE_EN_MASK                            (1 << 10)
 
 /*
@@ -722,10 +876,12 @@
  * CM_CLKSEL_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_MULT_SHIFT                                8
+#define OMAP4430_DPLL_MULT_WIDTH                                0xb
 #define OMAP4430_DPLL_MULT_MASK                                 (0x7ff << 8)
 
 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_MULT_USB_SHIFT                            8
+#define OMAP4430_DPLL_MULT_USB_WIDTH                            0xc
 #define OMAP4430_DPLL_MULT_USB_MASK                             (0xfff << 8)
 
 /*
@@ -734,10 +890,12 @@
  * CM_CLKMODE_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_REGM4XEN_SHIFT                            11
+#define OMAP4430_DPLL_REGM4XEN_WIDTH                            0x1
 #define OMAP4430_DPLL_REGM4XEN_MASK                             (1 << 11)
 
 /* Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_SD_DIV_SHIFT                              24
+#define OMAP4430_DPLL_SD_DIV_WIDTH                              0x8
 #define OMAP4430_DPLL_SD_DIV_MASK                               (0xff << 24)
 
 /*
@@ -746,6 +904,7 @@
  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_ACK_SHIFT                             13
+#define OMAP4430_DPLL_SSC_ACK_WIDTH                             0x1
 #define OMAP4430_DPLL_SSC_ACK_MASK                              (1 << 13)
 
 /*
@@ -754,6 +913,7 @@
  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                      14
+#define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH                      0x1
 #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       (1 << 14)
 
 /*
@@ -762,42 +922,52 @@
  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_EN_SHIFT                              12
+#define OMAP4430_DPLL_SSC_EN_WIDTH                              0x1
 #define OMAP4430_DPLL_SSC_EN_MASK                               (1 << 12)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 #define OMAP4430_DSS_DYNDEP_SHIFT                               8
+#define OMAP4430_DSS_DYNDEP_WIDTH                               0x1
 #define OMAP4430_DSS_DYNDEP_MASK                                (1 << 8)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
 #define OMAP4430_DSS_STATDEP_SHIFT                              8
+#define OMAP4430_DSS_STATDEP_WIDTH                              0x1
 #define OMAP4430_DSS_STATDEP_MASK                               (1 << 8)
 
 /* Used by CM_L3_2_DYNAMICDEP */
 #define OMAP4430_DUCATI_DYNDEP_SHIFT                            0
+#define OMAP4430_DUCATI_DYNDEP_WIDTH                            0x1
 #define OMAP4430_DUCATI_DYNDEP_MASK                             (1 << 0)
 
 /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
 #define OMAP4430_DUCATI_STATDEP_SHIFT                           0
+#define OMAP4430_DUCATI_STATDEP_WIDTH                           0x1
 #define OMAP4430_DUCATI_STATDEP_MASK                            (1 << 0)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_FREQ_UPDATE_SHIFT                              0
+#define OMAP4430_FREQ_UPDATE_WIDTH                              0x1
 #define OMAP4430_FREQ_UPDATE_MASK                               (1 << 0)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_FUNC_SHIFT                                     16
+#define OMAP4430_FUNC_WIDTH                                     0xc
 #define OMAP4430_FUNC_MASK                                      (0xfff << 16)
 
 /* Used by CM_L3_2_DYNAMICDEP */
 #define OMAP4430_GFX_DYNDEP_SHIFT                               10
+#define OMAP4430_GFX_DYNDEP_WIDTH                               0x1
 #define OMAP4430_GFX_DYNDEP_MASK                                (1 << 10)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_GFX_STATDEP_SHIFT                              10
+#define OMAP4430_GFX_STATDEP_WIDTH                              0x1
 #define OMAP4430_GFX_STATDEP_MASK                               (1 << 10)
 
 /* Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                         0
+#define OMAP4430_GPMC_FREQ_UPDATE_WIDTH                         0x1
 #define OMAP4430_GPMC_FREQ_UPDATE_MASK                          (1 << 0)
 
 /*
@@ -805,6 +975,7 @@
  * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                    0
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     (0x1f << 0)
 
 /*
@@ -812,6 +983,7 @@
  * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT               5
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH               0x1
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                (1 << 5)
 
 /*
@@ -819,6 +991,7 @@
  * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT              8
+#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH              0x1
 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               (1 << 8)
 
 /*
@@ -826,6 +999,7 @@
  * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                   12
+#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH                   0x1
 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    (1 << 12)
 
 /*
@@ -833,6 +1007,7 @@
  * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                    0
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     (0x1f << 0)
 
 /*
@@ -840,6 +1015,7 @@
  * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT               5
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH               0x1
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                (1 << 5)
 
 /*
@@ -847,6 +1023,7 @@
  * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT              8
+#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH              0x1
 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               (1 << 8)
 
 /*
@@ -854,38 +1031,47 @@
  * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                   12
+#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH                   0x1
 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    (1 << 12)
 
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                    0
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     (0x1f << 0)
 
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT               5
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH               0x1
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                (1 << 5)
 
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT              8
+#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH              0x1
 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               (1 << 8)
 
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                   12
+#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH                   0x1
 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    (1 << 12)
 
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                    0
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     (0x1f << 0)
 
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT               5
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH               0x1
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                (1 << 5)
 
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT              8
+#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH              0x1
 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               (1 << 8)
 
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                   12
+#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH                   0x1
 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    (1 << 12)
 
 /*
@@ -893,53 +1079,48 @@
  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
  * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
- * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
- * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
- * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
- * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
- * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
+ * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
+ * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
+ * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
- * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
- * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
- * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
- * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
- * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
- * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
- * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
- * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
- * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
+ * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+ * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
+ * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
  * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
- * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
- * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
- * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
- * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
- * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
- * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
- * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
- * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
- * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
- * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
+ * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
+ * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
+ * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
+ * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
+ * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
+ * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
  * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
  * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
- * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
  * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
- * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
- * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
- * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
+ * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
+ * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
  */
 #define OMAP4430_IDLEST_SHIFT                                   16
+#define OMAP4430_IDLEST_WIDTH                                   0x2
 #define OMAP4430_IDLEST_MASK                                    (0x3 << 16)
 
 /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_ISS_DYNDEP_SHIFT                               9
+#define OMAP4430_ISS_DYNDEP_WIDTH                               0x1
 #define OMAP4430_ISS_DYNDEP_MASK                                (1 << 9)
 
 /*
@@ -947,10 +1128,12 @@
  * CM_TESLA_STATICDEP
  */
 #define OMAP4430_ISS_STATDEP_SHIFT                              9
+#define OMAP4430_ISS_STATDEP_WIDTH                              0x1
 #define OMAP4430_ISS_STATDEP_MASK                               (1 << 9)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
 #define OMAP4430_IVAHD_DYNDEP_SHIFT                             2
+#define OMAP4430_IVAHD_DYNDEP_WIDTH                             0x1
 #define OMAP4430_IVAHD_DYNDEP_MASK                              (1 << 2)
 
 /*
@@ -959,10 +1142,12 @@
  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_IVAHD_STATDEP_SHIFT                            2
+#define OMAP4430_IVAHD_STATDEP_WIDTH                            0x1
 #define OMAP4430_IVAHD_STATDEP_MASK                             (1 << 2)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 #define OMAP4430_L3INIT_DYNDEP_SHIFT                            7
+#define OMAP4430_L3INIT_DYNDEP_WIDTH                            0x1
 #define OMAP4430_L3INIT_DYNDEP_MASK                             (1 << 7)
 
 /*
@@ -970,6 +1155,7 @@
  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3INIT_STATDEP_SHIFT                           7
+#define OMAP4430_L3INIT_STATDEP_WIDTH                           0x1
 #define OMAP4430_L3INIT_STATDEP_MASK                            (1 << 7)
 
 /*
@@ -977,6 +1163,7 @@
  * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
  */
 #define OMAP4430_L3_1_DYNDEP_SHIFT                              5
+#define OMAP4430_L3_1_DYNDEP_WIDTH                              0x1
 #define OMAP4430_L3_1_DYNDEP_MASK                               (1 << 5)
 
 /*
@@ -986,6 +1173,7 @@
  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3_1_STATDEP_SHIFT                             5
+#define OMAP4430_L3_1_STATDEP_WIDTH                             0x1
 #define OMAP4430_L3_1_STATDEP_MASK                              (1 << 5)
 
 /*
@@ -995,6 +1183,7 @@
  * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
  */
 #define OMAP4430_L3_2_DYNDEP_SHIFT                              6
+#define OMAP4430_L3_2_DYNDEP_WIDTH                              0x1
 #define OMAP4430_L3_2_DYNDEP_MASK                               (1 << 6)
 
 /*
@@ -1004,10 +1193,12 @@
  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3_2_STATDEP_SHIFT                             6
+#define OMAP4430_L3_2_STATDEP_WIDTH                             0x1
 #define OMAP4430_L3_2_STATDEP_MASK                              (1 << 6)
 
 /* Used by CM_L3_1_DYNAMICDEP */
 #define OMAP4430_L4CFG_DYNDEP_SHIFT                             12
+#define OMAP4430_L4CFG_DYNDEP_WIDTH                             0x1
 #define OMAP4430_L4CFG_DYNDEP_MASK                              (1 << 12)
 
 /*
@@ -1015,10 +1206,12 @@
  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4CFG_STATDEP_SHIFT                            12
+#define OMAP4430_L4CFG_STATDEP_WIDTH                            0x1
 #define OMAP4430_L4CFG_STATDEP_MASK                             (1 << 12)
 
 /* Used by CM_L3_2_DYNAMICDEP */
 #define OMAP4430_L4PER_DYNDEP_SHIFT                             13
+#define OMAP4430_L4PER_DYNDEP_WIDTH                             0x1
 #define OMAP4430_L4PER_DYNDEP_MASK                              (1 << 13)
 
 /*
@@ -1026,10 +1219,12 @@
  * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4PER_STATDEP_SHIFT                            13
+#define OMAP4430_L4PER_STATDEP_WIDTH                            0x1
 #define OMAP4430_L4PER_STATDEP_MASK                             (1 << 13)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 #define OMAP4430_L4SEC_DYNDEP_SHIFT                             14
+#define OMAP4430_L4SEC_DYNDEP_WIDTH                             0x1
 #define OMAP4430_L4SEC_DYNDEP_MASK                              (1 << 14)
 
 /*
@@ -1037,10 +1232,12 @@
  * CM_SDMA_STATICDEP
  */
 #define OMAP4430_L4SEC_STATDEP_SHIFT                            14
+#define OMAP4430_L4SEC_STATDEP_WIDTH                            0x1
 #define OMAP4430_L4SEC_STATDEP_MASK                             (1 << 14)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_L4WKUP_DYNDEP_SHIFT                            15
+#define OMAP4430_L4WKUP_DYNDEP_WIDTH                            0x1
 #define OMAP4430_L4WKUP_DYNDEP_MASK                             (1 << 15)
 
 /*
@@ -1048,6 +1245,7 @@
  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4WKUP_STATDEP_SHIFT                           15
+#define OMAP4430_L4WKUP_STATDEP_WIDTH                           0x1
 #define OMAP4430_L4WKUP_STATDEP_MASK                            (1 << 15)
 
 /*
@@ -1055,6 +1253,7 @@
  * CM_MPU_DYNAMICDEP
  */
 #define OMAP4430_MEMIF_DYNDEP_SHIFT                             4
+#define OMAP4430_MEMIF_DYNDEP_WIDTH                             0x1
 #define OMAP4430_MEMIF_DYNDEP_MASK                              (1 << 4)
 
 /*
@@ -1064,6 +1263,7 @@
  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_MEMIF_STATDEP_SHIFT                            4
+#define OMAP4430_MEMIF_STATDEP_WIDTH                            0x1
 #define OMAP4430_MEMIF_STATDEP_MASK                             (1 << 4)
 
 /*
@@ -1073,6 +1273,7 @@
  * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
  */
 #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                      8
+#define OMAP4430_MODFREQDIV_EXPONENT_WIDTH                      0x3
 #define OMAP4430_MODFREQDIV_EXPONENT_MASK                       (0x7 << 8)
 
 /*
@@ -1082,6 +1283,7 @@
  * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
  */
 #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                      0
+#define OMAP4430_MODFREQDIV_MANTISSA_WIDTH                      0x7
 #define OMAP4430_MODFREQDIV_MANTISSA_MASK                       (0x7f << 0)
 
 /*
@@ -1089,69 +1291,68 @@
  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
  * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
- * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
- * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
- * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
- * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
- * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
+ * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
+ * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
+ * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
- * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
- * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
- * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
- * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
- * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
- * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
- * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
- * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
- * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
+ * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+ * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
+ * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
  * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
- * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
- * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
- * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
- * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
- * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
- * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
- * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
- * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
- * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
- * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
+ * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
+ * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
+ * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
+ * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
+ * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
+ * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
  * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
  * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
- * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
  * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
- * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
- * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
- * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
+ * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
+ * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
  */
 #define OMAP4430_MODULEMODE_SHIFT                               0
+#define OMAP4430_MODULEMODE_WIDTH                               0x2
 #define OMAP4430_MODULEMODE_MASK                                (0x3 << 0)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4460_MPU_DYNDEP_SHIFT                               19
+#define OMAP4460_MPU_DYNDEP_WIDTH                               0x1
 #define OMAP4460_MPU_DYNDEP_MASK                                (1 << 19)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT                      9
+#define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH                      0x1
 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       (1 << 9)
 
 /* Used by CM_WKUP_BANDGAP_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT                       8
+#define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH                       0x1
 #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        (1 << 8)
 
 /* Used by CM_ALWON_USBPHY_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         8
+#define OMAP4430_OPTFCLKEN_CLK32K_WIDTH                         0x1
 #define OMAP4430_OPTFCLKEN_CLK32K_MASK                          (1 << 8)
 
 /* Used by CM_CAM_ISS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT                        8
+#define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH                        0x1
 #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         (1 << 8)
 
 /*
@@ -1160,126 +1361,157 @@
  * CM_WKUP_GPIO1_CLKCTRL
  */
 #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                          8
+#define OMAP4430_OPTFCLKEN_DBCLK_WIDTH                          0x1
 #define OMAP4430_OPTFCLKEN_DBCLK_MASK                           (1 << 8)
 
 /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT                        8
+#define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH                        0x1
 #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         (1 << 8)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT                         8
+#define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH                         0x1
 #define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          (1 << 8)
 
 /* Used by CM_WKUP_USIM_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK_SHIFT                           8
+#define OMAP4430_OPTFCLKEN_FCLK_WIDTH                           0x1
 #define OMAP4430_OPTFCLKEN_FCLK_MASK                            (1 << 8)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT                          8
+#define OMAP4430_OPTFCLKEN_FCLK0_WIDTH                          0x1
 #define OMAP4430_OPTFCLKEN_FCLK0_MASK                           (1 << 8)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT                          9
+#define OMAP4430_OPTFCLKEN_FCLK1_WIDTH                          0x1
 #define OMAP4430_OPTFCLKEN_FCLK1_MASK                           (1 << 9)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                          10
+#define OMAP4430_OPTFCLKEN_FCLK2_WIDTH                          0x1
 #define OMAP4430_OPTFCLKEN_FCLK2_MASK                           (1 << 10)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                     15
+#define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH                     0x1
 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      (1 << 15)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                13
+#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH                0x1
 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 (1 << 13)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                14
+#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH                0x1
 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 (1 << 14)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                 11
+#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH                 0x1
 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  (1 << 11)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                 12
+#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH                 0x1
 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  (1 << 12)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT                  8
+#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH                  0x1
 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   (1 << 8)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT                9
+#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH                0x1
 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 (1 << 9)
 
 /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT                        8
+#define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH                        0x1
 #define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         (1 << 8)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT                    10
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     (1 << 10)
 
 /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT              11
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH              0x1
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               (1 << 11)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT                        10
+#define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH                        0x1
 #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         (1 << 10)
 
 /* Used by CM_WKUP_BANDGAP_CLKCTRL */
 #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT                        8
+#define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH                        0x1
 #define OMAP4460_OPTFCLKEN_TS_FCLK_MASK                         (1 << 8)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT                         11
+#define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH                         0x1
 #define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          (1 << 11)
 
 /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                       8
+#define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH                       0x1
 #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        (1 << 8)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                    8
+#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     (1 << 8)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                    9
+#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     (1 << 9)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                    10
+#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     (1 << 10)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                    8
+#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     (1 << 8)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                    9
+#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     (1 << 9)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                    10
+#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     (1 << 10)
 
 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_XCLK_SHIFT                           8
+#define OMAP4430_OPTFCLKEN_XCLK_WIDTH                           0x1
 #define OMAP4430_OPTFCLKEN_XCLK_MASK                            (1 << 8)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_OVERRIDE_ENABLE_SHIFT                          19
+#define OMAP4430_OVERRIDE_ENABLE_WIDTH                          0x1
 #define OMAP4430_OVERRIDE_ENABLE_MASK                           (1 << 19)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_PAD_CLKS_GATE_SHIFT                            8
+#define OMAP4430_PAD_CLKS_GATE_WIDTH                            0x1
 #define OMAP4430_PAD_CLKS_GATE_MASK                             (1 << 8)
 
 /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
 #define OMAP4430_PERF_CURRENT_SHIFT                             0
+#define OMAP4430_PERF_CURRENT_WIDTH                             0x8
 #define OMAP4430_PERF_CURRENT_MASK                              (0xff << 0)
 
 /*
@@ -1288,74 +1520,85 @@
  * CM_IVA_DVFS_PERF_TESLA
  */
 #define OMAP4430_PERF_REQ_SHIFT                                 0
+#define OMAP4430_PERF_REQ_WIDTH                                 0x8
 #define OMAP4430_PERF_REQ_MASK                                  (0xff << 0)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE1_COMPLETED_SHIFT                         0
+#define OMAP4430_PHASE1_COMPLETED_WIDTH                         0x1
 #define OMAP4430_PHASE1_COMPLETED_MASK                          (1 << 0)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE2A_COMPLETED_SHIFT                        1
+#define OMAP4430_PHASE2A_COMPLETED_WIDTH                        0x1
 #define OMAP4430_PHASE2A_COMPLETED_MASK                         (1 << 1)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE2B_COMPLETED_SHIFT                        2
+#define OMAP4430_PHASE2B_COMPLETED_WIDTH                        0x1
 #define OMAP4430_PHASE2B_COMPLETED_MASK                         (1 << 2)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT                         20
+#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH                         0x2
 #define OMAP4430_PMD_STM_MUX_CTRL_MASK                          (0x3 << 20)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                       22
+#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH                       0x2
 #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        (0x3 << 22)
 
 /* Used by CM_DYN_DEP_PRESCAL */
 #define OMAP4430_PRESCAL_SHIFT                                  0
+#define OMAP4430_PRESCAL_WIDTH                                  0x6
 #define OMAP4430_PRESCAL_MASK                                   (0x3f << 0)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_R_RTL_SHIFT                                    11
+#define OMAP4430_R_RTL_WIDTH                                    0x5
 #define OMAP4430_R_RTL_MASK                                     (0x1f << 11)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_SAR_MODE_SHIFT                                 4
+#define OMAP4430_SAR_MODE_WIDTH                                 0x1
 #define OMAP4430_SAR_MODE_MASK                                  (1 << 4)
 
 /* Used by CM_SCALE_FCLK */
 #define OMAP4430_SCALE_FCLK_SHIFT                               0
+#define OMAP4430_SCALE_FCLK_WIDTH                               0x1
 #define OMAP4430_SCALE_FCLK_MASK                                (1 << 0)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_SCHEME_SHIFT                                   30
+#define OMAP4430_SCHEME_WIDTH                                   0x2
 #define OMAP4430_SCHEME_MASK                                    (0x3 << 30)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_SDMA_DYNDEP_SHIFT                              11
+#define OMAP4430_SDMA_DYNDEP_WIDTH                              0x1
 #define OMAP4430_SDMA_DYNDEP_MASK                               (1 << 11)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_SDMA_STATDEP_SHIFT                             11
+#define OMAP4430_SDMA_STATDEP_WIDTH                             0x1
 #define OMAP4430_SDMA_STATDEP_MASK                              (1 << 11)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT                         10
+#define OMAP4430_SLIMBUS_CLK_GATE_WIDTH                         0x1
 #define OMAP4430_SLIMBUS_CLK_GATE_MASK                          (1 << 10)
 
 /*
  * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
- * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
- * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL,
- * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
- * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
- * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
  * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL,
- * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
- * CM_TESLA_TESLA_CLKCTRL
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
  */
 #define OMAP4430_STBYST_SHIFT                                   18
+#define OMAP4430_STBYST_WIDTH                                   0x1
 #define OMAP4430_STBYST_MASK                                    (1 << 18)
 
 /*
@@ -1364,10 +1607,12 @@
  * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
  */
 #define OMAP4430_ST_DPLL_CLK_SHIFT                              0
+#define OMAP4430_ST_DPLL_CLK_WIDTH                              0x1
 #define OMAP4430_ST_DPLL_CLK_MASK                               (1 << 0)
 
 /* Used by CM_CLKDCOLDO_DPLL_USB */
 #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT                        9
+#define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH                        0x1
 #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         (1 << 9)
 
 /*
@@ -1375,14 +1620,17 @@
  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
  */
 #define OMAP4430_ST_DPLL_CLKOUT_SHIFT                           9
+#define OMAP4430_ST_DPLL_CLKOUT_WIDTH                           0x1
 #define OMAP4430_ST_DPLL_CLKOUT_MASK                            (1 << 9)
 
 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                        9
+#define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH                        0x1
 #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         (1 << 9)
 
 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT                         11
+#define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH                         0x1
 #define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          (1 << 11)
 
 /*
@@ -1390,6 +1638,7 @@
  * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                     9
+#define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH                     0x1
 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      (1 << 9)
 
 /*
@@ -1397,14 +1646,17 @@
  * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                     9
+#define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH                     0x1
 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      (1 << 9)
 
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                     9
+#define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH                     0x1
 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      (1 << 9)
 
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                     9
+#define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH                     0x1
 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      (1 << 9)
 
 /*
@@ -1413,18 +1665,22 @@
  * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
  */
 #define OMAP4430_ST_MN_BYPASS_SHIFT                             8
+#define OMAP4430_ST_MN_BYPASS_WIDTH                             0x1
 #define OMAP4430_ST_MN_BYPASS_MASK                              (1 << 8)
 
 /* Used by CM_SYS_CLKSEL */
 #define OMAP4430_SYS_CLKSEL_SHIFT                               0
+#define OMAP4430_SYS_CLKSEL_WIDTH                               0x3
 #define OMAP4430_SYS_CLKSEL_MASK                                (0x7 << 0)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_TESLA_DYNDEP_SHIFT                             1
+#define OMAP4430_TESLA_DYNDEP_WIDTH                             0x1
 #define OMAP4430_TESLA_DYNDEP_MASK                              (1 << 1)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_TESLA_STATDEP_SHIFT                            1
+#define OMAP4430_TESLA_STATDEP_WIDTH                            0x1
 #define OMAP4430_TESLA_STATDEP_MASK                             (1 << 1)
 
 /*
@@ -1433,13 +1689,16 @@
  * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
  */
 #define OMAP4430_WINDOWSIZE_SHIFT                               24
+#define OMAP4430_WINDOWSIZE_WIDTH                               0x4
 #define OMAP4430_WINDOWSIZE_MASK                                (0xf << 24)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_X_MAJOR_SHIFT                                  8
+#define OMAP4430_X_MAJOR_WIDTH                                  0x3
 #define OMAP4430_X_MAJOR_MASK                                   (0x7 << 8)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_Y_MINOR_SHIFT                                  0
+#define OMAP4430_Y_MINOR_WIDTH                                  0x6
 #define OMAP4430_Y_MINOR_MASK                                   (0x3f << 0)
 #endif
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index a911e76b4ecf..7f07ab02a5b3 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -35,7 +35,7 @@
 #define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP           0x3
 
 static const u8 cm_idlest_offs[] = {
-        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
+        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
 };
 
 u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index 088bbad73db5..57b2f3c2fbf3 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -71,6 +71,7 @@
 #define OMAP24XX_CM_FCLKEN2                             0x0004
 #define OMAP24XX_CM_ICLKEN4                             0x001c
 #define OMAP24XX_CM_AUTOIDLE4                           0x003c
+#define OMAP24XX_CM_IDLEST4                             0x002c
 
 #define OMAP2430_CM_IDLEST3                             0x0028
 
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 123186ac7d2e..a89e8256fd0e 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -354,6 +354,7 @@
 
 /* AM33XX CONTROL_STATUS bitfields (partial) */
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT            22
+#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH            0x2
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK             (0x3 << 22)
 
 /* CONTROL OMAP STATUS register to identify OMAP3 features */
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index d092d2a89ee0..c8c211731d26 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -433,35 +433,24 @@ static void omap_init_mcspi(void)
 static inline void omap_init_mcspi(void) {}
 #endif
 
-static struct resource omap2_pmu_resource = {
-        .start  = 3 + OMAP_INTC_START,
-        .flags  = IORESOURCE_IRQ,
-};
-
-static struct resource omap3_pmu_resource = {
-        .start  = 3 + OMAP_INTC_START,
-        .flags  = IORESOURCE_IRQ,
-};
-
-static struct platform_device omap_pmu_device = {
-        .name           = "arm-pmu",
-        .id             = -1,
-        .num_resources  = 1,
-};
-
-static void omap_init_pmu(void)
+/**
+ * omap_init_rng - bind the RNG hwmod to the RNG omap_device
+ *
+ * Bind the RNG hwmod to the RNG omap_device.  No return value.
+ */
+static void omap_init_rng(void)
 {
-        if (cpu_is_omap24xx())
-                omap_pmu_device.resource = &omap2_pmu_resource;
-        else if (cpu_is_omap34xx())
-                omap_pmu_device.resource = &omap3_pmu_resource;
-        else
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+
+        oh = omap_hwmod_lookup("rng");
+        if (!oh)
                 return;
 
-        platform_device_register(&omap_pmu_device);
+        pdev = omap_device_build("omap_rng", -1, oh, NULL, 0, NULL, 0, 0);
+        WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
 }
 
-
 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
 
 #ifdef CONFIG_ARCH_OMAP2
@@ -646,8 +635,8 @@ static int __init omap2_init_devices(void)
                 omap_init_mcpdm();
                 omap_init_mcspi();
         }
-        omap_init_pmu();
         omap_init_sti();
+        omap_init_rng();
         omap_init_sham();
         omap_init_aes();
         omap_init_vout();
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index af1ed7d24a1f..7012068ccbf6 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -76,14 +76,14 @@ struct omap_dss_hwmod_data {
         const int id;
 };
 
-static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
         { "dss_core", "omapdss_dss", -1 },
         { "dss_dispc", "omapdss_dispc", -1 },
         { "dss_rfbi", "omapdss_rfbi", -1 },
         { "dss_venc", "omapdss_venc", -1 },
 };
 
-static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
         { "dss_core", "omapdss_dss", -1 },
         { "dss_dispc", "omapdss_dispc", -1 },
         { "dss_rfbi", "omapdss_rfbi", -1 },
@@ -91,7 +91,7 @@ static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
         { "dss_dsi1", "omapdss_dsi", 0 },
 };
 
-static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
         { "dss_core", "omapdss_dss", -1 },
         { "dss_dispc", "omapdss_dispc", -1 },
         { "dss_rfbi", "omapdss_rfbi", -1 },
@@ -488,7 +488,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
 
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
                 if (oc->_clk)
-                        clk_enable(oc->_clk);
+                        clk_prepare_enable(oc->_clk);
 
         dispc_disable_outputs();
 
@@ -515,7 +515,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
 
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
                 if (oc->_clk)
-                        clk_disable(oc->_clk);
+                        clk_disable_unprepare(oc->_clk);
 
         r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
 
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 27d79deb4ba2..814e1808e158 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -63,8 +63,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
         const struct dpll_data *dd;
         int i = 0;
         int ret = -EINVAL;
+        const char *clk_name;
 
         dd = clk->dpll_data;
+        clk_name = __clk_get_name(clk);
 
         state <<= __ffs(dd->idlest_mask);
 
@@ -76,10 +78,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
 
         if (i == MAX_DPLL_WAIT_TRIES) {
                 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
-                       clk->name, (state) ? "locked" : "bypassed");
+                       clk_name, (state) ? "locked" : "bypassed");
         } else {
                 pr_debug("clock: %s transition to '%s' in %d loops\n",
-                         clk->name, (state) ? "locked" : "bypassed", i);
+                         clk_name, (state) ? "locked" : "bypassed", i);
 
                 ret = 0;
         }
@@ -93,7 +95,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
         unsigned long fint;
         u16 f = 0;
 
-        fint = clk->dpll_data->clk_ref->rate / n;
+        fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
 
         pr_debug("clock: fint is %lu\n", fint);
 
@@ -140,7 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
         u8 state = 1;
         int r = 0;
 
-        pr_debug("clock: locking DPLL %s\n", clk->name);
+        pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
 
         dd = clk->dpll_data;
         state <<= __ffs(dd->idlest_mask);
@@ -187,7 +189,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
                 return -EINVAL;
 
         pr_debug("clock: configuring DPLL %s for low-power bypass\n",
-                 clk->name);
+                 __clk_get_name(clk));
 
         ai = omap3_dpll_autoidle_read(clk);
 
@@ -217,7 +219,7 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
         if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
                 return -EINVAL;
 
-        pr_debug("clock: stopping DPLL %s\n", clk->name);
+        pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
 
         ai = omap3_dpll_autoidle_read(clk);
 
@@ -245,7 +247,7 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
 {
         unsigned long fint, clkinp; /* watch out for overflow */
 
-        clkinp = clk->parent->rate;
+        clkinp = __clk_get_rate(__clk_get_parent(clk));
         fint = (clkinp / n) * m;
 
         if (fint < 1000000000)
@@ -271,7 +273,7 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
         unsigned long clkinp, sd; /* watch out for overflow */
         int mod1, mod2;
 
-        clkinp = clk->parent->rate;
+        clkinp = __clk_get_rate(__clk_get_parent(clk));
 
         /*
          * target sigma-delta to near 250MHz
@@ -380,16 +382,19 @@ int omap3_noncore_dpll_enable(struct clk *clk)
 {
         int r;
         struct dpll_data *dd;
+        struct clk *parent;
 
         dd = clk->dpll_data;
         if (!dd)
                 return -EINVAL;
 
-        if (clk->rate == dd->clk_bypass->rate) {
-                WARN_ON(clk->parent != dd->clk_bypass);
+        parent = __clk_get_parent(clk);
+
+        if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
+                WARN_ON(parent != dd->clk_bypass);
                 r = _omap3_noncore_dpll_bypass(clk);
         } else {
-                WARN_ON(clk->parent != dd->clk_ref);
+                WARN_ON(parent != dd->clk_ref);
                 r = _omap3_noncore_dpll_lock(clk);
         }
         /*
@@ -432,7 +437,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 {
         struct clk *new_parent = NULL;
-        unsigned long hw_rate;
+        unsigned long hw_rate, bypass_rate;
         u16 freqsel = 0;
         struct dpll_data *dd;
         int ret;
@@ -456,7 +461,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
         omap2_clk_enable(dd->clk_bypass);
         omap2_clk_enable(dd->clk_ref);
 
-        if (dd->clk_bypass->rate == rate &&
+        bypass_rate = __clk_get_rate(dd->clk_bypass);
+        if (bypass_rate == rate &&
             (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
                 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
 
@@ -479,7 +485,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
                 }
 
                 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
-                         clk->name, rate);
+                         __clk_get_name(clk), rate);
 
                 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
                                                  dd->last_rounded_n, freqsel);
@@ -557,7 +563,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
 
         if (!dd->autoidle_reg) {
                 pr_debug("clock: DPLL %s: autoidle not supported\n",
-                        clk->name);
+                        __clk_get_name(clk));
                 return;
         }
 
@@ -591,7 +597,7 @@ void omap3_dpll_deny_idle(struct clk *clk)
 
         if (!dd->autoidle_reg) {
                 pr_debug("clock: DPLL %s: autoidle not supported\n",
-                        clk->name);
+                        __clk_get_name(clk));
                 return;
         }
 
@@ -617,11 +623,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
         unsigned long rate;
         u32 v;
         struct clk *pclk;
+        unsigned long parent_rate;
 
         /* Walk up the parents of clk, looking for a DPLL */
-        pclk = clk->parent;
+        pclk = __clk_get_parent(clk);
         while (pclk && !pclk->dpll_data)
-                pclk = pclk->parent;
+                pclk = __clk_get_parent(pclk);
 
         /* clk does not have a DPLL as a parent?  error in the clock data */
         if (!pclk) {
@@ -633,12 +640,13 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
 
         WARN_ON(!dd->enable_mask);
 
+        parent_rate = __clk_get_rate(__clk_get_parent(clk));
         v = __raw_readl(dd->control_reg) & dd->enable_mask;
         v >>= __ffs(dd->enable_mask);
         if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
-                rate = clk->parent->rate;
+                rate = parent_rate;
         else
-                rate = clk->parent->rate * 2;
+                rate = parent_rate * 2;
         return rate;
 }
 
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 72428bd45efc..8ab1e1bde5e9 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
+#include <linux/platform_device.h>
 
 #include <asm/mach-types.h>
 #include <plat/gpmc.h>
@@ -31,10 +32,13 @@
 #include <plat/cpu.h>
 #include <plat/gpmc.h>
 #include <plat/sdrc.h>
+#include <plat/omap_device.h>
 
 #include "soc.h"
 #include "common.h"
 
+#define DEVICE_NAME             "omap-gpmc"
+
 /* GPMC register offsets */
 #define GPMC_REVISION           0x00
 #define GPMC_SYSCONFIG          0x10
@@ -83,6 +87,12 @@
 #define ENABLE_PREFETCH         (0x1 << 7)
 #define DMA_MPU_MODE            2
 
+#define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
+#define GPMC_REVISION_MINOR(l)          (l & 0xf)
+
+#define GPMC_HAS_WR_ACCESS              0x1
+#define GPMC_HAS_WR_DATA_MUX_BUS        0x2
+
 /* XXX: Only NAND irq has been considered,currently these are the only ones used
  */
 #define GPMC_NR_IRQ             2
@@ -128,7 +138,10 @@ static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 static unsigned int gpmc_cs_map;        /* flag for cs which are initialized */
 static int gpmc_ecc_used = -EINVAL;     /* cs using ecc engine */
-
+static struct device *gpmc_dev;
+static int gpmc_irq;
+static resource_size_t phys_base, mem_size;
+static unsigned gpmc_capability;
 static void __iomem *gpmc_base;
 
 static struct clk *gpmc_l3_clk;
@@ -318,10 +331,10 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 
         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 
-        if (cpu_is_omap34xx()) {
+        if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
+        if (gpmc_capability & GPMC_HAS_WR_ACCESS)
                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
-        }
 
         /* caller is expected to have initialized CONFIG1 to cover
          * at least sync vs async
@@ -431,6 +444,20 @@ static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
         return r;
 }
 
+static int gpmc_cs_delete_mem(int cs)
+{
+        struct resource *res = &gpmc_cs_mem[cs];
+        int r;
+
+        spin_lock(&gpmc_mem_lock);
+        r = release_resource(&gpmc_cs_mem[cs]);
+        res->start = 0;
+        res->end = 0;
+        spin_unlock(&gpmc_mem_lock);
+
+        return r;
+}
+
 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 {
         struct resource *res = &gpmc_cs_mem[cs];
@@ -767,7 +794,7 @@ static void gpmc_irq_noop(struct irq_data *data) { }
 
 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
 
-static int gpmc_setup_irq(int gpmc_irq)
+static int gpmc_setup_irq(void)
 {
         int i;
         u32 regval;
@@ -811,7 +838,37 @@ static int gpmc_setup_irq(int gpmc_irq)
         return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
 }
 
-static void __init gpmc_mem_init(void)
+static __exit int gpmc_free_irq(void)
+{
+        int i;
+
+        if (gpmc_irq)
+                free_irq(gpmc_irq, NULL);
+
+        for (i = 0; i < GPMC_NR_IRQ; i++) {
+                irq_set_handler(gpmc_client_irq[i].irq, NULL);
+                irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
+                irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
+        }
+
+        irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
+
+        return 0;
+}
+
+static void __devexit gpmc_mem_exit(void)
+{
+        int cs;
+
+        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+                if (!gpmc_cs_mem_enabled(cs))
+                        continue;
+                gpmc_cs_delete_mem(cs);
+        }
+
+}
+
+static void __devinit gpmc_mem_init(void)
 {
         int cs;
         unsigned long boot_rom_space = 0;
@@ -838,65 +895,104 @@ static void __init gpmc_mem_init(void)
         }
 }
 
-static int __init gpmc_init(void)
+static __devinit int gpmc_probe(struct platform_device *pdev)
 {
         u32 l;
-        int ret = -EINVAL;
-        int gpmc_irq;
-        char *ck = NULL;
-
-        if (cpu_is_omap24xx()) {
-                ck = "core_l3_ck";
-                if (cpu_is_omap2420())
-                        l = OMAP2420_GPMC_BASE;
-                else
-                        l = OMAP34XX_GPMC_BASE;
-                gpmc_irq = 20 + OMAP_INTC_START;
-        } else if (cpu_is_omap34xx()) {
-                ck = "gpmc_fck";
-                l = OMAP34XX_GPMC_BASE;
-                gpmc_irq = 20 + OMAP_INTC_START;
-        } else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
-                /* Base address and irq number are same for OMAP4/5 */
-                ck = "gpmc_ck";
-                l = OMAP44XX_GPMC_BASE;
-                gpmc_irq = 20 + OMAP44XX_IRQ_GIC_START;
+        struct resource *res;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (res == NULL)
+                return -ENOENT;
+
+        phys_base = res->start;
+        mem_size = resource_size(res);
+
+        gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
+        if (!gpmc_base) {
+                dev_err(&pdev->dev, "error: request memory / ioremap\n");
+                return -EADDRNOTAVAIL;
         }
 
-        if (WARN_ON(!ck))
-                return ret;
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (res == NULL)
+                dev_warn(&pdev->dev, "Failed to get resource: irq\n");
+        else
+                gpmc_irq = res->start;
 
-        gpmc_l3_clk = clk_get(NULL, ck);
+        gpmc_l3_clk = clk_get(&pdev->dev, "fck");
         if (IS_ERR(gpmc_l3_clk)) {
-                printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
-                BUG();
+                dev_err(&pdev->dev, "error: clk_get\n");
+                gpmc_irq = 0;
+                return PTR_ERR(gpmc_l3_clk);
         }
 
-        gpmc_base = ioremap(l, SZ_4K);
-        if (!gpmc_base) {
-                clk_put(gpmc_l3_clk);
-                printk(KERN_ERR "Could not get GPMC register memory\n");
-                BUG();
-        }
+        clk_prepare_enable(gpmc_l3_clk);
 
-        clk_enable(gpmc_l3_clk);
+        gpmc_dev = &pdev->dev;
 
         l = gpmc_read_reg(GPMC_REVISION);
-        printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
-        /* Set smart idle mode and automatic L3 clock gating */
-        l = gpmc_read_reg(GPMC_SYSCONFIG);
-        l &= 0x03 << 3;
-        l |= (0x02 << 3) | (1 << 0);
-        gpmc_write_reg(GPMC_SYSCONFIG, l);
+        if (GPMC_REVISION_MAJOR(l) > 0x4)
+                gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
+        dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
+                 GPMC_REVISION_MINOR(l));
+
         gpmc_mem_init();
 
-        ret = gpmc_setup_irq(gpmc_irq);
-        if (ret)
-                pr_err("gpmc: irq-%d could not claim: err %d\n",
-                                                gpmc_irq, ret);
-        return ret;
+        if (IS_ERR_VALUE(gpmc_setup_irq()))
+                dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
+
+        return 0;
 }
+
+static __exit int gpmc_remove(struct platform_device *pdev)
+{
+        gpmc_free_irq();
+        gpmc_mem_exit();
+        gpmc_dev = NULL;
+        return 0;
+}
+
+static struct platform_driver gpmc_driver = {
+        .probe          = gpmc_probe,
+        .remove         = __devexit_p(gpmc_remove),
+        .driver         = {
+                .name   = DEVICE_NAME,
+                .owner  = THIS_MODULE,
+        },
+};
+
+static __init int gpmc_init(void)
+{
+        return platform_driver_register(&gpmc_driver);
+}
+
+static __exit void gpmc_exit(void)
+{
+        platform_driver_unregister(&gpmc_driver);
+
+}
+
 postcore_initcall(gpmc_init);
+module_exit(gpmc_exit);
+
+static int __init omap_gpmc_init(void)
+{
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+        char *oh_name = "gpmc";
+
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up %s\n", oh_name);
+                return -ENODEV;
+        }
+
+        pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
+        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
+
+        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
+}
+postcore_initcall(omap_gpmc_init);
 
 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
 {
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 00c006686b0d..299ca2821ad1 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -679,16 +679,25 @@ static int _init_main_clk(struct omap_hwmod *oh)
         if (!oh->main_clk)
                 return 0;
 
-        oh->_clk = omap_clk_get_by_name(oh->main_clk);
-        if (!oh->_clk) {
+        oh->_clk = clk_get(NULL, oh->main_clk);
+        if (IS_ERR(oh->_clk)) {
                 pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
                            oh->name, oh->main_clk);
                 return -EINVAL;
         }
+        /*
+         * HACK: This needs a re-visit once clk_prepare() is implemented
+         * to do something meaningful. Today its just a no-op.
+         * If clk_prepare() is used at some point to do things like
+         * voltage scaling etc, then this would have to be moved to
+         * some point where subsystems like i2c and pmic become
+         * available.
+         */
+        clk_prepare(oh->_clk);
 
         if (!oh->_clk->clkdm)
-                pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
-                           oh->main_clk, oh->_clk->name);
+                pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n",
+                           oh->name, oh->main_clk);
 
         return ret;
 }
@@ -715,13 +724,22 @@ static int _init_interface_clks(struct omap_hwmod *oh)
                 if (!os->clk)
                         continue;
 
-                c = omap_clk_get_by_name(os->clk);
-                if (!c) {
+                c = clk_get(NULL, os->clk);
+                if (IS_ERR(c)) {
                         pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
                                    oh->name, os->clk);
                         ret = -EINVAL;
                 }
                 os->_clk = c;
+                /*
+                 * HACK: This needs a re-visit once clk_prepare() is implemented
+                 * to do something meaningful. Today its just a no-op.
+                 * If clk_prepare() is used at some point to do things like
+                 * voltage scaling etc, then this would have to be moved to
+                 * some point where subsystems like i2c and pmic become
+                 * available.
+                 */
+                clk_prepare(os->_clk);
         }
 
         return ret;
@@ -742,13 +760,22 @@ static int _init_opt_clks(struct omap_hwmod *oh)
         int ret = 0;
 
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
-                c = omap_clk_get_by_name(oc->clk);
-                if (!c) {
+                c = clk_get(NULL, oc->clk);
+                if (IS_ERR(c)) {
                         pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
                                    oh->name, oc->clk);
                         ret = -EINVAL;
                 }
                 oc->_clk = c;
+                /*
+                 * HACK: This needs a re-visit once clk_prepare() is implemented
+                 * to do something meaningful. Today its just a no-op.
+                 * If clk_prepare() is used at some point to do things like
+                 * voltage scaling etc, then this would have to be moved to
+                 * some point where subsystems like i2c and pmic become
+                 * available.
+                 */
+                clk_prepare(oc->_clk);
         }
 
         return ret;
@@ -827,7 +854,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh)
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
                 if (oc->_clk) {
                         pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
-                                 oc->_clk->name);
+                                 __clk_get_name(oc->_clk));
                         clk_enable(oc->_clk);
                 }
 }
@@ -842,7 +869,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
                 if (oc->_clk) {
                         pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
-                                 oc->_clk->name);
+                                 __clk_get_name(oc->_clk));
                         clk_disable(oc->_clk);
                 }
 }
@@ -900,10 +927,10 @@ static void _am33xx_enable_module(struct omap_hwmod *oh)
  */
 static int _omap4_wait_target_disable(struct omap_hwmod *oh)
 {
-        if (!oh || !oh->clkdm)
+        if (!oh)
                 return -EINVAL;
 
-        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+        if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm)
                 return 0;
 
         if (oh->flags & HWMOD_NO_IDLEST)
@@ -1427,8 +1454,10 @@ static struct omap_hwmod *_lookup(const char *name)
  */
 static int _init_clkdm(struct omap_hwmod *oh)
 {
-        if (!oh->clkdm_name)
+        if (!oh->clkdm_name) {
+                pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name);
                 return 0;
+        }
 
         oh->clkdm = clkdm_lookup(oh->clkdm_name);
         if (!oh->clkdm) {
@@ -1556,6 +1585,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
 {
         struct omap_hwmod_rst_info ohri;
         int ret = -EINVAL;
+        int hwsup = 0;
 
         if (!oh)
                 return -EINVAL;
@@ -1567,10 +1597,46 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
         if (IS_ERR_VALUE(ret))
                 return ret;
 
+        if (oh->clkdm) {
+                /*
+                 * A clockdomain must be in SW_SUP otherwise reset
+                 * might not be completed. The clockdomain can be set
+                 * in HW_AUTO only when the module become ready.
+                 */
+                hwsup = clkdm_in_hwsup(oh->clkdm);
+                ret = clkdm_hwmod_enable(oh->clkdm, oh);
+                if (ret) {
+                        WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
+                             oh->name, oh->clkdm->name, ret);
+                        return ret;
+                }
+        }
+
+        _enable_clocks(oh);
+        if (soc_ops.enable_module)
+                soc_ops.enable_module(oh);
+
         ret = soc_ops.deassert_hardreset(oh, &ohri);
+
+        if (soc_ops.disable_module)
+                soc_ops.disable_module(oh);
+        _disable_clocks(oh);
+
         if (ret == -EBUSY)
                 pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
 
+        if (!ret) {
+                /*
+                 * Set the clockdomain to HW_AUTO, assuming that the
+                 * previous state was HW_AUTO.
+                 */
+                if (oh->clkdm && hwsup)
+                        clkdm_allow_idle(oh->clkdm);
+        } else {
+                if (oh->clkdm)
+                        clkdm_hwmod_disable(oh->clkdm, oh);
+        }
+
         return ret;
 }
 
@@ -1605,25 +1671,28 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
 }
 
 /**
- * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset
+ * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset
  * @oh: struct omap_hwmod *
  *
- * If any hardreset line associated with @oh is asserted, then return true.
- * Otherwise, if @oh has no hardreset lines associated with it, or if
- * no hardreset lines associated with @oh are asserted, then return false.
+ * If all hardreset lines associated with @oh are asserted, then return true.
+ * Otherwise, if part of @oh is out hardreset or if no hardreset lines
+ * associated with @oh are asserted, then return false.
  * This function is used to avoid executing some parts of the IP block
- * enable/disable sequence if a hardreset line is set.
+ * enable/disable sequence if its hardreset line is set.
  */
-static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
+static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh)
 {
-        int i;
+        int i, rst_cnt = 0;
 
         if (oh->rst_lines_cnt == 0)
                 return false;
 
         for (i = 0; i < oh->rst_lines_cnt; i++)
                 if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
-                        return true;
+                        rst_cnt++;
+
+        if (oh->rst_lines_cnt == rst_cnt)
+                return true;
 
         return false;
 }
@@ -1642,6 +1711,13 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
         if (!oh->clkdm || !oh->prcm.omap4.modulemode)
                 return -EINVAL;
 
+        /*
+         * Since integration code might still be doing something, only
+         * disable if all lines are under hardreset.
+         */
+        if (!_are_all_hardreset_lines_asserted(oh))
+                return 0;
+
         pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
 
         omap4_cminst_module_disable(oh->clkdm->prcm_partition,
@@ -1649,9 +1725,6 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
                                     oh->clkdm->clkdm_offs,
                                     oh->prcm.omap4.clkctrl_offs);
 
-        if (_are_any_hardreset_lines_asserted(oh))
-                return 0;
-
         v = _omap4_wait_target_disable(oh);
         if (v)
                 pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
@@ -1679,7 +1752,7 @@ static int _am33xx_disable_module(struct omap_hwmod *oh)
         am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs,
                                  oh->prcm.omap4.clkctrl_offs);
 
-        if (_are_any_hardreset_lines_asserted(oh))
+        if (_are_all_hardreset_lines_asserted(oh))
                 return 0;
 
         v = _am33xx_wait_target_disable(oh);
@@ -1907,7 +1980,7 @@ static int _enable(struct omap_hwmod *oh)
         }
 
         /*
-         * If an IP block contains HW reset lines and any of them are
+         * If an IP block contains HW reset lines and all of them are
          * asserted, we let integration code associated with that
          * block handle the enable.  We've received very little
          * information on what those driver authors need, and until
@@ -1915,7 +1988,7 @@ static int _enable(struct omap_hwmod *oh)
          * posted to the public lists, this is probably the best we
          * can do.
          */
-        if (_are_any_hardreset_lines_asserted(oh))
+        if (_are_all_hardreset_lines_asserted(oh))
                 return 0;
 
         /* Mux pins for device runtime if populated */
@@ -1934,7 +2007,8 @@ static int _enable(struct omap_hwmod *oh)
                  * completely the module. The clockdomain can be set
                  * in HW_AUTO only when the module become ready.
                  */
-                hwsup = clkdm_in_hwsup(oh->clkdm);
+                hwsup = clkdm_in_hwsup(oh->clkdm) &&
+                        !clkdm_missing_idle_reporting(oh->clkdm);
                 r = clkdm_hwmod_enable(oh->clkdm, oh);
                 if (r) {
                         WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
@@ -1996,7 +2070,7 @@ static int _idle(struct omap_hwmod *oh)
                 return -EINVAL;
         }
 
-        if (_are_any_hardreset_lines_asserted(oh))
+        if (_are_all_hardreset_lines_asserted(oh))
                 return 0;
 
         if (oh->class->sysc)
@@ -2084,7 +2158,7 @@ static int _shutdown(struct omap_hwmod *oh)
                 return -EINVAL;
         }
 
-        if (_are_any_hardreset_lines_asserted(oh))
+        if (_are_all_hardreset_lines_asserted(oh))
                 return 0;
 
         pr_debug("omap_hwmod: %s: disabling\n", oh->name);
@@ -2608,10 +2682,10 @@ static int _omap2_wait_target_ready(struct omap_hwmod *oh)
  */
 static int _omap4_wait_target_ready(struct omap_hwmod *oh)
 {
-        if (!oh || !oh->clkdm)
+        if (!oh)
                 return -EINVAL;
 
-        if (oh->flags & HWMOD_NO_IDLEST)
+        if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm)
                 return 0;
 
         if (!_find_mpu_rt_port(oh))
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 10575a1bc1f1..b5db6007c523 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -536,6 +536,15 @@ static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
         { }
 };
 
+static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
+        {
+                .pa_start       = 0x6800a000,
+                .pa_end         = 0x6800afff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_counter_32k_hwmod,
@@ -544,6 +553,14 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
+        .master         = &omap2xxx_l3_main_hwmod,
+        .slave          = &omap2xxx_gpmc_hwmod,
+        .clk            = "core_l3_ck",
+        .addr           = omap2420_gpmc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
         &omap2xxx_l3_main__l4_core,
         &omap2xxx_mpu__l3_main,
@@ -585,8 +602,10 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
         &omap2420_l4_core__mcbsp1,
         &omap2420_l4_core__mcbsp2,
         &omap2420_l4_core__msdi1,
+        &omap2xxx_l4_core__rng,
         &omap2420_l4_core__hdq1w,
         &omap2420_l4_wkup__counter_32k,
+        &omap2420_l3__gpmc,
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 60de70feeae5..c455e41b0237 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -888,6 +888,15 @@ static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
         { }
 };
 
+static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = {
+        {
+                .pa_start       = 0x6e000000,
+                .pa_end         = 0x6e000fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_counter_32k_hwmod,
@@ -896,6 +905,14 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
+        .master         = &omap2xxx_l3_main_hwmod,
+        .slave          = &omap2xxx_gpmc_hwmod,
+        .clk            = "core_l3_ck",
+        .addr           = omap2430_gpmc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
         &omap2xxx_l3_main__l4_core,
         &omap2xxx_mpu__l3_main,
@@ -945,7 +962,9 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
         &omap2430_l4_core__mcbsp4,
         &omap2430_l4_core__mcbsp5,
         &omap2430_l4_core__hdq1w,
+        &omap2xxx_l4_core__rng,
         &omap2430_l4_wkup__counter_32k,
+        &omap2430_l3__gpmc,
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index f853a0b1d5ca..1a1287d62648 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -129,6 +129,15 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
         { }
 };
 
+static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
+        {
+                .pa_start       = 0x480a0000,
+                .pa_end         = 0x480a004f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 /*
  * Common interconnect data
  */
@@ -372,3 +381,11 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_core -> rng */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_rng_hwmod,
+        .clk            = "rng_ick",
+        .addr           = omap2_rng_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index feeb401cf87e..35dcdb66a4e0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -173,6 +173,26 @@ struct omap_hwmod_class omap2xxx_mcspi_class = {
 };
 
 /*
+ * 'gpmc' class
+ * general purpose memory controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
+        .name   = "gpmc",
+        .sysc   = &omap2xxx_gpmc_sysc,
+};
+
+/*
  * IP blocks
  */
 
@@ -198,8 +218,14 @@ struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
 };
 
 /* MPU */
+static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = {
+        { .name = "pmu", .irq = 3 },
+        { .irq = -1 }
+};
+
 struct omap_hwmod omap2xxx_mpu_hwmod = {
         .name           = "mpu",
+        .mpu_irqs       = omap2xxx_mpu_irqs,
         .class          = &mpu_hwmod_class,
         .main_clk       = "mpu_ck",
 };
@@ -220,6 +246,11 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
         .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
 /* timer1 */
 
 struct omap_hwmod omap2xxx_timer1_hwmod = {
@@ -308,6 +339,7 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -326,6 +358,7 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -344,6 +377,7 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -362,6 +396,7 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -724,7 +759,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = {
         .dev_attr       = &omap_mcspi2_dev_attr,
 };
 
-
 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
         .name   = "counter",
 };
@@ -743,3 +777,77 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = {
         },
         .class          = &omap2xxx_counter_hwmod_class,
 };
+
+/* gpmc */
+static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
+        { .irq = 20 },
+        { .irq = -1 }
+};
+
+struct omap_hwmod omap2xxx_gpmc_hwmod = {
+        .name           = "gpmc",
+        .class          = &omap2xxx_gpmc_hwmod_class,
+        .mpu_irqs       = omap2xxx_gpmc_irqs,
+        .main_clk       = "gpmc_fck",
+        /*
+         * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
+         * block.  It is not being added due to any known bugs with
+         * resetting the GPMC IP block, but rather because any timings
+         * set by the bootloader are not being correctly programmed by
+         * the kernel from the board file or DT data.
+         * HWMOD_INIT_NO_RESET should be removed ASAP.
+         */
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
+                           HWMOD_NO_IDLEST),
+        .prcm           = {
+                .omap2  = {
+                        .prcm_reg_id = 3,
+                        .module_bit = OMAP24XX_EN_GPMC_MASK,
+                        .module_offs = CORE_MOD,
+                },
+        },
+};
+
+/* RNG */
+
+static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
+        .rev_offs       = 0x3c,
+        .sysc_offs      = 0x40,
+        .syss_offs      = 0x44,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2_rng_hwmod_class = {
+        .name           = "rng",
+        .sysc           = &omap2_rng_sysc,
+};
+
+static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
+        { .irq = 52 },
+        { .irq = -1 }
+};
+
+struct omap_hwmod omap2xxx_rng_hwmod = {
+        .name           = "rng",
+        .mpu_irqs       = omap2_rng_mpu_irqs,
+        .main_clk       = "l4_ck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 4,
+                        .module_bit = OMAP24XX_EN_RNG_SHIFT,
+                        .idlest_reg_id = 4,
+                        .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
+                },
+        },
+        /*
+         * XXX The first read from the SYSSTATUS register of the RNG
+         * after the SYSCONFIG SOFTRESET bit is set triggers an
+         * imprecise external abort.  It's unclear why this happens.
+         * Until this is analyzed, skip the IP block reset.
+         */
+        .flags          = HWMOD_INIT_NO_RESET,
+        .class          = &omap2_rng_hwmod_class,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 94b38af17055..285777241d5a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -27,6 +27,7 @@
 #include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <plat/dmtimer.h>
+#include <plat/iommu.h>
 
 #include "am35xx.h"
 
@@ -92,8 +93,14 @@ static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
 };
 
 /* MPU */
+static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
+        { .name = "pmu", .irq = 3 },
+        { .irq = -1 }
+};
+
 static struct omap_hwmod omap3xxx_mpu_hwmod = {
         .name           = "mpu",
+        .mpu_irqs       = omap3xxx_mpu_irqs,
         .class          = &mpu_hwmod_class,
         .main_clk       = "arm_fck",
 };
@@ -123,6 +130,24 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
         },
 };
 
+/*
+ * 'debugss' class
+ * debug and emulation sub system
+ */
+
+static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
+        .name   = "debugss",
+};
+
+/* debugss */
+static struct omap_hwmod omap3xxx_debugss_hwmod = {
+        .name           = "debugss",
+        .class          = &omap3xxx_debugss_hwmod_class,
+        .clkdm_name     = "emu_clkdm",
+        .main_clk       = "emu_src_ck",
+        .flags          = HWMOD_NO_IDLEST,
+};
+
 /* timer class */
 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
         .rev_offs       = 0x0000,
@@ -170,6 +195,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
         .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
+/* pwm timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
+};
+
 /* timer1 */
 static struct omap_hwmod omap3xxx_timer1_hwmod = {
         .name           = "timer1",
@@ -253,6 +288,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -270,6 +306,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -287,6 +324,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -304,7 +342,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
                 },
         },
-        .dev_attr       = &capability_pwm_dev_attr,
+        .dev_attr       = &capability_dsp_pwm_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -2033,6 +2071,33 @@ static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
         .class          = &omap2_hdq1w_class,
 };
 
+/* SAD2D */
+static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
+        { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
+        { .name = "rst_modem_sw", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_class omap3xxx_sad2d_class = {
+        .name                   = "sad2d",
+};
+
+static struct omap_hwmod omap3xxx_sad2d_hwmod = {
+        .name           = "sad2d",
+        .rst_lines      = omap3xxx_sad2d_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
+        .main_clk       = "sad2d_ick",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_SAD2D_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
+                },
+        },
+        .class          = &omap3xxx_sad2d_class,
+};
+
 /*
  * '32K sync counter' class
  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
@@ -2068,6 +2133,49 @@ static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
 };
 
 /*
+ * 'gpmc' class
+ * general purpose memory controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
+        .name   = "gpmc",
+        .sysc   = &omap3xxx_gpmc_sysc,
+};
+
+static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
+        { .irq = 20 },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod omap3xxx_gpmc_hwmod = {
+        .name           = "gpmc",
+        .class          = &omap3xxx_gpmc_hwmod_class,
+        .clkdm_name     = "core_l3_clkdm",
+        .mpu_irqs       = omap3xxx_gpmc_irqs,
+        .main_clk       = "gpmc_fck",
+        /*
+         * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
+         * block.  It is not being added due to any known bugs with
+         * resetting the GPMC IP block, but rather because any timings
+         * set by the bootloader are not being correctly programmed by
+         * the kernel from the board file or DT data.
+         * HWMOD_INIT_NO_RESET should be removed ASAP.
+         */
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
+                           HWMOD_NO_IDLEST),
+};
+
+/*
  * interfaces
  */
 
@@ -2102,6 +2210,23 @@ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
         .user   = OCP_USER_MPU,
 };
 
+static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
+        {
+                .pa_start       = 0x54000000,
+                .pa_end         = 0x547fffff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l3 -> debugss */
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
+        .master         = &omap3xxx_l3_main_hwmod,
+        .slave          = &omap3xxx_debugss_hwmod,
+        .addr           = omap3xxx_l4_emu_addrs,
+        .user           = OCP_USER_MPU,
+};
+
 /* DSS -> l3 */
 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
         .master         = &omap3430es1_dss_core_hwmod,
@@ -2137,6 +2262,14 @@ static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
         .user           = OCP_USER_MPU,
 };
 
+/* l3_core -> sad2d interface */
+static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
+        .master         = &omap3xxx_sad2d_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU,
+};
+
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
         .master = &omap3xxx_l4_core_hwmod,
@@ -2823,6 +2956,122 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/*
+ * 'mmu' class
+ * The memory management unit performs virtual to physical address translation
+ * for its requestors.
+ */
+
+static struct omap_hwmod_class_sysconfig mmu_sysc = {
+        .rev_offs       = 0x000,
+        .sysc_offs      = 0x010,
+        .syss_offs      = 0x014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
+        .name = "mmu",
+        .sysc = &mmu_sysc,
+};
+
+/* mmu isp */
+
+static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
+        .da_start       = 0x0,
+        .da_end         = 0xfffff000,
+        .nr_tlb_entries = 8,
+};
+
+static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
+        { .irq = 24 },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
+        {
+                .pa_start       = 0x480bd400,
+                .pa_end         = 0x480bd47f,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l4_core -> mmu isp */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mmu_isp_hwmod,
+        .addr           = omap3xxx_mmu_isp_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
+        .name           = "mmu_isp",
+        .class          = &omap3xxx_mmu_hwmod_class,
+        .mpu_irqs       = omap3xxx_mmu_isp_irqs,
+        .main_clk       = "cam_ick",
+        .dev_attr       = &mmu_isp_dev_attr,
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+#ifdef CONFIG_OMAP_IOMMU_IVA2
+
+/* mmu iva */
+
+static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
+        .da_start       = 0x11000000,
+        .da_end         = 0xfffff000,
+        .nr_tlb_entries = 32,
+};
+
+static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
+        { .irq = 28 },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
+        { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
+        {
+                .pa_start       = 0x5d000000,
+                .pa_end         = 0x5d00007f,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l3_main -> iva mmu */
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
+        .master         = &omap3xxx_l3_main_hwmod,
+        .slave          = &omap3xxx_mmu_iva_hwmod,
+        .addr           = omap3xxx_mmu_iva_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
+        .name           = "mmu_iva",
+        .class          = &omap3xxx_mmu_hwmod_class,
+        .mpu_irqs       = omap3xxx_mmu_iva_irqs,
+        .rst_lines      = omap3xxx_mmu_iva_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
+        .main_clk       = "iva2_ck",
+        .prcm = {
+                .omap2 = {
+                        .module_offs = OMAP3430_IVA2_MOD,
+                },
+        },
+        .dev_attr       = &mmu_iva_dev_attr,
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+#endif
+
 /* l4_per -> gpio4 */
 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
         {
@@ -3168,6 +3417,15 @@ static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
         { }
 };
 
+static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
+        {
+                .pa_start       = 0x6e000000,
+                .pa_end         = 0x6e000fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
         .master         = &omap3xxx_l4_wkup_hwmod,
         .slave          = &omap3xxx_counter_32k_hwmod,
@@ -3277,10 +3535,19 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
         .user           = OCP_USER_MPU,
 };
 
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
+        .master         = &omap3xxx_l3_main_hwmod,
+        .slave          = &omap3xxx_gpmc_hwmod,
+        .clk            = "core_l3_ick",
+        .addr           = omap3xxx_gpmc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
         &omap3xxx_l3_main__l4_core,
         &omap3xxx_l3_main__l4_per,
         &omap3xxx_mpu__l3_main,
+        &omap3xxx_l3_main__l4_debugss,
         &omap3xxx_l4_core__l4_wkup,
         &omap3xxx_l4_core__mmc3,
         &omap3_l4_core__uart1,
@@ -3322,6 +3589,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
         &omap34xx_l4_core__mcspi3,
         &omap34xx_l4_core__mcspi4,
         &omap3xxx_l4_wkup__counter_32k,
+        &omap3xxx_l3_main__gpmc,
         NULL,
 };
 
@@ -3371,6 +3639,11 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
         &omap34xx_l4_core__sr2,
         &omap3xxx_l4_core__mailbox,
         &omap3xxx_l4_core__hdq1w,
+        &omap3xxx_sad2d__l3,
+        &omap3xxx_l4_core__mmu_isp,
+#ifdef CONFIG_OMAP_IOMMU_IVA2
+        &omap3xxx_l3_main__mmu_iva,
+#endif
         NULL
 };
 
@@ -3391,6 +3664,11 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
         &omap3xxx_l4_core__es3plus_mmc1,
         &omap3xxx_l4_core__es3plus_mmc2,
         &omap3xxx_l4_core__hdq1w,
+        &omap3xxx_sad2d__l3,
+        &omap3xxx_l4_core__mmu_isp,
+#ifdef CONFIG_OMAP_IOMMU_IVA2
+        &omap3xxx_l3_main__mmu_iva,
+#endif
         NULL
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index c7dcb606cd0c..8d7a93525bc6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -30,6 +30,7 @@
 #include <plat/mmc.h>
 #include <plat/dmtimer.h>
 #include <plat/common.h>
+#include <plat/iommu.h>
 
 #include "omap_hwmod_common_data.h"
 #include "cm1_44xx.h"
@@ -202,6 +203,9 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
+                        .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
+                        .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
                 },
         },
 };
@@ -258,6 +262,11 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
         .name           = "mpu_private",
         .class          = &omap44xx_mpu_bus_hwmod_class,
         .clkdm_name     = "mpuss_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /*
@@ -342,6 +351,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
+                        .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
@@ -446,6 +456,11 @@ static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
         .class          = &omap44xx_ctrl_module_hwmod_class,
         .clkdm_name     = "l4_cfg_clkdm",
         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* ctrl_module_pad_core */
@@ -453,6 +468,11 @@ static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
         .name           = "ctrl_module_pad_core",
         .class          = &omap44xx_ctrl_module_hwmod_class,
         .clkdm_name     = "l4_cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* ctrl_module_wkup */
@@ -460,6 +480,11 @@ static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
         .name           = "ctrl_module_wkup",
         .class          = &omap44xx_ctrl_module_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* ctrl_module_pad_wkup */
@@ -467,6 +492,11 @@ static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
         .name           = "ctrl_module_pad_wkup",
         .class          = &omap44xx_ctrl_module_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /*
@@ -611,7 +641,6 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 
 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
         { .name = "dsp", .rst_shift = 0 },
-        { .name = "mmu_cache", .rst_shift = 1 },
 };
 
 static struct omap_hwmod omap44xx_dsp_hwmod = {
@@ -1323,6 +1352,14 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
         .name           = "gpmc",
         .class          = &omap44xx_gpmc_hwmod_class,
         .clkdm_name     = "l3_2_clkdm",
+        /*
+         * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
+         * block.  It is not being added due to any known bugs with
+         * resetting the GPMC IP block, but rather because any timings
+         * set by the bootloader are not being correctly programmed by
+         * the kernel from the board file or DT data.
+         * HWMOD_INIT_NO_RESET should be removed ASAP.
+         */
         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
         .mpu_irqs       = omap44xx_gpmc_irqs,
         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
@@ -1631,7 +1668,6 @@ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
         { .name = "cpu0", .rst_shift = 0 },
         { .name = "cpu1", .rst_shift = 1 },
-        { .name = "mmu_cache", .rst_shift = 2 },
 };
 
 static struct omap_hwmod omap44xx_ipu_hwmod = {
@@ -2438,6 +2474,137 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
 };
 
 /*
+ * 'mmu' class
+ * The memory management unit performs virtual to physical address translation
+ * for its requestors.
+ */
+
+static struct omap_hwmod_class_sysconfig mmu_sysc = {
+        .rev_offs       = 0x000,
+        .sysc_offs      = 0x010,
+        .syss_offs      = 0x014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
+        .name = "mmu",
+        .sysc = &mmu_sysc,
+};
+
+/* mmu ipu */
+
+static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
+        .da_start       = 0x0,
+        .da_end         = 0xfffff000,
+        .nr_tlb_entries = 32,
+};
+
+static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
+        { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
+        { .name = "mmu_cache", .rst_shift = 2 },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
+        {
+                .pa_start       = 0x55082000,
+                .pa_end         = 0x550820ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l3_main_2 -> mmu_ipu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_mmu_ipu_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_mmu_ipu_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
+        .name           = "mmu_ipu",
+        .class          = &omap44xx_mmu_hwmod_class,
+        .clkdm_name     = "ducati_clkdm",
+        .mpu_irqs       = omap44xx_mmu_ipu_irqs,
+        .rst_lines      = omap44xx_mmu_ipu_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
+        .main_clk       = "ducati_clk_mux_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
+                        .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .dev_attr       = &mmu_ipu_dev_attr,
+};
+
+/* mmu dsp */
+
+static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
+        .da_start       = 0x0,
+        .da_end         = 0xfffff000,
+        .nr_tlb_entries = 32,
+};
+
+static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
+        { .irq = 28 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
+        { .name = "mmu_cache", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
+        {
+                .pa_start       = 0x4a066000,
+                .pa_end         = 0x4a0660ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l4_cfg -> dsp */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_mmu_dsp_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmu_dsp_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
+        .name           = "mmu_dsp",
+        .class          = &omap44xx_mmu_hwmod_class,
+        .clkdm_name     = "tesla_clkdm",
+        .mpu_irqs       = omap44xx_mmu_dsp_irqs,
+        .rst_lines      = omap44xx_mmu_dsp_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
+        .main_clk       = "dpll_iva_m4x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
+                        .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .dev_attr       = &mmu_dsp_dev_attr,
+};
+
+/*
  * 'mpu' class
  * mpu sub-system
  */
@@ -2448,6 +2615,8 @@ static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
 
 /* mpu */
 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
+        { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
+        { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
@@ -2497,19 +2666,27 @@ static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
  * protocol
  */
 
+static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
         .name   = "ocp2scp",
+        .sysc   = &omap44xx_ocp2scp_sysc,
 };
 
 /* ocp2scp_usb_phy */
-static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
-        { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
-};
-
 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
         .name           = "ocp2scp_usb_phy",
         .class          = &omap44xx_ocp2scp_hwmod_class,
         .clkdm_name     = "l3_init_clkdm",
+        .main_clk       = "ocp2scp_usb_phy_phy_48m",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
@@ -2517,8 +2694,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
                         .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
-        .opt_clks       = ocp2scp_usb_phy_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
 };
 
 /*
@@ -2536,18 +2711,36 @@ static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
         .name           = "prcm_mpu",
         .class          = &omap44xx_prcm_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = HWMOD_NO_IDLEST,
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* cm_core_aon */
 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
         .name           = "cm_core_aon",
         .class          = &omap44xx_prcm_hwmod_class,
+        .flags          = HWMOD_NO_IDLEST,
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* cm_core */
 static struct omap_hwmod omap44xx_cm_core_hwmod = {
         .name           = "cm_core",
         .class          = &omap44xx_prcm_hwmod_class,
+        .flags          = HWMOD_NO_IDLEST,
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* prm */
@@ -2583,6 +2776,11 @@ static struct omap_hwmod omap44xx_scrm_hwmod = {
         .name           = "scrm",
         .class          = &omap44xx_scrm_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /*
@@ -2901,6 +3099,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
         .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
+/* pwm timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
+};
+
 /* timer1 */
 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
@@ -3005,6 +3213,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
 };
 
 /* timer6 */
@@ -3027,6 +3236,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
 };
 
 /* timer7 */
@@ -3048,6 +3258,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
 };
 
 /* timer8 */
@@ -3069,7 +3280,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .dev_attr       = &capability_pwm_dev_attr,
+        .dev_attr       = &capability_dsp_pwm_dev_attr,
 };
 
 /* timer9 */
@@ -5262,11 +5473,21 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
+        {
+                .pa_start       = 0x4a0ad000,
+                .pa_end         = 0x4a0ad01f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 /* l4_cfg -> ocp2scp_usb_phy */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
         .master         = &omap44xx_l4_cfg_hwmod,
         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
         .clk            = "l4_div_ck",
+        .addr           = omap44xx_ocp2scp_usb_phy_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -5886,7 +6107,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
         {
                 .pa_start       = 0x4a0ab000,
-                .pa_end         = 0x4a0ab003,
+                .pa_end         = 0x4a0ab7ff,
                 .flags          = ADDR_TYPE_RT
         },
         {
@@ -6097,6 +6318,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
         &omap44xx_l4_per__mmc3,
         &omap44xx_l4_per__mmc4,
         &omap44xx_l4_per__mmc5,
+        &omap44xx_l3_main_2__mmu_ipu,
+        &omap44xx_l4_cfg__mmu_dsp,
         &omap44xx_l3_main_2__ocmc_ram,
         &omap44xx_l4_cfg__ocp2scp_usb_phy,
         &omap44xx_mpu_private__prcm_mpu,
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index dddb677fed68..2bc8f1705d4a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -2,9 +2,8 @@
  * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
  *
  * Copyright (C) 2010-2011 Nokia Corporation
+ * Copyright (C) 2010-2012 Texas Instruments, Inc.
  * Paul Walmsley
- *
- * Copyright (C) 2010-2011 Texas Instruments, Inc.
  * Benoît Cousson
  *
  * This program is free software; you can redistribute it and/or modify
@@ -77,6 +76,8 @@ extern struct omap_hwmod omap2xxx_gpio4_hwmod;
 extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
 extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
 extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
+extern struct omap_hwmod omap2xxx_gpmc_hwmod;
+extern struct omap_hwmod omap2xxx_rng_hwmod;
 
 /* Common interface data across OMAP2xxx */
 extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
@@ -103,6 +104,7 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
 
 /* Common IP block data */
 extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 939bd6f70b51..abefbc4d8e0b 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -80,7 +80,8 @@ static void __init omap2_init_processor_devices(void)
 
 int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
 {
-        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+        if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) &&
+            !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING))
                 clkdm_allow_idle(clkdm);
         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
                  atomic_read(&clkdm->usecount) == 0)
@@ -188,7 +189,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
                 goto exit;
         }
 
-        freq = clk->rate;
+        freq = clk_get_rate(clk);
         clk_put(clk);
 
         rcu_read_lock();
diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c
new file mode 100644
index 000000000000..2a791766283d
--- /dev/null
+++ b/arch/arm/mach-omap2/pmu.c
@@ -0,0 +1,95 @@
+/*
+ * OMAP2 ARM Performance Monitoring Unit (PMU) Support
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Contacts:
+ * Jon Hunter <jon-hunter@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/pm_runtime.h>
+
+#include <asm/pmu.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+
+static char *omap2_pmu_oh_names[] = {"mpu"};
+static char *omap3_pmu_oh_names[] = {"mpu", "debugss"};
+static char *omap4430_pmu_oh_names[] = {"l3_main_3", "l3_instr", "debugss"};
+static struct platform_device *omap_pmu_dev;
+
+/**
+ * omap2_init_pmu - creates and registers PMU platform device
+ * @oh_num:     Number of OMAP HWMODs required to create PMU device
+ * @oh_names:   Array of OMAP HWMODS names required to create PMU device
+ *
+ * Uses OMAP HWMOD framework to create and register an ARM PMU device
+ * from a list of HWMOD names passed. Currently supports OMAP2, OMAP3
+ * and OMAP4 devices.
+ */
+static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[])
+{
+        int i;
+        struct omap_hwmod *oh[3];
+        char *dev_name = "arm-pmu";
+
+        if ((!oh_num) || (oh_num > 3))
+                return -EINVAL;
+
+        for (i = 0; i < oh_num; i++) {
+                oh[i] = omap_hwmod_lookup(oh_names[i]);
+                if (!oh[i]) {
+                        pr_err("Could not look up %s hwmod\n", oh_names[i]);
+                        return -ENODEV;
+                }
+        }
+
+        omap_pmu_dev = omap_device_build_ss(dev_name, -1, oh, oh_num, NULL, 0,
+                                            NULL, 0, 0);
+        WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n",
+             dev_name);
+
+        if (IS_ERR(omap_pmu_dev))
+                return PTR_ERR(omap_pmu_dev);
+
+        pm_runtime_enable(&omap_pmu_dev->dev);
+
+        return 0;
+}
+
+static int __init omap_init_pmu(void)
+{
+        unsigned oh_num;
+        char **oh_names;
+
+        /*
+         * To create an ARM-PMU device the following HWMODs
+         * are required for the various OMAP2+ devices.
+         *
+         * OMAP24xx:    mpu
+         * OMAP3xxx:    mpu, debugss
+         * OMAP4430:    l3_main_3, l3_instr, debugss
+         * OMAP4460/70: mpu, debugss
+         */
+        if (cpu_is_omap443x()) {
+                oh_num = ARRAY_SIZE(omap4430_pmu_oh_names);
+                oh_names = omap4430_pmu_oh_names;
+                /* XXX Remove the next two lines when CTI driver available */
+                pr_info("ARM PMU: not yet supported on OMAP4430 due to missing CTI driver\n");
+                return 0;
+        } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+                oh_num = ARRAY_SIZE(omap3_pmu_oh_names);
+                oh_names = omap3_pmu_oh_names;
+        } else {
+                oh_num = ARRAY_SIZE(omap2_pmu_oh_names);
+                oh_names = omap2_pmu_oh_names;
+        }
+
+        return omap2_init_pmu(oh_num, oh_names);
+}
+subsys_initcall(omap_init_pmu);
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
index aeac6f35ca10..aceb4f464c9b 100644
--- a/arch/arm/mach-omap2/powerdomain44xx.c
+++ b/arch/arm/mach-omap2/powerdomain44xx.c
@@ -1,7 +1,7 @@
 /*
  * OMAP4 powerdomain control
  *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010, 2012 Texas Instruments, Inc.
  * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
@@ -151,6 +151,34 @@ static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
         return v;
 }
 
+/**
+ * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
+ * @pwrdm: struct powerdomain * to read the state for
+ *
+ * Reads the previous logic powerstate for a powerdomain. This
+ * function must determine the previous logic powerstate by first
+ * checking the previous powerstate for the domain. If that was OFF,
+ * then logic has been lost. If previous state was RETENTION, the
+ * function reads the setting for the next retention logic state to
+ * see the actual value.  In every other case, the logic is
+ * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
+ * depending whether the logic was retained or not.
+ */
+static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
+{
+        int state;
+
+        state = omap4_pwrdm_read_prev_pwrst(pwrdm);
+
+        if (state == PWRDM_POWER_OFF)
+                return PWRDM_POWER_OFF;
+
+        if (state != PWRDM_POWER_RET)
+                return PWRDM_POWER_RET;
+
+        return omap4_pwrdm_read_logic_retst(pwrdm);
+}
+
 static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 {
         u32 m, v;
@@ -179,6 +207,35 @@ static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
         return v;
 }
 
+/**
+ * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
+ * @pwrdm: struct powerdomain * to read mem powerstate for
+ * @bank: memory bank index
+ *
+ * Reads the previous memory powerstate for a powerdomain. This
+ * function must determine the previous memory powerstate by first
+ * checking the previous powerstate for the domain. If that was OFF,
+ * then logic has been lost. If previous state was RETENTION, the
+ * function reads the setting for the next memory retention state to
+ * see the actual value.  In every other case, the logic is
+ * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
+ * depending whether logic was retained or not.
+ */
+static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        int state;
+
+        state = omap4_pwrdm_read_prev_pwrst(pwrdm);
+
+        if (state == PWRDM_POWER_OFF)
+                return PWRDM_POWER_OFF;
+
+        if (state != PWRDM_POWER_RET)
+                return PWRDM_POWER_RET;
+
+        return omap4_pwrdm_read_mem_retst(pwrdm, bank);
+}
+
 static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
 {
         u32 c = 0;
@@ -217,9 +274,11 @@ struct pwrdm_ops omap4_pwrdm_operations = {
         .pwrdm_clear_all_prev_pwrst     = omap4_pwrdm_clear_all_prev_pwrst,
         .pwrdm_set_logic_retst  = omap4_pwrdm_set_logic_retst,
         .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
+        .pwrdm_read_prev_logic_pwrst    = omap4_pwrdm_read_prev_logic_pwrst,
         .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
         .pwrdm_read_mem_pwrst   = omap4_pwrdm_read_mem_pwrst,
         .pwrdm_read_mem_retst   = omap4_pwrdm_read_mem_retst,
+        .pwrdm_read_prev_mem_pwrst      = omap4_pwrdm_read_prev_mem_pwrst,
         .pwrdm_set_mem_onst     = omap4_pwrdm_set_mem_onst,
         .pwrdm_set_mem_retst    = omap4_pwrdm_set_mem_retst,
         .pwrdm_wait_transition  = omap4_pwrdm_wait_transition,
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index e5f0503a68b0..72df97482cc0 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -109,6 +109,8 @@
 #define OMAP2430_EN_MDM_INTC_MASK                       (1 << 11)
 #define OMAP2430_EN_USBHS_SHIFT                         6
 #define OMAP2430_EN_USBHS_MASK                          (1 << 6)
+#define OMAP24XX_EN_GPMC_SHIFT                          1
+#define OMAP24XX_EN_GPMC_MASK                           (1 << 1)
 
 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
 #define OMAP2420_ST_MMC_SHIFT                           26
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index ac95daaa4702..3c434498e12e 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -33,10 +33,12 @@
 #ifdef CONFIG_MFD_OMAP_USB_HOST
 
 #define OMAP_USBHS_DEVICE       "usbhs_omap"
+#define OMAP_USBTLL_DEVICE      "usbhs_tll"
 #define USBHS_UHH_HWMODNAME     "usb_host_hs"
 #define USBHS_TLL_HWMODNAME     "usb_tll_hs"
 
 static struct usbhs_omap_platform_data          usbhs_data;
+static struct usbtll_omap_platform_data         usbtll_data;
 static struct ehci_hcd_omap_platform_data       ehci_data;
 static struct ohci_hcd_omap_platform_data       ohci_data;
 
@@ -485,13 +487,14 @@ void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 
 void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
 {
-        struct omap_hwmod       *oh[2];
+        struct omap_hwmod       *uhh_hwm, *tll_hwm;
         struct platform_device  *pdev;
         int                     bus_id = -1;
         int                     i;
 
         for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
                 usbhs_data.port_mode[i] = pdata->port_mode[i];
+                usbtll_data.port_mode[i] = pdata->port_mode[i];
                 ohci_data.port_mode[i] = pdata->port_mode[i];
                 ehci_data.port_mode[i] = pdata->port_mode[i];
                 ehci_data.reset_gpio_port[i] = pdata->reset_gpio_port[i];
@@ -510,25 +513,35 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
                 setup_4430ohci_io_mux(pdata->port_mode);
         }
 
-        oh[0] = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
-        if (!oh[0]) {
+        uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
+        if (!uhh_hwm) {
                 pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME);
                 return;
         }
 
-        oh[1] = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
-        if (!oh[1]) {
+        tll_hwm = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
+        if (!tll_hwm) {
                 pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME);
                 return;
         }
 
-        pdev = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2,
-                                (void *)&usbhs_data, sizeof(usbhs_data),
+        pdev = omap_device_build(OMAP_USBTLL_DEVICE, bus_id, tll_hwm,
+                                &usbtll_data, sizeof(usbtll_data),
                                 omap_uhhtll_latency,
                                 ARRAY_SIZE(omap_uhhtll_latency), false);
         if (IS_ERR(pdev)) {
-                pr_err("Could not build hwmod devices %s,%s\n",
-                        USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME);
+                pr_err("Could not build hwmod device %s\n",
+                       USBHS_TLL_HWMODNAME);
+                return;
+        }
+
+        pdev = omap_device_build(OMAP_USBHS_DEVICE, bus_id, uhh_hwm,
+                                &usbhs_data, sizeof(usbhs_data),
+                                omap_uhhtll_latency,
+                                ARRAY_SIZE(omap_uhhtll_latency), false);
+        if (IS_ERR(pdev)) {
+                pr_err("Could not build hwmod devices %s\n",
+                       USBHS_UHH_HWMODNAME);
                 return;
         }
 }
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index eaac83d1df6f..b5efc0fd31cb 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -113,7 +113,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
         /*
          * Setup MBUS dram target info.
          */
-        orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE);
+        orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                    (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE);
 }
 
 void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 073c7d799068..b3eb3da01160 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -42,12 +42,12 @@
  ****************************************************************************/
 static struct map_desc orion5x_io_desc[] __initdata = {
         {
-                .virtual        = ORION5X_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) ORION5X_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
                 .length         = ORION5X_REGS_SIZE,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = ORION5X_PCIE_WA_VIRT_BASE,
+                .virtual        = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
                 .length         = ORION5X_PCIE_WA_SIZE,
                 .type           = MT_DEVICE,
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 0e19db69f5c4..e533588880ff 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -701,7 +701,7 @@ static void __init dns323_init(void)
                  * Note: AFAIK, rev B1 needs the same treatement but I'll let
                  * somebody else test it.
                  */
-                writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c);
+                writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c);
                 break;
         }
 }
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
index 11a3c1e9801f..461fd69a10ae 100644
--- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -13,27 +13,27 @@
 
 #include <mach/orion5x.h>
 
-#define CPU_CONF                (ORION5X_BRIDGE_VIRT_BASE | 0x100)
+#define CPU_CONF                (ORION5X_BRIDGE_VIRT_BASE + 0x100)
 
-#define CPU_CTRL                (ORION5X_BRIDGE_VIRT_BASE | 0x104)
+#define CPU_CTRL                (ORION5X_BRIDGE_VIRT_BASE + 0x104)
 
-#define RSTOUTn_MASK            (ORION5X_BRIDGE_VIRT_BASE | 0x108)
+#define RSTOUTn_MASK            (ORION5X_BRIDGE_VIRT_BASE + 0x108)
 #define WDT_RESET_OUT_EN        0x0002
 
-#define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
+#define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
 
-#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE | 0x110)
+#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE + 0x110)
 
-#define POWER_MNG_CTRL_REG      (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
+#define POWER_MNG_CTRL_REG      (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
 
 #define WDT_INT_REQ             0x0008
 
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 
-#define MAIN_IRQ_CAUSE          (ORION5X_BRIDGE_VIRT_BASE | 0x200)
+#define MAIN_IRQ_CAUSE          (ORION5X_BRIDGE_VIRT_BASE + 0x200)
 
-#define MAIN_IRQ_MASK           (ORION5X_BRIDGE_VIRT_BASE | 0x204)
+#define MAIN_IRQ_MASK           (ORION5X_BRIDGE_VIRT_BASE + 0x204)
 
-#define TIMER_VIRT_BASE         (ORION5X_BRIDGE_VIRT_BASE | 0x300)
-#define TIMER_PHYS_BASE         (ORION5X_BRIDGE_PHYS_BASE | 0x300)
+#define TIMER_VIRT_BASE         (ORION5X_BRIDGE_VIRT_BASE + 0x300)
+#define TIMER_PHYS_BASE         (ORION5X_BRIDGE_PHYS_BASE + 0x300)
 #endif
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 1b60131b7f60..d265f5484a8e 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -37,7 +37,7 @@
  * fd000000     f0000000        16M     PCIe WA space (Orion-1/Orion-NAS only)
  ****************************************************************************/
 #define ORION5X_REGS_PHYS_BASE          0xf1000000
-#define ORION5X_REGS_VIRT_BASE          0xfe000000
+#define ORION5X_REGS_VIRT_BASE          IOMEM(0xfe000000)
 #define ORION5X_REGS_SIZE               SZ_1M
 
 #define ORION5X_PCIE_IO_PHYS_BASE       0xf2000000
@@ -53,7 +53,7 @@
 
 /* Relevant only for Orion-1/Orion-NAS */
 #define ORION5X_PCIE_WA_PHYS_BASE       0xf0000000
-#define ORION5X_PCIE_WA_VIRT_BASE       0xfd000000
+#define ORION5X_PCIE_WA_VIRT_BASE       IOMEM(0xfd000000)
 #define ORION5X_PCIE_WA_SIZE            SZ_16M
 
 #define ORION5X_PCIE_MEM_PHYS_BASE      0xe0000000
@@ -66,42 +66,42 @@
  * Orion Registers Map
  ******************************************************************************/
 
-#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x00000)
-#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE | 0x1500)
-#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
-#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
-#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
+#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x00000)
+#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE + 0x1500)
+#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE + 0x10000)
+#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE + 0x10000)
+#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE + (x))
 #define  GPIO_VIRT_BASE                 ORION5X_DEV_BUS_REG(0x0100)
-#define  SPI_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
-#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
-#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
+#define  SPI_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE + 0x0600)
+#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE + 0x1000)
+#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE + 0x2000)
+#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE + 0x2000)
+#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE + 0x2100)
+#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE + 0x2100)
 
-#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE | 0x20000)
-#define ORION5X_BRIDGE_PHYS_BASE        (ORION5X_REGS_PHYS_BASE | 0x20000)
+#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE + 0x20000)
+#define ORION5X_BRIDGE_PHYS_BASE        (ORION5X_REGS_PHYS_BASE + 0x20000)
 
-#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x30000)
+#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x30000)
 
-#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x40000)
+#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x40000)
 
-#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x50000)
-#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x50000)
+#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0x50000)
+#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x50000)
 
-#define ORION5X_XOR_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x60900)
-#define ORION5X_XOR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x60900)
+#define ORION5X_XOR_PHYS_BASE           (ORION5X_REGS_PHYS_BASE + 0x60900)
+#define ORION5X_XOR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x60900)
 
-#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x70000)
-#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x70000)
+#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE + 0x70000)
+#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x70000)
 
-#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x80000)
-#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x80000)
+#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0x80000)
+#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x80000)
 
-#define ORION5X_CRYPTO_PHYS_BASE        (ORION5X_REGS_PHYS_BASE | 0x90000)
+#define ORION5X_CRYPTO_PHYS_BASE        (ORION5X_REGS_PHYS_BASE + 0x90000)
 
-#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0xa0000)
-#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0xa0000)
+#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0xa0000)
+#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0xa0000)
 
 /*******************************************************************************
  * Device Bus Registers
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index e152641cdb0e..30a192b9c517 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -12,6 +12,7 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <mach/bridge-regs.h>
 #include <plat/orion-gpio.h>
 #include <plat/irq.h>
@@ -25,11 +26,11 @@ static int __initdata gpio0_irqs[4] = {
 
 void __init orion5x_init_irq(void)
 {
-        orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
+        orion_irq_init(0, MAIN_IRQ_MASK);
 
         /*
          * Initialize gpiolib for GPIOs 0-31.
          */
-        orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, 0,
                         IRQ_ORION5X_GPIO_START, gpio0_irqs);
 }
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 6921d49b988d..cd50e328db2a 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -38,7 +38,7 @@
 /*****************************************************************************
  * PCIe controller
  ****************************************************************************/
-#define PCIE_BASE       ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
+#define PCIE_BASE       (ORION5X_PCIE_VIRT_BASE)
 
 void __init orion5x_pcie_id(u32 *dev, u32 *rev)
 {
@@ -111,7 +111,7 @@ static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
                 return PCIBIOS_DEVICE_NOT_FOUND;
         }
 
-        ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
+        ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
                                     bus, devfn, where, size, val);
 
         return ret;
@@ -188,7 +188,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
 /*****************************************************************************
  * PCI controller
  ****************************************************************************/
-#define ORION5X_PCI_REG(x)      (ORION5X_PCI_VIRT_BASE | (x))
+#define ORION5X_PCI_REG(x)      (ORION5X_PCI_VIRT_BASE + (x))
 #define PCI_MODE                ORION5X_PCI_REG(0xd00)
 #define PCI_CMD                 ORION5X_PCI_REG(0xc00)
 #define PCI_P2P_CONF            ORION5X_PCI_REG(0x1d14)
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1111.h b/arch/arm/mach-sa1100/include/mach/SA-1111.h
deleted file mode 100644
index c38f60915cb6..000000000000
--- a/arch/arm/mach-sa1100/include/mach/SA-1111.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * Moved to new location
- */
-#warning using old SA-1111.h - update to <asm/hardware/sa1111.h>
-#include <asm/hardware/sa1111.h>
diff --git a/arch/arm/mach-sa1100/include/mach/lart.h b/arch/arm/mach-sa1100/include/mach/lart.h
deleted file mode 100644
index 8a5482d908db..000000000000
--- a/arch/arm/mach-sa1100/include/mach/lart.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _INCLUDE_LART_H
-#define _INCLUDE_LART_H
-
-#define LART_GPIO_ETH0                  GPIO_GPIO0
-#define LART_IRQ_ETH0                   IRQ_GPIO0
-
-#define LART_GPIO_IDE                   GPIO_GPIO1
-#define LART_IRQ_IDE                    IRQ_GPIO1
-
-#define LART_GPIO_UCB1200               GPIO_GPIO18
-#define LART_IRQ_UCB1200                IRQ_GPIO18
-
-#endif
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index f978c5d0e1ae..f67456286280 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -100,7 +100,7 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
         /* Tell ROM loader about our vector (in headsmp.S) */
         emev2_set_boot_vector(__pa(shmobile_secondary_vector));
 
-        gic_raise_softirq(cpumask_of(cpu), 1);
+        gic_raise_softirq(cpumask_of(cpu), 0);
         return 0;
 }
 
diff --git a/arch/arm/mach-tegra/include/mach/smmu.h b/arch/arm/mach-tegra/include/mach/smmu.h
deleted file mode 100644
index dad403a9cf00..000000000000
--- a/arch/arm/mach-tegra/include/mach/smmu.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * IOMMU API for SMMU in Tegra30
- *
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef MACH_SMMU_H
-#define MACH_SMMU_H
-
-enum smmu_hwgrp {
-        HWGRP_AFI,
-        HWGRP_AVPC,
-        HWGRP_DC,
-        HWGRP_DCB,
-        HWGRP_EPP,
-        HWGRP_G2,
-        HWGRP_HC,
-        HWGRP_HDA,
-        HWGRP_ISP,
-        HWGRP_MPE,
-        HWGRP_NV,
-        HWGRP_NV2,
-        HWGRP_PPCS,
-        HWGRP_SATA,
-        HWGRP_VDE,
-        HWGRP_VI,
-
-        HWGRP_COUNT,
-
-        HWGRP_END = ~0,
-};
-
-#define HWG_AFI         (1 << HWGRP_AFI)
-#define HWG_AVPC        (1 << HWGRP_AVPC)
-#define HWG_DC          (1 << HWGRP_DC)
-#define HWG_DCB         (1 << HWGRP_DCB)
-#define HWG_EPP         (1 << HWGRP_EPP)
-#define HWG_G2          (1 << HWGRP_G2)
-#define HWG_HC          (1 << HWGRP_HC)
-#define HWG_HDA         (1 << HWGRP_HDA)
-#define HWG_ISP         (1 << HWGRP_ISP)
-#define HWG_MPE         (1 << HWGRP_MPE)
-#define HWG_NV          (1 << HWGRP_NV)
-#define HWG_NV2         (1 << HWGRP_NV2)
-#define HWG_PPCS        (1 << HWGRP_PPCS)
-#define HWG_SATA        (1 << HWGRP_SATA)
-#define HWG_VDE         (1 << HWGRP_VDE)
-#define HWG_VI          (1 << HWGRP_VI)
-
-#endif  /* MACH_SMMU_H */
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
index 0d4620ed853c..96800aa1316d 100644
--- a/arch/arm/mach-u300/i2c.c
+++ b/arch/arm/mach-u300/i2c.c
@@ -9,7 +9,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/i2c.h>
-#include <linux/mfd/abx500.h>
+#include <linux/mfd/ab3100.h>
 #include <linux/regulator/machine.h>
 #include <linux/amba/bus.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 5f6b7d543e55..560e0df728f8 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -659,6 +659,7 @@ static void __init v2m_dt_init(void)
 
 const static char *v2m_dt_match[] __initconst = {
         "arm,vexpress",
+        "xen,xenvm",
         NULL,
 };
 
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 9107231aacc5..b9f60ebe3bc4 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -699,7 +699,6 @@ do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
         unsigned long instr = *pinstr;
         u16 tinst1 = (instr >> 16) & 0xffff;
         u16 tinst2 = instr & 0xffff;
-        poffset->un = 0;
 
         switch (tinst1 & 0xffe0) {
         /* A6.3.5 Load/Store multiple */
@@ -854,9 +853,10 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
                 break;
 
         case 0x08000000:        /* ldm or stm, or thumb-2 32bit instruction */
-                if (thumb2_32b)
+                if (thumb2_32b) {
+                        offset.un = 0;
                         handler = do_alignment_t32_to_handler(&instr, regs, &offset);
-                else
+                } else
                         handler = do_alignment_ldmstm;
                 break;
 
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 577baf7d0a8d..8a97e6443c62 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -368,14 +368,18 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
                 /* l2x0 controller is disabled */
                 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
 
-                l2x0_saved_regs.aux_ctrl = aux;
-
                 l2x0_inv_all();
 
                 /* enable L2X0 */
                 writel_relaxed(1, l2x0_base + L2X0_CTRL);
         }
 
+        /* Re-read it in case some bits are reserved. */
+        aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+
+        /* Save the value for resuming. */
+        l2x0_saved_regs.aux_ctrl = aux;
+
         outer_cache.inv_range = l2x0_inv_range;
         outer_cache.clean_range = l2x0_clean_range;
         outer_cache.flush_range = l2x0_flush_range;
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 39e3fb3db801..3b172275262e 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -211,6 +211,9 @@ ENTRY(v7_coherent_user_range)
  * isn't mapped, fail with -EFAULT.
  */
 9001:
+#ifdef CONFIG_ARM_ERRATA_775420
+        dsb
+#endif
         mov     r0, #-EFAULT
         mov     pc, lr
  UNWIND(.fnend          )
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 9aec41fa80ae..ad722f1208a5 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -324,7 +324,7 @@ phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align)
 
         BUG_ON(!arm_memblock_steal_permitted);
 
-        phys = memblock_alloc(size, align);
+        phys = memblock_alloc_base(size, align, MEMBLOCK_ALLOC_ANYWHERE);
         memblock_free(phys, size);
         memblock_remove(phys, size);
 
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 9d869f93a3da..5dcc2fd46c46 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -248,6 +248,7 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
         if (!area)
                 return NULL;
         addr = (unsigned long)area->addr;
+        area->phys_addr = __pfn_to_phys(pfn);
 
 #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
         if (DOMAIN_IO == 0 &&
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index cb3e3eef55c0..6b46cee2f9cd 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -15,7 +15,11 @@ config IMX_HAVE_PLATFORM_GPIO_KEYS
 
 config IMX_HAVE_PLATFORM_IMX21_HCD
         bool
-        
+
+config IMX_HAVE_PLATFORM_IMX27_CODA
+        bool
+        default y if SOC_IMX27
+
 config IMX_HAVE_PLATFORM_IMX2_WDT
         bool
 
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index c11ac8472beb..76f3195475d0 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
 obj-y += platform-gpio-mxc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
 obj-y += platform-imx-dma.o
diff --git a/arch/arm/plat-mxc/devices/platform-imx27-coda.c b/arch/arm/plat-mxc/devices/platform-imx27-coda.c
new file mode 100644
index 000000000000..8b12aacdf396
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx27-coda.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2012 Vista Silicon
+ * Javier Martin <javier.martin@vista-silicon.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_imx27_coda_data imx27_coda_data __initconst = {
+        .iobase = MX27_VPU_BASE_ADDR,
+        .iosize = SZ_512,
+        .irq = MX27_INT_VPU,
+};
+#endif
+
+struct platform_device *__init imx_add_imx27_coda(
+                const struct imx_imx27_coda_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return imx_add_platform_device_dmamask("coda-imx27", 0, res, 2, NULL,
+                                        0, DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 9e3e3d8ae8c2..eaf79d220c9a 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -83,6 +83,14 @@ struct platform_device *__init imx_add_imx21_hcd(
                 const struct imx_imx21_hcd_data *data,
                 const struct mx21_usbh_platform_data *pdata);
 
+struct imx_imx27_coda_data {
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_imx27_coda(
+                const struct imx_imx27_coda_data *data);
+
 struct imx_imx2_wdt_data {
         int id;
         resource_size_t iobase;
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 706b7e29397f..9d7ac20ef8f9 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -312,33 +312,6 @@ void clk_enable_init_clocks(void)
         }
 }
 
-/**
- * omap_clk_get_by_name - locate OMAP struct clk by its name
- * @name: name of the struct clk to locate
- *
- * Locate an OMAP struct clk by its name.  Assumes that struct clk
- * names are unique.  Returns NULL if not found or a pointer to the
- * struct clk if found.
- */
-struct clk *omap_clk_get_by_name(const char *name)
-{
-        struct clk *c;
-        struct clk *ret = NULL;
-
-        mutex_lock(&clocks_mutex);
-
-        list_for_each_entry(c, &clocks, node) {
-                if (!strcmp(c->name, name)) {
-                        ret = c;
-                        break;
-                }
-        }
-
-        mutex_unlock(&clocks_mutex);
-
-        return ret;
-}
-
 int omap_clk_enable_autoidle_all(void)
 {
         struct clk *c;
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 656b9862279e..e2e2d045e428 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -19,6 +19,11 @@ struct module;
 struct clk;
 struct clockdomain;
 
+/* Temporary, needed during the common clock framework conversion */
+#define __clk_get_name(clk)     (clk->name)
+#define __clk_get_parent(clk)   (clk->parent)
+#define __clk_get_rate(clk)     (clk->rate)
+
 /**
  * struct clkops - some clock function pointers
  * @enable: fn ptr that enables the current clock in hardware
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 19e7fa577bd0..85868e98c11c 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -60,6 +60,7 @@
 #define OMAP_TIMER_ALWON                                0x40000000
 #define OMAP_TIMER_HAS_PWM                              0x20000000
 #define OMAP_TIMER_NEEDS_RESET                          0x10000000
+#define OMAP_TIMER_HAS_DSP_IRQ                          0x08000000
 
 struct omap_timer_capability_dev_attr {
         u32 timer_capability;
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 88be3e628b33..68b5f0362f35 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -103,6 +103,19 @@ struct iommu_functions {
         ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len);
 };
 
+/**
+ * struct omap_mmu_dev_attr - OMAP mmu device attributes for omap_hwmod
+ * @da_start:           device address where the va space starts.
+ * @da_end:             device address where the va space ends.
+ * @nr_tlb_entries:     number of entries supported by the translation
+ *                      look-aside buffer (TLB).
+ */
+struct omap_mmu_dev_attr {
+        u32 da_start;
+        u32 da_end;
+        int nr_tlb_entries;
+};
+
 struct iommu_platform_data {
         const char *name;
         const char *clk_name;
@@ -126,6 +139,7 @@ struct omap_iommu_arch_data {
         struct omap_iommu *iommu_dev;
 };
 
+#ifdef CONFIG_IOMMU_API
 /**
  * dev_to_omap_iommu() - retrieves an omap iommu object from a user device
  * @dev: iommu client device
@@ -136,6 +150,7 @@ static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
 
         return arch_data->iommu_dev;
 }
+#endif
 
 /* IOMMU errors */
 #define OMAP_IOMMU_ERR_TLB_MISS         (1 << 0)
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index e7259c0d33ec..106f50665804 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -120,6 +120,10 @@ int omap_device_get_context_loss_count(struct platform_device *pdev);
 
 /* Other */
 
+int omap_device_assert_hardreset(struct platform_device *pdev,
+                                 const char *name);
+int omap_device_deassert_hardreset(struct platform_device *pdev,
+                                 const char *name);
 int omap_device_idle_hwmods(struct omap_device *od);
 int omap_device_enable_hwmods(struct omap_device *od);
 
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 05330735f23f..b3349f7b1a2c 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -2,7 +2,7 @@
  * omap_hwmod macros, structures
  *
  * Copyright (C) 2009-2011 Nokia Corporation
- * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2012 Texas Instruments, Inc.
  * Paul Walmsley
  *
  * Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -384,21 +384,38 @@ struct omap_hwmod_omap2_prcm {
         u8 idlest_stdby_bit;
 };
 
+/*
+ * Possible values for struct omap_hwmod_omap4_prcm.flags
+ *
+ * HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT: Some IP blocks don't have a PRCM
+ *     module-level context loss register associated with them; this
+ *     flag bit should be set in those cases
+ */
+#define HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT         (1 << 0)
 
 /**
  * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
  * @clkctrl_reg: PRCM address of the clock control register
  * @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
+ * @lostcontext_mask: bitmask for selecting bits from RM_*_CONTEXT register
  * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM
  * @submodule_wkdep_bit: bit shift of the WKDEP range
+ * @flags: PRCM register capabilities for this IP block
+ *
+ * If @lostcontext_mask is not defined, context loss check code uses
+ * whole register without masking. @lostcontext_mask should only be
+ * defined in cases where @context_offs register is shared by two or
+ * more hwmods.
  */
 struct omap_hwmod_omap4_prcm {
         u16             clkctrl_offs;
         u16             rstctrl_offs;
         u16             rstst_offs;
         u16             context_offs;
+        u32             lostcontext_mask;
         u8              submodule_wkdep_bit;
         u8              modulemode;
+        u8              flags;
 };
 
 
@@ -591,9 +608,7 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
 int __init omap_hwmod_setup_one(const char *name);
 
 int omap_hwmod_enable(struct omap_hwmod *oh);
-int _omap_hwmod_enable(struct omap_hwmod *oh);
 int omap_hwmod_idle(struct omap_hwmod *oh);
-int _omap_hwmod_idle(struct omap_hwmod *oh);
 int omap_hwmod_shutdown(struct omap_hwmod *oh);
 
 int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
@@ -627,11 +642,6 @@ int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
 int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
                                  struct omap_hwmod *init_oh);
 
-int omap_hwmod_set_clockact_both(struct omap_hwmod *oh);
-int omap_hwmod_set_clockact_main(struct omap_hwmod *oh);
-int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh);
-int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
-
 int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
 int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
 
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index bd20588c356b..87ee140fefaa 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -4,6 +4,7 @@
 #define __ASM_ARCH_OMAP_USB_H
 
 #include <linux/io.h>
+#include <linux/platform_device.h>
 #include <linux/usb/musb.h>
 
 #define OMAP3_HS_USB_PORTS      3
@@ -63,6 +64,10 @@ struct usbhs_omap_platform_data {
         struct ehci_hcd_omap_platform_data      *ehci_data;
         struct ohci_hcd_omap_platform_data      *ohci_data;
 };
+
+struct usbtll_omap_platform_data {
+        enum usbhs_omap_port_mode               port_mode[OMAP3_HS_USB_PORTS];
+};
 /*-------------------------------------------------------------------------*/
 
 struct omap_musb_board_data {
@@ -81,6 +86,8 @@ enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
 extern void usb_musb_init(struct omap_musb_board_data *board_data);
 
 extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
+extern int omap_tll_enable(void);
+extern int omap_tll_disable(void);
 
 extern int omap4430_phy_power(struct device *dev, int ID, int on);
 extern int omap4430_phy_set_clk(struct device *dev, int on);
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index d5f617c542d3..cee85a55bd82 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -261,10 +261,10 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
                 return;
         }
 
-        r = omap_clk_get_by_name(clk_name);
+        r = clk_get(NULL, clk_name);
         if (IS_ERR(r)) {
                 dev_err(&od->pdev->dev,
-                        "omap_clk_get_by_name for %s failed\n", clk_name);
+                        "clk_get for %s failed\n", clk_name);
                 return;
         }
 
@@ -983,6 +983,61 @@ int omap_device_shutdown(struct platform_device *pdev)
 }
 
 /**
+ * omap_device_assert_hardreset - set a device's hardreset line
+ * @pdev: struct platform_device * to reset
+ * @name: const char * name of the reset line
+ *
+ * Set the hardreset line identified by @name on the IP blocks
+ * associated with the hwmods backing the platform_device @pdev.  All
+ * of the hwmods associated with @pdev must have the same hardreset
+ * line linked to them for this to work.  Passes along the return value
+ * of omap_hwmod_assert_hardreset() in the event of any failure, or
+ * returns 0 upon success.
+ */
+int omap_device_assert_hardreset(struct platform_device *pdev, const char *name)
+{
+        struct omap_device *od = to_omap_device(pdev);
+        int ret = 0;
+        int i;
+
+        for (i = 0; i < od->hwmods_cnt; i++) {
+                ret = omap_hwmod_assert_hardreset(od->hwmods[i], name);
+                if (ret)
+                        break;
+        }
+
+        return ret;
+}
+
+/**
+ * omap_device_deassert_hardreset - release a device's hardreset line
+ * @pdev: struct platform_device * to reset
+ * @name: const char * name of the reset line
+ *
+ * Release the hardreset line identified by @name on the IP blocks
+ * associated with the hwmods backing the platform_device @pdev.  All
+ * of the hwmods associated with @pdev must have the same hardreset
+ * line linked to them for this to work.  Passes along the return
+ * value of omap_hwmod_deassert_hardreset() in the event of any
+ * failure, or returns 0 upon success.
+ */
+int omap_device_deassert_hardreset(struct platform_device *pdev,
+                                   const char *name)
+{
+        struct omap_device *od = to_omap_device(pdev);
+        int ret = 0;
+        int i;
+
+        for (i = 0; i < od->hwmods_cnt; i++) {
+                ret = omap_hwmod_deassert_hardreset(od->hwmods[i], name);
+                if (ret)
+                        break;
+        }
+
+        return ret;
+}
+
+/**
  * omap_device_align_pm_lat - activate/deactivate device to match wakeup lat lim
  * @od: struct omap_device *
  *
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index c20ce0f5ce33..a82cecb84948 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -1,10 +1,10 @@
 #
 # Makefile for the linux kernel.
 #
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 
-obj-y   := irq.o pcie.o time.o common.o mpp.o addr-map.o
-obj-m   :=
-obj-n   :=
-obj-    :=
+obj-y                             += addr-map.o
 
-obj-$(CONFIG_GENERIC_GPIO) += gpio.o
+orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += $(orion-gpio-y)
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c
index 367ca89ac403..a7b8060c293a 100644
--- a/arch/arm/plat-orion/addr-map.c
+++ b/arch/arm/plat-orion/addr-map.c
@@ -48,7 +48,7 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
 static void __init __iomem *
 orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
 {
-        return (void __iomem *)(cfg->bridge_virt_base + (win << 4));
+        return cfg->bridge_virt_base + (win << 4);
 }
 
 /*
@@ -143,19 +143,16 @@ void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
  * Setup MBUS dram target info.
  */
 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-                                        const u32 ddr_window_cpu_base)
+                                        const void __iomem *ddr_window_cpu_base)
 {
-        void __iomem *addr;
         int i;
         int cs;
 
         orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 
-        addr = (void __iomem *)ddr_window_cpu_base;
-
         for (i = 0, cs = 0; i < 4; i++) {
-                u32 base = readl(addr + DDR_BASE_CS_OFF(i));
-                u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
+                u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
+                u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
 
                 /*
                  * Chip select enabled?
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 87f53caef655..b8a688cad4c2 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -86,13 +86,13 @@ static void __init uart_complete(
         struct platform_device *orion_uart,
         struct plat_serial8250_port *data,
         struct resource *resources,
-        unsigned int membase,
+        void __iomem *membase,
         resource_size_t mapbase,
         unsigned int irq,
         struct clk *clk)
 {
         data->mapbase = mapbase;
-        data->membase = (void __iomem *)membase;
+        data->membase = membase;
         data->irq = irq;
         data->uartclk = uart_get_clk_rate(clk);
         orion_uart->dev.platform_data = data;
@@ -120,7 +120,7 @@ static struct platform_device orion_uart0 = {
         .id                     = PLAT8250_DEV_PLATFORM,
 };
 
-void __init orion_uart0_init(unsigned int membase,
+void __init orion_uart0_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk)
@@ -148,7 +148,7 @@ static struct platform_device orion_uart1 = {
         .id                     = PLAT8250_DEV_PLATFORM1,
 };
 
-void __init orion_uart1_init(unsigned int membase,
+void __init orion_uart1_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk)
@@ -176,7 +176,7 @@ static struct platform_device orion_uart2 = {
         .id                     = PLAT8250_DEV_PLATFORM2,
 };
 
-void __init orion_uart2_init(unsigned int membase,
+void __init orion_uart2_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk)
@@ -204,7 +204,7 @@ static struct platform_device orion_uart3 = {
         .id                     = 3,
 };
 
-void __init orion_uart3_init(unsigned int membase,
+void __init orion_uart3_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk)
diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
index fd556f77562c..ec63e4a627d0 100644
--- a/arch/arm/plat-orion/include/plat/addr-map.h
+++ b/arch/arm/plat-orion/include/plat/addr-map.h
@@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info;
 struct orion_addr_map_cfg {
         const int num_wins;     /* Total number of windows */
         const int remappable_wins;
-        const u32 bridge_virt_base;
+        void __iomem *bridge_virt_base;
 
         /* If NULL, the default cpu_win_can_remap will be used, using
            the value in remappable_wins */
@@ -49,5 +49,5 @@ void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
                                 const u8 attr, const int remap);
 
 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-                                        const u32 ddr_window_cpu_base);
+                                        const void __iomem *ddr_window_cpu_base);
 #endif
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index ae2377ef63e5..6bbc3fe5f58e 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -13,22 +13,22 @@
 
 struct dsa_platform_data;
 
-void __init orion_uart0_init(unsigned int membase,
+void __init orion_uart0_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk);
 
-void __init orion_uart1_init(unsigned int membase,
+void __init orion_uart1_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk);
 
-void __init orion_uart2_init(unsigned int membase,
+void __init orion_uart2_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk);
 
-void __init orion_uart3_init(unsigned int membase,
+void __init orion_uart3_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk);
diff --git a/arch/arm/plat-orion/include/plat/mpp.h b/arch/arm/plat-orion/include/plat/mpp.h
index 723adce99f41..254552fee889 100644
--- a/arch/arm/plat-orion/include/plat/mpp.h
+++ b/arch/arm/plat-orion/include/plat/mpp.h
@@ -29,6 +29,6 @@
 #define MPP_OUTPUT_MASK         GENERIC_MPP(0, 0x0, 0, 1)
 
 void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
-                           unsigned int mpp_max, unsigned int dev_bus);
+                           unsigned int mpp_max, void __iomem *dev_bus);
 
 #endif
diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h
index 4d5f1f6e18df..07527e417c62 100644
--- a/arch/arm/plat-orion/include/plat/time.h
+++ b/arch/arm/plat-orion/include/plat/time.h
@@ -11,9 +11,9 @@
 #ifndef __PLAT_TIME_H
 #define __PLAT_TIME_H
 
-void orion_time_set_base(u32 timer_base);
+void orion_time_set_base(void __iomem *timer_base);
 
-void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask,
+void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask,
                      unsigned int irq, unsigned int tclk);
 
 
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
index 7740bb31d662..e686fe76a96b 100644
--- a/arch/arm/plat-orion/mpp.c
+++ b/arch/arm/plat-orion/mpp.c
@@ -18,15 +18,15 @@
 #include <plat/mpp.h>
 
 /* Address of the ith MPP control register */
-static __init unsigned long mpp_ctrl_addr(unsigned int i,
-                                          unsigned long dev_bus)
+static __init void __iomem *mpp_ctrl_addr(unsigned int i,
+                                          void __iomem *dev_bus)
 {
         return dev_bus + (i) * 4;
 }
 
 
 void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
-                           unsigned int mpp_max, unsigned int dev_bus)
+                           unsigned int mpp_max, void __iomem *dev_bus)
 {
         unsigned int mpp_nr_regs = (1 + mpp_max/8);
         u32 mpp_ctrl[mpp_nr_regs];
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 1ed8d1397fcf..0f4fa863dd55 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -180,13 +180,13 @@ static struct irqaction orion_timer_irq = {
 };
 
 void __init
-orion_time_set_base(u32 _timer_base)
+orion_time_set_base(void __iomem *_timer_base)
 {
-        timer_base = (void __iomem *)_timer_base;
+        timer_base = _timer_base;
 }
 
 void __init
-orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
+orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
                 unsigned int irq, unsigned int tclk)
 {
         u32 u;
@@ -194,7 +194,7 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
         /*
          * Set SoC-specific data.
          */
-        bridge_base = (void __iomem *)_bridge_base;
+        bridge_base = _bridge_base;
         bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
 
         ticks_per_jiffy = (tclk + HZ/2) / HZ;
diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c
index 6e70d03824a1..091ae1030045 100644
--- a/arch/arm/plat-versatile/fpga-irq.c
+++ b/arch/arm/plat-versatile/fpga-irq.c
@@ -5,6 +5,8 @@
 #include <linux/io.h>
 #include <linux/irqdomain.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
@@ -14,11 +16,17 @@
 #define IRQ_RAW_STATUS          0x04
 #define IRQ_ENABLE_SET          0x08
 #define IRQ_ENABLE_CLEAR        0x0c
+#define INT_SOFT_SET            0x10
+#define INT_SOFT_CLEAR          0x14
+#define FIQ_STATUS              0x20
+#define FIQ_RAW_STATUS          0x24
+#define FIQ_ENABLE              0x28
+#define FIQ_ENABLE_SET          0x28
+#define FIQ_ENABLE_CLEAR        0x2C
 
 /**
  * struct fpga_irq_data - irq data container for the FPGA IRQ controller
  * @base: memory offset in virtual memory
- * @irq_start: first IRQ number handled by this instance
  * @chip: chip container for this instance
  * @domain: IRQ domain for this instance
  * @valid: mask for valid IRQs on this controller
@@ -26,7 +34,6 @@
  */
 struct fpga_irq_data {
         void __iomem *base;
-        unsigned int irq_start;
         struct irq_chip chip;
         u32 valid;
         struct irq_domain *domain;
@@ -125,34 +132,79 @@ static struct irq_domain_ops fpga_irqdomain_ops = {
         .xlate = irq_domain_xlate_onetwocell,
 };
 
-void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
-                          int parent_irq, u32 valid, struct device_node *node)
-{
+static __init struct fpga_irq_data *
+fpga_irq_prep_struct(void __iomem *base, const char *name, u32 valid) {
         struct fpga_irq_data *f;
 
         if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
                 printk(KERN_ERR "%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__);
-                return;
+                return NULL;
         }
-
         f = &fpga_irq_devices[fpga_irq_id];
         f->base = base;
-        f->irq_start = irq_start;
         f->chip.name = name;
         f->chip.irq_ack = fpga_irq_mask;
         f->chip.irq_mask = fpga_irq_mask;
         f->chip.irq_unmask = fpga_irq_unmask;
         f->valid = valid;
+        fpga_irq_id++;
+
+        return f;
+}
+
+void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
+                          int parent_irq, u32 valid, struct device_node *node)
+{
+        struct fpga_irq_data *f;
+
+        f = fpga_irq_prep_struct(base, name, valid);
+        if (!f)
+                return;
 
         if (parent_irq != -1) {
                 irq_set_handler_data(parent_irq, f);
                 irq_set_chained_handler(parent_irq, fpga_irq_handle);
         }
 
-        f->domain = irq_domain_add_legacy(node, fls(valid), f->irq_start, 0,
+        f->domain = irq_domain_add_legacy(node, fls(valid), irq_start, 0,
                                           &fpga_irqdomain_ops, f);
         pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
                 fpga_irq_id, name, base, f->used_irqs);
+}
 
-        fpga_irq_id++;
+#ifdef CONFIG_OF
+int __init fpga_irq_of_init(struct device_node *node,
+                            struct device_node *parent)
+{
+        struct fpga_irq_data *f;
+        void __iomem *base;
+        u32 clear_mask;
+        u32 valid_mask;
+
+        if (WARN_ON(!node))
+                return -ENODEV;
+
+        base = of_iomap(node, 0);
+        WARN(!base, "unable to map fpga irq registers\n");
+
+        if (of_property_read_u32(node, "clear-mask", &clear_mask))
+                clear_mask = 0;
+
+        if (of_property_read_u32(node, "valid-mask", &valid_mask))
+                valid_mask = 0;
+
+        f = fpga_irq_prep_struct(base, node->name, valid_mask);
+        if (!f)
+                return -ENOMEM;
+
+        writel(clear_mask, base + IRQ_ENABLE_CLEAR);
+        writel(clear_mask, base + FIQ_ENABLE_CLEAR);
+
+        f->domain = irq_domain_add_linear(node, fls(valid_mask), &fpga_irqdomain_ops, f);
+        f->used_irqs = hweight32(valid_mask);
+
+        pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
+                fpga_irq_id, node->name, base, f->used_irqs);
+        return 0;
 }
+#endif
diff --git a/arch/arm/plat-versatile/include/plat/fpga-irq.h b/arch/arm/plat-versatile/include/plat/fpga-irq.h
index 91bcfb67551d..1fac9651d3ca 100644
--- a/arch/arm/plat-versatile/include/plat/fpga-irq.h
+++ b/arch/arm/plat-versatile/include/plat/fpga-irq.h
@@ -7,5 +7,7 @@ struct pt_regs;
 void fpga_handle_irq(struct pt_regs *regs);
 void fpga_irq_init(void __iomem *, const char *, int, int, u32,
                 struct device_node *node);
+int fpga_irq_of_init(struct device_node *node,
+                     struct device_node *parent);
 
 #endif
diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile
new file mode 100644
index 000000000000..43841033afd3
--- /dev/null
+++ b/arch/arm/xen/Makefile
@@ -0,0 +1 @@
+obj-y           := enlighten.o hypercall.o grant-table.o
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
new file mode 100644
index 000000000000..59bcb96ac369
--- /dev/null
+++ b/arch/arm/xen/enlighten.c
@@ -0,0 +1,168 @@
+#include <xen/xen.h>
+#include <xen/events.h>
+#include <xen/grant_table.h>
+#include <xen/hvm.h>
+#include <xen/interface/xen.h>
+#include <xen/interface/memory.h>
+#include <xen/interface/hvm/params.h>
+#include <xen/features.h>
+#include <xen/platform_pci.h>
+#include <xen/xenbus.h>
+#include <asm/xen/hypervisor.h>
+#include <asm/xen/hypercall.h>
+#include <linux/interrupt.h>
+#include <linux/irqreturn.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+
+struct start_info _xen_start_info;
+struct start_info *xen_start_info = &_xen_start_info;
+EXPORT_SYMBOL_GPL(xen_start_info);
+
+enum xen_domain_type xen_domain_type = XEN_NATIVE;
+EXPORT_SYMBOL_GPL(xen_domain_type);
+
+struct shared_info xen_dummy_shared_info;
+struct shared_info *HYPERVISOR_shared_info = (void *)&xen_dummy_shared_info;
+
+DEFINE_PER_CPU(struct vcpu_info *, xen_vcpu);
+
+/* TODO: to be removed */
+__read_mostly int xen_have_vector_callback;
+EXPORT_SYMBOL_GPL(xen_have_vector_callback);
+
+int xen_platform_pci_unplug = XEN_UNPLUG_ALL;
+EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
+
+static __read_mostly int xen_events_irq = -1;
+
+int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
+                               unsigned long addr,
+                               unsigned long mfn, int nr,
+                               pgprot_t prot, unsigned domid)
+{
+        return -ENOSYS;
+}
+EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
+
+/*
+ * see Documentation/devicetree/bindings/arm/xen.txt for the
+ * documentation of the Xen Device Tree format.
+ */
+#define GRANT_TABLE_PHYSADDR 0
+static int __init xen_guest_init(void)
+{
+        struct xen_add_to_physmap xatp;
+        static struct shared_info *shared_info_page = 0;
+        struct device_node *node;
+        int len;
+        const char *s = NULL;
+        const char *version = NULL;
+        const char *xen_prefix = "xen,xen-";
+        struct resource res;
+
+        node = of_find_compatible_node(NULL, NULL, "xen,xen");
+        if (!node) {
+                pr_debug("No Xen support\n");
+                return 0;
+        }
+        s = of_get_property(node, "compatible", &len);
+        if (strlen(xen_prefix) + 3  < len &&
+                        !strncmp(xen_prefix, s, strlen(xen_prefix)))
+                version = s + strlen(xen_prefix);
+        if (version == NULL) {
+                pr_debug("Xen version not found\n");
+                return 0;
+        }
+        if (of_address_to_resource(node, GRANT_TABLE_PHYSADDR, &res))
+                return 0;
+        xen_hvm_resume_frames = res.start >> PAGE_SHIFT;
+        xen_events_irq = irq_of_parse_and_map(node, 0);
+        pr_info("Xen %s support found, events_irq=%d gnttab_frame_pfn=%lx\n",
+                        version, xen_events_irq, xen_hvm_resume_frames);
+        xen_domain_type = XEN_HVM_DOMAIN;
+
+        xen_setup_features();
+        if (xen_feature(XENFEAT_dom0))
+                xen_start_info->flags |= SIF_INITDOMAIN|SIF_PRIVILEGED;
+        else
+                xen_start_info->flags &= ~(SIF_INITDOMAIN|SIF_PRIVILEGED);
+
+        if (!shared_info_page)
+                shared_info_page = (struct shared_info *)
+                        get_zeroed_page(GFP_KERNEL);
+        if (!shared_info_page) {
+                pr_err("not enough memory\n");
+                return -ENOMEM;
+        }
+        xatp.domid = DOMID_SELF;
+        xatp.idx = 0;
+        xatp.space = XENMAPSPACE_shared_info;
+        xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT;
+        if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
+                BUG();
+
+        HYPERVISOR_shared_info = (struct shared_info *)shared_info_page;
+
+        /* xen_vcpu is a pointer to the vcpu_info struct in the shared_info
+         * page, we use it in the event channel upcall and in some pvclock
+         * related functions. We don't need the vcpu_info placement
+         * optimizations because we don't use any pv_mmu or pv_irq op on
+         * HVM.
+         * The shared info contains exactly 1 CPU (the boot CPU). The guest
+         * is required to use VCPUOP_register_vcpu_info to place vcpu info
+         * for secondary CPUs as they are brought up. */
+        per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
+
+        gnttab_init();
+        if (!xen_initial_domain())
+                xenbus_probe(NULL);
+
+        return 0;
+}
+core_initcall(xen_guest_init);
+
+static irqreturn_t xen_arm_callback(int irq, void *arg)
+{
+        xen_hvm_evtchn_do_upcall();
+        return IRQ_HANDLED;
+}
+
+static int __init xen_init_events(void)
+{
+        if (!xen_domain() || xen_events_irq < 0)
+                return -ENODEV;
+
+        xen_init_IRQ();
+
+        if (request_percpu_irq(xen_events_irq, xen_arm_callback,
+                        "events", xen_vcpu)) {
+                pr_err("Error requesting IRQ %d\n", xen_events_irq);
+                return -EINVAL;
+        }
+
+        enable_percpu_irq(xen_events_irq, 0);
+
+        return 0;
+}
+postcore_initcall(xen_init_events);
+
+/* XXX: only until balloon is properly working */
+int alloc_xenballooned_pages(int nr_pages, struct page **pages, bool highmem)
+{
+        *pages = alloc_pages(highmem ? GFP_HIGHUSER : GFP_KERNEL,
+                        get_order(nr_pages));
+        if (*pages == NULL)
+                return -ENOMEM;
+        return 0;
+}
+EXPORT_SYMBOL_GPL(alloc_xenballooned_pages);
+
+void free_xenballooned_pages(int nr_pages, struct page **pages)
+{
+        kfree(*pages);
+        *pages = NULL;
+}
+EXPORT_SYMBOL_GPL(free_xenballooned_pages);
diff --git a/arch/arm/xen/grant-table.c b/arch/arm/xen/grant-table.c
new file mode 100644
index 000000000000..dbd1330c0196
--- /dev/null
+++ b/arch/arm/xen/grant-table.c
@@ -0,0 +1,53 @@
+/******************************************************************************
+ * grant_table.c
+ * ARM specific part
+ *
+ * Granting foreign access to our memory reservation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <xen/interface/xen.h>
+#include <xen/page.h>
+#include <xen/grant_table.h>
+
+int arch_gnttab_map_shared(unsigned long *frames, unsigned long nr_gframes,
+                           unsigned long max_nr_gframes,
+                           void **__shared)
+{
+        return -ENOSYS;
+}
+
+void arch_gnttab_unmap(void *shared, unsigned long nr_gframes)
+{
+        return;
+}
+
+int arch_gnttab_map_status(uint64_t *frames, unsigned long nr_gframes,
+                           unsigned long max_nr_gframes,
+                           grant_status_t **__shared)
+{
+        return -ENOSYS;
+}
diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S
new file mode 100644
index 000000000000..074f5ed101b9
--- /dev/null
+++ b/arch/arm/xen/hypercall.S
@@ -0,0 +1,106 @@
+/******************************************************************************
+ * hypercall.S
+ *
+ * Xen hypercall wrappers
+ *
+ * Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Citrix, 2012
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+/*
+ * The Xen hypercall calling convention is very similar to the ARM
+ * procedure calling convention: the first paramter is passed in r0, the
+ * second in r1, the third in r2 and the fourth in r3. Considering that
+ * Xen hypercalls have 5 arguments at most, the fifth paramter is passed
+ * in r4, differently from the procedure calling convention of using the
+ * stack for that case.
+ *
+ * The hypercall number is passed in r12.
+ *
+ * The return value is in r0.
+ *
+ * The hvc ISS is required to be 0xEA1, that is the Xen specific ARM
+ * hypercall tag.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <xen/interface/xen.h>
+
+
+/* HVC 0xEA1 */
+#ifdef CONFIG_THUMB2_KERNEL
+#define xen_hvc .word 0xf7e08ea1
+#else
+#define xen_hvc .word 0xe140ea71
+#endif
+
+#define HYPERCALL_SIMPLE(hypercall)             \
+ENTRY(HYPERVISOR_##hypercall)                   \
+        mov r12, #__HYPERVISOR_##hypercall;     \
+        xen_hvc;                                                        \
+        mov pc, lr;                                                     \
+ENDPROC(HYPERVISOR_##hypercall)
+
+#define HYPERCALL0 HYPERCALL_SIMPLE
+#define HYPERCALL1 HYPERCALL_SIMPLE
+#define HYPERCALL2 HYPERCALL_SIMPLE
+#define HYPERCALL3 HYPERCALL_SIMPLE
+#define HYPERCALL4 HYPERCALL_SIMPLE
+
+#define HYPERCALL5(hypercall)                   \
+ENTRY(HYPERVISOR_##hypercall)                   \
+        stmdb sp!, {r4}                                         \
+        ldr r4, [sp, #4]                                        \
+        mov r12, #__HYPERVISOR_##hypercall;     \
+        xen_hvc                                                         \
+        ldm sp!, {r4}                                           \
+        mov pc, lr                                                      \
+ENDPROC(HYPERVISOR_##hypercall)
+
+                .text
+
+HYPERCALL2(xen_version);
+HYPERCALL3(console_io);
+HYPERCALL3(grant_table_op);
+HYPERCALL2(sched_op);
+HYPERCALL2(event_channel_op);
+HYPERCALL2(hvm_op);
+HYPERCALL2(memory_op);
+HYPERCALL2(physdev_op);
+
+ENTRY(privcmd_call)
+        stmdb sp!, {r4}
+        mov r12, r0
+        mov r0, r1
+        mov r1, r2
+        mov r2, r3
+        ldr r3, [sp, #8]
+        ldr r4, [sp, #4]
+        xen_hvc
+        ldm sp!, {r4}
+        mov pc, lr
+ENDPROC(privcmd_call);
diff --git a/arch/arm64/include/asm/compat.h b/arch/arm64/include/asm/compat.h
index a670a33ad736..37e610dc084e 100644
--- a/arch/arm64/include/asm/compat.h
+++ b/arch/arm64/include/asm/compat.h
@@ -55,6 +55,7 @@ typedef s64		compat_s64;
 typedef u32             compat_uint_t;
 typedef u32             compat_ulong_t;
 typedef u64             compat_u64;
+typedef u32             compat_uptr_t;
 
 struct compat_timespec {
         compat_time_t   tv_sec;
@@ -130,6 +131,64 @@ typedef u32		compat_old_sigset_t;
 
 typedef u32             compat_sigset_word;
 
+typedef union compat_sigval {
+        compat_int_t    sival_int;
+        compat_uptr_t   sival_ptr;
+} compat_sigval_t;
+
+typedef struct compat_siginfo {
+        int si_signo;
+        int si_errno;
+        int si_code;
+
+        union {
+                /* The padding is the same size as AArch64. */
+                int _pad[128/sizeof(int) - 3];
+
+                /* kill() */
+                struct {
+                        compat_pid_t _pid;      /* sender's pid */
+                        __compat_uid32_t _uid;  /* sender's uid */
+                } _kill;
+
+                /* POSIX.1b timers */
+                struct {
+                        compat_timer_t _tid;    /* timer id */
+                        int _overrun;           /* overrun count */
+                        compat_sigval_t _sigval;        /* same as below */
+                        int _sys_private;       /* not to be passed to user */
+                } _timer;
+
+                /* POSIX.1b signals */
+                struct {
+                        compat_pid_t _pid;      /* sender's pid */
+                        __compat_uid32_t _uid;  /* sender's uid */
+                        compat_sigval_t _sigval;
+                } _rt;
+
+                /* SIGCHLD */
+                struct {
+                        compat_pid_t _pid;      /* which child */
+                        __compat_uid32_t _uid;  /* sender's uid */
+                        int _status;            /* exit code */
+                        compat_clock_t _utime;
+                        compat_clock_t _stime;
+                } _sigchld;
+
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+                struct {
+                        compat_uptr_t _addr; /* faulting insn/memory ref. */
+                        short _addr_lsb; /* LSB of the reported address */
+                } _sigfault;
+
+                /* SIGPOLL */
+                struct {
+                        compat_long_t _band;    /* POLL_IN, POLL_OUT, POLL_MSG */
+                        int _fd;
+                } _sigpoll;
+        } _sifields;
+} compat_siginfo_t;
+
 #define COMPAT_OFF_T_MAX        0x7fffffff
 #define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
 
@@ -139,7 +198,6 @@ typedef u32		compat_sigset_word;
  * as pointers because the syscall entry code will have
  * appropriately converted them already.
  */
-typedef u32             compat_uptr_t;
 
 static inline void __user *compat_ptr(compat_uptr_t uptr)
 {
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index f8190ba45a3e..db05f9766112 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -35,7 +35,8 @@
 #define COMPAT_HWCAP_IDIVT      (1 << 18)
 #define COMPAT_HWCAP_IDIV       (COMPAT_HWCAP_IDIVA|COMPAT_HWCAP_IDIVT)
 
-#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
 /*
  * This yields a mask that user programs can use to figure out what
  * instruction set this cpu supports.
@@ -49,5 +50,6 @@
 
 extern unsigned int elf_hwcap;
 #endif
+#endif
 
 #endif
diff --git a/arch/arm64/include/asm/stat.h b/arch/arm64/include/asm/stat.h
index d87225cbead8..a9f580c28f7b 100644
--- a/arch/arm64/include/asm/stat.h
+++ b/arch/arm64/include/asm/stat.h
@@ -18,7 +18,8 @@
 
 #include <asm-generic/stat.h>
 
-#if defined(__KERNEL__) && defined(CONFIG_COMPAT)
+#ifdef __KERNEL__
+#ifdef CONFIG_COMPAT
 
 #include <asm/compat.h>
 
@@ -58,5 +59,6 @@ struct stat64 {
 };
 
 #endif
+#endif
 
 #endif
diff --git a/arch/arm64/include/asm/unistd.h b/arch/arm64/include/asm/unistd.h
index fe18a683274f..8f03dee066ed 100644
--- a/arch/arm64/include/asm/unistd.h
+++ b/arch/arm64/include/asm/unistd.h
@@ -13,15 +13,13 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
-#if !defined(__ASM_UNISTD_H) || defined(__SYSCALL)
-#define __ASM_UNISTD_H
 
 #ifndef __SYSCALL_COMPAT
 #include <asm-generic/unistd.h>
 #endif
 
-#if defined(__KERNEL__) && defined(CONFIG_COMPAT)
+#ifdef __KERNEL__
+#ifdef CONFIG_COMPAT
 #include <asm/unistd32.h>
 #endif
-
-#endif /* __ASM_UNISTD_H */
+#endif
diff --git a/arch/arm64/include/asm/unistd32.h b/arch/arm64/include/asm/unistd32.h
index a50405f5ee42..3ba1f1a90629 100644
--- a/arch/arm64/include/asm/unistd32.h
+++ b/arch/arm64/include/asm/unistd32.h
@@ -16,8 +16,6 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
-#if !defined(__ASM_UNISTD32_H) || defined(__SYSCALL)
-#define __ASM_UNISTD32_H
 
 #ifndef __SYSCALL
 #define __SYSCALL(x, y)
@@ -754,5 +752,3 @@ __SYSCALL(__NR_syncfs, sys_syncfs)
 #define __ARCH_WANT_SYS_SIGPENDING
 #define __ARCH_WANT_SYS_SIGPROCMASK
 #define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
-
-#endif /* __ASM_UNISTD32_H */
diff --git a/arch/arm64/kernel/signal32.c b/arch/arm64/kernel/signal32.c
index ac74c2f261e3..0790a87a4346 100644
--- a/arch/arm64/kernel/signal32.c
+++ b/arch/arm64/kernel/signal32.c
@@ -30,59 +30,6 @@
 #include <asm/uaccess.h>
 #include <asm/unistd.h>
 
-typedef struct compat_siginfo {
-        int si_signo;
-        int si_errno;
-        int si_code;
-
-        union {
-                /* The padding is the same size as AArch64. */
-                int _pad[SI_PAD_SIZE];
-
-                /* kill() */
-                struct {
-                        compat_pid_t _pid;      /* sender's pid */
-                        __compat_uid32_t _uid;  /* sender's uid */
-                } _kill;
-
-                /* POSIX.1b timers */
-                struct {
-                        compat_timer_t _tid;    /* timer id */
-                        int _overrun;           /* overrun count */
-                        compat_sigval_t _sigval;        /* same as below */
-                        int _sys_private;       /* not to be passed to user */
-                } _timer;
-
-                /* POSIX.1b signals */
-                struct {
-                        compat_pid_t _pid;      /* sender's pid */
-                        __compat_uid32_t _uid;  /* sender's uid */
-                        compat_sigval_t _sigval;
-                } _rt;
-
-                /* SIGCHLD */
-                struct {
-                        compat_pid_t _pid;      /* which child */
-                        __compat_uid32_t _uid;  /* sender's uid */
-                        int _status;            /* exit code */
-                        compat_clock_t _utime;
-                        compat_clock_t _stime;
-                } _sigchld;
-
-                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
-                struct {
-                        compat_uptr_t _addr; /* faulting insn/memory ref. */
-                        short _addr_lsb; /* LSB of the reported address */
-                } _sigfault;
-
-                /* SIGPOLL */
-                struct {
-                        compat_long_t _band;    /* POLL_IN, POLL_OUT, POLL_MSG */
-                        int _fd;
-                } _sigpoll;
-        } _sifields;
-} compat_siginfo_t;
-
 struct compat_sigaction {
         compat_uptr_t                   sa_handler;
         compat_ulong_t                  sa_flags;
diff --git a/arch/avr32/include/asm/elf.h b/arch/avr32/include/asm/elf.h
index 3b3159b710d4..e2c328739808 100644
--- a/arch/avr32/include/asm/elf.h
+++ b/arch/avr32/include/asm/elf.h
@@ -102,6 +102,7 @@ typedef struct user_fpu_struct elf_fpregset_t;
 
 #define ELF_PLATFORM  (NULL)
 
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX_32BIT)
+#define SET_PERSONALITY(ex) \
+        set_personality(PER_LINUX_32BIT | (current->personality & (~PER_MASK)))
 
 #endif /* __ASM_AVR32_ELF_H */
diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h
index e6c6812a9abd..14bc98ff668f 100644
--- a/arch/blackfin/include/asm/elf.h
+++ b/arch/blackfin/include/asm/elf.h
@@ -132,6 +132,7 @@ do {											\
 
 #define ELF_PLATFORM  (NULL)
 
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) \
+        set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
 
 #endif
diff --git a/arch/c6x/Makefile b/arch/c6x/Makefile
index 1d08dd070277..a9eb9597e03c 100644
--- a/arch/c6x/Makefile
+++ b/arch/c6x/Makefile
@@ -6,6 +6,8 @@
 # for more details.
 #
 
+KBUILD_DEFCONFIG := dsk6455_defconfig
+
 cflags-y += -mno-dsbt -msdata=none
 
 cflags-$(CONFIG_C6X_BIG_KERNEL) += -mlong-calls
diff --git a/arch/c6x/include/asm/Kbuild b/arch/c6x/include/asm/Kbuild
index f08e89183cda..277f1a4ecb09 100644
--- a/arch/c6x/include/asm/Kbuild
+++ b/arch/c6x/include/asm/Kbuild
@@ -40,6 +40,7 @@ generic-y += sembuf.h
 generic-y += shmbuf.h
 generic-y += shmparam.h
 generic-y += siginfo.h
+generic-y += signal.h
 generic-y += socket.h
 generic-y += sockios.h
 generic-y += stat.h
diff --git a/arch/c6x/include/asm/elf.h b/arch/c6x/include/asm/elf.h
index f4552db20b4a..32b997126adf 100644
--- a/arch/c6x/include/asm/elf.h
+++ b/arch/c6x/include/asm/elf.h
@@ -77,7 +77,8 @@ do {								\
 
 #define ELF_PLATFORM  (NULL)
 
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) \
+        set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
 
 /* C6X specific section types */
 #define SHT_C6000_UNWIND        0x70000001
diff --git a/arch/c6x/include/asm/signal.h b/arch/c6x/include/asm/signal.h
deleted file mode 100644
index f1cd870596a3..000000000000
--- a/arch/c6x/include/asm/signal.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef _ASM_C6X_SIGNAL_H
-#define _ASM_C6X_SIGNAL_H
-
-#include <asm-generic/signal.h>
-
-#ifndef __ASSEMBLY__
-#include <linux/linkage.h>
-
-struct pt_regs;
-
-extern asmlinkage int do_rt_sigreturn(struct pt_regs *regs);
-extern asmlinkage void do_notify_resume(struct pt_regs *regs,
-                                        u32 thread_info_flags,
-                                        int syscall);
-#endif
-
-#endif /* _ASM_C6X_SIGNAL_H */
diff --git a/arch/c6x/include/asm/unistd.h b/arch/c6x/include/asm/unistd.h
index 6d54ea4262eb..ed2259043eec 100644
--- a/arch/c6x/include/asm/unistd.h
+++ b/arch/c6x/include/asm/unistd.h
@@ -13,8 +13,6 @@
  *   NON INFRINGEMENT.  See the GNU General Public License for
  *   more details.
  */
-#if !defined(_ASM_C6X_UNISTD_H) || defined(__SYSCALL)
-#define _ASM_C6X_UNISTD_H
 
 /* Use the standard ABI for syscalls. */
 #include <asm-generic/unistd.h>
@@ -22,5 +20,3 @@
 /* C6X-specific syscalls. */
 #define __NR_cache_sync (__NR_arch_specific_syscall + 0)
 __SYSCALL(__NR_cache_sync, sys_cache_sync)
-
-#endif /* _ASM_C6X_UNISTD_H */
diff --git a/arch/cris/include/asm/elf.h b/arch/cris/include/asm/elf.h
index 8a3d8e2b33c1..8182f2dc89d0 100644
--- a/arch/cris/include/asm/elf.h
+++ b/arch/cris/include/asm/elf.h
@@ -86,6 +86,7 @@ typedef unsigned long elf_fpregset_t;
 
 #define ELF_PLATFORM  (NULL)
 
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) \
+        set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
 
 #endif
diff --git a/arch/frv/include/asm/elf.h b/arch/frv/include/asm/elf.h
index c3819804a74b..9ccbc80f0b11 100644
--- a/arch/frv/include/asm/elf.h
+++ b/arch/frv/include/asm/elf.h
@@ -137,6 +137,7 @@ do {											\
 
 #define ELF_PLATFORM  (NULL)
 
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) \
+        set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
 
 #endif
diff --git a/arch/frv/kernel/pm.c b/arch/frv/kernel/pm.c
index 5fa3889d858b..0b579927439d 100644
--- a/arch/frv/kernel/pm.c
+++ b/arch/frv/kernel/pm.c
@@ -153,23 +153,22 @@ static int user_atoi(char __user *ubuf, size_t len)
 static int sysctl_pm_do_suspend(ctl_table *ctl, int write,
                                 void __user *buffer, size_t *lenp, loff_t *fpos)
 {
-        int retval, mode;
+        int mode;
 
         if (*lenp <= 0)
                 return -EIO;
 
         mode = user_atoi(buffer, *lenp);
-        if ((mode != 1) && (mode != 5))
-                return -EINVAL;
+        switch (mode) {
+        case 1:
+            return pm_do_suspend();
 
-        if (retval == 0) {
-                if (mode == 5)
-                    retval = pm_do_bus_sleep();
-                else
-                    retval = pm_do_suspend();
-        }
+        case 5:
+            return pm_do_bus_sleep();
 
-        return retval;
+        default:
+            return -EINVAL;
+        }
 }
 
 static int try_set_cmode(int new_cmode)
diff --git a/arch/frv/kernel/setup.c b/arch/frv/kernel/setup.c
index 75cf7f4b2fa8..1f1e5efb3385 100644
--- a/arch/frv/kernel/setup.c
+++ b/arch/frv/kernel/setup.c
@@ -184,7 +184,7 @@ static struct clock_cmode __pminitdata clock_cmodes_fr555[16] = {
         [6]     = {     _x1,    _x1_5,  _x1_5,  _x4_5,  _x0_375 },
 };
 
-static const struct clock_cmode __pminitdata *clock_cmodes;
+static const struct clock_cmode __pminitconst *clock_cmodes;
 static int __pminitdata clock_doubled;
 
 static struct uart_port __pminitdata __frv_uart0 = {
diff --git a/arch/frv/mb93090-mb00/pci-irq.c b/arch/frv/mb93090-mb00/pci-irq.c
index 20f6497b2cd5..c677b9d81d30 100644
--- a/arch/frv/mb93090-mb00/pci-irq.c
+++ b/arch/frv/mb93090-mb00/pci-irq.c
@@ -28,7 +28,7 @@
  *
  */
 
-static const uint8_t __initdata pci_bus0_irq_routing[32][4] = {
+static const uint8_t __initconst pci_bus0_irq_routing[32][4] = {
         [0 ] = { IRQ_FPGA_MB86943_PCI_INTA },
         [16] = { IRQ_FPGA_RTL8029_INTA },
         [17] = { IRQ_FPGA_PCI_INTC, IRQ_FPGA_PCI_INTD, IRQ_FPGA_PCI_INTA, IRQ_FPGA_PCI_INTB },
diff --git a/arch/h8300/include/asm/elf.h b/arch/h8300/include/asm/elf.h
index c24fa250d653..41193c396bff 100644
--- a/arch/h8300/include/asm/elf.h
+++ b/arch/h8300/include/asm/elf.h
@@ -54,7 +54,8 @@ typedef unsigned long elf_fpregset_t;
 
 #define ELF_PLATFORM  (NULL)
 
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) \
+        set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
 
 #define R_H8_NONE       0
 #define R_H8_DIR32      1
diff --git a/arch/h8300/kernel/sys_h8300.c b/arch/h8300/kernel/sys_h8300.c
index aaf5e5a48f93..4bdc7311784e 100644
--- a/arch/h8300/kernel/sys_h8300.c
+++ b/arch/h8300/kernel/sys_h8300.c
@@ -51,6 +51,7 @@ asmlinkage void syscall_print(void *dummy,...)
  * Do a system call from kernel instead of calling sys_execve so we
  * end up with proper pt_regs.
  */
+asmlinkage
 int kernel_execve(const char *filename,
                   const char *const argv[],
                   const char *const envp[])
diff --git a/arch/h8300/kernel/timer/itu.c b/arch/h8300/kernel/timer/itu.c
index a2ae5e952137..0a8b5cd5bf38 100644
--- a/arch/h8300/kernel/timer/itu.c
+++ b/arch/h8300/kernel/timer/itu.c
@@ -62,7 +62,7 @@ static struct irqaction itu_irq = {
         .flags          = IRQF_DISABLED | IRQF_TIMER,
 };
 
-static const int __initdata divide_rate[] = {1, 2, 4, 8};
+static const int __initconst divide_rate[] = {1, 2, 4, 8};
 
 void __init h8300_timer_setup(void)
 {
diff --git a/arch/h8300/kernel/timer/timer16.c b/arch/h8300/kernel/timer/timer16.c
index ae0d38161139..462d9f581719 100644
--- a/arch/h8300/kernel/timer/timer16.c
+++ b/arch/h8300/kernel/timer/timer16.c
@@ -57,7 +57,7 @@ static struct irqaction timer16_irq = {
         .flags          = IRQF_DISABLED | IRQF_TIMER,
 };
 
-static const int __initdata divide_rate[] = {1, 2, 4, 8};
+static const int __initconst divide_rate[] = {1, 2, 4, 8};
 
 void __init h8300_timer_setup(void)
 {
diff --git a/arch/h8300/kernel/timer/timer8.c b/arch/h8300/kernel/timer/timer8.c
index 7a1533fad47d..505f3415b40f 100644
--- a/arch/h8300/kernel/timer/timer8.c
+++ b/arch/h8300/kernel/timer/timer8.c
@@ -77,7 +77,7 @@ static struct irqaction timer8_irq = {
         .flags          = IRQF_DISABLED | IRQF_TIMER,
 };
 
-static const int __initdata divide_rate[] = {8, 64, 8192};
+static const int __initconst divide_rate[] = {8, 64, 8192};
 
 void __init h8300_timer_setup(void)
 {
diff --git a/arch/h8300/kernel/timer/tpu.c b/arch/h8300/kernel/timer/tpu.c
index 2193a2e2859a..0350f6204ecf 100644
--- a/arch/h8300/kernel/timer/tpu.c
+++ b/arch/h8300/kernel/timer/tpu.c
@@ -66,7 +66,7 @@ static struct irqaction tpu_irq = {
         .flags          = IRQF_DISABLED | IRQF_TIMER,
 };
 
-static const int __initdata divide_rate[] = {
+static const int __initconst divide_rate[] = {
 #if CONFIG_H8300_TPU_CH == 0
         1,4,16,64,0,0,0,0,
 #elif (CONFIG_H8300_TPU_CH == 1) || (CONFIG_H8300_TPU_CH == 5)
diff --git a/arch/h8300/platform/h8300h/irq.c b/arch/h8300/platform/h8300h/irq.c
index bc4f51bceef5..0a50353e09d5 100644
--- a/arch/h8300/platform/h8300h/irq.c
+++ b/arch/h8300/platform/h8300h/irq.c
@@ -14,14 +14,14 @@
 #include <asm/gpio-internal.h>
 #include <asm/regs306x.h>
 
-const int __initdata h8300_saved_vectors[] = {
+const int __initconst h8300_saved_vectors[] = {
 #if defined(CONFIG_GDB_DEBUG)
         TRAP3_VEC,      /* TRAPA #3 is GDB breakpoint */
 #endif
         -1,
 };
 
-const h8300_vector __initdata h8300_trap_table[] = {
+const h8300_vector __initconst h8300_trap_table[] = {
         0, 0, 0, 0, 0, 0, 0, 0,
         system_call,
         0,
diff --git a/arch/h8300/platform/h8s/irq.c b/arch/h8300/platform/h8s/irq.c
index 7b5f29febc07..f3a5511c16b1 100644
--- a/arch/h8300/platform/h8s/irq.c
+++ b/arch/h8300/platform/h8s/irq.c
@@ -18,7 +18,7 @@
 #include <asm/regs267x.h>
 
 /* saved vector list */
-const int __initdata h8300_saved_vectors[]={
+const int __initconst h8300_saved_vectors[] = {
 #if defined(CONFIG_GDB_DEBUG)
         TRACE_VEC,
         TRAP3_VEC,
@@ -27,7 +27,7 @@ const int __initdata h8300_saved_vectors[]={
 };
 
 /* trap entry table */
-const H8300_VECTOR __initdata h8300_trap_table[] = {
+const H8300_VECTOR __initconst h8300_trap_table[] = {
         0,0,0,0,0,
         trace_break,  /* TRACE */
         0,0,
diff --git a/arch/hexagon/include/asm/elf.h b/arch/hexagon/include/asm/elf.h
index 37976a0d3650..82b499621e05 100644
--- a/arch/hexagon/include/asm/elf.h
+++ b/arch/hexagon/include/asm/elf.h
@@ -217,7 +217,8 @@ do {					\
 #define ELF_PLATFORM  (NULL)
 
 #ifdef __KERNEL__
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) \
+        set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
 #endif
 
 #define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
diff --git a/arch/hexagon/include/asm/unistd.h b/arch/hexagon/include/asm/unistd.h
index 4d0ecde3665f..c0d5565030ae 100644
--- a/arch/hexagon/include/asm/unistd.h
+++ b/arch/hexagon/include/asm/unistd.h
@@ -18,9 +18,6 @@
  * 02110-1301, USA.
  */
 
-#if !defined(_ASM_HEXAGON_UNISTD_H) || defined(__SYSCALL)
-#define _ASM_HEXAGON_UNISTD_H
-
 /*
  *  The kernel pulls this unistd.h in three different ways:
  *  1.  the "normal" way which gets all the __NR defines
@@ -32,5 +29,3 @@
 #define sys_mmap2 sys_mmap_pgoff
 
 #include <asm-generic/unistd.h>
-
-#endif
diff --git a/arch/ia64/include/asm/xen/interface.h b/arch/ia64/include/asm/xen/interface.h
index 3d52a5bbd857..e88c5de27410 100644
--- a/arch/ia64/include/asm/xen/interface.h
+++ b/arch/ia64/include/asm/xen/interface.h
@@ -71,6 +71,7 @@
  * with Xen so that we could have one ABI that works for 32 and 64 bit
  * guests. */
 typedef unsigned long xen_pfn_t;
+typedef unsigned long xen_ulong_t;
 /* Guest handles for primitive C types. */
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint, unsigned int);
diff --git a/arch/ia64/xen/irq_xen.c b/arch/ia64/xen/irq_xen.c
index 3bb12230721f..01f479ee1c43 100644
--- a/arch/ia64/xen/irq_xen.c
+++ b/arch/ia64/xen/irq_xen.c
@@ -433,7 +433,7 @@ xen_resend_irq(unsigned int vector)
         (void)resend_irq_on_evtchn(vector);
 }
 
-const struct pv_irq_ops xen_irq_ops __initdata = {
+const struct pv_irq_ops xen_irq_ops __initconst = {
         .register_ipi = xen_register_ipi,
 
         .assign_irq_vector = xen_assign_irq_vector,
diff --git a/arch/ia64/xen/irq_xen.h b/arch/ia64/xen/irq_xen.h
index 26110f330c87..1778517b90fe 100644
--- a/arch/ia64/xen/irq_xen.h
+++ b/arch/ia64/xen/irq_xen.h
@@ -27,7 +27,7 @@ extern void (*late_time_init)(void);
 extern char xen_event_callback;
 void __init xen_init_IRQ(void);
 
-extern const struct pv_irq_ops xen_irq_ops __initdata;
+extern const struct pv_irq_ops xen_irq_ops __initconst;
 extern void xen_smp_intr_init(void);
 extern void xen_send_ipi(int cpu, int vec);
 
diff --git a/arch/m32r/include/asm/elf.h b/arch/m32r/include/asm/elf.h
index b8da7d0574d2..70896161c636 100644
--- a/arch/m32r/include/asm/elf.h
+++ b/arch/m32r/include/asm/elf.h
@@ -128,6 +128,7 @@ typedef elf_fpreg_t elf_fpregset_t;
    intent than poking at uname or /proc/cpuinfo.  */
 #define ELF_PLATFORM    (NULL)
 
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) \
+        set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
 
 #endif  /* _ASM_M32R__ELF_H */
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index 7cafb537d03c..d2b3935ae147 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -34,10 +34,9 @@ static inline void __clear_cache_all(void)
 {
 #ifdef CACHE_INVALIDATE
         __asm__ __volatile__ (
-                "movel  %0, %%d0\n\t"
-                "movec  %%d0, %%CACR\n\t"
+                "movec  %0, %%CACR\n\t"
                 "nop\n\t"
-                : : "i" (CACHE_INVALIDATE) : "d0" );
+                : : "r" (CACHE_INVALIDATE) );
 #endif
 }
 
@@ -58,10 +57,9 @@ static inline void __flush_icache_all(void)
 {
 #ifdef CACHE_INVALIDATEI
         __asm__ __volatile__ (
-                "movel  %0, %%d0\n\t"
-                "movec  %%d0, %%CACR\n\t"
+                "movec  %0, %%CACR\n\t"
                 "nop\n\t"
-                : : "i" (CACHE_INVALIDATEI) : "d0" );
+                : : "r" (CACHE_INVALIDATEI) );
 #endif
 }
 
@@ -72,19 +70,18 @@ static inline void __flush_dcache_all(void)
 #endif
 #ifdef CACHE_INVALIDATED
         __asm__ __volatile__ (
-                "movel  %0, %%d0\n\t"
-                "movec  %%d0, %%CACR\n\t"
+                "movec  %0, %%CACR\n\t"
                 "nop\n\t"
-                : : "i" (CACHE_INVALIDATED) : "d0" );
+                : : "r" (CACHE_INVALIDATED) );
 #else
-        /* Flush the wrtite buffer */
+        /* Flush the write buffer */
         __asm__ __volatile__ ( "nop" );
 #endif
 }
 
 /*
  * Push cache entries at supplied address. We want to write back any dirty
- * data and the invalidate the cache lines associated with this address.
+ * data and then invalidate the cache lines associated with this address.
  */
 static inline void cache_push(unsigned long paddr, int len)
 {
diff --git a/arch/m68k/include/asm/elf.h b/arch/m68k/include/asm/elf.h
index e9b7cda59744..f83c1d0a87cf 100644
--- a/arch/m68k/include/asm/elf.h
+++ b/arch/m68k/include/asm/elf.h
@@ -113,6 +113,7 @@ typedef struct user_m68kfp_struct elf_fpregset_t;
 
 #define ELF_PLATFORM  (NULL)
 
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) \
+        set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
 
 #endif
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 69722366b084..4cf864f5ea7a 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -21,33 +21,33 @@
 /*
  *      Define the 5206 SIM register set addresses.
  */
-#define MCFSIM_SIMR             0x03            /* SIM Config reg (r/w) */
-#define MCFSIM_ICR1             0x14            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x15            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x16            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x17            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x18            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x19            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x1a            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x1b            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x1c            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x1d            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x1e            /* Intr Ctrl reg 11 (r/w) */
-#define MCFSIM_ICR12            0x1f            /* Intr Ctrl reg 12 (r/w) */
-#define MCFSIM_ICR13            0x20            /* Intr Ctrl reg 13 (r/w) */
+#define MCFSIM_SIMR             (MCF_MBAR + 0x03)       /* SIM Config reg */
+#define MCFSIM_ICR1             (MCF_MBAR + 0x14)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x15)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x16)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x17)       /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5             (MCF_MBAR + 0x18)       /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6             (MCF_MBAR + 0x19)       /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7             (MCF_MBAR + 0x1a)       /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8             (MCF_MBAR + 0x1b)       /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9             (MCF_MBAR + 0x1c)       /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10            (MCF_MBAR + 0x1d)       /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11            (MCF_MBAR + 0x1e)       /* Intr Ctrl reg 11 */
+#define MCFSIM_ICR12            (MCF_MBAR + 0x1f)       /* Intr Ctrl reg 12 */
+#define MCFSIM_ICR13            (MCF_MBAR + 0x20)       /* Intr Ctrl reg 13 */
 #ifdef CONFIG_M5206e
-#define MCFSIM_ICR14            0x21            /* Intr Ctrl reg 14 (r/w) */
-#define MCFSIM_ICR15            0x22            /* Intr Ctrl reg 15 (r/w) */
+#define MCFSIM_ICR14            (MCF_MBAR + 0x21)       /* Intr Ctrl reg 14 */
+#define MCFSIM_ICR15            (MCF_MBAR + 0x22)       /* Intr Ctrl reg 15 */
 #endif
 
-#define MCFSIM_IMR              0x36            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_IPR              0x3a            /* Interrupt Pend reg (r/w) */
+#define MCFSIM_IMR              (MCF_MBAR + 0x36)       /* Interrupt Mask */
+#define MCFSIM_IPR              (MCF_MBAR + 0x3a)       /* Interrupt Pending */
 
-#define MCFSIM_RSR              0x40            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x41            /* System Protection reg (r/w)*/
+#define MCFSIM_RSR              (MCF_MBAR + 0x40)       /* Reset Status */
+#define MCFSIM_SYPCR            (MCF_MBAR + 0x41)       /* System Protection */
 
-#define MCFSIM_SWIVR            0x42            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x43            /* SW Watchdog service (r/w) */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x42)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x43)       /* SW Watchdog srv */
 
 #define MCFSIM_DCRR             (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
 #define MCFSIM_DCTR             (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
@@ -58,36 +58,36 @@
 #define MCFSIM_DMR1             (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
 #define MCFSIM_DCR1             (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
 
-#define MCFSIM_CSAR0            0x64            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x68            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x6e            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x70            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x74            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x7a            /* CS 1 Control reg (r/w) */
-#define MCFSIM_CSAR2            0x7c            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x80            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0x86            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0x88            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0x8c            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0x92            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSAR4            0x94            /* CS 4 Address reg (r/w) */
-#define MCFSIM_CSMR4            0x98            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0x9e            /* CS 4 Control reg (r/w) */
-#define MCFSIM_CSAR5            0xa0            /* CS 5 Address reg (r/w) */
-#define MCFSIM_CSMR5            0xa4            /* CS 5 Mask reg (r/w) */
-#define MCFSIM_CSCR5            0xaa            /* CS 5 Control reg (r/w) */
-#define MCFSIM_CSAR6            0xac            /* CS 6 Address reg (r/w) */
-#define MCFSIM_CSMR6            0xb0            /* CS 6 Mask reg (r/w) */
-#define MCFSIM_CSCR6            0xb6            /* CS 6 Control reg (r/w) */
-#define MCFSIM_CSAR7            0xb8            /* CS 7 Address reg (r/w) */
-#define MCFSIM_CSMR7            0xbc            /* CS 7 Mask reg (r/w) */
-#define MCFSIM_CSCR7            0xc2            /* CS 7 Control reg (r/w) */
-#define MCFSIM_DMCR             0xc6            /* Default control */
+#define MCFSIM_CSAR0            (MCF_MBAR + 0x64)       /* CS 0 Address reg */
+#define MCFSIM_CSMR0            (MCF_MBAR + 0x68)       /* CS 0 Mask reg */
+#define MCFSIM_CSCR0            (MCF_MBAR + 0x6e)       /* CS 0 Control reg */
+#define MCFSIM_CSAR1            (MCF_MBAR + 0x70)       /* CS 1 Address reg */
+#define MCFSIM_CSMR1            (MCF_MBAR + 0x74)       /* CS 1 Mask reg */
+#define MCFSIM_CSCR1            (MCF_MBAR + 0x7a)       /* CS 1 Control reg */
+#define MCFSIM_CSAR2            (MCF_MBAR + 0x7c)       /* CS 2 Address reg */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x80)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0x86)       /* CS 2 Control reg */
+#define MCFSIM_CSAR3            (MCF_MBAR + 0x88)       /* CS 3 Address reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0x8c)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0x92)       /* CS 3 Control reg */
+#define MCFSIM_CSAR4            (MCF_MBAR + 0x94)       /* CS 4 Address reg */
+#define MCFSIM_CSMR4            (MCF_MBAR + 0x98)       /* CS 4 Mask reg */
+#define MCFSIM_CSCR4            (MCF_MBAR + 0x9e)       /* CS 4 Control reg */
+#define MCFSIM_CSAR5            (MCF_MBAR + 0xa0)       /* CS 5 Address reg */
+#define MCFSIM_CSMR5            (MCF_MBAR + 0xa4)       /* CS 5 Mask reg */
+#define MCFSIM_CSCR5            (MCF_MBAR + 0xaa)       /* CS 5 Control reg */
+#define MCFSIM_CSAR6            (MCF_MBAR + 0xac)       /* CS 6 Address reg */
+#define MCFSIM_CSMR6            (MCF_MBAR + 0xb0)       /* CS 6 Mask reg */
+#define MCFSIM_CSCR6            (MCF_MBAR + 0xb6)       /* CS 6 Control reg */
+#define MCFSIM_CSAR7            (MCF_MBAR + 0xb8)       /* CS 7 Address reg */
+#define MCFSIM_CSMR7            (MCF_MBAR + 0xbc)       /* CS 7 Mask reg */
+#define MCFSIM_CSCR7            (MCF_MBAR + 0xc2)       /* CS 7 Control reg */
+#define MCFSIM_DMCR             (MCF_MBAR + 0xc6)       /* Default control */
 
 #ifdef CONFIG_M5206e
-#define MCFSIM_PAR              0xca            /* Pin Assignment reg (r/w) */
+#define MCFSIM_PAR              (MCF_MBAR + 0xca)       /* Pin Assignment */
 #else
-#define MCFSIM_PAR              0xcb            /* Pin Assignment reg (r/w) */
+#define MCFSIM_PAR              (MCF_MBAR + 0xcb)       /* Pin Assignment */
 #endif
 
 #define MCFTIMER_BASE1          (MCF_MBAR + 0x100)      /* Base of TIMER1 */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 91d3abc3f2a5..5e06b4eb57f3 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -176,21 +176,29 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PODR                    MCFGPIO_PODR_ADDR
-#define MCFGPIO_PDDR                    MCFGPIO_PDDR_ADDR
-#define MCFGPIO_PPDR                    MCFGPIO_PPDSDR_ADDR
-#define MCFGPIO_SETR                    MCFGPIO_PPDSDR_ADDR
-#define MCFGPIO_CLRR                    MCFGPIO_PCLRR_ADDR
+#define MCFGPIO_PODR            MCFGPIO_PODR_ADDR
+#define MCFGPIO_PDDR            MCFGPIO_PDDR_ADDR
+#define MCFGPIO_PPDR            MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_SETR            MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_CLRR            MCFGPIO_PCLRR_ADDR
 
-#define MCFGPIO_PIN_MAX                 107
-#define MCFGPIO_IRQ_MAX                 8
-#define MCFGPIO_IRQ_VECBASE             MCFINT_VECBASE
+#define MCFGPIO_PIN_MAX         107
+#define MCFGPIO_IRQ_MAX         8
+#define MCFGPIO_IRQ_VECBASE     MCFINT_VECBASE
 
 /*
  * Pin Assignment
 */
+#define MCFGPIO_PAR_AD          (MCF_IPSBAR + 0x100040)
+#define MCFGPIO_PAR_BUSCTL      (MCF_IPSBAR + 0x100042)
+#define MCFGPIO_PAR_BS          (MCF_IPSBAR + 0x100044)
+#define MCFGPIO_PAR_CS          (MCF_IPSBAR + 0x100045)
+#define MCFGPIO_PAR_SDRAM       (MCF_IPSBAR + 0x100046)
+#define MCFGPIO_PAR_FECI2C      (MCF_IPSBAR + 0x100047)
+#define MCFGPIO_PAR_UART        (MCF_IPSBAR + 0x100048)
 #define MCFGPIO_PAR_QSPI        (MCF_IPSBAR + 0x10004A)
 #define MCFGPIO_PAR_TIMER       (MCF_IPSBAR + 0x10004C)
+#define MCFGPIO_PAR_ETPU        (MCF_IPSBAR + 0x10004E)
 
 /*
  * DMA unit base addresses.
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 7f0c2c3660fd..fdf45e6807c9 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -25,41 +25,41 @@
 /*
  *      Define the 5249 SIM register set addresses.
  */
-#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
-#define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
-#define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
-#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
-#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
-#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
+#define MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status */
+#define MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog srv */
+#define MCFSIM_PAR              (MCF_MBAR + 0x04)       /* Pin Assignment */
+#define MCFSIM_IRQPAR           (MCF_MBAR + 0x06)       /* Intr Assignment */
+#define MCFSIM_MPARK            (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
+#define MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pending */
+#define MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
+#define MCFSIM_AVR              (MCF_MBAR + 0x4b)       /* Autovector Ctrl */
+#define MCFSIM_ICR0             (MCF_MBAR + 0x4c)       /* Intr Ctrl reg 0 */
+#define MCFSIM_ICR1             (MCF_MBAR + 0x4d)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x4e)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x4f)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x50)       /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5             (MCF_MBAR + 0x51)       /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6             (MCF_MBAR + 0x52)       /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7             (MCF_MBAR + 0x53)       /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8             (MCF_MBAR + 0x54)       /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9             (MCF_MBAR + 0x55)       /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10            (MCF_MBAR + 0x56)       /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11            (MCF_MBAR + 0x57)       /* Intr Ctrl reg 11 */
+
+#define MCFSIM_CSAR0            (MCF_MBAR + 0x80)       /* CS 0 Address reg */
+#define MCFSIM_CSMR0            (MCF_MBAR + 0x84)       /* CS 0 Mask reg */
+#define MCFSIM_CSCR0            (MCF_MBAR + 0x8a)       /* CS 0 Control reg */
+#define MCFSIM_CSAR1            (MCF_MBAR + 0x8c)       /* CS 1 Address reg */
+#define MCFSIM_CSMR1            (MCF_MBAR + 0x90)       /* CS 1 Mask reg */
+#define MCFSIM_CSCR1            (MCF_MBAR + 0x96)       /* CS 1 Control reg */
+#define MCFSIM_CSAR2            (MCF_MBAR + 0x98)       /* CS 2 Address reg */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x9c)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0xa2)       /* CS 2 Control reg */
+#define MCFSIM_CSAR3            (MCF_MBAR + 0xa4)       /* CS 3 Address reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0xa8)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0xae)       /* CS 3 Control reg */
 
 #define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
 #define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
@@ -134,23 +134,23 @@
 #define MCFSIM2_GPIO1ENABLE     (MCF_MBAR2 + 0x0B8)     /* GPIO1 enabled */
 #define MCFSIM2_GPIO1FUNC       (MCF_MBAR2 + 0x0BC)     /* GPIO1 function */
 
-#define MCFSIM2_GPIOINTSTAT     0xc0            /* GPIO interrupt status */
-#define MCFSIM2_GPIOINTCLEAR    0xc0            /* GPIO interrupt clear */
-#define MCFSIM2_GPIOINTENABLE   0xc4            /* GPIO interrupt enable */
+#define MCFSIM2_GPIOINTSTAT     (MCF_MBAR2 + 0xc0)      /* GPIO intr status */
+#define MCFSIM2_GPIOINTCLEAR    (MCF_MBAR2 + 0xc0)      /* GPIO intr clear */
+#define MCFSIM2_GPIOINTENABLE   (MCF_MBAR2 + 0xc4)      /* GPIO intr enable */
 
-#define MCFSIM2_INTLEVEL1       0x140           /* Interrupt level reg 1 */
-#define MCFSIM2_INTLEVEL2       0x144           /* Interrupt level reg 2 */
-#define MCFSIM2_INTLEVEL3       0x148           /* Interrupt level reg 3 */
-#define MCFSIM2_INTLEVEL4       0x14c           /* Interrupt level reg 4 */
-#define MCFSIM2_INTLEVEL5       0x150           /* Interrupt level reg 5 */
-#define MCFSIM2_INTLEVEL6       0x154           /* Interrupt level reg 6 */
-#define MCFSIM2_INTLEVEL7       0x158           /* Interrupt level reg 7 */
-#define MCFSIM2_INTLEVEL8       0x15c           /* Interrupt level reg 8 */
+#define MCFSIM2_INTLEVEL1       (MCF_MBAR2 + 0x140)     /* Intr level reg 1 */
+#define MCFSIM2_INTLEVEL2       (MCF_MBAR2 + 0x144)     /* Intr level reg 2 */
+#define MCFSIM2_INTLEVEL3       (MCF_MBAR2 + 0x148)     /* Intr level reg 3 */
+#define MCFSIM2_INTLEVEL4       (MCF_MBAR2 + 0x14c)     /* Intr level reg 4 */
+#define MCFSIM2_INTLEVEL5       (MCF_MBAR2 + 0x150)     /* Intr level reg 5 */
+#define MCFSIM2_INTLEVEL6       (MCF_MBAR2 + 0x154)     /* Intr level reg 6 */
+#define MCFSIM2_INTLEVEL7       (MCF_MBAR2 + 0x158)     /* Intr level reg 7 */
+#define MCFSIM2_INTLEVEL8       (MCF_MBAR2 + 0x15c)     /* Intr level reg 8 */
 
-#define MCFSIM2_DMAROUTE        0x188           /* DMA routing */
+#define MCFSIM2_DMAROUTE        (MCF_MBAR2 + 0x188)     /* DMA routing */
 
-#define MCFSIM2_IDECONFIG1      0x18c           /* IDEconfig1 */
-#define MCFSIM2_IDECONFIG2      0x190           /* IDEconfig2 */
+#define MCFSIM2_IDECONFIG1      (MCF_MBAR2 + 0x18c)     /* IDEconfig1 */
+#define MCFSIM2_IDECONFIG2      (MCF_MBAR2 + 0x190)     /* IDEconfig2 */
 
 /*
  * Define the base interrupt for the second interrupt controller.
diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h
index 6da24f653902..acab61cb91ed 100644
--- a/arch/m68k/include/asm/m525xsim.h
+++ b/arch/m68k/include/asm/m525xsim.h
@@ -26,41 +26,41 @@
 /*
  *      Define the 525x SIM register set addresses.
  */
-#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
-#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
-#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSAR4            0xb0            /* CS 4 Address reg (r/w) */
-#define MCFSIM_CSMR4            0xb4            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
+#define MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status */
+#define MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog srv */
+#define MCFSIM_MPARK            (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
+#define MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pending */
+#define MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
+#define MCFSIM_ICR0             (MCF_MBAR + 0x4c)       /* Intr Ctrl reg 0 */
+#define MCFSIM_ICR1             (MCF_MBAR + 0x4d)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x4e)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x4f)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x50)       /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5             (MCF_MBAR + 0x51)       /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6             (MCF_MBAR + 0x52)       /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7             (MCF_MBAR + 0x53)       /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8             (MCF_MBAR + 0x54)       /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9             (MCF_MBAR + 0x55)       /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10            (MCF_MBAR + 0x56)       /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11            (MCF_MBAR + 0x57)       /* Intr Ctrl reg 11 */
+
+#define MCFSIM_CSAR0            (MCF_MBAR + 0x80)       /* CS 0 Address reg */
+#define MCFSIM_CSMR0            (MCF_MBAR + 0x84)       /* CS 0 Mask reg */
+#define MCFSIM_CSCR0            (MCF_MBAR + 0x8a)       /* CS 0 Control reg */
+#define MCFSIM_CSAR1            (MCF_MBAR + 0x8c)       /* CS 1 Address reg */
+#define MCFSIM_CSMR1            (MCF_MBAR + 0x90)       /* CS 1 Mask reg */
+#define MCFSIM_CSCR1            (MCF_MBAR + 0x96)       /* CS 1 Control reg */
+#define MCFSIM_CSAR2            (MCF_MBAR + 0x98)       /* CS 2 Address reg */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x9c)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0xa2)       /* CS 2 Control reg */
+#define MCFSIM_CSAR3            (MCF_MBAR + 0xa4)       /* CS 3 Address reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0xa8)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0xae)       /* CS 3 Control reg */
+#define MCFSIM_CSAR4            (MCF_MBAR + 0xb0)       /* CS 4 Address reg */
+#define MCFSIM_CSMR4            (MCF_MBAR + 0xb4)       /* CS 4 Mask reg */
+#define MCFSIM_CSCR4            (MCF_MBAR + 0xba)       /* CS 4 Control reg */
 
 #define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
 #define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index a58f1760d858..1fb01bb05d6c 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -21,52 +21,52 @@
 /*
  *      Define the 5272 SIM register set addresses.
  */
-#define MCFSIM_SCR              0x04            /* SIM Config reg (r/w) */
-#define MCFSIM_SPR              0x06            /* System Protection reg (r/w)*/
-#define MCFSIM_PMR              0x08            /* Power Management reg (r/w) */
-#define MCFSIM_APMR             0x0e            /* Active Low Power reg (r/w) */
-#define MCFSIM_DIR              0x10            /* Device Identity reg (r/w) */
-
-#define MCFSIM_ICR1             0x20            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x24            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x28            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x2c            /* Intr Ctrl reg 4 (r/w) */
-
-#define MCFSIM_ISR              0x30            /* Interrupt Source reg (r/w) */
-#define MCFSIM_PITR             0x34            /* Interrupt Transition (r/w) */
-#define MCFSIM_PIWR             0x38            /* Interrupt Wakeup reg (r/w) */
-#define MCFSIM_PIVR             0x3f            /* Interrupt Vector reg (r/w( */
-
-#define MCFSIM_WRRR             0x280           /* Watchdog reference (r/w) */
-#define MCFSIM_WIRR             0x284           /* Watchdog interrupt (r/w) */
-#define MCFSIM_WCR              0x288           /* Watchdog counter (r/w) */
-#define MCFSIM_WER              0x28c           /* Watchdog event (r/w) */
-
-#define MCFSIM_CSBR0            0x40            /* CS0 Base Address (r/w) */
-#define MCFSIM_CSOR0            0x44            /* CS0 Option (r/w) */
-#define MCFSIM_CSBR1            0x48            /* CS1 Base Address (r/w) */
-#define MCFSIM_CSOR1            0x4c            /* CS1 Option (r/w) */
-#define MCFSIM_CSBR2            0x50            /* CS2 Base Address (r/w) */
-#define MCFSIM_CSOR2            0x54            /* CS2 Option (r/w) */
-#define MCFSIM_CSBR3            0x58            /* CS3 Base Address (r/w) */
-#define MCFSIM_CSOR3            0x5c            /* CS3 Option (r/w) */
-#define MCFSIM_CSBR4            0x60            /* CS4 Base Address (r/w) */
-#define MCFSIM_CSOR4            0x64            /* CS4 Option (r/w) */
-#define MCFSIM_CSBR5            0x68            /* CS5 Base Address (r/w) */
-#define MCFSIM_CSOR5            0x6c            /* CS5 Option (r/w) */
-#define MCFSIM_CSBR6            0x70            /* CS6 Base Address (r/w) */
-#define MCFSIM_CSOR6            0x74            /* CS6 Option (r/w) */
-#define MCFSIM_CSBR7            0x78            /* CS7 Base Address (r/w) */
-#define MCFSIM_CSOR7            0x7c            /* CS7 Option (r/w) */
-
-#define MCFSIM_SDCR             0x180           /* SDRAM Configuration (r/w) */
-#define MCFSIM_SDTR             0x184           /* SDRAM Timing (r/w) */
-#define MCFSIM_DCAR0            0x4c            /* DRAM 0 Address reg(r/w) */
-#define MCFSIM_DCMR0            0x50            /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DCCR0            0x57            /* DRAM 0 Control reg (r/w) */
-#define MCFSIM_DCAR1            0x58            /* DRAM 1 Address reg (r/w) */
-#define MCFSIM_DCMR1            0x5c            /* DRAM 1 Mask reg (r/w) */
-#define MCFSIM_DCCR1            0x63            /* DRAM 1 Control reg (r/w) */
+#define MCFSIM_SCR              (MCF_MBAR + 0x04)       /* SIM Config reg */
+#define MCFSIM_SPR              (MCF_MBAR + 0x06)       /* System Protection */
+#define MCFSIM_PMR              (MCF_MBAR + 0x08)       /* Power Management */
+#define MCFSIM_APMR             (MCF_MBAR + 0x0e)       /* Active Low Power */
+#define MCFSIM_DIR              (MCF_MBAR + 0x10)       /* Device Identity */
+
+#define MCFSIM_ICR1             (MCF_MBAR + 0x20)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x24)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x28)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x2c)       /* Intr Ctrl reg 4 */
+
+#define MCFSIM_ISR              (MCF_MBAR + 0x30)       /* Intr Source */
+#define MCFSIM_PITR             (MCF_MBAR + 0x34)       /* Intr Transition */
+#define MCFSIM_PIWR             (MCF_MBAR + 0x38)       /* Intr Wakeup */
+#define MCFSIM_PIVR             (MCF_MBAR + 0x3f)       /* Intr Vector */
+
+#define MCFSIM_WRRR             (MCF_MBAR + 0x280)      /* Watchdog reference */
+#define MCFSIM_WIRR             (MCF_MBAR + 0x284)      /* Watchdog interrupt */
+#define MCFSIM_WCR              (MCF_MBAR + 0x288)      /* Watchdog counter */
+#define MCFSIM_WER              (MCF_MBAR + 0x28c)      /* Watchdog event */
+
+#define MCFSIM_CSBR0            (MCF_MBAR + 0x40)       /* CS0 Base Address */
+#define MCFSIM_CSOR0            (MCF_MBAR + 0x44)       /* CS0 Option */
+#define MCFSIM_CSBR1            (MCF_MBAR + 0x48)       /* CS1 Base Address */
+#define MCFSIM_CSOR1            (MCF_MBAR + 0x4c)       /* CS1 Option */
+#define MCFSIM_CSBR2            (MCF_MBAR + 0x50)       /* CS2 Base Address */
+#define MCFSIM_CSOR2            (MCF_MBAR + 0x54)       /* CS2 Option */
+#define MCFSIM_CSBR3            (MCF_MBAR + 0x58)       /* CS3 Base Address */
+#define MCFSIM_CSOR3            (MCF_MBAR + 0x5c)       /* CS3 Option */
+#define MCFSIM_CSBR4            (MCF_MBAR + 0x60)       /* CS4 Base Address */
+#define MCFSIM_CSOR4            (MCF_MBAR + 0x64)       /* CS4 Option */
+#define MCFSIM_CSBR5            (MCF_MBAR + 0x68)       /* CS5 Base Address */
+#define MCFSIM_CSOR5            (MCF_MBAR + 0x6c)       /* CS5 Option */
+#define MCFSIM_CSBR6            (MCF_MBAR + 0x70)       /* CS6 Base Address */
+#define MCFSIM_CSOR6            (MCF_MBAR + 0x74)       /* CS6 Option */
+#define MCFSIM_CSBR7            (MCF_MBAR + 0x78)       /* CS7 Base Address */
+#define MCFSIM_CSOR7            (MCF_MBAR + 0x7c)       /* CS7 Option */
+
+#define MCFSIM_SDCR             (MCF_MBAR + 0x180)      /* SDRAM Config */
+#define MCFSIM_SDTR             (MCF_MBAR + 0x184)      /* SDRAM Timing */
+#define MCFSIM_DCAR0            (MCF_MBAR + 0x4c)       /* DRAM 0 Address */
+#define MCFSIM_DCMR0            (MCF_MBAR + 0x50)       /* DRAM 0 Mask */
+#define MCFSIM_DCCR0            (MCF_MBAR + 0x57)       /* DRAM 0 Control */
+#define MCFSIM_DCAR1            (MCF_MBAR + 0x58)       /* DRAM 1 Address */
+#define MCFSIM_DCMR1            (MCF_MBAR + 0x5c)       /* DRAM 1 Mask reg */
+#define MCFSIM_DCCR1            (MCF_MBAR + 0x63)       /* DRAM 1 Control */
 
 #define MCFUART_BASE0           (MCF_MBAR + 0x100) /* Base address UART0 */
 #define MCFUART_BASE1           (MCF_MBAR + 0x140) /* Base address UART1 */
@@ -132,8 +132,9 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PIN_MAX                 48
-#define MCFGPIO_IRQ_MAX                 -1
-#define MCFGPIO_IRQ_VECBASE             -1
+#define MCFGPIO_PIN_MAX         48
+#define MCFGPIO_IRQ_MAX         -1
+#define MCFGPIO_IRQ_VECBASE     -1
+
 /****************************************************************************/
 #endif  /* m5272sim_h */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 71aa5104d3d6..1bebbe78055a 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -184,19 +184,33 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PODR                    MCFGPIO_PODR_ADDR
-#define MCFGPIO_PDDR                    MCFGPIO_PDDR_ADDR
-#define MCFGPIO_PPDR                    MCFGPIO_PPDSDR_ADDR
-#define MCFGPIO_SETR                    MCFGPIO_PPDSDR_ADDR
-#define MCFGPIO_CLRR                    MCFGPIO_PCLRR_ADDR
+#define MCFGPIO_PODR            MCFGPIO_PODR_ADDR
+#define MCFGPIO_PDDR            MCFGPIO_PDDR_ADDR
+#define MCFGPIO_PPDR            MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_SETR            MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_CLRR            MCFGPIO_PCLRR_ADDR
 
-#define MCFGPIO_PIN_MAX                 100
-#define MCFGPIO_IRQ_MAX                 8
-#define MCFGPIO_IRQ_VECBASE             MCFINT_VECBASE
+#define MCFGPIO_PIN_MAX         100
+#define MCFGPIO_IRQ_MAX         8
+#define MCFGPIO_IRQ_VECBASE     MCFINT_VECBASE
 
+/*
+ * Port Pin Assignment registers.
+ */
+#define MCFGPIO_PAR_AD          (MCF_IPSBAR + 0x100040)
+#define MCFGPIO_PAR_BUSCTL      (MCF_IPSBAR + 0x100042)
+#define MCFGPIO_PAR_BS          (MCF_IPSBAR + 0x100044)
+#define MCFGPIO_PAR_CS          (MCF_IPSBAR + 0x100045)
+#define MCFGPIO_PAR_SDRAM       (MCF_IPSBAR + 0x100046)
+#define MCFGPIO_PAR_FECI2C      (MCF_IPSBAR + 0x100047)
+#define MCFGPIO_PAR_UART        (MCF_IPSBAR + 0x100048)
 #define MCFGPIO_PAR_QSPI        (MCF_IPSBAR + 0x10004A)
 #define MCFGPIO_PAR_TIMER       (MCF_IPSBAR + 0x10004C)
-#endif
+
+#define UART0_ENABLE_MASK       0x000f
+#define UART1_ENABLE_MASK       0x0ff0
+#define UART2_ENABLE_MASK       0x3000
+#endif /* CONFIG_M5271 */
 
 #ifdef CONFIG_M5275
 #define MCFGPIO_PODR_BUSCTL     (MCF_IPSBAR + 0x100004)
@@ -279,18 +293,36 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PODR                    MCFGPIO_PODR_BUSCTL
-#define MCFGPIO_PDDR                    MCFGPIO_PDDR_BUSCTL
-#define MCFGPIO_PPDR                    MCFGPIO_PPDSDR_BUSCTL
-#define MCFGPIO_SETR                    MCFGPIO_PPDSDR_BUSCTL
-#define MCFGPIO_CLRR                    MCFGPIO_PCLRR_BUSCTL
+#define MCFGPIO_PODR            MCFGPIO_PODR_BUSCTL
+#define MCFGPIO_PDDR            MCFGPIO_PDDR_BUSCTL
+#define MCFGPIO_PPDR            MCFGPIO_PPDSDR_BUSCTL
+#define MCFGPIO_SETR            MCFGPIO_PPDSDR_BUSCTL
+#define MCFGPIO_CLRR            MCFGPIO_PCLRR_BUSCTL
 
-#define MCFGPIO_PIN_MAX                 148
-#define MCFGPIO_IRQ_MAX                 8
-#define MCFGPIO_IRQ_VECBASE             MCFINT_VECBASE
+#define MCFGPIO_PIN_MAX         148
+#define MCFGPIO_IRQ_MAX         8
+#define MCFGPIO_IRQ_VECBASE     MCFINT_VECBASE
 
+/*
+ * Port Pin Assignment registers.
+ */
+#define MCFGPIO_PAR_AD          (MCF_IPSBAR + 0x100070)
+#define MCFGPIO_PAR_CS          (MCF_IPSBAR + 0x100071)
+#define MCFGPIO_PAR_BUSCTL      (MCF_IPSBAR + 0x100072)
+#define MCFGPIO_PAR_USB         (MCF_IPSBAR + 0x100076)
+#define MCFGPIO_PAR_FEC0HL      (MCF_IPSBAR + 0x100078)
+#define MCFGPIO_PAR_FEC1HL      (MCF_IPSBAR + 0x100079)
+#define MCFGPIO_PAR_TIMER       (MCF_IPSBAR + 0x10007A)
+#define MCFGPIO_PAR_UART        (MCF_IPSBAR + 0x10007C)
 #define MCFGPIO_PAR_QSPI        (MCF_IPSBAR + 0x10007E)
-#endif
+#define MCFGPIO_PAR_SDRAM       (MCF_IPSBAR + 0x100080)
+#define MCFGPIO_PAR_FECI2C      (MCF_IPSBAR + 0x100082)
+#define MCFGPIO_PAR_BS          (MCF_IPSBAR + 0x100084)
+
+#define UART0_ENABLE_MASK       0x000f
+#define UART1_ENABLE_MASK       0x00f0
+#define UART2_ENABLE_MASK       0x3f00
+#endif /* CONFIG_M5275 */
 
 /*
  * PIT timer base addresses.
@@ -311,22 +343,6 @@
 #define MCFEPORT_EPFR           (MCF_IPSBAR + 0x130006)
 
 /*
- *      GPIO pins setups to enable the UARTs.
- */
-#ifdef CONFIG_M5271
-#define MCF_GPIO_PAR_UART       0x100048        /* PAR UART address */
-#define UART0_ENABLE_MASK       0x000f
-#define UART1_ENABLE_MASK       0x0ff0
-#define UART2_ENABLE_MASK       0x3000
-#endif
-#ifdef CONFIG_M5275
-#define MCF_GPIO_PAR_UART       0x10007c        /* PAR UART address */
-#define UART0_ENABLE_MASK       0x000f
-#define UART1_ENABLE_MASK       0x00f0
-#define UART2_ENABLE_MASK       0x3f00 
-#endif
-
-/*
  *  Reset Control Unit (relative to IPSBAR).
  */
 #define MCF_RCR                 (MCF_IPSBAR + 0x110000)
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 4acb3c0a642e..cf68ca0ac3a5 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -233,23 +233,6 @@
 #define MCFGPIO_IRQ_VECBASE     MCFINT_VECBASE
 #define MCFGPIO_PIN_MAX         180
 
-
-/*
- *      Derek Cheung - 6 Feb 2005
- *              add I2C and QSPI register definition using Freescale's MCF5282
- */
-/* set Port AS pin for I2C or UART */
-#define MCF5282_GPIO_PASPAR     (volatile u16 *) (MCF_IPSBAR + 0x00100056)
-
-/* Port UA Pin Assignment Register (8 Bit) */
-#define MCF5282_GPIO_PUAPAR     0x10005C
-
-/* Interrupt Mask Register Register Low */ 
-#define MCF5282_INTC0_IMRL      (volatile u32 *) (MCF_IPSBAR + 0x0C0C)
-/* Interrupt Control Register 7 */
-#define MCF5282_INTC0_ICR17     (volatile u8 *) (MCF_IPSBAR + 0x0C51)
-
-
 /*
  *  Reset Control Unit (relative to IPSBAR).
  */
@@ -259,37 +242,5 @@
 #define MCF_RCR_SWRESET         0x80            /* Software reset bit */
 #define MCF_RCR_FRCSTOUT        0x40            /* Force external reset */
 
-/*********************************************************************
-*
-* Inter-IC (I2C) Module
-*
-*********************************************************************/
-/* Read/Write access macros for general use */
-#define MCF5282_I2C_I2ADR       (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address 
-#define MCF5282_I2C_I2FDR       (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider
-#define MCF5282_I2C_I2CR        (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control
-#define MCF5282_I2C_I2SR        (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status
-#define MCF5282_I2C_I2DR        (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O
-
-/* Bit level definitions and macros */
-#define MCF5282_I2C_I2ADR_ADDR(x)                       (((x)&0x7F)<<0x01)
-
-#define MCF5282_I2C_I2FDR_IC(x)                         (((x)&0x3F))
-
-#define MCF5282_I2C_I2CR_IEN    (0x80)  // I2C enable
-#define MCF5282_I2C_I2CR_IIEN   (0x40)  // interrupt enable
-#define MCF5282_I2C_I2CR_MSTA   (0x20)  // master/slave mode
-#define MCF5282_I2C_I2CR_MTX    (0x10)  // transmit/receive mode
-#define MCF5282_I2C_I2CR_TXAK   (0x08)  // transmit acknowledge enable
-#define MCF5282_I2C_I2CR_RSTA   (0x04)  // repeat start
-
-#define MCF5282_I2C_I2SR_ICF    (0x80)  // data transfer bit
-#define MCF5282_I2C_I2SR_IAAS   (0x40)  // I2C addressed as a slave
-#define MCF5282_I2C_I2SR_IBB    (0x20)  // I2C bus busy
-#define MCF5282_I2C_I2SR_IAL    (0x10)  // aribitration lost
-#define MCF5282_I2C_I2SR_SRW    (0x04)  // slave read/write
-#define MCF5282_I2C_I2SR_IIF    (0x02)  // I2C interrupt
-#define MCF5282_I2C_I2SR_RXAK   (0x01)  // received acknowledge
-
-
+/****************************************************************************/
 #endif  /* m528xsim_h */
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 3bc3adaa7ee0..5d0bb7ec31f8 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -23,71 +23,71 @@
 /*
  *      Define the 5307 SIM register set addresses.
  */
-#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
-#define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
-#define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
-#define MCFSIM_PLLCR            0x08            /* PLL Control Reg*/
-#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
-#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
+#define MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status reg */
+#define MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog service*/
+#define MCFSIM_PAR              (MCF_MBAR + 0x04)       /* Pin Assignment */
+#define MCFSIM_IRQPAR           (MCF_MBAR + 0x06)       /* Itr Assignment */
+#define MCFSIM_PLLCR            (MCF_MBAR + 0x08)       /* PLL Ctrl Reg */
+#define MCFSIM_MPARK            (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
+#define MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pend */
+#define MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
+#define MCFSIM_AVR              (MCF_MBAR + 0x4b)       /* Autovector Ctrl */
+#define MCFSIM_ICR0             (MCF_MBAR + 0x4c)       /* Intr Ctrl reg 0 */
+#define MCFSIM_ICR1             (MCF_MBAR + 0x4d)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x4e)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x4f)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x50)       /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5             (MCF_MBAR + 0x51)       /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6             (MCF_MBAR + 0x52)       /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7             (MCF_MBAR + 0x53)       /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8             (MCF_MBAR + 0x54)       /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9             (MCF_MBAR + 0x55)       /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10            (MCF_MBAR + 0x56)       /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11            (MCF_MBAR + 0x57)       /* Intr Ctrl reg 11 */
+
+#define MCFSIM_CSAR0            (MCF_MBAR + 0x80)       /* CS 0 Address reg */
+#define MCFSIM_CSMR0            (MCF_MBAR + 0x84)       /* CS 0 Mask reg */
+#define MCFSIM_CSCR0            (MCF_MBAR + 0x8a)       /* CS 0 Control reg */
+#define MCFSIM_CSAR1            (MCF_MBAR + 0x8c)       /* CS 1 Address reg */
+#define MCFSIM_CSMR1            (MCF_MBAR + 0x90)       /* CS 1 Mask reg */
+#define MCFSIM_CSCR1            (MCF_MBAR + 0x96)       /* CS 1 Control reg */
 
 #ifdef CONFIG_OLDMASK
-#define MCFSIM_CSBAR            0x98            /* CS Base Address reg (r/w) */
-#define MCFSIM_CSBAMR           0x9c            /* CS Base Mask reg (r/w) */
-#define MCFSIM_CSMR2            0x9e            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSMR3            0xaa            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSMR4            0xb6            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
-#define MCFSIM_CSMR5            0xc2            /* CS 5 Mask reg (r/w) */
-#define MCFSIM_CSCR5            0xc6            /* CS 5 Control reg (r/w) */
-#define MCFSIM_CSMR6            0xce            /* CS 6 Mask reg (r/w) */
-#define MCFSIM_CSCR6            0xd2            /* CS 6 Control reg (r/w) */
-#define MCFSIM_CSMR7            0xda            /* CS 7 Mask reg (r/w) */
-#define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
+#define MCFSIM_CSBAR            (MCF_MBAR + 0x98)       /* CS Base Address */
+#define MCFSIM_CSBAMR           (MCF_MBAR + 0x9c)       /* CS Base Mask */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x9e)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0xa2)       /* CS 2 Control reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0xaa)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0xae)       /* CS 3 Control reg */
+#define MCFSIM_CSMR4            (MCF_MBAR + 0xb6)       /* CS 4 Mask reg */
+#define MCFSIM_CSCR4            (MCF_MBAR + 0xba)       /* CS 4 Control reg */
+#define MCFSIM_CSMR5            (MCF_MBAR + 0xc2)       /* CS 5 Mask reg */
+#define MCFSIM_CSCR5            (MCF_MBAR + 0xc6)       /* CS 5 Control reg */
+#define MCFSIM_CSMR6            (MCF_MBAR + 0xce)       /* CS 6 Mask reg */
+#define MCFSIM_CSCR6            (MCF_MBAR + 0xd2)       /* CS 6 Control reg */
+#define MCFSIM_CSMR7            (MCF_MBAR + 0xda)       /* CS 7 Mask reg */
+#define MCFSIM_CSCR7            (MCF_MBAR + 0xde)       /* CS 7 Control reg */
 #else
-#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSAR4            0xb0            /* CS 4 Address reg (r/w) */
-#define MCFSIM_CSMR4            0xb4            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
-#define MCFSIM_CSAR5            0xbc            /* CS 5 Address reg (r/w) */
-#define MCFSIM_CSMR5            0xc0            /* CS 5 Mask reg (r/w) */
-#define MCFSIM_CSCR5            0xc6            /* CS 5 Control reg (r/w) */
-#define MCFSIM_CSAR6            0xc8            /* CS 6 Address reg (r/w) */
-#define MCFSIM_CSMR6            0xcc            /* CS 6 Mask reg (r/w) */
-#define MCFSIM_CSCR6            0xd2            /* CS 6 Control reg (r/w) */
-#define MCFSIM_CSAR7            0xd4            /* CS 7 Address reg (r/w) */
-#define MCFSIM_CSMR7            0xd8            /* CS 7 Mask reg (r/w) */
-#define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
+#define MCFSIM_CSAR2            (MCF_MBAR + 0x98)       /* CS 2 Address reg */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x9c)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0xa2)       /* CS 2 Control reg */
+#define MCFSIM_CSAR3            (MCF_MBAR + 0xa4)       /* CS 3 Address reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0xa8)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0xae)       /* CS 3 Control reg */
+#define MCFSIM_CSAR4            (MCF_MBAR + 0xb0)       /* CS 4 Address reg */
+#define MCFSIM_CSMR4            (MCF_MBAR + 0xb4)       /* CS 4 Mask reg */
+#define MCFSIM_CSCR4            (MCF_MBAR + 0xba)       /* CS 4 Control reg */
+#define MCFSIM_CSAR5            (MCF_MBAR + 0xbc)       /* CS 5 Address reg */
+#define MCFSIM_CSMR5            (MCF_MBAR + 0xc0)       /* CS 5 Mask reg */
+#define MCFSIM_CSCR5            (MCF_MBAR + 0xc6)       /* CS 5 Control reg */
+#define MCFSIM_CSAR6            (MCF_MBAR + 0xc8)       /* CS 6 Address reg */
+#define MCFSIM_CSMR6            (MCF_MBAR + 0xcc)       /* CS 6 Mask reg */
+#define MCFSIM_CSCR6            (MCF_MBAR + 0xd2)       /* CS 6 Control reg */
+#define MCFSIM_CSAR7            (MCF_MBAR + 0xd4)       /* CS 7 Address reg */
+#define MCFSIM_CSMR7            (MCF_MBAR + 0xd8)       /* CS 7 Mask reg */
+#define MCFSIM_CSCR7            (MCF_MBAR + 0xde)       /* CS 7 Control reg */
 #endif /* CONFIG_OLDMASK */
 
 #define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
@@ -127,9 +127,9 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PIN_MAX                 16
-#define MCFGPIO_IRQ_MAX                 -1
-#define MCFGPIO_IRQ_VECBASE             -1
+#define MCFGPIO_PIN_MAX         16
+#define MCFGPIO_IRQ_MAX         -1
+#define MCFGPIO_IRQ_VECBASE     -1
 
 
 /* Definition offset address for CS2-7  -- old mask 5307 */
@@ -167,9 +167,9 @@
 /*
  *       Defines for the IRQPAR Register
  */
-#define IRQ5_LEVEL4     0x80
-#define IRQ3_LEVEL6     0x40
-#define IRQ1_LEVEL2     0x20
+#define IRQ5_LEVEL4             0x80
+#define IRQ3_LEVEL6             0x40
+#define IRQ1_LEVEL2             0x20
 
 /*
  *      Define system peripheral IRQ usage.
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 5ca7b298c6eb..8668e47ced0e 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -15,10 +15,6 @@
 
 #include <asm/m53xxacr.h>
 
-#define MCF_REG32(x) (*(volatile unsigned long  *)(x))
-#define MCF_REG16(x) (*(volatile unsigned short *)(x))
-#define MCF_REG08(x) (*(volatile unsigned char  *)(x))
-
 #define MCFINT_VECBASE      64
 #define MCFINT_UART0        26          /* Interrupt number for UART0 */
 #define MCFINT_UART1        27          /* Interrupt number for UART1 */
@@ -38,7 +34,7 @@
 
 #define MCF_IRQ_QSPI        (MCFINT_VECBASE + MCFINT_QSPI)
 
-#define MCF_WTM_WCR     MCF_REG16(0xFC098000)
+#define MCF_WTM_WCR             0xFC098000
 
 /*
  *      Define the 532x SIM register set addresses.
@@ -152,42 +148,6 @@
 #define MCFPM_PPMHR1            0xfc040038
 #define MCFPM_LPCR              0xec090007
 
-/*********************************************************************
- *
- * Inter-IC (I2C) Module
- *
- *********************************************************************/
-
-/* Read/Write access macros for general use */
-#define MCF532x_I2C_I2ADR       (volatile u8 *) (0xFC058000) // Address 
-#define MCF532x_I2C_I2FDR       (volatile u8 *) (0xFC058004) // Freq Divider
-#define MCF532x_I2C_I2CR        (volatile u8 *) (0xFC058008) // Control
-#define MCF532x_I2C_I2SR        (volatile u8 *) (0xFC05800C) // Status
-#define MCF532x_I2C_I2DR        (volatile u8 *) (0xFC058010) // Data I/O
-
-/* Bit level definitions and macros */
-#define MCF532x_I2C_I2ADR_ADDR(x)                       (((x)&0x7F)<<0x01)
-
-#define MCF532x_I2C_I2FDR_IC(x)                         (((x)&0x3F))
-
-#define MCF532x_I2C_I2CR_IEN    (0x80)  // I2C enable
-#define MCF532x_I2C_I2CR_IIEN   (0x40)  // interrupt enable
-#define MCF532x_I2C_I2CR_MSTA   (0x20)  // master/slave mode
-#define MCF532x_I2C_I2CR_MTX    (0x10)  // transmit/receive mode
-#define MCF532x_I2C_I2CR_TXAK   (0x08)  // transmit acknowledge enable
-#define MCF532x_I2C_I2CR_RSTA   (0x04)  // repeat start
-
-#define MCF532x_I2C_I2SR_ICF    (0x80)  // data transfer bit
-#define MCF532x_I2C_I2SR_IAAS   (0x40)  // I2C addressed as a slave
-#define MCF532x_I2C_I2SR_IBB    (0x20)  // I2C bus busy
-#define MCF532x_I2C_I2SR_IAL    (0x10)  // aribitration lost
-#define MCF532x_I2C_I2SR_SRW    (0x04)  // slave read/write
-#define MCF532x_I2C_I2SR_IIF    (0x02)  // I2C interrupt
-#define MCF532x_I2C_I2SR_RXAK   (0x01)  // received acknowledge
-
-#define MCF532x_PAR_FECI2C      (volatile u8 *) (0xFC0A4053)
-
-
 /*
  *      The M5329EVB board needs a help getting its devices initialized 
  *      at kernel start time if dBUG doesn't set it up (for example 
@@ -217,13 +177,13 @@
  *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_CCM_CCR               MCF_REG16(0xFC0A0004)
-#define MCF_CCM_RCON              MCF_REG16(0xFC0A0008)
-#define MCF_CCM_CIR               MCF_REG16(0xFC0A000A)
-#define MCF_CCM_MISCCR            MCF_REG16(0xFC0A0010)
-#define MCF_CCM_CDR               MCF_REG16(0xFC0A0012)
-#define MCF_CCM_UHCSR             MCF_REG16(0xFC0A0014)
-#define MCF_CCM_UOCSR             MCF_REG16(0xFC0A0016)
+#define MCF_CCM_CCR               0xFC0A0004
+#define MCF_CCM_RCON              0xFC0A0008
+#define MCF_CCM_CIR               0xFC0A000A
+#define MCF_CCM_MISCCR            0xFC0A0010
+#define MCF_CCM_CDR               0xFC0A0012
+#define MCF_CCM_UHCSR             0xFC0A0014
+#define MCF_CCM_UOCSR             0xFC0A0016
 
 /* Bit definitions and macros for MCF_CCM_CCR */
 #define MCF_CCM_CCR_RESERVED      (0x0001)
@@ -287,104 +247,29 @@
 
 /*********************************************************************
  *
- * DMA Timers (DTIM)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_DTIM0_DTMR           MCF_REG16(0xFC070000)
-#define MCF_DTIM0_DTXMR          MCF_REG08(0xFC070002)
-#define MCF_DTIM0_DTER           MCF_REG08(0xFC070003)
-#define MCF_DTIM0_DTRR           MCF_REG32(0xFC070004)
-#define MCF_DTIM0_DTCR           MCF_REG32(0xFC070008)
-#define MCF_DTIM0_DTCN           MCF_REG32(0xFC07000C)
-#define MCF_DTIM1_DTMR           MCF_REG16(0xFC074000)
-#define MCF_DTIM1_DTXMR          MCF_REG08(0xFC074002)
-#define MCF_DTIM1_DTER           MCF_REG08(0xFC074003)
-#define MCF_DTIM1_DTRR           MCF_REG32(0xFC074004)
-#define MCF_DTIM1_DTCR           MCF_REG32(0xFC074008)
-#define MCF_DTIM1_DTCN           MCF_REG32(0xFC07400C)
-#define MCF_DTIM2_DTMR           MCF_REG16(0xFC078000)
-#define MCF_DTIM2_DTXMR          MCF_REG08(0xFC078002)
-#define MCF_DTIM2_DTER           MCF_REG08(0xFC078003)
-#define MCF_DTIM2_DTRR           MCF_REG32(0xFC078004)
-#define MCF_DTIM2_DTCR           MCF_REG32(0xFC078008)
-#define MCF_DTIM2_DTCN           MCF_REG32(0xFC07800C)
-#define MCF_DTIM3_DTMR           MCF_REG16(0xFC07C000)
-#define MCF_DTIM3_DTXMR          MCF_REG08(0xFC07C002)
-#define MCF_DTIM3_DTER           MCF_REG08(0xFC07C003)
-#define MCF_DTIM3_DTRR           MCF_REG32(0xFC07C004)
-#define MCF_DTIM3_DTCR           MCF_REG32(0xFC07C008)
-#define MCF_DTIM3_DTCN           MCF_REG32(0xFC07C00C)
-#define MCF_DTIM_DTMR(x)         MCF_REG16(0xFC070000+((x)*0x4000))
-#define MCF_DTIM_DTXMR(x)        MCF_REG08(0xFC070002+((x)*0x4000))
-#define MCF_DTIM_DTER(x)         MCF_REG08(0xFC070003+((x)*0x4000))
-#define MCF_DTIM_DTRR(x)         MCF_REG32(0xFC070004+((x)*0x4000))
-#define MCF_DTIM_DTCR(x)         MCF_REG32(0xFC070008+((x)*0x4000))
-#define MCF_DTIM_DTCN(x)         MCF_REG32(0xFC07000C+((x)*0x4000))
-
-/* Bit definitions and macros for MCF_DTIM_DTMR */
-#define MCF_DTIM_DTMR_RST        (0x0001)
-#define MCF_DTIM_DTMR_CLK(x)     (((x)&0x0003)<<1)
-#define MCF_DTIM_DTMR_FRR        (0x0008)
-#define MCF_DTIM_DTMR_ORRI       (0x0010)
-#define MCF_DTIM_DTMR_OM         (0x0020)
-#define MCF_DTIM_DTMR_CE(x)      (((x)&0x0003)<<6)
-#define MCF_DTIM_DTMR_PS(x)      (((x)&0x00FF)<<8)
-#define MCF_DTIM_DTMR_CE_ANY     (0x00C0)
-#define MCF_DTIM_DTMR_CE_FALL    (0x0080)
-#define MCF_DTIM_DTMR_CE_RISE    (0x0040)
-#define MCF_DTIM_DTMR_CE_NONE    (0x0000)
-#define MCF_DTIM_DTMR_CLK_DTIN   (0x0006)
-#define MCF_DTIM_DTMR_CLK_DIV16  (0x0004)
-#define MCF_DTIM_DTMR_CLK_DIV1   (0x0002)
-#define MCF_DTIM_DTMR_CLK_STOP   (0x0000)
-
-/* Bit definitions and macros for MCF_DTIM_DTXMR */
-#define MCF_DTIM_DTXMR_MODE16    (0x01)
-#define MCF_DTIM_DTXMR_DMAEN     (0x80)
-
-/* Bit definitions and macros for MCF_DTIM_DTER */
-#define MCF_DTIM_DTER_CAP        (0x01)
-#define MCF_DTIM_DTER_REF        (0x02)
-
-/* Bit definitions and macros for MCF_DTIM_DTRR */
-#define MCF_DTIM_DTRR_REF(x)     (((x)&0xFFFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_DTIM_DTCR */
-#define MCF_DTIM_DTCR_CAP(x)     (((x)&0xFFFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_DTIM_DTCN */
-#define MCF_DTIM_DTCN_CNT(x)     (((x)&0xFFFFFFFF)<<0)
-
-/*********************************************************************
- *
  * FlexBus Chip Selects (FBCS)
  *
  *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_FBCS0_CSAR          MCF_REG32(0xFC008000)
-#define MCF_FBCS0_CSMR          MCF_REG32(0xFC008004)
-#define MCF_FBCS0_CSCR          MCF_REG32(0xFC008008)
-#define MCF_FBCS1_CSAR          MCF_REG32(0xFC00800C)
-#define MCF_FBCS1_CSMR          MCF_REG32(0xFC008010)
-#define MCF_FBCS1_CSCR          MCF_REG32(0xFC008014)
-#define MCF_FBCS2_CSAR          MCF_REG32(0xFC008018)
-#define MCF_FBCS2_CSMR          MCF_REG32(0xFC00801C)
-#define MCF_FBCS2_CSCR          MCF_REG32(0xFC008020)
-#define MCF_FBCS3_CSAR          MCF_REG32(0xFC008024)
-#define MCF_FBCS3_CSMR          MCF_REG32(0xFC008028)
-#define MCF_FBCS3_CSCR          MCF_REG32(0xFC00802C)
-#define MCF_FBCS4_CSAR          MCF_REG32(0xFC008030)
-#define MCF_FBCS4_CSMR          MCF_REG32(0xFC008034)
-#define MCF_FBCS4_CSCR          MCF_REG32(0xFC008038)
-#define MCF_FBCS5_CSAR          MCF_REG32(0xFC00803C)
-#define MCF_FBCS5_CSMR          MCF_REG32(0xFC008040)
-#define MCF_FBCS5_CSCR          MCF_REG32(0xFC008044)
-#define MCF_FBCS_CSAR(x)        MCF_REG32(0xFC008000+((x)*0x00C))
-#define MCF_FBCS_CSMR(x)        MCF_REG32(0xFC008004+((x)*0x00C))
-#define MCF_FBCS_CSCR(x)        MCF_REG32(0xFC008008+((x)*0x00C))
+#define MCF_FBCS0_CSAR          0xFC008000
+#define MCF_FBCS0_CSMR          0xFC008004
+#define MCF_FBCS0_CSCR          0xFC008008
+#define MCF_FBCS1_CSAR          0xFC00800C
+#define MCF_FBCS1_CSMR          0xFC008010
+#define MCF_FBCS1_CSCR          0xFC008014
+#define MCF_FBCS2_CSAR          0xFC008018
+#define MCF_FBCS2_CSMR          0xFC00801C
+#define MCF_FBCS2_CSCR          0xFC008020
+#define MCF_FBCS3_CSAR          0xFC008024
+#define MCF_FBCS3_CSMR          0xFC008028
+#define MCF_FBCS3_CSCR          0xFC00802C
+#define MCF_FBCS4_CSAR          0xFC008030
+#define MCF_FBCS4_CSMR          0xFC008034
+#define MCF_FBCS4_CSCR          0xFC008038
+#define MCF_FBCS5_CSAR          0xFC00803C
+#define MCF_FBCS5_CSMR          0xFC008040
+#define MCF_FBCS5_CSCR          0xFC008044
 
 /* Bit definitions and macros for MCF_FBCS_CSAR */
 #define MCF_FBCS_CSAR_BA(x)     ((x)&0xFFFF0000)
@@ -501,32 +386,32 @@
 #define MCFGPIO_PCLRR_LCDDATAL          (0xFC0A404B)
 #define MCFGPIO_PCLRR_LCDCTLH           (0xFC0A404C)
 #define MCFGPIO_PCLRR_LCDCTLL           (0xFC0A404D)
-#define MCF_GPIO_PAR_FEC                MCF_REG08(0xFC0A4050)
-#define MCF_GPIO_PAR_PWM                MCF_REG08(0xFC0A4051)
-#define MCF_GPIO_PAR_BUSCTL             MCF_REG08(0xFC0A4052)
-#define MCF_GPIO_PAR_FECI2C             MCF_REG08(0xFC0A4053)
-#define MCF_GPIO_PAR_BE                 MCF_REG08(0xFC0A4054)
-#define MCF_GPIO_PAR_CS                 MCF_REG08(0xFC0A4055)
-#define MCF_GPIO_PAR_SSI                MCF_REG16(0xFC0A4056)
-#define MCF_GPIO_PAR_UART               MCF_REG16(0xFC0A4058)
-#define MCF_GPIO_PAR_QSPI               MCF_REG16(0xFC0A405A)
-#define MCF_GPIO_PAR_TIMER              MCF_REG08(0xFC0A405C)
-#define MCF_GPIO_PAR_LCDDATA            MCF_REG08(0xFC0A405D)
-#define MCF_GPIO_PAR_LCDCTL             MCF_REG16(0xFC0A405E)
-#define MCF_GPIO_PAR_IRQ                MCF_REG16(0xFC0A4060)
-#define MCF_GPIO_MSCR_FLEXBUS           MCF_REG08(0xFC0A4064)
-#define MCF_GPIO_MSCR_SDRAM             MCF_REG08(0xFC0A4065)
-#define MCF_GPIO_DSCR_I2C               MCF_REG08(0xFC0A4068)
-#define MCF_GPIO_DSCR_PWM               MCF_REG08(0xFC0A4069)
-#define MCF_GPIO_DSCR_FEC               MCF_REG08(0xFC0A406A)
-#define MCF_GPIO_DSCR_UART              MCF_REG08(0xFC0A406B)
-#define MCF_GPIO_DSCR_QSPI              MCF_REG08(0xFC0A406C)
-#define MCF_GPIO_DSCR_TIMER             MCF_REG08(0xFC0A406D)
-#define MCF_GPIO_DSCR_SSI               MCF_REG08(0xFC0A406E)
-#define MCF_GPIO_DSCR_LCD               MCF_REG08(0xFC0A406F)
-#define MCF_GPIO_DSCR_DEBUG             MCF_REG08(0xFC0A4070)
-#define MCF_GPIO_DSCR_CLKRST            MCF_REG08(0xFC0A4071)
-#define MCF_GPIO_DSCR_IRQ               MCF_REG08(0xFC0A4072)
+#define MCFGPIO_PAR_FEC                 (0xFC0A4050)
+#define MCFGPIO_PAR_PWM                 (0xFC0A4051)
+#define MCFGPIO_PAR_BUSCTL              (0xFC0A4052)
+#define MCFGPIO_PAR_FECI2C              (0xFC0A4053)
+#define MCFGPIO_PAR_BE                  (0xFC0A4054)
+#define MCFGPIO_PAR_CS                  (0xFC0A4055)
+#define MCFGPIO_PAR_SSI                 (0xFC0A4056)
+#define MCFGPIO_PAR_UART                (0xFC0A4058)
+#define MCFGPIO_PAR_QSPI                (0xFC0A405A)
+#define MCFGPIO_PAR_TIMER               (0xFC0A405C)
+#define MCFGPIO_PAR_LCDDATA             (0xFC0A405D)
+#define MCFGPIO_PAR_LCDCTL              (0xFC0A405E)
+#define MCFGPIO_PAR_IRQ                 (0xFC0A4060)
+#define MCFGPIO_MSCR_FLEXBUS            (0xFC0A4064)
+#define MCFGPIO_MSCR_SDRAM              (0xFC0A4065)
+#define MCFGPIO_DSCR_I2C                (0xFC0A4068)
+#define MCFGPIO_DSCR_PWM                (0xFC0A4069)
+#define MCFGPIO_DSCR_FEC                (0xFC0A406A)
+#define MCFGPIO_DSCR_UART               (0xFC0A406B)
+#define MCFGPIO_DSCR_QSPI               (0xFC0A406C)
+#define MCFGPIO_DSCR_TIMER              (0xFC0A406D)
+#define MCFGPIO_DSCR_SSI                (0xFC0A406E)
+#define MCFGPIO_DSCR_LCD                (0xFC0A406F)
+#define MCFGPIO_DSCR_DEBUG              (0xFC0A4070)
+#define MCFGPIO_DSCR_CLKRST             (0xFC0A4071)
+#define MCFGPIO_DSCR_IRQ                (0xFC0A4072)
 
 /* Bit definitions and macros for MCF_GPIO_PODR_FECH */
 #define MCF_GPIO_PODR_FECH_PODR_FECH0              (0x01)
@@ -1215,709 +1100,6 @@
 #define MCFGPIO_IRQ_MAX                 8
 #define MCFGPIO_IRQ_VECBASE             MCFINT_VECBASE
 
-
-/*********************************************************************
- *
- * Interrupt Controller (INTC)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_INTC0_IPRH             MCF_REG32(0xFC048000)
-#define MCF_INTC0_IPRL             MCF_REG32(0xFC048004)
-#define MCF_INTC0_IMRH             MCF_REG32(0xFC048008)
-#define MCF_INTC0_IMRL             MCF_REG32(0xFC04800C)
-#define MCF_INTC0_INTFRCH          MCF_REG32(0xFC048010)
-#define MCF_INTC0_INTFRCL          MCF_REG32(0xFC048014)
-#define MCF_INTC0_ICONFIG          MCF_REG16(0xFC04801A)
-#define MCF_INTC0_SIMR             MCF_REG08(0xFC04801C)
-#define MCF_INTC0_CIMR             MCF_REG08(0xFC04801D)
-#define MCF_INTC0_CLMASK           MCF_REG08(0xFC04801E)
-#define MCF_INTC0_SLMASK           MCF_REG08(0xFC04801F)
-#define MCF_INTC0_ICR0             MCF_REG08(0xFC048040)
-#define MCF_INTC0_ICR1             MCF_REG08(0xFC048041)
-#define MCF_INTC0_ICR2             MCF_REG08(0xFC048042)
-#define MCF_INTC0_ICR3             MCF_REG08(0xFC048043)
-#define MCF_INTC0_ICR4             MCF_REG08(0xFC048044)
-#define MCF_INTC0_ICR5             MCF_REG08(0xFC048045)
-#define MCF_INTC0_ICR6             MCF_REG08(0xFC048046)
-#define MCF_INTC0_ICR7             MCF_REG08(0xFC048047)
-#define MCF_INTC0_ICR8             MCF_REG08(0xFC048048)
-#define MCF_INTC0_ICR9             MCF_REG08(0xFC048049)
-#define MCF_INTC0_ICR10            MCF_REG08(0xFC04804A)
-#define MCF_INTC0_ICR11            MCF_REG08(0xFC04804B)
-#define MCF_INTC0_ICR12            MCF_REG08(0xFC04804C)
-#define MCF_INTC0_ICR13            MCF_REG08(0xFC04804D)
-#define MCF_INTC0_ICR14            MCF_REG08(0xFC04804E)
-#define MCF_INTC0_ICR15            MCF_REG08(0xFC04804F)
-#define MCF_INTC0_ICR16            MCF_REG08(0xFC048050)
-#define MCF_INTC0_ICR17            MCF_REG08(0xFC048051)
-#define MCF_INTC0_ICR18            MCF_REG08(0xFC048052)
-#define MCF_INTC0_ICR19            MCF_REG08(0xFC048053)
-#define MCF_INTC0_ICR20            MCF_REG08(0xFC048054)
-#define MCF_INTC0_ICR21            MCF_REG08(0xFC048055)
-#define MCF_INTC0_ICR22            MCF_REG08(0xFC048056)
-#define MCF_INTC0_ICR23            MCF_REG08(0xFC048057)
-#define MCF_INTC0_ICR24            MCF_REG08(0xFC048058)
-#define MCF_INTC0_ICR25            MCF_REG08(0xFC048059)
-#define MCF_INTC0_ICR26            MCF_REG08(0xFC04805A)
-#define MCF_INTC0_ICR27            MCF_REG08(0xFC04805B)
-#define MCF_INTC0_ICR28            MCF_REG08(0xFC04805C)
-#define MCF_INTC0_ICR29            MCF_REG08(0xFC04805D)
-#define MCF_INTC0_ICR30            MCF_REG08(0xFC04805E)
-#define MCF_INTC0_ICR31            MCF_REG08(0xFC04805F)
-#define MCF_INTC0_ICR32            MCF_REG08(0xFC048060)
-#define MCF_INTC0_ICR33            MCF_REG08(0xFC048061)
-#define MCF_INTC0_ICR34            MCF_REG08(0xFC048062)
-#define MCF_INTC0_ICR35            MCF_REG08(0xFC048063)
-#define MCF_INTC0_ICR36            MCF_REG08(0xFC048064)
-#define MCF_INTC0_ICR37            MCF_REG08(0xFC048065)
-#define MCF_INTC0_ICR38            MCF_REG08(0xFC048066)
-#define MCF_INTC0_ICR39            MCF_REG08(0xFC048067)
-#define MCF_INTC0_ICR40            MCF_REG08(0xFC048068)
-#define MCF_INTC0_ICR41            MCF_REG08(0xFC048069)
-#define MCF_INTC0_ICR42            MCF_REG08(0xFC04806A)
-#define MCF_INTC0_ICR43            MCF_REG08(0xFC04806B)
-#define MCF_INTC0_ICR44            MCF_REG08(0xFC04806C)
-#define MCF_INTC0_ICR45            MCF_REG08(0xFC04806D)
-#define MCF_INTC0_ICR46            MCF_REG08(0xFC04806E)
-#define MCF_INTC0_ICR47            MCF_REG08(0xFC04806F)
-#define MCF_INTC0_ICR48            MCF_REG08(0xFC048070)
-#define MCF_INTC0_ICR49            MCF_REG08(0xFC048071)
-#define MCF_INTC0_ICR50            MCF_REG08(0xFC048072)
-#define MCF_INTC0_ICR51            MCF_REG08(0xFC048073)
-#define MCF_INTC0_ICR52            MCF_REG08(0xFC048074)
-#define MCF_INTC0_ICR53            MCF_REG08(0xFC048075)
-#define MCF_INTC0_ICR54            MCF_REG08(0xFC048076)
-#define MCF_INTC0_ICR55            MCF_REG08(0xFC048077)
-#define MCF_INTC0_ICR56            MCF_REG08(0xFC048078)
-#define MCF_INTC0_ICR57            MCF_REG08(0xFC048079)
-#define MCF_INTC0_ICR58            MCF_REG08(0xFC04807A)
-#define MCF_INTC0_ICR59            MCF_REG08(0xFC04807B)
-#define MCF_INTC0_ICR60            MCF_REG08(0xFC04807C)
-#define MCF_INTC0_ICR61            MCF_REG08(0xFC04807D)
-#define MCF_INTC0_ICR62            MCF_REG08(0xFC04807E)
-#define MCF_INTC0_ICR63            MCF_REG08(0xFC04807F)
-#define MCF_INTC0_ICR(x)           MCF_REG08(0xFC048040+((x)*0x001))
-#define MCF_INTC0_SWIACK           MCF_REG08(0xFC0480E0)
-#define MCF_INTC0_L1IACK           MCF_REG08(0xFC0480E4)
-#define MCF_INTC0_L2IACK           MCF_REG08(0xFC0480E8)
-#define MCF_INTC0_L3IACK           MCF_REG08(0xFC0480EC)
-#define MCF_INTC0_L4IACK           MCF_REG08(0xFC0480F0)
-#define MCF_INTC0_L5IACK           MCF_REG08(0xFC0480F4)
-#define MCF_INTC0_L6IACK           MCF_REG08(0xFC0480F8)
-#define MCF_INTC0_L7IACK           MCF_REG08(0xFC0480FC)
-#define MCF_INTC0_LIACK(x)         MCF_REG08(0xFC0480E4+((x)*0x004))
-#define MCF_INTC1_IPRH             MCF_REG32(0xFC04C000)
-#define MCF_INTC1_IPRL             MCF_REG32(0xFC04C004)
-#define MCF_INTC1_IMRH             MCF_REG32(0xFC04C008)
-#define MCF_INTC1_IMRL             MCF_REG32(0xFC04C00C)
-#define MCF_INTC1_INTFRCH          MCF_REG32(0xFC04C010)
-#define MCF_INTC1_INTFRCL          MCF_REG32(0xFC04C014)
-#define MCF_INTC1_ICONFIG          MCF_REG16(0xFC04C01A)
-#define MCF_INTC1_SIMR             MCF_REG08(0xFC04C01C)
-#define MCF_INTC1_CIMR             MCF_REG08(0xFC04C01D)
-#define MCF_INTC1_CLMASK           MCF_REG08(0xFC04C01E)
-#define MCF_INTC1_SLMASK           MCF_REG08(0xFC04C01F)
-#define MCF_INTC1_ICR0             MCF_REG08(0xFC04C040)
-#define MCF_INTC1_ICR1             MCF_REG08(0xFC04C041)
-#define MCF_INTC1_ICR2             MCF_REG08(0xFC04C042)
-#define MCF_INTC1_ICR3             MCF_REG08(0xFC04C043)
-#define MCF_INTC1_ICR4             MCF_REG08(0xFC04C044)
-#define MCF_INTC1_ICR5             MCF_REG08(0xFC04C045)
-#define MCF_INTC1_ICR6             MCF_REG08(0xFC04C046)
-#define MCF_INTC1_ICR7             MCF_REG08(0xFC04C047)
-#define MCF_INTC1_ICR8             MCF_REG08(0xFC04C048)
-#define MCF_INTC1_ICR9             MCF_REG08(0xFC04C049)
-#define MCF_INTC1_ICR10            MCF_REG08(0xFC04C04A)
-#define MCF_INTC1_ICR11            MCF_REG08(0xFC04C04B)
-#define MCF_INTC1_ICR12            MCF_REG08(0xFC04C04C)
-#define MCF_INTC1_ICR13            MCF_REG08(0xFC04C04D)
-#define MCF_INTC1_ICR14            MCF_REG08(0xFC04C04E)
-#define MCF_INTC1_ICR15            MCF_REG08(0xFC04C04F)
-#define MCF_INTC1_ICR16            MCF_REG08(0xFC04C050)
-#define MCF_INTC1_ICR17            MCF_REG08(0xFC04C051)
-#define MCF_INTC1_ICR18            MCF_REG08(0xFC04C052)
-#define MCF_INTC1_ICR19            MCF_REG08(0xFC04C053)
-#define MCF_INTC1_ICR20            MCF_REG08(0xFC04C054)
-#define MCF_INTC1_ICR21            MCF_REG08(0xFC04C055)
-#define MCF_INTC1_ICR22            MCF_REG08(0xFC04C056)
-#define MCF_INTC1_ICR23            MCF_REG08(0xFC04C057)
-#define MCF_INTC1_ICR24            MCF_REG08(0xFC04C058)
-#define MCF_INTC1_ICR25            MCF_REG08(0xFC04C059)
-#define MCF_INTC1_ICR26            MCF_REG08(0xFC04C05A)
-#define MCF_INTC1_ICR27            MCF_REG08(0xFC04C05B)
-#define MCF_INTC1_ICR28            MCF_REG08(0xFC04C05C)
-#define MCF_INTC1_ICR29            MCF_REG08(0xFC04C05D)
-#define MCF_INTC1_ICR30            MCF_REG08(0xFC04C05E)
-#define MCF_INTC1_ICR31            MCF_REG08(0xFC04C05F)
-#define MCF_INTC1_ICR32            MCF_REG08(0xFC04C060)
-#define MCF_INTC1_ICR33            MCF_REG08(0xFC04C061)
-#define MCF_INTC1_ICR34            MCF_REG08(0xFC04C062)
-#define MCF_INTC1_ICR35            MCF_REG08(0xFC04C063)
-#define MCF_INTC1_ICR36            MCF_REG08(0xFC04C064)
-#define MCF_INTC1_ICR37            MCF_REG08(0xFC04C065)
-#define MCF_INTC1_ICR38            MCF_REG08(0xFC04C066)
-#define MCF_INTC1_ICR39            MCF_REG08(0xFC04C067)
-#define MCF_INTC1_ICR40            MCF_REG08(0xFC04C068)
-#define MCF_INTC1_ICR41            MCF_REG08(0xFC04C069)
-#define MCF_INTC1_ICR42            MCF_REG08(0xFC04C06A)
-#define MCF_INTC1_ICR43            MCF_REG08(0xFC04C06B)
-#define MCF_INTC1_ICR44            MCF_REG08(0xFC04C06C)
-#define MCF_INTC1_ICR45            MCF_REG08(0xFC04C06D)
-#define MCF_INTC1_ICR46            MCF_REG08(0xFC04C06E)
-#define MCF_INTC1_ICR47            MCF_REG08(0xFC04C06F)
-#define MCF_INTC1_ICR48            MCF_REG08(0xFC04C070)
-#define MCF_INTC1_ICR49            MCF_REG08(0xFC04C071)
-#define MCF_INTC1_ICR50            MCF_REG08(0xFC04C072)
-#define MCF_INTC1_ICR51            MCF_REG08(0xFC04C073)
-#define MCF_INTC1_ICR52            MCF_REG08(0xFC04C074)
-#define MCF_INTC1_ICR53            MCF_REG08(0xFC04C075)
-#define MCF_INTC1_ICR54            MCF_REG08(0xFC04C076)
-#define MCF_INTC1_ICR55            MCF_REG08(0xFC04C077)
-#define MCF_INTC1_ICR56            MCF_REG08(0xFC04C078)
-#define MCF_INTC1_ICR57            MCF_REG08(0xFC04C079)
-#define MCF_INTC1_ICR58            MCF_REG08(0xFC04C07A)
-#define MCF_INTC1_ICR59            MCF_REG08(0xFC04C07B)
-#define MCF_INTC1_ICR60            MCF_REG08(0xFC04C07C)
-#define MCF_INTC1_ICR61            MCF_REG08(0xFC04C07D)
-#define MCF_INTC1_ICR62            MCF_REG08(0xFC04C07E)
-#define MCF_INTC1_ICR63            MCF_REG08(0xFC04C07F)
-#define MCF_INTC1_ICR(x)           MCF_REG08(0xFC04C040+((x)*0x001))
-#define MCF_INTC1_SWIACK           MCF_REG08(0xFC04C0E0)
-#define MCF_INTC1_L1IACK           MCF_REG08(0xFC04C0E4)
-#define MCF_INTC1_L2IACK           MCF_REG08(0xFC04C0E8)
-#define MCF_INTC1_L3IACK           MCF_REG08(0xFC04C0EC)
-#define MCF_INTC1_L4IACK           MCF_REG08(0xFC04C0F0)
-#define MCF_INTC1_L5IACK           MCF_REG08(0xFC04C0F4)
-#define MCF_INTC1_L6IACK           MCF_REG08(0xFC04C0F8)
-#define MCF_INTC1_L7IACK           MCF_REG08(0xFC04C0FC)
-#define MCF_INTC1_LIACK(x)         MCF_REG08(0xFC04C0E4+((x)*0x004))
-#define MCF_INTC_IPRH(x)           MCF_REG32(0xFC048000+((x)*0x4000))
-#define MCF_INTC_IPRL(x)           MCF_REG32(0xFC048004+((x)*0x4000))
-#define MCF_INTC_IMRH(x)           MCF_REG32(0xFC048008+((x)*0x4000))
-#define MCF_INTC_IMRL(x)           MCF_REG32(0xFC04800C+((x)*0x4000))
-#define MCF_INTC_INTFRCH(x)        MCF_REG32(0xFC048010+((x)*0x4000))
-#define MCF_INTC_INTFRCL(x)        MCF_REG32(0xFC048014+((x)*0x4000))
-#define MCF_INTC_ICONFIG(x)        MCF_REG16(0xFC04801A+((x)*0x4000))
-#define MCF_INTC_SIMR(x)           MCF_REG08(0xFC04801C+((x)*0x4000))
-#define MCF_INTC_CIMR(x)           MCF_REG08(0xFC04801D+((x)*0x4000))
-#define MCF_INTC_CLMASK(x)         MCF_REG08(0xFC04801E+((x)*0x4000))
-#define MCF_INTC_SLMASK(x)         MCF_REG08(0xFC04801F+((x)*0x4000))
-#define MCF_INTC_ICR0(x)           MCF_REG08(0xFC048040+((x)*0x4000))
-#define MCF_INTC_ICR1(x)           MCF_REG08(0xFC048041+((x)*0x4000))
-#define MCF_INTC_ICR2(x)           MCF_REG08(0xFC048042+((x)*0x4000))
-#define MCF_INTC_ICR3(x)           MCF_REG08(0xFC048043+((x)*0x4000))
-#define MCF_INTC_ICR4(x)           MCF_REG08(0xFC048044+((x)*0x4000))
-#define MCF_INTC_ICR5(x)           MCF_REG08(0xFC048045+((x)*0x4000))
-#define MCF_INTC_ICR6(x)           MCF_REG08(0xFC048046+((x)*0x4000))
-#define MCF_INTC_ICR7(x)           MCF_REG08(0xFC048047+((x)*0x4000))
-#define MCF_INTC_ICR8(x)           MCF_REG08(0xFC048048+((x)*0x4000))
-#define MCF_INTC_ICR9(x)           MCF_REG08(0xFC048049+((x)*0x4000))
-#define MCF_INTC_ICR10(x)          MCF_REG08(0xFC04804A+((x)*0x4000))
-#define MCF_INTC_ICR11(x)          MCF_REG08(0xFC04804B+((x)*0x4000))
-#define MCF_INTC_ICR12(x)          MCF_REG08(0xFC04804C+((x)*0x4000))
-#define MCF_INTC_ICR13(x)          MCF_REG08(0xFC04804D+((x)*0x4000))
-#define MCF_INTC_ICR14(x)          MCF_REG08(0xFC04804E+((x)*0x4000))
-#define MCF_INTC_ICR15(x)          MCF_REG08(0xFC04804F+((x)*0x4000))
-#define MCF_INTC_ICR16(x)          MCF_REG08(0xFC048050+((x)*0x4000))
-#define MCF_INTC_ICR17(x)          MCF_REG08(0xFC048051+((x)*0x4000))
-#define MCF_INTC_ICR18(x)          MCF_REG08(0xFC048052+((x)*0x4000))
-#define MCF_INTC_ICR19(x)          MCF_REG08(0xFC048053+((x)*0x4000))
-#define MCF_INTC_ICR20(x)          MCF_REG08(0xFC048054+((x)*0x4000))
-#define MCF_INTC_ICR21(x)          MCF_REG08(0xFC048055+((x)*0x4000))
-#define MCF_INTC_ICR22(x)          MCF_REG08(0xFC048056+((x)*0x4000))
-#define MCF_INTC_ICR23(x)          MCF_REG08(0xFC048057+((x)*0x4000))
-#define MCF_INTC_ICR24(x)          MCF_REG08(0xFC048058+((x)*0x4000))
-#define MCF_INTC_ICR25(x)          MCF_REG08(0xFC048059+((x)*0x4000))
-#define MCF_INTC_ICR26(x)          MCF_REG08(0xFC04805A+((x)*0x4000))
-#define MCF_INTC_ICR27(x)          MCF_REG08(0xFC04805B+((x)*0x4000))
-#define MCF_INTC_ICR28(x)          MCF_REG08(0xFC04805C+((x)*0x4000))
-#define MCF_INTC_ICR29(x)          MCF_REG08(0xFC04805D+((x)*0x4000))
-#define MCF_INTC_ICR30(x)          MCF_REG08(0xFC04805E+((x)*0x4000))
-#define MCF_INTC_ICR31(x)          MCF_REG08(0xFC04805F+((x)*0x4000))
-#define MCF_INTC_ICR32(x)          MCF_REG08(0xFC048060+((x)*0x4000))
-#define MCF_INTC_ICR33(x)          MCF_REG08(0xFC048061+((x)*0x4000))
-#define MCF_INTC_ICR34(x)          MCF_REG08(0xFC048062+((x)*0x4000))
-#define MCF_INTC_ICR35(x)          MCF_REG08(0xFC048063+((x)*0x4000))
-#define MCF_INTC_ICR36(x)          MCF_REG08(0xFC048064+((x)*0x4000))
-#define MCF_INTC_ICR37(x)          MCF_REG08(0xFC048065+((x)*0x4000))
-#define MCF_INTC_ICR38(x)          MCF_REG08(0xFC048066+((x)*0x4000))
-#define MCF_INTC_ICR39(x)          MCF_REG08(0xFC048067+((x)*0x4000))
-#define MCF_INTC_ICR40(x)          MCF_REG08(0xFC048068+((x)*0x4000))
-#define MCF_INTC_ICR41(x)          MCF_REG08(0xFC048069+((x)*0x4000))
-#define MCF_INTC_ICR42(x)          MCF_REG08(0xFC04806A+((x)*0x4000))
-#define MCF_INTC_ICR43(x)          MCF_REG08(0xFC04806B+((x)*0x4000))
-#define MCF_INTC_ICR44(x)          MCF_REG08(0xFC04806C+((x)*0x4000))
-#define MCF_INTC_ICR45(x)          MCF_REG08(0xFC04806D+((x)*0x4000))
-#define MCF_INTC_ICR46(x)          MCF_REG08(0xFC04806E+((x)*0x4000))
-#define MCF_INTC_ICR47(x)          MCF_REG08(0xFC04806F+((x)*0x4000))
-#define MCF_INTC_ICR48(x)          MCF_REG08(0xFC048070+((x)*0x4000))
-#define MCF_INTC_ICR49(x)          MCF_REG08(0xFC048071+((x)*0x4000))
-#define MCF_INTC_ICR50(x)          MCF_REG08(0xFC048072+((x)*0x4000))
-#define MCF_INTC_ICR51(x)          MCF_REG08(0xFC048073+((x)*0x4000))
-#define MCF_INTC_ICR52(x)          MCF_REG08(0xFC048074+((x)*0x4000))
-#define MCF_INTC_ICR53(x)          MCF_REG08(0xFC048075+((x)*0x4000))
-#define MCF_INTC_ICR54(x)          MCF_REG08(0xFC048076+((x)*0x4000))
-#define MCF_INTC_ICR55(x)          MCF_REG08(0xFC048077+((x)*0x4000))
-#define MCF_INTC_ICR56(x)          MCF_REG08(0xFC048078+((x)*0x4000))
-#define MCF_INTC_ICR57(x)          MCF_REG08(0xFC048079+((x)*0x4000))
-#define MCF_INTC_ICR58(x)          MCF_REG08(0xFC04807A+((x)*0x4000))
-#define MCF_INTC_ICR59(x)          MCF_REG08(0xFC04807B+((x)*0x4000))
-#define MCF_INTC_ICR60(x)          MCF_REG08(0xFC04807C+((x)*0x4000))
-#define MCF_INTC_ICR61(x)          MCF_REG08(0xFC04807D+((x)*0x4000))
-#define MCF_INTC_ICR62(x)          MCF_REG08(0xFC04807E+((x)*0x4000))
-#define MCF_INTC_ICR63(x)          MCF_REG08(0xFC04807F+((x)*0x4000))
-#define MCF_INTC_SWIACK(x)         MCF_REG08(0xFC0480E0+((x)*0x4000))
-#define MCF_INTC_L1IACK(x)         MCF_REG08(0xFC0480E4+((x)*0x4000))
-#define MCF_INTC_L2IACK(x)         MCF_REG08(0xFC0480E8+((x)*0x4000))
-#define MCF_INTC_L3IACK(x)         MCF_REG08(0xFC0480EC+((x)*0x4000))
-#define MCF_INTC_L4IACK(x)         MCF_REG08(0xFC0480F0+((x)*0x4000))
-#define MCF_INTC_L5IACK(x)         MCF_REG08(0xFC0480F4+((x)*0x4000))
-#define MCF_INTC_L6IACK(x)         MCF_REG08(0xFC0480F8+((x)*0x4000))
-#define MCF_INTC_L7IACK(x)         MCF_REG08(0xFC0480FC+((x)*0x4000))
-
-/* Bit definitions and macros for MCF_INTC_IPRH */
-#define MCF_INTC_IPRH_INT32        (0x00000001)
-#define MCF_INTC_IPRH_INT33        (0x00000002)
-#define MCF_INTC_IPRH_INT34        (0x00000004)
-#define MCF_INTC_IPRH_INT35        (0x00000008)
-#define MCF_INTC_IPRH_INT36        (0x00000010)
-#define MCF_INTC_IPRH_INT37        (0x00000020)
-#define MCF_INTC_IPRH_INT38        (0x00000040)
-#define MCF_INTC_IPRH_INT39        (0x00000080)
-#define MCF_INTC_IPRH_INT40        (0x00000100)
-#define MCF_INTC_IPRH_INT41        (0x00000200)
-#define MCF_INTC_IPRH_INT42        (0x00000400)
-#define MCF_INTC_IPRH_INT43        (0x00000800)
-#define MCF_INTC_IPRH_INT44        (0x00001000)
-#define MCF_INTC_IPRH_INT45        (0x00002000)
-#define MCF_INTC_IPRH_INT46        (0x00004000)
-#define MCF_INTC_IPRH_INT47        (0x00008000)
-#define MCF_INTC_IPRH_INT48        (0x00010000)
-#define MCF_INTC_IPRH_INT49        (0x00020000)
-#define MCF_INTC_IPRH_INT50        (0x00040000)
-#define MCF_INTC_IPRH_INT51        (0x00080000)
-#define MCF_INTC_IPRH_INT52        (0x00100000)
-#define MCF_INTC_IPRH_INT53        (0x00200000)
-#define MCF_INTC_IPRH_INT54        (0x00400000)
-#define MCF_INTC_IPRH_INT55        (0x00800000)
-#define MCF_INTC_IPRH_INT56        (0x01000000)
-#define MCF_INTC_IPRH_INT57        (0x02000000)
-#define MCF_INTC_IPRH_INT58        (0x04000000)
-#define MCF_INTC_IPRH_INT59        (0x08000000)
-#define MCF_INTC_IPRH_INT60        (0x10000000)
-#define MCF_INTC_IPRH_INT61        (0x20000000)
-#define MCF_INTC_IPRH_INT62        (0x40000000)
-#define MCF_INTC_IPRH_INT63        (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_IPRL */
-#define MCF_INTC_IPRL_INT0         (0x00000001)
-#define MCF_INTC_IPRL_INT1         (0x00000002)
-#define MCF_INTC_IPRL_INT2         (0x00000004)
-#define MCF_INTC_IPRL_INT3         (0x00000008)
-#define MCF_INTC_IPRL_INT4         (0x00000010)
-#define MCF_INTC_IPRL_INT5         (0x00000020)
-#define MCF_INTC_IPRL_INT6         (0x00000040)
-#define MCF_INTC_IPRL_INT7         (0x00000080)
-#define MCF_INTC_IPRL_INT8         (0x00000100)
-#define MCF_INTC_IPRL_INT9         (0x00000200)
-#define MCF_INTC_IPRL_INT10        (0x00000400)
-#define MCF_INTC_IPRL_INT11        (0x00000800)
-#define MCF_INTC_IPRL_INT12        (0x00001000)
-#define MCF_INTC_IPRL_INT13        (0x00002000)
-#define MCF_INTC_IPRL_INT14        (0x00004000)
-#define MCF_INTC_IPRL_INT15        (0x00008000)
-#define MCF_INTC_IPRL_INT16        (0x00010000)
-#define MCF_INTC_IPRL_INT17        (0x00020000)
-#define MCF_INTC_IPRL_INT18        (0x00040000)
-#define MCF_INTC_IPRL_INT19        (0x00080000)
-#define MCF_INTC_IPRL_INT20        (0x00100000)
-#define MCF_INTC_IPRL_INT21        (0x00200000)
-#define MCF_INTC_IPRL_INT22        (0x00400000)
-#define MCF_INTC_IPRL_INT23        (0x00800000)
-#define MCF_INTC_IPRL_INT24        (0x01000000)
-#define MCF_INTC_IPRL_INT25        (0x02000000)
-#define MCF_INTC_IPRL_INT26        (0x04000000)
-#define MCF_INTC_IPRL_INT27        (0x08000000)
-#define MCF_INTC_IPRL_INT28        (0x10000000)
-#define MCF_INTC_IPRL_INT29        (0x20000000)
-#define MCF_INTC_IPRL_INT30        (0x40000000)
-#define MCF_INTC_IPRL_INT31        (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_IMRH */
-#define MCF_INTC_IMRH_INT_MASK32   (0x00000001)
-#define MCF_INTC_IMRH_INT_MASK33   (0x00000002)
-#define MCF_INTC_IMRH_INT_MASK34   (0x00000004)
-#define MCF_INTC_IMRH_INT_MASK35   (0x00000008)
-#define MCF_INTC_IMRH_INT_MASK36   (0x00000010)
-#define MCF_INTC_IMRH_INT_MASK37   (0x00000020)
-#define MCF_INTC_IMRH_INT_MASK38   (0x00000040)
-#define MCF_INTC_IMRH_INT_MASK39   (0x00000080)
-#define MCF_INTC_IMRH_INT_MASK40   (0x00000100)
-#define MCF_INTC_IMRH_INT_MASK41   (0x00000200)
-#define MCF_INTC_IMRH_INT_MASK42   (0x00000400)
-#define MCF_INTC_IMRH_INT_MASK43   (0x00000800)
-#define MCF_INTC_IMRH_INT_MASK44   (0x00001000)
-#define MCF_INTC_IMRH_INT_MASK45   (0x00002000)
-#define MCF_INTC_IMRH_INT_MASK46   (0x00004000)
-#define MCF_INTC_IMRH_INT_MASK47   (0x00008000)
-#define MCF_INTC_IMRH_INT_MASK48   (0x00010000)
-#define MCF_INTC_IMRH_INT_MASK49   (0x00020000)
-#define MCF_INTC_IMRH_INT_MASK50   (0x00040000)
-#define MCF_INTC_IMRH_INT_MASK51   (0x00080000)
-#define MCF_INTC_IMRH_INT_MASK52   (0x00100000)
-#define MCF_INTC_IMRH_INT_MASK53   (0x00200000)
-#define MCF_INTC_IMRH_INT_MASK54   (0x00400000)
-#define MCF_INTC_IMRH_INT_MASK55   (0x00800000)
-#define MCF_INTC_IMRH_INT_MASK56   (0x01000000)
-#define MCF_INTC_IMRH_INT_MASK57   (0x02000000)
-#define MCF_INTC_IMRH_INT_MASK58   (0x04000000)
-#define MCF_INTC_IMRH_INT_MASK59   (0x08000000)
-#define MCF_INTC_IMRH_INT_MASK60   (0x10000000)
-#define MCF_INTC_IMRH_INT_MASK61   (0x20000000)
-#define MCF_INTC_IMRH_INT_MASK62   (0x40000000)
-#define MCF_INTC_IMRH_INT_MASK63   (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_IMRL */
-#define MCF_INTC_IMRL_INT_MASK0    (0x00000001)
-#define MCF_INTC_IMRL_INT_MASK1    (0x00000002)
-#define MCF_INTC_IMRL_INT_MASK2    (0x00000004)
-#define MCF_INTC_IMRL_INT_MASK3    (0x00000008)
-#define MCF_INTC_IMRL_INT_MASK4    (0x00000010)
-#define MCF_INTC_IMRL_INT_MASK5    (0x00000020)
-#define MCF_INTC_IMRL_INT_MASK6    (0x00000040)
-#define MCF_INTC_IMRL_INT_MASK7    (0x00000080)
-#define MCF_INTC_IMRL_INT_MASK8    (0x00000100)
-#define MCF_INTC_IMRL_INT_MASK9    (0x00000200)
-#define MCF_INTC_IMRL_INT_MASK10   (0x00000400)
-#define MCF_INTC_IMRL_INT_MASK11   (0x00000800)
-#define MCF_INTC_IMRL_INT_MASK12   (0x00001000)
-#define MCF_INTC_IMRL_INT_MASK13   (0x00002000)
-#define MCF_INTC_IMRL_INT_MASK14   (0x00004000)
-#define MCF_INTC_IMRL_INT_MASK15   (0x00008000)
-#define MCF_INTC_IMRL_INT_MASK16   (0x00010000)
-#define MCF_INTC_IMRL_INT_MASK17   (0x00020000)
-#define MCF_INTC_IMRL_INT_MASK18   (0x00040000)
-#define MCF_INTC_IMRL_INT_MASK19   (0x00080000)
-#define MCF_INTC_IMRL_INT_MASK20   (0x00100000)
-#define MCF_INTC_IMRL_INT_MASK21   (0x00200000)
-#define MCF_INTC_IMRL_INT_MASK22   (0x00400000)
-#define MCF_INTC_IMRL_INT_MASK23   (0x00800000)
-#define MCF_INTC_IMRL_INT_MASK24   (0x01000000)
-#define MCF_INTC_IMRL_INT_MASK25   (0x02000000)
-#define MCF_INTC_IMRL_INT_MASK26   (0x04000000)
-#define MCF_INTC_IMRL_INT_MASK27   (0x08000000)
-#define MCF_INTC_IMRL_INT_MASK28   (0x10000000)
-#define MCF_INTC_IMRL_INT_MASK29   (0x20000000)
-#define MCF_INTC_IMRL_INT_MASK30   (0x40000000)
-#define MCF_INTC_IMRL_INT_MASK31   (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_INTFRCH */
-#define MCF_INTC_INTFRCH_INTFRC32  (0x00000001)
-#define MCF_INTC_INTFRCH_INTFRC33  (0x00000002)
-#define MCF_INTC_INTFRCH_INTFRC34  (0x00000004)
-#define MCF_INTC_INTFRCH_INTFRC35  (0x00000008)
-#define MCF_INTC_INTFRCH_INTFRC36  (0x00000010)
-#define MCF_INTC_INTFRCH_INTFRC37  (0x00000020)
-#define MCF_INTC_INTFRCH_INTFRC38  (0x00000040)
-#define MCF_INTC_INTFRCH_INTFRC39  (0x00000080)
-#define MCF_INTC_INTFRCH_INTFRC40  (0x00000100)
-#define MCF_INTC_INTFRCH_INTFRC41  (0x00000200)
-#define MCF_INTC_INTFRCH_INTFRC42  (0x00000400)
-#define MCF_INTC_INTFRCH_INTFRC43  (0x00000800)
-#define MCF_INTC_INTFRCH_INTFRC44  (0x00001000)
-#define MCF_INTC_INTFRCH_INTFRC45  (0x00002000)
-#define MCF_INTC_INTFRCH_INTFRC46  (0x00004000)
-#define MCF_INTC_INTFRCH_INTFRC47  (0x00008000)
-#define MCF_INTC_INTFRCH_INTFRC48  (0x00010000)
-#define MCF_INTC_INTFRCH_INTFRC49  (0x00020000)
-#define MCF_INTC_INTFRCH_INTFRC50  (0x00040000)
-#define MCF_INTC_INTFRCH_INTFRC51  (0x00080000)
-#define MCF_INTC_INTFRCH_INTFRC52  (0x00100000)
-#define MCF_INTC_INTFRCH_INTFRC53  (0x00200000)
-#define MCF_INTC_INTFRCH_INTFRC54  (0x00400000)
-#define MCF_INTC_INTFRCH_INTFRC55  (0x00800000)
-#define MCF_INTC_INTFRCH_INTFRC56  (0x01000000)
-#define MCF_INTC_INTFRCH_INTFRC57  (0x02000000)
-#define MCF_INTC_INTFRCH_INTFRC58  (0x04000000)
-#define MCF_INTC_INTFRCH_INTFRC59  (0x08000000)
-#define MCF_INTC_INTFRCH_INTFRC60  (0x10000000)
-#define MCF_INTC_INTFRCH_INTFRC61  (0x20000000)
-#define MCF_INTC_INTFRCH_INTFRC62  (0x40000000)
-#define MCF_INTC_INTFRCH_INTFRC63  (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_INTFRCL */
-#define MCF_INTC_INTFRCL_INTFRC0   (0x00000001)
-#define MCF_INTC_INTFRCL_INTFRC1   (0x00000002)
-#define MCF_INTC_INTFRCL_INTFRC2   (0x00000004)
-#define MCF_INTC_INTFRCL_INTFRC3   (0x00000008)
-#define MCF_INTC_INTFRCL_INTFRC4   (0x00000010)
-#define MCF_INTC_INTFRCL_INTFRC5   (0x00000020)
-#define MCF_INTC_INTFRCL_INTFRC6   (0x00000040)
-#define MCF_INTC_INTFRCL_INTFRC7   (0x00000080)
-#define MCF_INTC_INTFRCL_INTFRC8   (0x00000100)
-#define MCF_INTC_INTFRCL_INTFRC9   (0x00000200)
-#define MCF_INTC_INTFRCL_INTFRC10  (0x00000400)
-#define MCF_INTC_INTFRCL_INTFRC11  (0x00000800)
-#define MCF_INTC_INTFRCL_INTFRC12  (0x00001000)
-#define MCF_INTC_INTFRCL_INTFRC13  (0x00002000)
-#define MCF_INTC_INTFRCL_INTFRC14  (0x00004000)
-#define MCF_INTC_INTFRCL_INTFRC15  (0x00008000)
-#define MCF_INTC_INTFRCL_INTFRC16  (0x00010000)
-#define MCF_INTC_INTFRCL_INTFRC17  (0x00020000)
-#define MCF_INTC_INTFRCL_INTFRC18  (0x00040000)
-#define MCF_INTC_INTFRCL_INTFRC19  (0x00080000)
-#define MCF_INTC_INTFRCL_INTFRC20  (0x00100000)
-#define MCF_INTC_INTFRCL_INTFRC21  (0x00200000)
-#define MCF_INTC_INTFRCL_INTFRC22  (0x00400000)
-#define MCF_INTC_INTFRCL_INTFRC23  (0x00800000)
-#define MCF_INTC_INTFRCL_INTFRC24  (0x01000000)
-#define MCF_INTC_INTFRCL_INTFRC25  (0x02000000)
-#define MCF_INTC_INTFRCL_INTFRC26  (0x04000000)
-#define MCF_INTC_INTFRCL_INTFRC27  (0x08000000)
-#define MCF_INTC_INTFRCL_INTFRC28  (0x10000000)
-#define MCF_INTC_INTFRCL_INTFRC29  (0x20000000)
-#define MCF_INTC_INTFRCL_INTFRC30  (0x40000000)
-#define MCF_INTC_INTFRCL_INTFRC31  (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_ICONFIG */
-#define MCF_INTC_ICONFIG_EMASK     (0x0020)
-#define MCF_INTC_ICONFIG_ELVLPRI1  (0x0200)
-#define MCF_INTC_ICONFIG_ELVLPRI2  (0x0400)
-#define MCF_INTC_ICONFIG_ELVLPRI3  (0x0800)
-#define MCF_INTC_ICONFIG_ELVLPRI4  (0x1000)
-#define MCF_INTC_ICONFIG_ELVLPRI5  (0x2000)
-#define MCF_INTC_ICONFIG_ELVLPRI6  (0x4000)
-#define MCF_INTC_ICONFIG_ELVLPRI7  (0x8000)
-
-/* Bit definitions and macros for MCF_INTC_SIMR */
-#define MCF_INTC_SIMR_SIMR(x)      (((x)&0x7F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_CIMR */
-#define MCF_INTC_CIMR_CIMR(x)      (((x)&0x7F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_CLMASK */
-#define MCF_INTC_CLMASK_CLMASK(x)  (((x)&0x0F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_SLMASK */
-#define MCF_INTC_SLMASK_SLMASK(x)  (((x)&0x0F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_ICR */
-#define MCF_INTC_ICR_IL(x)         (((x)&0x07)<<0)
-
-/* Bit definitions and macros for MCF_INTC_SWIACK */
-#define MCF_INTC_SWIACK_VECTOR(x)  (((x)&0xFF)<<0)
-
-/* Bit definitions and macros for MCF_INTC_LIACK */
-#define MCF_INTC_LIACK_VECTOR(x)   (((x)&0xFF)<<0)
-
-/********************************************************************/
-/*********************************************************************
-*
-* LCD Controller (LCDC)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_LCDC_LSSAR                  MCF_REG32(0xFC0AC000)
-#define MCF_LCDC_LSR                    MCF_REG32(0xFC0AC004)
-#define MCF_LCDC_LVPWR                  MCF_REG32(0xFC0AC008)
-#define MCF_LCDC_LCPR                   MCF_REG32(0xFC0AC00C)
-#define MCF_LCDC_LCWHBR                 MCF_REG32(0xFC0AC010)
-#define MCF_LCDC_LCCMR                  MCF_REG32(0xFC0AC014)
-#define MCF_LCDC_LPCR                   MCF_REG32(0xFC0AC018)
-#define MCF_LCDC_LHCR                   MCF_REG32(0xFC0AC01C)
-#define MCF_LCDC_LVCR                   MCF_REG32(0xFC0AC020)
-#define MCF_LCDC_LPOR                   MCF_REG32(0xFC0AC024)
-#define MCF_LCDC_LSCR                   MCF_REG32(0xFC0AC028)
-#define MCF_LCDC_LPCCR                  MCF_REG32(0xFC0AC02C)
-#define MCF_LCDC_LDCR                   MCF_REG32(0xFC0AC030)
-#define MCF_LCDC_LRMCR                  MCF_REG32(0xFC0AC034)
-#define MCF_LCDC_LICR                   MCF_REG32(0xFC0AC038)
-#define MCF_LCDC_LIER                   MCF_REG32(0xFC0AC03C)
-#define MCF_LCDC_LISR                   MCF_REG32(0xFC0AC040)
-#define MCF_LCDC_LGWSAR                 MCF_REG32(0xFC0AC050)
-#define MCF_LCDC_LGWSR                  MCF_REG32(0xFC0AC054)
-#define MCF_LCDC_LGWVPWR                MCF_REG32(0xFC0AC058)
-#define MCF_LCDC_LGWPOR                 MCF_REG32(0xFC0AC05C)
-#define MCF_LCDC_LGWPR                  MCF_REG32(0xFC0AC060)
-#define MCF_LCDC_LGWCR                  MCF_REG32(0xFC0AC064)
-#define MCF_LCDC_LGWDCR                 MCF_REG32(0xFC0AC068)
-#define MCF_LCDC_BPLUT_BASE             MCF_REG32(0xFC0AC800)
-#define MCF_LCDC_GWLUT_BASE             MCF_REG32(0xFC0ACC00)
-
-/* Bit definitions and macros for MCF_LCDC_LSSAR */
-#define MCF_LCDC_LSSAR_SSA(x)           (((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for MCF_LCDC_LSR */
-#define MCF_LCDC_LSR_YMAX(x)            (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LSR_XMAX(x)            (((x)&0x0000003F)<<20)
-
-/* Bit definitions and macros for MCF_LCDC_LVPWR */
-#define MCF_LCDC_LVPWR_VPW(x)           (((x)&0x000003FF)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LCPR */
-#define MCF_LCDC_LCPR_CYP(x)            (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LCPR_CXP(x)            (((x)&0x000003FF)<<16)
-#define MCF_LCDC_LCPR_OP                (0x10000000)
-#define MCF_LCDC_LCPR_CC(x)             (((x)&0x00000003)<<30)
-#define MCF_LCDC_LCPR_CC_TRANSPARENT    (0x00000000)
-#define MCF_LCDC_LCPR_CC_OR             (0x40000000)
-#define MCF_LCDC_LCPR_CC_XOR            (0x80000000)
-#define MCF_LCDC_LCPR_CC_AND            (0xC0000000)
-#define MCF_LCDC_LCPR_OP_ON             (0x10000000)
-#define MCF_LCDC_LCPR_OP_OFF            (0x00000000)
-
-/* Bit definitions and macros for MCF_LCDC_LCWHBR */
-#define MCF_LCDC_LCWHBR_BD(x)           (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LCWHBR_CH(x)           (((x)&0x0000001F)<<16)
-#define MCF_LCDC_LCWHBR_CW(x)           (((x)&0x0000001F)<<24)
-#define MCF_LCDC_LCWHBR_BK_EN           (0x80000000)
-#define MCF_LCDC_LCWHBR_BK_EN_ON        (0x80000000)
-#define MCF_LCDC_LCWHBR_BK_EN_OFF       (0x00000000)
-
-/* Bit definitions and macros for MCF_LCDC_LCCMR */
-#define MCF_LCDC_LCCMR_CUR_COL_B(x)     (((x)&0x0000003F)<<0)
-#define MCF_LCDC_LCCMR_CUR_COL_G(x)     (((x)&0x0000003F)<<6)
-#define MCF_LCDC_LCCMR_CUR_COL_R(x)     (((x)&0x0000003F)<<12)
-
-/* Bit definitions and macros for MCF_LCDC_LPCR */
-#define MCF_LCDC_LPCR_PCD(x)            (((x)&0x0000003F)<<0)
-#define MCF_LCDC_LPCR_SHARP             (0x00000040)
-#define MCF_LCDC_LPCR_SCLKSEL           (0x00000080)
-#define MCF_LCDC_LPCR_ACD(x)            (((x)&0x0000007F)<<8)
-#define MCF_LCDC_LPCR_ACDSEL            (0x00008000)
-#define MCF_LCDC_LPCR_REV_VS            (0x00010000)
-#define MCF_LCDC_LPCR_SWAP_SEL          (0x00020000)
-#define MCF_LCDC_LPCR_ENDSEL            (0x00040000)
-#define MCF_LCDC_LPCR_SCLKIDLE          (0x00080000)
-#define MCF_LCDC_LPCR_OEPOL             (0x00100000)
-#define MCF_LCDC_LPCR_CLKPOL            (0x00200000)
-#define MCF_LCDC_LPCR_LPPOL             (0x00400000)
-#define MCF_LCDC_LPCR_FLM               (0x00800000)
-#define MCF_LCDC_LPCR_PIXPOL            (0x01000000)
-#define MCF_LCDC_LPCR_BPIX(x)           (((x)&0x00000007)<<25)
-#define MCF_LCDC_LPCR_PBSIZ(x)          (((x)&0x00000003)<<28)
-#define MCF_LCDC_LPCR_COLOR             (0x40000000)
-#define MCF_LCDC_LPCR_TFT               (0x80000000)
-#define MCF_LCDC_LPCR_MODE_MONOCGROME   (0x00000000)
-#define MCF_LCDC_LPCR_MODE_CSTN         (0x40000000)
-#define MCF_LCDC_LPCR_MODE_TFT          (0xC0000000)
-#define MCF_LCDC_LPCR_PBSIZ_1           (0x00000000)
-#define MCF_LCDC_LPCR_PBSIZ_2           (0x10000000)
-#define MCF_LCDC_LPCR_PBSIZ_4           (0x20000000)
-#define MCF_LCDC_LPCR_PBSIZ_8           (0x30000000)
-#define MCF_LCDC_LPCR_BPIX_1bpp         (0x00000000)
-#define MCF_LCDC_LPCR_BPIX_2bpp         (0x02000000)
-#define MCF_LCDC_LPCR_BPIX_4bpp         (0x04000000)
-#define MCF_LCDC_LPCR_BPIX_8bpp         (0x06000000)
-#define MCF_LCDC_LPCR_BPIX_12bpp        (0x08000000)
-#define MCF_LCDC_LPCR_BPIX_16bpp        (0x0A000000)
-#define MCF_LCDC_LPCR_BPIX_18bpp        (0x0C000000)
-
-#define MCF_LCDC_LPCR_PANEL_TYPE(x)     (((x)&0x00000003)<<30) 
-
-/* Bit definitions and macros for MCF_LCDC_LHCR */
-#define MCF_LCDC_LHCR_H_WAIT_2(x)       (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LHCR_H_WAIT_1(x)       (((x)&0x000000FF)<<8)
-#define MCF_LCDC_LHCR_H_WIDTH(x)        (((x)&0x0000003F)<<26)
-
-/* Bit definitions and macros for MCF_LCDC_LVCR */
-#define MCF_LCDC_LVCR_V_WAIT_2(x)       (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LVCR_V_WAIT_1(x)       (((x)&0x000000FF)<<8)
-#define MCF_LCDC_LVCR_V_WIDTH(x)      (((x)&0x0000003F)<<26)
-
-/* Bit definitions and macros for MCF_LCDC_LPOR */
-#define MCF_LCDC_LPOR_POS(x)            (((x)&0x0000001F)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LPCCR */
-#define MCF_LCDC_LPCCR_PW(x)            (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LPCCR_CC_EN            (0x00000100)
-#define MCF_LCDC_LPCCR_SCR(x)           (((x)&0x00000003)<<9)
-#define MCF_LCDC_LPCCR_LDMSK            (0x00008000)
-#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x)  (((x)&0x000001FF)<<16)
-#define MCF_LCDC_LPCCR_SCR_LINEPULSE    (0x00000000)
-#define MCF_LCDC_LPCCR_SCR_PIXELCLK     (0x00002000)
-#define MCF_LCDC_LPCCR_SCR_LCDCLOCK     (0x00004000)
-
-/* Bit definitions and macros for MCF_LCDC_LDCR */
-#define MCF_LCDC_LDCR_TM(x)             (((x)&0x0000001F)<<0)
-#define MCF_LCDC_LDCR_HM(x)             (((x)&0x0000001F)<<16)
-#define MCF_LCDC_LDCR_BURST             (0x80000000)
-
-/* Bit definitions and macros for MCF_LCDC_LRMCR */
-#define MCF_LCDC_LRMCR_SEL_REF          (0x00000001)
-
-/* Bit definitions and macros for MCF_LCDC_LICR */
-#define MCF_LCDC_LICR_INTCON            (0x00000001)
-#define MCF_LCDC_LICR_INTSYN            (0x00000004)
-#define MCF_LCDC_LICR_GW_INT_CON        (0x00000010)
-
-/* Bit definitions and macros for MCF_LCDC_LIER */
-#define MCF_LCDC_LIER_BOF_EN            (0x00000001)
-#define MCF_LCDC_LIER_EOF_EN            (0x00000002)
-#define MCF_LCDC_LIER_ERR_RES_EN        (0x00000004)
-#define MCF_LCDC_LIER_UDR_ERR_EN        (0x00000008)
-#define MCF_LCDC_LIER_GW_BOF_EN         (0x00000010)
-#define MCF_LCDC_LIER_GW_EOF_EN         (0x00000020)
-#define MCF_LCDC_LIER_GW_ERR_RES_EN     (0x00000040)
-#define MCF_LCDC_LIER_GW_UDR_ERR_EN     (0x00000080)
-
-/* Bit definitions and macros for MCF_LCDC_LISR */
-#define MCF_LCDC_LISR_BOF               (0x00000001)
-#define MCF_LCDC_LISR_EOF               (0x00000002)
-#define MCF_LCDC_LISR_ERR_RES           (0x00000004)
-#define MCF_LCDC_LISR_UDR_ERR           (0x00000008)
-#define MCF_LCDC_LISR_GW_BOF            (0x00000010)
-#define MCF_LCDC_LISR_GW_EOF            (0x00000020)
-#define MCF_LCDC_LISR_GW_ERR_RES        (0x00000040)
-#define MCF_LCDC_LISR_GW_UDR_ERR        (0x00000080)
-
-/* Bit definitions and macros for MCF_LCDC_LGWSAR */
-#define MCF_LCDC_LGWSAR_GWSA(x)         (((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for MCF_LCDC_LGWSR */
-#define MCF_LCDC_LGWSR_GWH(x)           (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LGWSR_GWW(x)           (((x)&0x0000003F)<<20)
-
-/* Bit definitions and macros for MCF_LCDC_LGWVPWR */
-#define MCF_LCDC_LGWVPWR_GWVPW(x)       (((x)&0x000003FF)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LGWPOR */
-#define MCF_LCDC_LGWPOR_GWPO(x)         (((x)&0x0000001F)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LGWPR */
-#define MCF_LCDC_LGWPR_GWYP(x)          (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LGWPR_GWXP(x)          (((x)&0x000003FF)<<16)
-
-/* Bit definitions and macros for MCF_LCDC_LGWCR */
-#define MCF_LCDC_LGWCR_GWCKB(x)         (((x)&0x0000003F)<<0)
-#define MCF_LCDC_LGWCR_GWCKG(x)         (((x)&0x0000003F)<<6)
-#define MCF_LCDC_LGWCR_GWCKR(x)         (((x)&0x0000003F)<<12)
-#define MCF_LCDC_LGWCR_GW_RVS           (0x00200000)
-#define MCF_LCDC_LGWCR_GWE              (0x00400000)
-#define MCF_LCDC_LGWCR_GWCKE            (0x00800000)
-#define MCF_LCDC_LGWCR_GWAV(x)          (((x)&0x000000FF)<<24)
-
-/* Bit definitions and macros for MCF_LCDC_LGWDCR */
-#define MCF_LCDC_LGWDCR_GWTM(x)         (((x)&0x0000001F)<<0)
-#define MCF_LCDC_LGWDCR_GWHM(x)         (((x)&0x0000001F)<<16)
-#define MCF_LCDC_LGWDCR_GWBT            (0x80000000)
-
-/* Bit definitions and macros for MCF_LCDC_LSCR */
-#define MCF_LCDC_LSCR_PS_RISE_DELAY(x)    (((x)&0x0000003F)<<26)
-#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x)   (((x)&0x000000FF)<<16)
-#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8)
-#define MCF_LCDC_LSCR_GRAY_2(x)                   (((x)&0x0000000F)<<4)
-#define MCF_LCDC_LSCR_GRAY_1(x)                   (((x)&0x0000000F)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */
-#define MCF_LCDC_BPLUT_BASE_BASE(x)     (((x)&0xFFFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */
-#define MCF_LCDC_GWLUT_BASE_BASE(x)     (((x)&0xFFFFFFFF)<<0)
-
 /*********************************************************************
  *
  * Phase Locked Loop (PLL)
@@ -1925,10 +1107,10 @@
  *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_PLL_PODR              MCF_REG08(0xFC0C0000)
-#define MCF_PLL_PLLCR             MCF_REG08(0xFC0C0004)
-#define MCF_PLL_PMDR              MCF_REG08(0xFC0C0008)
-#define MCF_PLL_PFDR              MCF_REG08(0xFC0C000C)
+#define MCF_PLL_PODR              0xFC0C0000
+#define MCF_PLL_PLLCR             0xFC0C0004
+#define MCF_PLL_PMDR              0xFC0C0008
+#define MCF_PLL_PFDR              0xFC0C000C
 
 /* Bit definitions and macros for MCF_PLL_PODR */
 #define MCF_PLL_PODR_BUSDIV(x)    (((x)&0x0F)<<0)
@@ -1951,15 +1133,15 @@
  *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_SCM_MPR                     MCF_REG32(0xFC000000)
-#define MCF_SCM_PACRA                   MCF_REG32(0xFC000020)
-#define MCF_SCM_PACRB                   MCF_REG32(0xFC000024)
-#define MCF_SCM_PACRC                   MCF_REG32(0xFC000028)
-#define MCF_SCM_PACRD                   MCF_REG32(0xFC00002C)
-#define MCF_SCM_PACRE                   MCF_REG32(0xFC000040)
-#define MCF_SCM_PACRF                   MCF_REG32(0xFC000044)
+#define MCF_SCM_MPR                     0xFC000000
+#define MCF_SCM_PACRA                   0xFC000020
+#define MCF_SCM_PACRB                   0xFC000024
+#define MCF_SCM_PACRC                   0xFC000028
+#define MCF_SCM_PACRD                   0xFC00002C
+#define MCF_SCM_PACRE                   0xFC000040
+#define MCF_SCM_PACRF                   0xFC000044
 
-#define MCF_SCM_BCR                     MCF_REG32(0xFC040024)
+#define MCF_SCM_BCR                     0xFC040024
 
 /*********************************************************************
  *
@@ -1968,17 +1150,16 @@
  *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_SDRAMC_SDMR                 MCF_REG32(0xFC0B8000)
-#define MCF_SDRAMC_SDCR                 MCF_REG32(0xFC0B8004)
-#define MCF_SDRAMC_SDCFG1               MCF_REG32(0xFC0B8008)
-#define MCF_SDRAMC_SDCFG2               MCF_REG32(0xFC0B800C)
-#define MCF_SDRAMC_LIMP_FIX             MCF_REG32(0xFC0B8080)
-#define MCF_SDRAMC_SDDS                 MCF_REG32(0xFC0B8100)
-#define MCF_SDRAMC_SDCS0                MCF_REG32(0xFC0B8110)
-#define MCF_SDRAMC_SDCS1                MCF_REG32(0xFC0B8114)
-#define MCF_SDRAMC_SDCS2                MCF_REG32(0xFC0B8118)
-#define MCF_SDRAMC_SDCS3                MCF_REG32(0xFC0B811C)
-#define MCF_SDRAMC_SDCS(x)              MCF_REG32(0xFC0B8110+((x)*0x004))
+#define MCF_SDRAMC_SDMR                 0xFC0B8000
+#define MCF_SDRAMC_SDCR                 0xFC0B8004
+#define MCF_SDRAMC_SDCFG1               0xFC0B8008
+#define MCF_SDRAMC_SDCFG2               0xFC0B800C
+#define MCF_SDRAMC_LIMP_FIX             0xFC0B8080
+#define MCF_SDRAMC_SDDS                 0xFC0B8100
+#define MCF_SDRAMC_SDCS0                0xFC0B8110
+#define MCF_SDRAMC_SDCS1                0xFC0B8114
+#define MCF_SDRAMC_SDCS2                0xFC0B8118
+#define MCF_SDRAMC_SDCS3                0xFC0B811C
 
 /* Bit definitions and macros for MCF_SDRAMC_SDMR */
 #define MCF_SDRAMC_SDMR_CMD             (0x00010000)
@@ -2046,143 +1227,9 @@
 #define MCF_SDRAMC_SDCS_CSSZ_2GBYTE     (0x0000001E)
 #define MCF_SDRAMC_SDCS_CSSZ_4GBYTE     (0x0000001F)
 
-/*********************************************************************
- *
- *      FlexCAN module registers
- *
- *********************************************************************/
-#define MCF_FLEXCAN_BASEADDR(x)         (0xFC020000+(x)*0x0800)
-#define MCF_FLEXCAN_CANMCR(x)           MCF_REG32(0xFC020000+(x)*0x0800+0x00)
-#define MCF_FLEXCAN_CANCTRL(x)          MCF_REG32(0xFC020000+(x)*0x0800+0x04)
-#define MCF_FLEXCAN_TIMER(x)            MCF_REG32(0xFC020000+(x)*0x0800+0x08)
-#define MCF_FLEXCAN_RXGMASK(x)          MCF_REG32(0xFC020000+(x)*0x0800+0x10)
-#define MCF_FLEXCAN_RX14MASK(x)         MCF_REG32(0xFC020000+(x)*0x0800+0x14)
-#define MCF_FLEXCAN_RX15MASK(x)         MCF_REG32(0xFC020000+(x)*0x0800+0x18)
-#define MCF_FLEXCAN_ERRCNT(x)           MCF_REG32(0xFC020000+(x)*0x0800+0x1C)
-#define MCF_FLEXCAN_ERRSTAT(x)          MCF_REG32(0xFC020000+(x)*0x0800+0x20)
-#define MCF_FLEXCAN_IMASK(x)            MCF_REG32(0xFC020000+(x)*0x0800+0x28)
-#define MCF_FLEXCAN_IFLAG(x)            MCF_REG32(0xFC020000+(x)*0x0800+0x30)
-
-#define MCF_FLEXCAN_MB_CNT(x,y)         MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0)
-#define MCF_FLEXCAN_MB_ID(x,y)          MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4)
-#define MCF_FLEXCAN_MB_DB(x,y,z)        MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1)
-
-/*
- *      FlexCAN Module Configuration Register
- */
-#define CANMCR_MDIS             (0x80000000)
-#define CANMCR_FRZ              (0x40000000)
-#define CANMCR_HALT             (0x10000000)
-#define CANMCR_SOFTRST          (0x02000000)
-#define CANMCR_FRZACK           (0x01000000)
-#define CANMCR_SUPV             (0x00800000)
-#define CANMCR_MAXMB(x)         ((x)&0x0F)
-
-/*
- *      FlexCAN Control Register
- */
-#define CANCTRL_PRESDIV(x)      (((x)&0xFF)<<24)
-#define CANCTRL_RJW(x)          (((x)&0x03)<<22)
-#define CANCTRL_PSEG1(x)        (((x)&0x07)<<19)
-#define CANCTRL_PSEG2(x)        (((x)&0x07)<<16)
-#define CANCTRL_BOFFMSK         (0x00008000)
-#define CANCTRL_ERRMSK          (0x00004000)
-#define CANCTRL_CLKSRC          (0x00002000)
-#define CANCTRL_LPB             (0x00001000)
-#define CANCTRL_SAMP            (0x00000080)
-#define CANCTRL_BOFFREC         (0x00000040)
-#define CANCTRL_TSYNC           (0x00000020)
-#define CANCTRL_LBUF            (0x00000010)
-#define CANCTRL_LOM             (0x00000008)
-#define CANCTRL_PROPSEG(x)      ((x)&0x07)
-
-/*
- *      FlexCAN Error Counter Register
- */
-#define ERRCNT_RXECTR(x)        (((x)&0xFF)<<8)
-#define ERRCNT_TXECTR(x)        ((x)&0xFF)
-
-/*
- *      FlexCAN Error and Status Register
- */
-#define ERRSTAT_BITERR(x)       (((x)&0x03)<<14)
-#define ERRSTAT_ACKERR           (0x00002000)
-#define ERRSTAT_CRCERR           (0x00001000)
-#define ERRSTAT_FRMERR           (0x00000800)
-#define ERRSTAT_STFERR           (0x00000400)
-#define ERRSTAT_TXWRN            (0x00000200)
-#define ERRSTAT_RXWRN            (0x00000100)
-#define ERRSTAT_IDLE             (0x00000080)
-#define ERRSTAT_TXRX             (0x00000040)
-#define ERRSTAT_FLTCONF(x)       (((x)&0x03)<<4)
-#define ERRSTAT_BOFFINT          (0x00000004)
-#define ERRSTAT_ERRINT           (0x00000002)
-
 /*
- *      Interrupt Mask Register
- */
-#define IMASK_BUF15M            (0x8000)
-#define IMASK_BUF14M            (0x4000)
-#define IMASK_BUF13M            (0x2000)
-#define IMASK_BUF12M            (0x1000)
-#define IMASK_BUF11M            (0x0800)
-#define IMASK_BUF10M            (0x0400)
-#define IMASK_BUF9M             (0x0200)
-#define IMASK_BUF8M             (0x0100)
-#define IMASK_BUF7M             (0x0080)
-#define IMASK_BUF6M             (0x0040)
-#define IMASK_BUF5M             (0x0020)
-#define IMASK_BUF4M             (0x0010)
-#define IMASK_BUF3M             (0x0008)
-#define IMASK_BUF2M             (0x0004)
-#define IMASK_BUF1M             (0x0002)
-#define IMASK_BUF0M             (0x0001)
-#define IMASK_BUFnM(x)          (0x1<<(x))
-#define IMASK_BUFF_ENABLE_ALL   (0x1111)
-#define IMASK_BUFF_DISABLE_ALL  (0x0000)
-
-/*
- *      Interrupt Flag Register
- */
-#define IFLAG_BUF15M            (0x8000)
-#define IFLAG_BUF14M            (0x4000)
-#define IFLAG_BUF13M            (0x2000)
-#define IFLAG_BUF12M            (0x1000)
-#define IFLAG_BUF11M            (0x0800)
-#define IFLAG_BUF10M            (0x0400)
-#define IFLAG_BUF9M             (0x0200)
-#define IFLAG_BUF8M             (0x0100)
-#define IFLAG_BUF7M             (0x0080)
-#define IFLAG_BUF6M             (0x0040)
-#define IFLAG_BUF5M             (0x0020)
-#define IFLAG_BUF4M             (0x0010)
-#define IFLAG_BUF3M             (0x0008)
-#define IFLAG_BUF2M             (0x0004)
-#define IFLAG_BUF1M             (0x0002)
-#define IFLAG_BUF0M             (0x0001)
-#define IFLAG_BUFF_SET_ALL      (0xFFFF)
-#define IFLAG_BUFF_CLEAR_ALL    (0x0000)
-#define IFLAG_BUFnM(x)          (0x1<<(x))
-
-/*
- *      Message Buffers
- */
-#define MB_CNT_CODE(x)          (((x)&0x0F)<<24)
-#define MB_CNT_SRR              (0x00400000)
-#define MB_CNT_IDE              (0x00200000)
-#define MB_CNT_RTR              (0x00100000)
-#define MB_CNT_LENGTH(x)        (((x)&0x0F)<<16)
-#define MB_CNT_TIMESTAMP(x)     ((x)&0xFFFF)
-#define MB_ID_STD(x)            (((x)&0x07FF)<<18)
-#define MB_ID_EXT(x)            ((x)&0x3FFFF)
-
-/*********************************************************************
- *
  * Edge Port Module (EPORT)
- *
- *********************************************************************/
-
-/* Register read/write macros */
+ */
 #define MCFEPORT_EPPAR                (0xFC094000)
 #define MCFEPORT_EPDDR                (0xFC094002)
 #define MCFEPORT_EPIER                (0xFC094003)
@@ -2190,91 +1237,5 @@
 #define MCFEPORT_EPPDR                (0xFC094005)
 #define MCFEPORT_EPFR                 (0xFC094006)
 
-/* Bit definitions and macros for MCF_EPORT_EPPAR */
-#define MCF_EPORT_EPPAR_EPPA1(x)       (((x)&0x0003)<<2)
-#define MCF_EPORT_EPPAR_EPPA2(x)       (((x)&0x0003)<<4)
-#define MCF_EPORT_EPPAR_EPPA3(x)       (((x)&0x0003)<<6)
-#define MCF_EPORT_EPPAR_EPPA4(x)       (((x)&0x0003)<<8)
-#define MCF_EPORT_EPPAR_EPPA5(x)       (((x)&0x0003)<<10)
-#define MCF_EPORT_EPPAR_EPPA6(x)       (((x)&0x0003)<<12)
-#define MCF_EPORT_EPPAR_EPPA7(x)       (((x)&0x0003)<<14)
-#define MCF_EPORT_EPPAR_LEVEL          (0)
-#define MCF_EPORT_EPPAR_RISING         (1)
-#define MCF_EPORT_EPPAR_FALLING        (2)
-#define MCF_EPORT_EPPAR_BOTH           (3)
-#define MCF_EPORT_EPPAR_EPPA7_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA7_RISING   (0x4000)
-#define MCF_EPORT_EPPAR_EPPA7_FALLING  (0x8000)
-#define MCF_EPORT_EPPAR_EPPA7_BOTH     (0xC000)
-#define MCF_EPORT_EPPAR_EPPA6_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA6_RISING   (0x1000)
-#define MCF_EPORT_EPPAR_EPPA6_FALLING  (0x2000)
-#define MCF_EPORT_EPPAR_EPPA6_BOTH     (0x3000)
-#define MCF_EPORT_EPPAR_EPPA5_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA5_RISING   (0x0400)
-#define MCF_EPORT_EPPAR_EPPA5_FALLING  (0x0800)
-#define MCF_EPORT_EPPAR_EPPA5_BOTH     (0x0C00)
-#define MCF_EPORT_EPPAR_EPPA4_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA4_RISING   (0x0100)
-#define MCF_EPORT_EPPAR_EPPA4_FALLING  (0x0200)
-#define MCF_EPORT_EPPAR_EPPA4_BOTH     (0x0300)
-#define MCF_EPORT_EPPAR_EPPA3_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA3_RISING   (0x0040)
-#define MCF_EPORT_EPPAR_EPPA3_FALLING  (0x0080)
-#define MCF_EPORT_EPPAR_EPPA3_BOTH     (0x00C0)
-#define MCF_EPORT_EPPAR_EPPA2_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA2_RISING   (0x0010)
-#define MCF_EPORT_EPPAR_EPPA2_FALLING  (0x0020)
-#define MCF_EPORT_EPPAR_EPPA2_BOTH     (0x0030)
-#define MCF_EPORT_EPPAR_EPPA1_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA1_RISING   (0x0004)
-#define MCF_EPORT_EPPAR_EPPA1_FALLING  (0x0008)
-#define MCF_EPORT_EPPAR_EPPA1_BOTH     (0x000C)
-
-/* Bit definitions and macros for MCF_EPORT_EPDDR */
-#define MCF_EPORT_EPDDR_EPDD1          (0x02)
-#define MCF_EPORT_EPDDR_EPDD2          (0x04)
-#define MCF_EPORT_EPDDR_EPDD3          (0x08)
-#define MCF_EPORT_EPDDR_EPDD4          (0x10)
-#define MCF_EPORT_EPDDR_EPDD5          (0x20)
-#define MCF_EPORT_EPDDR_EPDD6          (0x40)
-#define MCF_EPORT_EPDDR_EPDD7          (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPIER */
-#define MCF_EPORT_EPIER_EPIE1          (0x02)
-#define MCF_EPORT_EPIER_EPIE2          (0x04)
-#define MCF_EPORT_EPIER_EPIE3          (0x08)
-#define MCF_EPORT_EPIER_EPIE4          (0x10)
-#define MCF_EPORT_EPIER_EPIE5          (0x20)
-#define MCF_EPORT_EPIER_EPIE6          (0x40)
-#define MCF_EPORT_EPIER_EPIE7          (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPDR */
-#define MCF_EPORT_EPDR_EPD1            (0x02)
-#define MCF_EPORT_EPDR_EPD2            (0x04)
-#define MCF_EPORT_EPDR_EPD3            (0x08)
-#define MCF_EPORT_EPDR_EPD4            (0x10)
-#define MCF_EPORT_EPDR_EPD5            (0x20)
-#define MCF_EPORT_EPDR_EPD6            (0x40)
-#define MCF_EPORT_EPDR_EPD7            (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPPDR */
-#define MCF_EPORT_EPPDR_EPPD1          (0x02)
-#define MCF_EPORT_EPPDR_EPPD2          (0x04)
-#define MCF_EPORT_EPPDR_EPPD3          (0x08)
-#define MCF_EPORT_EPPDR_EPPD4          (0x10)
-#define MCF_EPORT_EPPDR_EPPD5          (0x20)
-#define MCF_EPORT_EPPDR_EPPD6          (0x40)
-#define MCF_EPORT_EPPDR_EPPD7          (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPFR */
-#define MCF_EPORT_EPFR_EPF1            (0x02)
-#define MCF_EPORT_EPFR_EPF2            (0x04)
-#define MCF_EPORT_EPFR_EPF3            (0x08)
-#define MCF_EPORT_EPFR_EPF4            (0x10)
-#define MCF_EPORT_EPFR_EPF5            (0x20)
-#define MCF_EPORT_EPFR_EPF6            (0x40)
-#define MCF_EPORT_EPFR_EPF7            (0x80)
-
 /********************************************************************/
 #endif  /* m532xsim_h */
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 79f58dd6a83d..a7550bc5cd1e 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -23,55 +23,55 @@
 /*
  *      Define the 5407 SIM register set addresses.
  */
-#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
-#define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
-#define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
-#define MCFSIM_PLLCR            0x08            /* PLL Control Reg*/
-#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
-#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
-
-#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSAR4            0xb0            /* CS 4 Address reg (r/w) */
-#define MCFSIM_CSMR4            0xb4            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
-#define MCFSIM_CSAR5            0xbc            /* CS 5 Address reg (r/w) */
-#define MCFSIM_CSMR5            0xc0            /* CS 5 Mask reg (r/w) */
-#define MCFSIM_CSCR5            0xc6            /* CS 5 Control reg (r/w) */
-#define MCFSIM_CSAR6            0xc8            /* CS 6 Address reg (r/w) */
-#define MCFSIM_CSMR6            0xcc            /* CS 6 Mask reg (r/w) */
-#define MCFSIM_CSCR6            0xd2            /* CS 6 Control reg (r/w) */
-#define MCFSIM_CSAR7            0xd4            /* CS 7 Address reg (r/w) */
-#define MCFSIM_CSMR7            0xd8            /* CS 7 Mask reg (r/w) */
-#define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
+#define MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status */
+#define MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog service*/
+#define MCFSIM_PAR              (MCF_MBAR + 0x04)       /* Pin Assignment */
+#define MCFSIM_IRQPAR           (MCF_MBAR + 0x06)       /* Intr Assignment */
+#define MCFSIM_PLLCR            (MCF_MBAR + 0x08)       /* PLL Ctrl */
+#define MCFSIM_MPARK            (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
+#define MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pending */
+#define MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
+#define MCFSIM_AVR              (MCF_MBAR + 0x4b)       /* Autovector Ctrl */
+#define MCFSIM_ICR0             (MCF_MBAR + 0x4c)       /* Intr Ctrl reg 0 */
+#define MCFSIM_ICR1             (MCF_MBAR + 0x4d)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x4e)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x4f)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x50)       /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5             (MCF_MBAR + 0x51)       /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6             (MCF_MBAR + 0x52)       /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7             (MCF_MBAR + 0x53)       /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8             (MCF_MBAR + 0x54)       /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9             (MCF_MBAR + 0x55)       /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10            (MCF_MBAR + 0x56)       /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11            (MCF_MBAR + 0x57)       /* Intr Ctrl reg 11 */
+
+#define MCFSIM_CSAR0            (MCF_MBAR + 0x80)       /* CS 0 Address reg */
+#define MCFSIM_CSMR0            (MCF_MBAR + 0x84)       /* CS 0 Mask reg */
+#define MCFSIM_CSCR0            (MCF_MBAR + 0x8a)       /* CS 0 Control reg */
+#define MCFSIM_CSAR1            (MCF_MBAR + 0x8c)       /* CS 1 Address reg */
+#define MCFSIM_CSMR1            (MCF_MBAR + 0x90)       /* CS 1 Mask reg */
+#define MCFSIM_CSCR1            (MCF_MBAR + 0x96)       /* CS 1 Control reg */
+
+#define MCFSIM_CSAR2            (MCF_MBAR + 0x98)       /* CS 2 Address reg */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x9c)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0xa2)       /* CS 2 Control reg */
+#define MCFSIM_CSAR3            (MCF_MBAR + 0xa4)       /* CS 3 Address reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0xa8)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0xae)       /* CS 3 Control reg */
+#define MCFSIM_CSAR4            (MCF_MBAR + 0xb0)       /* CS 4 Address reg */
+#define MCFSIM_CSMR4            (MCF_MBAR + 0xb4)       /* CS 4 Mask reg */
+#define MCFSIM_CSCR4            (MCF_MBAR + 0xba)       /* CS 4 Control reg */
+#define MCFSIM_CSAR5            (MCF_MBAR + 0xbc)       /* CS 5 Address reg */
+#define MCFSIM_CSMR5            (MCF_MBAR + 0xc0)       /* CS 5 Mask reg */
+#define MCFSIM_CSCR5            (MCF_MBAR + 0xc6)       /* CS 5 Control reg */
+#define MCFSIM_CSAR6            (MCF_MBAR + 0xc8)       /* CS 6 Address reg */
+#define MCFSIM_CSMR6            (MCF_MBAR + 0xcc)       /* CS 6 Mask reg */
+#define MCFSIM_CSCR6            (MCF_MBAR + 0xd2)       /* CS 6 Control reg */
+#define MCFSIM_CSAR7            (MCF_MBAR + 0xd4)       /* CS 7 Address reg */
+#define MCFSIM_CSMR7            (MCF_MBAR + 0xd8)       /* CS 7 Mask reg */
+#define MCFSIM_CSCR7            (MCF_MBAR + 0xde)       /* CS 7 Control reg */
 
 #define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
 #define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
@@ -102,9 +102,9 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PIN_MAX                 16
-#define MCFGPIO_IRQ_MAX                 -1
-#define MCFGPIO_IRQ_VECBASE             -1
+#define MCFGPIO_PIN_MAX         16
+#define MCFGPIO_IRQ_MAX         -1
+#define MCFGPIO_IRQ_VECBASE     -1
 
 /*
  *      Some symbol defines for the above...
@@ -130,9 +130,9 @@
 /*
  *       Defines for the IRQPAR Register
  */
-#define IRQ5_LEVEL4     0x80
-#define IRQ3_LEVEL6     0x40
-#define IRQ1_LEVEL2     0x20
+#define IRQ5_LEVEL4             0x80
+#define IRQ3_LEVEL6             0x40
+#define IRQ1_LEVEL2             0x20
 
 /*
  *      Define system peripheral IRQ usage.
diff --git a/arch/m68k/include/asm/m54xxgpt.h b/arch/m68k/include/asm/m54xxgpt.h
index df75dd87ae7a..0b69cd1ed0ed 100644
--- a/arch/m68k/include/asm/m54xxgpt.h
+++ b/arch/m68k/include/asm/m54xxgpt.h
@@ -16,26 +16,26 @@
 *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_GPT_GMS0       0x000800
-#define MCF_GPT_GCIR0      0x000804
-#define MCF_GPT_GPWM0      0x000808
-#define MCF_GPT_GSR0       0x00080C
-#define MCF_GPT_GMS1       0x000810
-#define MCF_GPT_GCIR1      0x000814
-#define MCF_GPT_GPWM1      0x000818
-#define MCF_GPT_GSR1       0x00081C
-#define MCF_GPT_GMS2       0x000820
-#define MCF_GPT_GCIR2      0x000824
-#define MCF_GPT_GPWM2      0x000828
-#define MCF_GPT_GSR2       0x00082C
-#define MCF_GPT_GMS3       0x000830
-#define MCF_GPT_GCIR3      0x000834
-#define MCF_GPT_GPWM3      0x000838
-#define MCF_GPT_GSR3       0x00083C
-#define MCF_GPT_GMS(x)     (0x000800+((x)*0x010))
-#define MCF_GPT_GCIR(x)    (0x000804+((x)*0x010))
-#define MCF_GPT_GPWM(x)    (0x000808+((x)*0x010))
-#define MCF_GPT_GSR(x)     (0x00080C+((x)*0x010))
+#define MCF_GPT_GMS0       (MCF_MBAR + 0x000800)
+#define MCF_GPT_GCIR0      (MCF_MBAR + 0x000804)
+#define MCF_GPT_GPWM0      (MCF_MBAR + 0x000808)
+#define MCF_GPT_GSR0       (MCF_MBAR + 0x00080C)
+#define MCF_GPT_GMS1       (MCF_MBAR + 0x000810)
+#define MCF_GPT_GCIR1      (MCF_MBAR + 0x000814)
+#define MCF_GPT_GPWM1      (MCF_MBAR + 0x000818)
+#define MCF_GPT_GSR1       (MCF_MBAR + 0x00081C)
+#define MCF_GPT_GMS2       (MCF_MBAR + 0x000820)
+#define MCF_GPT_GCIR2      (MCF_MBAR + 0x000824)
+#define MCF_GPT_GPWM2      (MCF_MBAR + 0x000828)
+#define MCF_GPT_GSR2       (MCF_MBAR + 0x00082C)
+#define MCF_GPT_GMS3       (MCF_MBAR + 0x000830)
+#define MCF_GPT_GCIR3      (MCF_MBAR + 0x000834)
+#define MCF_GPT_GPWM3      (MCF_MBAR + 0x000838)
+#define MCF_GPT_GSR3       (MCF_MBAR + 0x00083C)
+#define MCF_GPT_GMS(x)     (MCF_MBAR + 0x000800 + ((x) * 0x010))
+#define MCF_GPT_GCIR(x)    (MCF_MBAR + 0x000804 + ((x) * 0x010))
+#define MCF_GPT_GPWM(x)    (MCF_MBAR + 0x000808 + ((x) * 0x010))
+#define MCF_GPT_GSR(x)     (MCF_MBAR + 0x00080C + ((x) * 0x010))
 
 /* Bit definitions and macros for MCF_GPT_GMS */
 #define MCF_GPT_GMS_TMS(x)         (((x)&0x00000007)<<0)
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index d3c5e0dbdadf..d3bd83887429 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -47,6 +47,12 @@
 #define MCF_IRQ_UART3           (MCFINT_VECBASE + 32)
 
 /*
+ *      Slice Timer support.
+ */
+#define MCFSLT_TIMER0           (MCF_MBAR + 0x900)      /* Base addr TIMER0 */
+#define MCFSLT_TIMER1           (MCF_MBAR + 0x910)      /* Base addr TIMER1 */
+
+/*
  *      Generic GPIO support
  */
 #define MCFGPIO_PIN_MAX         0       /* I am too lazy to count */
@@ -64,15 +70,25 @@
 #define MCFEPORT_EPFR           (MCF_MBAR + 0xf0c)      /* Flags */
 
 /*
- *      Some PSC related definitions
+ *      Pin Assignment register definitions
  */
-#define MCF_PAR_PSC(x)          (0x000A4F-((x)&0x3))
+#define MCFGPIO_PAR_FBCTL       (MCF_MBAR + 0xA40)
+#define MCFGPIO_PAR_FBCS        (MCF_MBAR + 0xA42)
+#define MCFGPIO_PAR_DMA         (MCF_MBAR + 0xA43)
+#define MCFGPIO_PAR_FECI2CIRQ   (MCF_MBAR + 0xA44)
+#define MCFGPIO_PAR_PCIBG       (MCF_MBAR + 0xA48)      /* PCI bus grant */
+#define MCFGPIO_PAR_PCIBR       (MCF_MBAR + 0xA4A)      /* PCI */
+#define MCFGPIO_PAR_PSC0        (MCF_MBAR + 0xA4F)
+#define MCFGPIO_PAR_PSC1        (MCF_MBAR + 0xA4E)
+#define MCFGPIO_PAR_PSC2        (MCF_MBAR + 0xA4D)
+#define MCFGPIO_PAR_PSC3        (MCF_MBAR + 0xA4C)
+#define MCFGPIO_PAR_DSPI        (MCF_MBAR + 0xA50)
+#define MCFGPIO_PAR_TIMER       (MCF_MBAR + 0xA52)
+
 #define MCF_PAR_SDA             (0x0008)
 #define MCF_PAR_SCL             (0x0004)
 #define MCF_PAR_PSC_TXD         (0x04)
 #define MCF_PAR_PSC_RXD         (0x08)
-#define MCF_PAR_PSC_RTS(x)      (((x)&0x03)<<4)
-#define MCF_PAR_PSC_CTS(x)      (((x)&0x03)<<6)
 #define MCF_PAR_PSC_CTS_GPIO    (0x00)
 #define MCF_PAR_PSC_CTS_BCLK    (0x80)
 #define MCF_PAR_PSC_CTS_CTS     (0xC0)
@@ -81,7 +97,4 @@
 #define MCF_PAR_PSC_RTS_RTS     (0x30)
 #define MCF_PAR_PSC_CANRX       (0x40)
 
-#define MCF_PAR_PCIBG           (CONFIG_MBAR + 0xa48)   /* PCI bus grant */
-#define MCF_PAR_PCIBR           (CONFIG_MBAR + 0xa4a)   /* PCI */
-
 #endif  /* m54xxsim_h */
diff --git a/arch/m68k/include/asm/mcfslt.h b/arch/m68k/include/asm/mcfslt.h
index d0d0ecba5333..c2314b6f8caa 100644
--- a/arch/m68k/include/asm/mcfslt.h
+++ b/arch/m68k/include/asm/mcfslt.h
@@ -13,13 +13,6 @@
 /****************************************************************************/
 
 /*
- *      Get address specific defines for the 547x.
- */
-#define MCFSLT_TIMER0           0x900   /* Base address of TIMER0 */
-#define MCFSLT_TIMER1           0x910   /* Base address of TIMER1 */
-
-
-/*
  *      Define the SLT timer register set addresses.
  */
 #define MCFSLT_STCNT            0x00    /* Terminal count */
diff --git a/arch/m68k/include/asm/nettel.h b/arch/m68k/include/asm/nettel.h
index 4dec2d9fb994..2a7a7667d807 100644
--- a/arch/m68k/include/asm/nettel.h
+++ b/arch/m68k/include/asm/nettel.h
@@ -21,6 +21,7 @@
 #ifdef CONFIG_COLDFIRE
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
+#include <asm/io.h>
 #endif
 
 /*---------------------------------------------------------------------------*/
@@ -86,16 +87,12 @@ static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
  */
 static __inline__ unsigned int mcf_getppdata(void)
 {
-        volatile unsigned short *pp;
-        pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
-        return((unsigned int) *pp);
+        return readw(MCFSIM_PBDAT);
 }
 
 static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
 {
-        volatile unsigned short *pp;
-        pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
-        *pp = (*pp & ~mask) | bits;
+        write((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT);
 }
 #endif
 
diff --git a/arch/m68k/platform/68VZ328/Makefile b/arch/m68k/platform/68VZ328/Makefile
index a49d75e65489..816674164682 100644
--- a/arch/m68k/platform/68VZ328/Makefile
+++ b/arch/m68k/platform/68VZ328/Makefile
@@ -1,11 +1,5 @@
 #
-# Makefile for arch/m68knommu/platform/68VZ328.
+# Makefile for arch/m68k/platform/68VZ328.
 #
 
 obj-y           := config.o
-extra-$(DRAGEN2):= screen.h
-
-$(obj)/screen.h: $(src)/screen.xbm $(src)/xbm2lcd.pl
-        perl $(src)/xbm2lcd.pl < $(src)/screen.xbm > $(obj)/screen.h
-
-clean-files := $(obj)/screen.h
diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c
index 81f0fb5e51cf..71ea4c02795d 100644
--- a/arch/m68k/platform/coldfire/device.c
+++ b/arch/m68k/platform/coldfire/device.c
@@ -347,12 +347,12 @@ static void __init mcf_uart_set_irq(void)
 {
 #ifdef MCFUART_UIVR
         /* UART0 interrupt setup */
-        writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
+        writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
         writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
         mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
 
         /* UART1 interrupt setup */
-        writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
+        writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
         writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
         mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
 #endif
diff --git a/arch/m68k/platform/coldfire/head.S b/arch/m68k/platform/coldfire/head.S
index b88f5716f357..fa31be297b85 100644
--- a/arch/m68k/platform/coldfire/head.S
+++ b/arch/m68k/platform/coldfire/head.S
@@ -60,7 +60,7 @@
 
 #elif defined(CONFIG_M5272)
 .macro GET_MEM_SIZE
-        movel   MCF_MBAR+MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
+        movel   MCFSIM_CSOR7,%d0        /* get SDRAM address mask */
         andil   #0xfffff000,%d0         /* mask out chip select options */
         negl    %d0                     /* negate bits */
 .endm
diff --git a/arch/m68k/platform/coldfire/intc-5249.c b/arch/m68k/platform/coldfire/intc-5249.c
index f343bf7bf5b0..0864b836699a 100644
--- a/arch/m68k/platform/coldfire/intc-5249.c
+++ b/arch/m68k/platform/coldfire/intc-5249.c
@@ -20,22 +20,22 @@
 static void intc2_irq_gpio_mask(struct irq_data *d)
 {
         u32 imr;
-        imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        imr = readl(MCFSIM2_GPIOINTENABLE);
         imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
-        writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        writel(imr, MCFSIM2_GPIOINTENABLE);
 }
 
 static void intc2_irq_gpio_unmask(struct irq_data *d)
 {
         u32 imr;
-        imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        imr = readl(MCFSIM2_GPIOINTENABLE);
         imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
-        writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        writel(imr, MCFSIM2_GPIOINTENABLE);
 }
 
 static void intc2_irq_gpio_ack(struct irq_data *d)
 {
-        writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR);
+        writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCFSIM2_GPIOINTCLEAR);
 }
 
 static struct irq_chip intc2_irq_gpio_chip = {
diff --git a/arch/m68k/platform/coldfire/intc-5272.c b/arch/m68k/platform/coldfire/intc-5272.c
index 7160e618b0a9..d7b695629a7e 100644
--- a/arch/m68k/platform/coldfire/intc-5272.c
+++ b/arch/m68k/platform/coldfire/intc-5272.c
@@ -86,7 +86,7 @@ static void intc_irq_mask(struct irq_data *d)
                 u32 v;
                 irq -= MCFINT_VECBASE;
                 v = 0x8 << intc_irqmap[irq].index;
-                writel(v, MCF_MBAR + intc_irqmap[irq].icr);
+                writel(v, intc_irqmap[irq].icr);
         }
 }
 
@@ -98,7 +98,7 @@ static void intc_irq_unmask(struct irq_data *d)
                 u32 v;
                 irq -= MCFINT_VECBASE;
                 v = 0xd << intc_irqmap[irq].index;
-                writel(v, MCF_MBAR + intc_irqmap[irq].icr);
+                writel(v, intc_irqmap[irq].icr);
         }
 }
 
@@ -111,10 +111,10 @@ static void intc_irq_ack(struct irq_data *d)
                 irq -= MCFINT_VECBASE;
                 if (intc_irqmap[irq].ack) {
                         u32 v;
-                        v = readl(MCF_MBAR + intc_irqmap[irq].icr);
+                        v = readl(intc_irqmap[irq].icr);
                         v &= (0x7 << intc_irqmap[irq].index);
                         v |= (0x8 << intc_irqmap[irq].index);
-                        writel(v, MCF_MBAR + intc_irqmap[irq].icr);
+                        writel(v, intc_irqmap[irq].icr);
                 }
         }
 }
@@ -127,12 +127,12 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
                 irq -= MCFINT_VECBASE;
                 if (intc_irqmap[irq].ack) {
                         u32 v;
-                        v = readl(MCF_MBAR + MCFSIM_PITR);
+                        v = readl(MCFSIM_PITR);
                         if (type == IRQ_TYPE_EDGE_FALLING)
                                 v &= ~(0x1 << (32 - irq));
                         else
                                 v |= (0x1 << (32 - irq));
-                        writel(v, MCF_MBAR + MCFSIM_PITR);
+                        writel(v, MCFSIM_PITR);
                 }
         }
         return 0;
@@ -163,10 +163,10 @@ void __init init_IRQ(void)
         int irq, edge;
 
         /* Mask all interrupt sources */
-        writel(0x88888888, MCF_MBAR + MCFSIM_ICR1);
-        writel(0x88888888, MCF_MBAR + MCFSIM_ICR2);
-        writel(0x88888888, MCF_MBAR + MCFSIM_ICR3);
-        writel(0x88888888, MCF_MBAR + MCFSIM_ICR4);
+        writel(0x88888888, MCFSIM_ICR1);
+        writel(0x88888888, MCFSIM_ICR2);
+        writel(0x88888888, MCFSIM_ICR3);
+        writel(0x88888888, MCFSIM_ICR4);
 
         for (irq = 0; (irq < NR_IRQS); irq++) {
                 irq_set_chip(irq, &intc_irq_chip);
diff --git a/arch/m68k/platform/coldfire/intc.c b/arch/m68k/platform/coldfire/intc.c
index 5c0c150b4067..cce257420388 100644
--- a/arch/m68k/platform/coldfire/intc.c
+++ b/arch/m68k/platform/coldfire/intc.c
@@ -45,23 +45,23 @@ unsigned char mcf_irq2imr[NR_IRQS];
 void mcf_setimr(int index)
 {
         u16 imr;
-        imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
-        __raw_writew(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readw(MCFSIM_IMR);
+        __raw_writew(imr | (0x1 << index), MCFSIM_IMR);
 }
 
 void mcf_clrimr(int index)
 {
         u16 imr;
-        imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
-        __raw_writew(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readw(MCFSIM_IMR);
+        __raw_writew(imr & ~(0x1 << index), MCFSIM_IMR);
 }
 
 void mcf_maskimr(unsigned int mask)
 {
         u16 imr;
-        imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readw(MCFSIM_IMR);
         imr |= mask;
-        __raw_writew(imr, MCF_MBAR + MCFSIM_IMR);
+        __raw_writew(imr, MCFSIM_IMR);
 }
 
 #else
@@ -69,23 +69,23 @@ void mcf_maskimr(unsigned int mask)
 void mcf_setimr(int index)
 {
         u32 imr;
-        imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
-        __raw_writel(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readl(MCFSIM_IMR);
+        __raw_writel(imr | (0x1 << index), MCFSIM_IMR);
 }
 
 void mcf_clrimr(int index)
 {
         u32 imr;
-        imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
-        __raw_writel(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readl(MCFSIM_IMR);
+        __raw_writel(imr & ~(0x1 << index), MCFSIM_IMR);
 }
 
 void mcf_maskimr(unsigned int mask)
 {
         u32 imr;
-        imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readl(MCFSIM_IMR);
         imr |= mask;
-        __raw_writel(imr, MCF_MBAR + MCFSIM_IMR);
+        __raw_writel(imr, MCFSIM_IMR);
 }
 
 #endif
@@ -104,9 +104,9 @@ void mcf_autovector(int irq)
 #ifdef MCFSIM_AVR
         if ((irq >= EIRQ1) && (irq <= EIRQ7)) {
                 u8 avec;
-                avec = __raw_readb(MCF_MBAR + MCFSIM_AVR);
+                avec = __raw_readb(MCFSIM_AVR);
                 avec |= (0x1 << (irq - EIRQ1 + 1));
-                __raw_writeb(avec, MCF_MBAR + MCFSIM_AVR);
+                __raw_writeb(avec, MCFSIM_AVR);
         }
 #endif
 }
diff --git a/arch/m68k/platform/coldfire/m523x.c b/arch/m68k/platform/coldfire/m523x.c
index d47dfd8f50a2..ff37fe9553ea 100644
--- a/arch/m68k/platform/coldfire/m523x.c
+++ b/arch/m68k/platform/coldfire/m523x.c
@@ -42,14 +42,8 @@ static void __init m523x_qspi_init(void)
 
 static void __init m523x_fec_init(void)
 {
-        u16 par;
-        u8 v;
-
         /* Set multi-function pins to ethernet use */
-        par = readw(MCF_IPSBAR + 0x100082);
-        writew(par | 0xf00, MCF_IPSBAR + 0x100082);
-        v = readb(MCF_IPSBAR + 0x100078);
-        writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
+        writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
 }
 
 /***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m5249.c b/arch/m68k/platform/coldfire/m5249.c
index 300e729a58d0..23b19cb7ab50 100644
--- a/arch/m68k/platform/coldfire/m5249.c
+++ b/arch/m68k/platform/coldfire/m5249.c
@@ -57,7 +57,7 @@ static void __init m5249_qspi_init(void)
 {
         /* QSPI irq setup */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
-               MCF_MBAR + MCFSIM_QSPIICR);
+               MCFSIM_QSPIICR);
         mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
 }
 
@@ -72,11 +72,11 @@ static void __init m5249_smc91x_init(void)
         u32  gpio;
 
         /* Set the GPIO line as interrupt source for smc91x device */
-        gpio = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
-        writel(gpio | 0x40, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        gpio = readl(MCFSIM2_GPIOINTENABLE);
+        writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
 
-        gpio = readl(MCF_MBAR2 + MCFSIM2_INTLEVEL5);
-        writel(gpio | 0x04000000, MCF_MBAR2 + MCFSIM2_INTLEVEL5);
+        gpio = readl(MCFSIM2_INTLEVEL5);
+        writel(gpio | 0x04000000, MCFSIM2_INTLEVEL5);
 }
 
 #endif /* CONFIG_M5249C3 */
diff --git a/arch/m68k/platform/coldfire/m525x.c b/arch/m68k/platform/coldfire/m525x.c
index 8ce905f9b84f..fce8f8a45bf0 100644
--- a/arch/m68k/platform/coldfire/m525x.c
+++ b/arch/m68k/platform/coldfire/m525x.c
@@ -30,7 +30,7 @@ static void __init m525x_qspi_init(void)
 
         /* QSPI irq setup */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
-               MCF_MBAR + MCFSIM_QSPIICR);
+               MCFSIM_QSPIICR);
         mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
 }
@@ -42,7 +42,7 @@ static void __init m525x_i2c_init(void)
 
         /* first I2C controller uses regular irq setup */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
-                        MCF_MBAR + MCFSIM_I2CICR);
+                MCFSIM_I2CICR);
         mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
 
         /* second I2C controller is completely different */
diff --git a/arch/m68k/platform/coldfire/m5272.c b/arch/m68k/platform/coldfire/m5272.c
index e68bc7a148eb..45b246d052ef 100644
--- a/arch/m68k/platform/coldfire/m5272.c
+++ b/arch/m68k/platform/coldfire/m5272.c
@@ -35,13 +35,13 @@ static void __init m5272_uarts_init(void)
         u32 v;
 
         /* Enable the output lines for the serial ports */
-        v = readl(MCF_MBAR + MCFSIM_PBCNT);
+        v = readl(MCFSIM_PBCNT);
         v = (v & ~0x000000ff) | 0x00000055;
-        writel(v, MCF_MBAR + MCFSIM_PBCNT);
+        writel(v, MCFSIM_PBCNT);
 
-        v = readl(MCF_MBAR + MCFSIM_PDCNT);
+        v = readl(MCFSIM_PDCNT);
         v = (v & ~0x000003fc) | 0x000002a8;
-        writel(v, MCF_MBAR + MCFSIM_PDCNT);
+        writel(v, MCFSIM_PDCNT);
 }
 
 /***************************************************************************/
@@ -50,9 +50,9 @@ static void m5272_cpu_reset(void)
 {
         local_irq_disable();
         /* Set watchdog to reset, and enabled */
-        __raw_writew(0, MCF_MBAR + MCFSIM_WIRR);
-        __raw_writew(1, MCF_MBAR + MCFSIM_WRRR);
-        __raw_writew(0, MCF_MBAR + MCFSIM_WCR);
+        __raw_writew(0, MCFSIM_WIRR);
+        __raw_writew(1, MCFSIM_WRRR);
+        __raw_writew(0, MCFSIM_WCR);
         for (;;)
                 /* wait for watchdog to timeout */;
 }
@@ -62,11 +62,8 @@ static void m5272_cpu_reset(void)
 void __init config_BSP(char *commandp, int size)
 {
 #if defined (CONFIG_MOD5272)
-        volatile unsigned char  *pivrp;
-
         /* Set base of device vectors to be 64 */
-        pivrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_PIVR);
-        *pivrp = 0x40;
+        writeb(0x40, MCFSIM_PIVR);
 #endif
 
 #if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
diff --git a/arch/m68k/platform/coldfire/m527x.c b/arch/m68k/platform/coldfire/m527x.c
index b3cb378c5e94..1431ba03c602 100644
--- a/arch/m68k/platform/coldfire/m527x.c
+++ b/arch/m68k/platform/coldfire/m527x.c
@@ -53,9 +53,9 @@ static void __init m527x_uarts_init(void)
         /*
          * External Pin Mask Setting & Enable External Pin for Interface
          */
-        sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
+        sepmask = readw(MCFGPIO_PAR_UART);
         sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
-        writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART);
+        writew(sepmask, MCFGPIO_PAR_UART);
 }
 
 /***************************************************************************/
@@ -67,19 +67,19 @@ static void __init m527x_fec_init(void)
 
         /* Set multi-function pins to ethernet mode for fec0 */
 #if defined(CONFIG_M5271)
-        v = readb(MCF_IPSBAR + 0x100047);
-        writeb(v | 0xf0, MCF_IPSBAR + 0x100047);
+        v = readb(MCFGPIO_PAR_FECI2C);
+        writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
 #else
-        par = readw(MCF_IPSBAR + 0x100082);
-        writew(par | 0xf00, MCF_IPSBAR + 0x100082);
-        v = readb(MCF_IPSBAR + 0x100078);
-        writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
+        par = readw(MCFGPIO_PAR_FECI2C);
+        writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
+        v = readb(MCFGPIO_PAR_FEC0HL);
+        writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
 
         /* Set multi-function pins to ethernet mode for fec1 */
-        par = readw(MCF_IPSBAR + 0x100082);
-        writew(par | 0xa0, MCF_IPSBAR + 0x100082);
-        v = readb(MCF_IPSBAR + 0x100079);
-        writeb(v | 0xc0, MCF_IPSBAR + 0x100079);
+        par = readw(MCFGPIO_PAR_FECI2C);
+        writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
+        v = readb(MCFGPIO_PAR_FEC1HL);
+        writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
 #endif
 }
 
diff --git a/arch/m68k/platform/coldfire/m528x.c b/arch/m68k/platform/coldfire/m528x.c
index f1319e5d2546..f9f7e6a13d04 100644
--- a/arch/m68k/platform/coldfire/m528x.c
+++ b/arch/m68k/platform/coldfire/m528x.c
@@ -53,9 +53,9 @@ static void __init m528x_fec_init(void)
         u16 v16;
 
         /* Set multi-function pins to ethernet mode for fec0 */
-        v16 = readw(MCF_IPSBAR + 0x100056);
-        writew(v16 | 0xf00, MCF_IPSBAR + 0x100056);
-        writeb(0xc0, MCF_IPSBAR + 0x100058);
+        v16 = readw(MCFGPIO_PASPAR);
+        writew(v16 | 0xf00, MCFGPIO_PASPAR);
+        writeb(0xc0, MCFGPIO_PEHLPAR);
 }
 
 /***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m532x.c b/arch/m68k/platform/coldfire/m532x.c
index 4819a44991ed..7951d1d43357 100644
--- a/arch/m68k/platform/coldfire/m532x.c
+++ b/arch/m68k/platform/coldfire/m532x.c
@@ -172,7 +172,7 @@ static void __init m532x_clk_init(void)
 static void __init m532x_qspi_init(void)
 {
         /* setup QSPS pins for QSPI with gpio CS control */
-        writew(0x01f0, MCF_GPIO_PAR_QSPI);
+        writew(0x01f0, MCFGPIO_PAR_QSPI);
 }
 
 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
@@ -182,18 +182,24 @@ static void __init m532x_qspi_init(void)
 static void __init m532x_uarts_init(void)
 {
         /* UART GPIO initialization */
-        MCF_GPIO_PAR_UART |= 0x0FFF;
+        writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART);
 }
 
 /***************************************************************************/
 
 static void __init m532x_fec_init(void)
 {
+        u8 v;
+
         /* Set multi-function pins to ethernet mode for fec0 */
-        MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
-                MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
-        MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
-                MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
+        v = readb(MCFGPIO_PAR_FECI2C);
+        v |= MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
+                MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO;
+        writeb(v, MCFGPIO_PAR_FECI2C);
+
+        v = readb(MCFGPIO_PAR_FEC);
+        v = MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC;
+        writeb(v, MCFGPIO_PAR_FEC);
 }
 
 /***************************************************************************/
@@ -298,7 +304,7 @@ asmlinkage void __init sysinit(void)
 void wtm_init(void)
 {
         /* Disable watchdog timer */
-        MCF_WTM_WCR = 0;
+        writew(0, MCF_WTM_WCR);
 }
 
 #define MCF_SCM_BCR_GBW         (0x00000100)
@@ -307,53 +313,53 @@ void wtm_init(void)
 void scm_init(void)
 {
         /* All masters are trusted */
-        MCF_SCM_MPR = 0x77777777;
+        writel(0x77777777, MCF_SCM_MPR);
     
         /* Allow supervisor/user, read/write, and trusted/untrusted
            access to all slaves */
-        MCF_SCM_PACRA = 0;
-        MCF_SCM_PACRB = 0;
-        MCF_SCM_PACRC = 0;
-        MCF_SCM_PACRD = 0;
-        MCF_SCM_PACRE = 0;
-        MCF_SCM_PACRF = 0;
+        writel(0, MCF_SCM_PACRA);
+        writel(0, MCF_SCM_PACRB);
+        writel(0, MCF_SCM_PACRC);
+        writel(0, MCF_SCM_PACRD);
+        writel(0, MCF_SCM_PACRE);
+        writel(0, MCF_SCM_PACRF);
 
         /* Enable bursts */
-        MCF_SCM_BCR = (MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW);
+        writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR);
 }
 
 
 void fbcs_init(void)
 {
-        MCF_GPIO_PAR_CS = 0x0000003E;
+        writeb(0x3E, MCFGPIO_PAR_CS);
 
         /* Latch chip select */
-        MCF_FBCS1_CSAR = 0x10080000;
+        writel(0x10080000, MCF_FBCS1_CSAR);
 
-        MCF_FBCS1_CSCR = 0x002A3780;
-        MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V);
+        writel(0x002A3780, MCF_FBCS1_CSCR);
+        writel(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
 
         /* Initialize latch to drive signals to inactive states */
-        *((u16 *)(0x10080000)) = 0xFFFF;
+        writew(0xffff, 0x10080000);
 
         /* External SRAM */
-        MCF_FBCS1_CSAR = EXT_SRAM_ADDRESS;
-        MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16
-                        | MCF_FBCS_CSCR_AA
-                        | MCF_FBCS_CSCR_SBM
-                        | MCF_FBCS_CSCR_WS(1));
-        MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K
-                        | MCF_FBCS_CSMR_V);
+        writel(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR);
+        writel(MCF_FBCS_CSCR_PS_16 |
+                MCF_FBCS_CSCR_AA |
+                MCF_FBCS_CSCR_SBM |
+                MCF_FBCS_CSCR_WS(1),
+                MCF_FBCS1_CSCR);
+        writel(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
 
         /* Boot Flash connected to FBCS0 */
-        MCF_FBCS0_CSAR = FLASH_ADDRESS;
-        MCF_FBCS0_CSCR = (MCF_FBCS_CSCR_PS_16
-                        | MCF_FBCS_CSCR_BEM
-                        | MCF_FBCS_CSCR_AA
-                        | MCF_FBCS_CSCR_SBM
-                        | MCF_FBCS_CSCR_WS(7));
-        MCF_FBCS0_CSMR = (MCF_FBCS_CSMR_BAM_32M
-                        | MCF_FBCS_CSMR_V);
+        writel(FLASH_ADDRESS, MCF_FBCS0_CSAR);
+        writel(MCF_FBCS_CSCR_PS_16 |
+                MCF_FBCS_CSCR_BEM |
+                MCF_FBCS_CSCR_AA |
+                MCF_FBCS_CSCR_SBM |
+                MCF_FBCS_CSCR_WS(7),
+                MCF_FBCS0_CSCR);
+        writel(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR);
 }
 
 void sdramc_init(void)
@@ -362,102 +368,102 @@ void sdramc_init(void)
          * Check to see if the SDRAM has already been initialized
          * by a run control tool
          */
-        if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) {
+        if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) {
                 /* SDRAM chip select initialization */
                 
                 /* Initialize SDRAM chip select */
-                MCF_SDRAMC_SDCS0 = (0
-                        | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS)
-                        | MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE));
+                writel(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) |
+                        MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE),
+                        MCF_SDRAMC_SDCS0);
 
         /*
          * Basic configuration and initialization
          */
-        MCF_SDRAMC_SDCFG1 = (0
-                | MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5 ))
-                | MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
-                | MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
-                | MCF_SDRAMC_SDCFG1_ACT2RW((int)((SDRAM_TRCD ) + 0.5))
-                | MCF_SDRAMC_SDCFG1_PRE2ACT((int)((SDRAM_TRP ) + 0.5))
-                | MCF_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC) ) + 0.5))
-                | MCF_SDRAMC_SDCFG1_WTLAT(3));
-        MCF_SDRAMC_SDCFG2 = (0
-                | MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL/2 + 1)
-                | MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL/2 + SDRAM_TWR)
-                | MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL+SDRAM_BL/2-1.0)+0.5))
-                | MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1));
+        writel(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) |
+                MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) |
+                MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL * 2) + 2)) |
+                MCF_SDRAMC_SDCFG1_ACT2RW((int)(SDRAM_TRCD + 0.5)) |
+                MCF_SDRAMC_SDCFG1_PRE2ACT((int)(SDRAM_TRP + 0.5)) |
+                MCF_SDRAMC_SDCFG1_REF2ACT((int)(SDRAM_TRFC + 0.5)) |
+                MCF_SDRAMC_SDCFG1_WTLAT(3),
+                MCF_SDRAMC_SDCFG1);
+        writel(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) |
+                MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL / 2 + SDRAM_TWR) |
+                MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL + SDRAM_BL / 2 - 1.0) + 0.5)) |
+                MCF_SDRAMC_SDCFG2_BL(SDRAM_BL - 1),
+                MCF_SDRAMC_SDCFG2);
 
             
         /*
          * Precharge and enable write to SDMR
          */
-        MCF_SDRAMC_SDCR = (0
-                | MCF_SDRAMC_SDCR_MODE_EN
-                | MCF_SDRAMC_SDCR_CKE
-                | MCF_SDRAMC_SDCR_DDR
-                | MCF_SDRAMC_SDCR_MUX(1)
-                | MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
-                | MCF_SDRAMC_SDCR_PS_16
-                | MCF_SDRAMC_SDCR_IPALL);            
+        writel(MCF_SDRAMC_SDCR_MODE_EN |
+                MCF_SDRAMC_SDCR_CKE |
+                MCF_SDRAMC_SDCR_DDR |
+                MCF_SDRAMC_SDCR_MUX(1) |
+                MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI / (SYSTEM_PERIOD * 64)) - 1) + 0.5)) |
+                MCF_SDRAMC_SDCR_PS_16 |
+                MCF_SDRAMC_SDCR_IPALL,
+                MCF_SDRAMC_SDCR);
 
         /*
          * Write extended mode register
          */
-        MCF_SDRAMC_SDMR = (0
-                | MCF_SDRAMC_SDMR_BNKAD_LEMR
-                | MCF_SDRAMC_SDMR_AD(0x0)
-                | MCF_SDRAMC_SDMR_CMD);
+        writel(MCF_SDRAMC_SDMR_BNKAD_LEMR |
+                MCF_SDRAMC_SDMR_AD(0x0) |
+                MCF_SDRAMC_SDMR_CMD,
+                MCF_SDRAMC_SDMR);
 
         /*
          * Write mode register and reset DLL
          */
-        MCF_SDRAMC_SDMR = (0
-                | MCF_SDRAMC_SDMR_BNKAD_LMR
-                | MCF_SDRAMC_SDMR_AD(0x163)
-                | MCF_SDRAMC_SDMR_CMD);
+        writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
+                MCF_SDRAMC_SDMR_AD(0x163) |
+                MCF_SDRAMC_SDMR_CMD,
+                MCF_SDRAMC_SDMR);
 
         /*
          * Execute a PALL command
          */
-        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
+        writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR);
 
         /*
          * Perform two REF cycles
          */
-        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
-        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
+        writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
+        writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
 
         /*
          * Write mode register and clear reset DLL
          */
-        MCF_SDRAMC_SDMR = (0
-                | MCF_SDRAMC_SDMR_BNKAD_LMR
-                | MCF_SDRAMC_SDMR_AD(0x063)
-                | MCF_SDRAMC_SDMR_CMD);
+        writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
+                MCF_SDRAMC_SDMR_AD(0x063) |
+                MCF_SDRAMC_SDMR_CMD,
+                MCF_SDRAMC_SDMR);
                                 
         /*
          * Enable auto refresh and lock SDMR
          */
-        MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
-        MCF_SDRAMC_SDCR |= (0
-                | MCF_SDRAMC_SDCR_REF
-                | MCF_SDRAMC_SDCR_DQS_OE(0xC));
+        writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN,
+                MCF_SDRAMC_SDCR);
+        writel(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC),
+                MCF_SDRAMC_SDCR);
         }
 }
 
 void gpio_init(void)
 {
         /* Enable UART0 pins */
-        MCF_GPIO_PAR_UART = ( 0
-                | MCF_GPIO_PAR_UART_PAR_URXD0
-                | MCF_GPIO_PAR_UART_PAR_UTXD0);
-
-        /* Initialize TIN3 as a GPIO output to enable the write
-           half of the latch */
-        MCF_GPIO_PAR_TIMER = 0x00;
-        __raw_writeb(0x08, MCFGPIO_PDDR_TIMER);
-        __raw_writeb(0x00, MCFGPIO_PCLRR_TIMER);
+        writew(MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0,
+                MCFGPIO_PAR_UART);
 
+        /*
+         * Initialize TIN3 as a GPIO output to enable the write
+         * half of the latch.
+         */
+        writeb(0x00, MCFGPIO_PAR_TIMER);
+        writeb(0x08, MCFGPIO_PDDR_TIMER);
+        writeb(0x00, MCFGPIO_PCLRR_TIMER);
 }
 
 int clock_pll(int fsys, int flags)
@@ -469,7 +475,7 @@ int clock_pll(int fsys, int flags)
         
         if (fsys == 0) {
                 /* Return current PLL output */
-                mfd = MCF_PLL_PFDR;
+                mfd = readb(MCF_PLL_PFDR);
 
                 return (fref * mfd / (BUSDIV * 4));
         }
@@ -495,9 +501,10 @@ int clock_pll(int fsys, int flags)
          * If it has then the SDRAM needs to be put into self refresh
          * mode before reprogramming the PLL.
          */
-        if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
+        if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
                 /* Put SDRAM into self refresh mode */
-                MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
+                writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
+                        MCF_SDRAMC_SDCR);
 
         /*
          * Initialize the PLL to generate the new system clock frequency.
@@ -508,11 +515,10 @@ int clock_pll(int fsys, int flags)
         clock_limp(DEFAULT_LPD);
                                         
         /* Reprogram PLL for desired fsys */
-        MCF_PLL_PODR = (0
-                | MCF_PLL_PODR_CPUDIV(BUSDIV/3)
-                | MCF_PLL_PODR_BUSDIV(BUSDIV));
+        writeb(MCF_PLL_PODR_CPUDIV(BUSDIV/3) | MCF_PLL_PODR_BUSDIV(BUSDIV),
+                MCF_PLL_PODR);
                                                 
-        MCF_PLL_PFDR = mfd;
+        writeb(mfd, MCF_PLL_PFDR);
                 
         /* Exit LIMP mode */
         clock_exit_limp();
@@ -520,12 +526,13 @@ int clock_pll(int fsys, int flags)
         /*
          * Return the SDRAM to normal operation if it is in use.
          */
-        if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
+        if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
                 /* Exit self refresh mode */
-                MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;
+                writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
+                        MCF_SDRAMC_SDCR);
 
         /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */
-        MCF_SDRAMC_LIMP_FIX = MCF_SDRAMC_REFRESH;
+        writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
 
         /* wait for DQS logic to relock */
         for (i = 0; i < 0x200; i++)
@@ -546,14 +553,12 @@ int clock_limp(int div)
     
         /* Save of the current value of the SSIDIV so we don't
            overwrite the value*/
-        temp = (MCF_CCM_CDR & MCF_CCM_CDR_SSIDIV(0xF));
+        temp = readw(MCF_CCM_CDR) & MCF_CCM_CDR_SSIDIV(0xF);
       
         /* Apply the divider to the system clock */
-        MCF_CCM_CDR = ( 0
-                | MCF_CCM_CDR_LPDIV(div)
-                | MCF_CCM_CDR_SSIDIV(temp));
+        writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR);
     
-        MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP;
+        writew(readw(MCF_CCM_MISCCR) | MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
     
         return (FREF/(3*(1 << div)));
 }
@@ -563,10 +568,10 @@ int clock_exit_limp(void)
         int fout;
         
         /* Exit LIMP mode */
-        MCF_CCM_MISCCR = (MCF_CCM_MISCCR & ~ MCF_CCM_MISCCR_LIMP);
+        writew(readw(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
 
         /* Wait for PLL to lock */
-        while (!(MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK))
+        while (!(readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_PLL_LOCK))
                 ;
         
         fout = get_sys_clock();
@@ -579,10 +584,10 @@ int get_sys_clock(void)
         int divider;
         
         /* Test to see if device is in LIMP mode */
-        if (MCF_CCM_MISCCR & MCF_CCM_MISCCR_LIMP) {
-                divider = MCF_CCM_CDR & MCF_CCM_CDR_LPDIV(0xF);
+        if (readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_LIMP) {
+                divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF);
                 return (FREF/(2 << divider));
         }
         else
-                return ((FREF * MCF_PLL_PFDR) / (BUSDIV * 4));
+                return (FREF * readb(MCF_PLL_PFDR)) / (BUSDIV * 4);
 }
diff --git a/arch/m68k/platform/coldfire/m54xx.c b/arch/m68k/platform/coldfire/m54xx.c
index 2081c6cbb3de..b587bf35175b 100644
--- a/arch/m68k/platform/coldfire/m54xx.c
+++ b/arch/m68k/platform/coldfire/m54xx.c
@@ -30,14 +30,12 @@
 static void __init m54xx_uarts_init(void)
 {
         /* enable io pins */
-        __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD,
-                MCF_MBAR + MCF_PAR_PSC(0));
+        __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
         __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
-                MCF_MBAR + MCF_PAR_PSC(1));
+                MCFGPIO_PAR_PSC1);
         __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
-                MCF_PAR_PSC_CTS_CTS, MCF_MBAR + MCF_PAR_PSC(2));
-        __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD,
-                MCF_MBAR + MCF_PAR_PSC(3));
+                MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
+        __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
 }
 
 /***************************************************************************/
@@ -46,10 +44,10 @@ static void mcf54xx_reset(void)
 {
         /* disable interrupts and enable the watchdog */
         asm("movew #0x2700, %sr\n");
-        __raw_writel(0, MCF_MBAR + MCF_GPT_GMS0);
-        __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0);
+        __raw_writel(0, MCF_GPT_GMS0);
+        __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
         __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
-                                                MCF_MBAR + MCF_GPT_GMS0);
+                MCF_GPT_GMS0);
 }
 
 /***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/nettel.c b/arch/m68k/platform/coldfire/nettel.c
index e925ea4602f8..ddc48ec1b800 100644
--- a/arch/m68k/platform/coldfire/nettel.c
+++ b/arch/m68k/platform/coldfire/nettel.c
@@ -121,14 +121,14 @@ static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flasha
 
 static void __init nettel_smc91x_init(void)
 {
-        writew(0x00ec, MCF_MBAR + MCFSIM_PADDR);
+        writew(0x00ec, MCFSIM_PADDR);
         mcf_setppdata(0, 0x0080);
         writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
         writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR);
         mcf_setppdata(0x0080, 0);
 
         /* Set correct chip select timing for SMC9196 accesses */
-        writew(0x1180, MCF_MBAR + MCFSIM_CSCR3);
+        writew(0x1180, MCFSIM_CSCR3);
 
         /* Set the SMC interrupts to be auto-vectored */
         mcf_autovector(NETTEL_SMC0_IRQ);
diff --git a/arch/m68k/platform/coldfire/pci.c b/arch/m68k/platform/coldfire/pci.c
index 553210d3d4c1..8572246db84d 100644
--- a/arch/m68k/platform/coldfire/pci.c
+++ b/arch/m68k/platform/coldfire/pci.c
@@ -272,8 +272,8 @@ static int __init mcf_pci_init(void)
                 PACR_EXTMINTE(0x1f), PACR);
 
         /* Set required multi-function pins for PCI bus use */
-        __raw_writew(0x3ff, MCF_PAR_PCIBG);
-        __raw_writew(0x3ff, MCF_PAR_PCIBR);
+        __raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
+        __raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
 
         /* Set up config space for local host bus controller */
         __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
diff --git a/arch/m68k/platform/coldfire/reset.c b/arch/m68k/platform/coldfire/reset.c
index 933e54eacc69..f30952f0cbe6 100644
--- a/arch/m68k/platform/coldfire/reset.c
+++ b/arch/m68k/platform/coldfire/reset.c
@@ -27,7 +27,7 @@ static void mcf_cpu_reset(void)
 {
         local_irq_disable();
         /* Set watchdog to soft reset, and enabled */
-        __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
+        __raw_writeb(0xc0, MCFSIM_SYPCR);
         for (;;)
                 /* wait for watchdog to timeout */;
 }
diff --git a/arch/m68k/platform/coldfire/sltimers.c b/arch/m68k/platform/coldfire/sltimers.c
index 2027fc20b876..bb5a25ada848 100644
--- a/arch/m68k/platform/coldfire/sltimers.c
+++ b/arch/m68k/platform/coldfire/sltimers.c
@@ -32,7 +32,7 @@
 /*
  *      By default use Slice Timer 1 as the profiler clock timer.
  */
-#define PA(a)   (MCF_MBAR + MCFSLT_TIMER1 + (a))
+#define PA(a)   (MCFSLT_TIMER1 + (a))
 
 /*
  *      Choose a reasonably fast profile timer. Make it an odd value to
@@ -76,7 +76,7 @@ void mcfslt_profile_init(void)
 /*
  *      By default use Slice Timer 0 as the system clock timer.
  */
-#define TA(a)   (MCF_MBAR + MCFSLT_TIMER0 + (a))
+#define TA(a)   (MCFSLT_TIMER0 + (a))
 
 static u32 mcfslt_cycles_per_jiffy;
 static u32 mcfslt_cnt;
diff --git a/arch/m68k/platform/coldfire/timers.c b/arch/m68k/platform/coldfire/timers.c
index 0a273e75408c..51f6d2af807f 100644
--- a/arch/m68k/platform/coldfire/timers.c
+++ b/arch/m68k/platform/coldfire/timers.c
@@ -56,13 +56,13 @@ static void init_timer_irq(void)
 #ifdef MCFSIM_ICR_AUTOVEC
         /* Timer1 is always used as system timer */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
-                MCF_MBAR + MCFSIM_TIMER1ICR);
+                MCFSIM_TIMER1ICR);
         mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
 
 #ifdef CONFIG_HIGHPROFILE
         /* Timer2 is to be used as a high speed profile timer  */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
-                MCF_MBAR + MCFSIM_TIMER2ICR);
+                MCFSIM_TIMER2ICR);
         mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
 #endif
 #endif /* MCFSIM_ICR_AUTOVEC */
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index ab9afcaa7f6a..6133bed2b855 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -243,14 +243,11 @@ choice
 config MICROBLAZE_4K_PAGES
         bool "4k page size"
 
-config MICROBLAZE_8K_PAGES
-        bool "8k page size"
-
 config MICROBLAZE_16K_PAGES
         bool "16k page size"
 
-config MICROBLAZE_32K_PAGES
-        bool "32k page size"
+config MICROBLAZE_64K_PAGES
+        bool "64k page size"
 
 endchoice
 
diff --git a/arch/microblaze/include/asm/clinkage.h b/arch/microblaze/include/asm/clinkage.h
deleted file mode 100644
index 9e218435a55c..000000000000
--- a/arch/microblaze/include/asm/clinkage.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <linux/linkage.h>
diff --git a/arch/microblaze/include/asm/elf.h b/arch/microblaze/include/asm/elf.h
index 834849f59ae8..640ddd4b6a9b 100644
--- a/arch/microblaze/include/asm/elf.h
+++ b/arch/microblaze/include/asm/elf.h
@@ -116,7 +116,8 @@ do {							\
 } while (0)
 
 #ifdef __KERNEL__
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX_32BIT)
+#define SET_PERSONALITY(ex) \
+        set_personality(PER_LINUX_32BIT | (current->personality & (~PER_MASK)))
 #endif
 
 #endif /* __uClinux__ */
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index 8cdac14b55b0..4fbfdc1ac7f8 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -35,6 +35,10 @@ extern resource_size_t isa_mem_base;
 
 #define IO_SPACE_LIMIT (0xFFFFFFFF)
 
+/* the following is needed to support PCI with some drivers */
+
+#define mmiowb()
+
 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
 {
         return *(volatile unsigned char __force *)addr;
@@ -248,4 +252,94 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
 #define ioport_map(port, nr)    ((void __iomem *)(port))
 #define ioport_unmap(addr)
 
+/* from asm-generic/io.h */
+#ifndef insb
+static inline void insb(unsigned long addr, void *buffer, int count)
+{
+        if (count) {
+                u8 *buf = buffer;
+                do {
+                        u8 x = inb(addr);
+                        *buf++ = x;
+                } while (--count);
+        }
+}
+#endif
+
+#ifndef insw
+static inline void insw(unsigned long addr, void *buffer, int count)
+{
+        if (count) {
+                u16 *buf = buffer;
+                do {
+                        u16 x = inw(addr);
+                        *buf++ = x;
+                } while (--count);
+        }
+}
+#endif
+
+#ifndef insl
+static inline void insl(unsigned long addr, void *buffer, int count)
+{
+        if (count) {
+                u32 *buf = buffer;
+                do {
+                        u32 x = inl(addr);
+                        *buf++ = x;
+                } while (--count);
+        }
+}
+#endif
+
+#ifndef outsb
+static inline void outsb(unsigned long addr, const void *buffer, int count)
+{
+        if (count) {
+                const u8 *buf = buffer;
+                do {
+                        outb(*buf++, addr);
+                } while (--count);
+        }
+}
+#endif
+
+#ifndef outsw
+static inline void outsw(unsigned long addr, const void *buffer, int count)
+{
+        if (count) {
+                const u16 *buf = buffer;
+                do {
+                        outw(*buf++, addr);
+                } while (--count);
+        }
+}
+#endif
+
+#ifndef outsl
+static inline void outsl(unsigned long addr, const void *buffer, int count)
+{
+        if (count) {
+                const u32 *buf = buffer;
+                do {
+                        outl(*buf++, addr);
+                } while (--count);
+        }
+}
+#endif
+
+#define ioread8_rep(p, dst, count) \
+        insb((unsigned long) (p), (dst), (count))
+#define ioread16_rep(p, dst, count) \
+        insw((unsigned long) (p), (dst), (count))
+#define ioread32_rep(p, dst, count) \
+        insl((unsigned long) (p), (dst), (count))
+
+#define iowrite8_rep(p, src, count) \
+        outsb((unsigned long) (p), (src), (count))
+#define iowrite16_rep(p, src, count) \
+        outsw((unsigned long) (p), (src), (count))
+#define iowrite32_rep(p, src, count) \
+        outsl((unsigned long) (p), (src), (count))
+
 #endif /* _ASM_MICROBLAZE_IO_H */
diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h
index 287c5485d286..85a5ae8e9bd0 100644
--- a/arch/microblaze/include/asm/page.h
+++ b/arch/microblaze/include/asm/page.h
@@ -23,12 +23,10 @@
 #ifdef __KERNEL__
 
 /* PAGE_SHIFT determines the page size */
-#if defined(CONFIG_MICROBLAZE_32K_PAGES)
-#define PAGE_SHIFT              15
+#if defined(CONFIG_MICROBLAZE_64K_PAGES)
+#define PAGE_SHIFT              16
 #elif defined(CONFIG_MICROBLAZE_16K_PAGES)
 #define PAGE_SHIFT              14
-#elif defined(CONFIG_MICROBLAZE_8K_PAGES)
-#define PAGE_SHIFT              13
 #else
 #define PAGE_SHIFT              12
 #endif
@@ -37,6 +35,8 @@
 
 #define LOAD_OFFSET     ASM_CONST((CONFIG_KERNEL_START-CONFIG_KERNEL_BASE_ADDR))
 
+#define PTE_SHIFT       (PAGE_SHIFT - 2)        /* 1024 ptes per page */
+
 #ifndef __ASSEMBLY__
 
 /* MS be sure that SLAB allocates aligned objects */
@@ -71,7 +71,6 @@ extern unsigned int __page_offset;
  * The basic type of a PTE - 32 bit physical addressing.
  */
 typedef unsigned long pte_basic_t;
-#define PTE_SHIFT       (PAGE_SHIFT - 2)        /* 1024 ptes per page */
 #define PTE_FMT         "%.8lx"
 
 #endif /* CONFIG_MMU */
diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h
index a0da88bf70c5..41cc841091b0 100644
--- a/arch/microblaze/include/asm/pci.h
+++ b/arch/microblaze/include/asm/pci.h
@@ -22,6 +22,8 @@
 #include <asm/prom.h>
 #include <asm/pci-bridge.h>
 
+#include <asm-generic/pci-dma-compat.h>
+
 #define PCIBIOS_MIN_IO          0x1000
 #define PCIBIOS_MIN_MEM         0x10000000
 
diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
index 3ef7b9cafeca..a7311cd9dee0 100644
--- a/arch/microblaze/include/asm/pgtable.h
+++ b/arch/microblaze/include/asm/pgtable.h
@@ -234,12 +234,6 @@ static inline pte_t pte_mkspecial(pte_t pte)	{ return pte; }
 #ifndef _PAGE_SHARED
 #define _PAGE_SHARED    0
 #endif
-#ifndef _PAGE_HWWRITE
-#define _PAGE_HWWRITE   0
-#endif
-#ifndef _PAGE_HWEXEC
-#define _PAGE_HWEXEC    0
-#endif
 #ifndef _PAGE_EXEC
 #define _PAGE_EXEC      0
 #endif
diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S
index 98b17f9f904b..eef84de5e8c8 100644
--- a/arch/microblaze/kernel/head.S
+++ b/arch/microblaze/kernel/head.S
@@ -109,20 +109,24 @@ no_fdt_arg:
 #ifndef CONFIG_CMDLINE_BOOL
 /*
  * handling command line
- * copy command line to __init_end. There is space for storing command line.
+ * copy command line directly to cmd_line placed in data section.
  */
+        beqid   r5, skip        /* Skip if NULL pointer */
         or      r6, r0, r0              /* incremment */
-        ori     r4, r0, __init_end      /* load address of command line */
+        ori     r4, r0, cmd_line        /* load address of command line */
         tophys(r4,r4)                   /* convert to phys address */
         ori     r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
 _copy_command_line:
-        lbu     r2, r5, r6 /* r2=r5+r6 - r5 contain pointer to command line */
-        sb      r2, r4, r6              /* addr[r4+r6]= r2*/
+        /* r2=r5+r6 - r5 contain pointer to command line */
+        lbu             r2, r5, r6
+        beqid   r2, skip                /* Skip if no data */
+        sb              r2, r4, r6              /* addr[r4+r6]= r2*/
         addik   r6, r6, 1               /* increment counting */
         bgtid   r3, _copy_command_line  /* loop for all entries       */
-        addik   r3, r3, -1              /* descrement loop */
+        addik   r3, r3, -1              /* decrement loop */
         addik   r5, r4, 0               /* add new space for command line */
         tovirt(r5,r5)
+skip:
 #endif /* CONFIG_CMDLINE_BOOL */
 
 #ifdef NOT_COMPILE
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index aa510f450ac6..61b3a1fed46f 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -75,6 +75,7 @@
 #include <asm/mmu.h>
 #include <asm/pgtable.h>
 #include <asm/signal.h>
+#include <asm/registers.h>
 #include <asm/asm-offsets.h>
 
 #undef DEBUG
@@ -581,7 +582,7 @@ ex_handler_done:
                  * tried to access a kernel or read-protected page - always
                  * a SEGV). All other faults here must be stores, so no
                  * need to check ESR_S as well. */
-                andi    r4, r4, 0x800           /* ESR_Z - zone protection */
+                andi    r4, r4, ESR_DIZ         /* ESR_Z - zone protection */
                 bnei    r4, ex2
 
                 ori     r4, r0, swapper_pg_dir
@@ -595,25 +596,25 @@ ex_handler_done:
                  * tried to access a kernel or read-protected page - always
                  * a SEGV). All other faults here must be stores, so no
                  * need to check ESR_S as well. */
-                andi    r4, r4, 0x800           /* ESR_Z */
+                andi    r4, r4, ESR_DIZ         /* ESR_Z */
                 bnei    r4, ex2
                 /* get current task address */
                 addi    r4 ,CURRENT_TASK, TOPHYS(0);
                 lwi     r4, r4, TASK_THREAD+PGDIR
         ex4:
                 tophys(r4,r4)
-                BSRLI(r5,r3,20)         /* Create L1 (pgdir/pmd) address */
-                andi    r5, r5, 0xffc
+                /* Create L1 (pgdir/pmd) address */
+                BSRLI(r5,r3, PGDIR_SHIFT - 2)
+                andi    r5, r5, PAGE_SIZE - 4
 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
                 or      r4, r4, r5
                 lwi     r4, r4, 0               /* Get L1 entry */
-                andi    r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
+                andi    r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
                 beqi    r5, ex2                 /* Bail if no table */
 
                 tophys(r5,r5)
-                BSRLI(r6,r3,10)                 /* Compute PTE address */
-                andi    r6, r6, 0xffc
-                andi    r5, r5, 0xfffff003
+                BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
+                andi    r6, r6, PAGE_SIZE - 4
                 or      r5, r5, r6
                 lwi     r4, r5, 0               /* Get Linux PTE */
 
@@ -632,7 +633,9 @@ ex_handler_done:
                  * Many of these bits are software only. Bits we don't set
                  * here we (properly should) assume have the appropriate value.
                  */
-                andni   r4, r4, 0x0ce2          /* Make sure 20, 21 are zero */
+/* Ignore memory coherent, just LSB on ZSEL is used + EX/WR */
+                andi    r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
+                                                TLB_ZSEL(1) | TLB_ATTR_MASK
                 ori     r4, r4, _PAGE_HWEXEC    /* make it executable */
 
                 /* find the TLB index that caused the fault. It has to be here*/
@@ -701,18 +704,18 @@ ex_handler_done:
                 lwi     r4, r4, TASK_THREAD+PGDIR
         ex6:
                 tophys(r4,r4)
-                BSRLI(r5,r3,20)         /* Create L1 (pgdir/pmd) address */
-                andi    r5, r5, 0xffc
+                /* Create L1 (pgdir/pmd) address */
+                BSRLI(r5,r3, PGDIR_SHIFT - 2)
+                andi    r5, r5, PAGE_SIZE - 4
 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
                 or      r4, r4, r5
                 lwi     r4, r4, 0               /* Get L1 entry */
-                andi    r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
+                andi    r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
                 beqi    r5, ex7                 /* Bail if no table */
 
                 tophys(r5,r5)
-                BSRLI(r6,r3,10)                 /* Compute PTE address */
-                andi    r6, r6, 0xffc
-                andi    r5, r5, 0xfffff003
+                BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
+                andi    r6, r6, PAGE_SIZE - 4
                 or      r5, r5, r6
                 lwi     r4, r5, 0               /* Get Linux PTE */
 
@@ -731,7 +734,8 @@ ex_handler_done:
                  * here we (properly should) assume have the appropriate value.
                  */
                 brid    finish_tlb_load
-                andni   r4, r4, 0x0ce2          /* Make sure 20, 21 are zero */
+                andi    r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
+                                                TLB_ZSEL(1) | TLB_ATTR_MASK
         ex7:
                 /* The bailout. Restore registers to pre-exception conditions
                  * and call the heavyweights to help us out.
@@ -771,18 +775,18 @@ ex_handler_done:
                 lwi     r4, r4, TASK_THREAD+PGDIR
         ex9:
                 tophys(r4,r4)
-                BSRLI(r5,r3,20)         /* Create L1 (pgdir/pmd) address */
-                andi    r5, r5, 0xffc
+                /* Create L1 (pgdir/pmd) address */
+                BSRLI(r5,r3, PGDIR_SHIFT - 2)
+                andi    r5, r5, PAGE_SIZE - 4
 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
                 or      r4, r4, r5
                 lwi     r4, r4, 0               /* Get L1 entry */
-                andi    r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
+                andi    r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
                 beqi    r5, ex10                /* Bail if no table */
 
                 tophys(r5,r5)
-                BSRLI(r6,r3,10)                 /* Compute PTE address */
-                andi    r6, r6, 0xffc
-                andi    r5, r5, 0xfffff003
+                BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
+                andi    r6, r6, PAGE_SIZE - 4
                 or      r5, r5, r6
                 lwi     r4, r5, 0               /* Get Linux PTE */
 
@@ -801,7 +805,8 @@ ex_handler_done:
                  * here we (properly should) assume have the appropriate value.
                  */
                 brid    finish_tlb_load
-                andni   r4, r4, 0x0ce2          /* Make sure 20, 21 are zero */
+                andi    r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
+                                                TLB_ZSEL(1) | TLB_ATTR_MASK
         ex10:
                 /* The bailout. Restore registers to pre-exception conditions
                  * and call the heavyweights to help us out.
@@ -854,8 +859,14 @@ ex_handler_done:
                  * set of bits. These are size, valid, E, U0, and ensure
                  * bits 20 and 21 are zero.
                  */
-                andi    r3, r3, 0xfffff000
-                ori     r3, r3, 0x0c0
+                andi    r3, r3, PAGE_MASK
+#ifdef CONFIG_MICROBLAZE_64K_PAGES
+                ori     r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_64K)
+#elif CONFIG_MICROBLAZE_16K_PAGES
+                ori     r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_16K)
+#else
+                ori     r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_4K)
+#endif
                 mts     rtlbhi, r3              /* Load TLB HI */
                 nop
 
diff --git a/arch/microblaze/kernel/reset.c b/arch/microblaze/kernel/reset.c
index 88a01636f785..2e5079ab53d2 100644
--- a/arch/microblaze/kernel/reset.c
+++ b/arch/microblaze/kernel/reset.c
@@ -26,13 +26,14 @@ void of_platform_reset_gpio_probe(void)
                                    "hard-reset-gpios", 0);
 
         if (!gpio_is_valid(handle)) {
-                printk(KERN_INFO "Skipping unavailable RESET gpio %d (%s)\n",
+                pr_info("Skipping unavailable RESET gpio %d (%s)\n",
                                 handle, "reset");
+                return;
         }
 
         ret = gpio_request(handle, "reset");
         if (ret < 0) {
-                printk(KERN_INFO "GPIO pin is already allocated\n");
+                pr_info("GPIO pin is already allocated\n");
                 return;
         }
 
@@ -49,7 +50,7 @@ void of_platform_reset_gpio_probe(void)
         /* Setup output direction */
         gpio_set_value(handle, 0);
 
-        printk(KERN_INFO "RESET: Registered gpio device: %d, current val: %d\n",
+        pr_info("RESET: Registered gpio device: %d, current val: %d\n",
                                                         handle, reset_val);
         return;
 err:
@@ -60,7 +61,10 @@ err:
 
 static void gpio_system_reset(void)
 {
-        gpio_set_value(handle, 1 - reset_val);
+        if (gpio_is_valid(handle))
+                gpio_set_value(handle, 1 - reset_val);
+        else
+                pr_notice("Reset GPIO unavailable - halting!\n");
 }
 #else
 #define gpio_system_reset() do {} while (0)
@@ -72,30 +76,29 @@ void of_platform_reset_gpio_probe(void)
 
 void machine_restart(char *cmd)
 {
-        printk(KERN_NOTICE "Machine restart...\n");
+        pr_notice("Machine restart...\n");
         gpio_system_reset();
-        dump_stack();
         while (1)
                 ;
 }
 
 void machine_shutdown(void)
 {
-        printk(KERN_NOTICE "Machine shutdown...\n");
+        pr_notice("Machine shutdown...\n");
         while (1)
                 ;
 }
 
 void machine_halt(void)
 {
-        printk(KERN_NOTICE "Machine halt...\n");
+        pr_notice("Machine halt...\n");
         while (1)
                 ;
 }
 
 void machine_power_off(void)
 {
-        printk(KERN_NOTICE "Machine power off...\n");
+        pr_notice("Machine power off...\n");
         while (1)
                 ;
 }
diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c
index 4da971d4392f..954348f83505 100644
--- a/arch/microblaze/kernel/setup.c
+++ b/arch/microblaze/kernel/setup.c
@@ -40,7 +40,12 @@ DEFINE_PER_CPU(unsigned int, R11_SAVE);	/* Temp variable for entry */
 DEFINE_PER_CPU(unsigned int, CURRENT_SAVE);     /* Saved current pointer */
 
 unsigned int boot_cpuid;
-char cmd_line[COMMAND_LINE_SIZE];
+/*
+ * Placed cmd_line to .data section because can be initialized from
+ * ASM code. Default position is BSS section which is cleared
+ * in machine_early_init().
+ */
+char cmd_line[COMMAND_LINE_SIZE] __attribute__ ((section(".data")));
 
 void __init setup_arch(char **cmdline_p)
 {
@@ -64,7 +69,7 @@ void __init setup_arch(char **cmdline_p)
         xilinx_pci_init();
 
 #if defined(CONFIG_SELFMOD_INTC) || defined(CONFIG_SELFMOD_TIMER)
-        printk(KERN_NOTICE "Self modified code enable\n");
+        pr_notice("Self modified code enable\n");
 #endif
 
 #ifdef CONFIG_VT
@@ -130,12 +135,6 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
         memset(__bss_start, 0, __bss_stop-__bss_start);
         memset(_ssbss, 0, _esbss-_ssbss);
 
-        /* Copy command line passed from bootloader */
-#ifndef CONFIG_CMDLINE_BOOL
-        if (cmdline && cmdline[0] != '\0')
-                strlcpy(cmd_line, cmdline, COMMAND_LINE_SIZE);
-#endif
-
         lockdep_init();
 
 /* initialize device tree for usage in early_printk */
diff --git a/arch/microblaze/kernel/signal.c b/arch/microblaze/kernel/signal.c
index 76b9722557db..c1220dbf87cd 100644
--- a/arch/microblaze/kernel/signal.c
+++ b/arch/microblaze/kernel/signal.c
@@ -290,15 +290,7 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
         case -ERESTARTNOINTR:
 do_restart:
                 /* offset of 4 bytes to re-execute trap (brki) instruction */
-#ifndef CONFIG_MMU
                 regs->pc -= 4;
-#else
-                /* offset of 8 bytes required = 4 for rtbd
-                   offset, plus 4 for size of
-                        "brki r14,8"
-                   instruction. */
-                regs->pc -= 8;
-#endif
                 break;
         }
 }
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
index 522defa7d41f..aec5020a6e31 100644
--- a/arch/microblaze/kernel/timer.c
+++ b/arch/microblaze/kernel/timer.c
@@ -116,21 +116,21 @@ static void microblaze_timer_set_mode(enum clock_event_mode mode,
 {
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
-                printk(KERN_INFO "%s: periodic\n", __func__);
+                pr_info("%s: periodic\n", __func__);
                 microblaze_timer0_start_periodic(freq_div_hz);
                 break;
         case CLOCK_EVT_MODE_ONESHOT:
-                printk(KERN_INFO "%s: oneshot\n", __func__);
+                pr_info("%s: oneshot\n", __func__);
                 break;
         case CLOCK_EVT_MODE_UNUSED:
-                printk(KERN_INFO "%s: unused\n", __func__);
+                pr_info("%s: unused\n", __func__);
                 break;
         case CLOCK_EVT_MODE_SHUTDOWN:
-                printk(KERN_INFO "%s: shutdown\n", __func__);
+                pr_info("%s: shutdown\n", __func__);
                 microblaze_timer0_stop();
                 break;
         case CLOCK_EVT_MODE_RESUME:
-                printk(KERN_INFO "%s: resume\n", __func__);
+                pr_info("%s: resume\n", __func__);
                 break;
         }
 }
@@ -257,7 +257,15 @@ void __init time_init(void)
                                 0
                         };
 #endif
-        timer = of_find_compatible_node(NULL, NULL, "xlnx,xps-timer-1.00.a");
+        prop = of_get_property(of_chosen, "system-timer", NULL);
+        if (prop)
+                timer = of_find_node_by_phandle(be32_to_cpup(prop));
+        else
+                pr_info("No chosen timer found, using default\n");
+
+        if (!timer)
+                timer = of_find_compatible_node(NULL, NULL,
+                                                "xlnx,xps-timer-1.00.a");
         BUG_ON(!timer);
 
         timer_baseaddr = be32_to_cpup(of_get_property(timer, "reg", NULL));
@@ -266,14 +274,14 @@ void __init time_init(void)
         timer_num = be32_to_cpup(of_get_property(timer,
                                                 "xlnx,one-timer-only", NULL));
         if (timer_num) {
-                printk(KERN_EMERG "Please enable two timers in HW\n");
+                pr_emerg("Please   enable two timers in HW\n");
                 BUG();
         }
 
 #ifdef CONFIG_SELFMOD_TIMER
         selfmod_function((int *) arr_func, timer_baseaddr);
 #endif
-        printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n",
+        pr_info("%s #0 at 0x%08x, irq=%d\n",
                 timer->name, timer_baseaddr, irq);
 
         /* If there is clock-frequency property than use it */
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 764e37a9dbb3..654b1ad39f05 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -225,7 +225,7 @@ KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)
 LDFLAGS                 += -m $(ld-emul)
 
 ifdef CONFIG_MIPS
-CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -xc /dev/null | \
+CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -x c /dev/null | \
         egrep -vw '__GNUC_(|MINOR_|PATCHLEVEL_)_' | \
         sed -e "s/^\#define /-D'/" -e "s/ /'='/" -e "s/$$/'/")
 ifdef CONFIG_64BIT
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index feb05258a4d1..dd18e4b761a8 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -632,7 +632,7 @@ static struct board_info __initdata board_DWVS0 = {
 /*
  * all boards
  */
-static const struct board_info __initdata *bcm963xx_boards[] = {
+static const struct board_info __initconst *bcm963xx_boards[] = {
 #ifdef CONFIG_BCM63XX_CPU_6328
         &board_96328avng,
 #endif
diff --git a/arch/mips/include/asm/compat-signal.h b/arch/mips/include/asm/compat-signal.h
index 368a99e5c3e1..6599a901b63e 100644
--- a/arch/mips/include/asm/compat-signal.h
+++ b/arch/mips/include/asm/compat-signal.h
@@ -10,68 +10,6 @@
 
 #include <asm/uaccess.h>
 
-#define SI_PAD_SIZE32   ((SI_MAX_SIZE/sizeof(int)) - 3)
-
-typedef struct compat_siginfo {
-        int si_signo;
-        int si_code;
-        int si_errno;
-
-        union {
-                int _pad[SI_PAD_SIZE32];
-
-                /* kill() */
-                struct {
-                        compat_pid_t _pid;      /* sender's pid */
-                        compat_uid_t _uid;      /* sender's uid */
-                } _kill;
-
-                /* SIGCHLD */
-                struct {
-                        compat_pid_t _pid;      /* which child */
-                        compat_uid_t _uid;      /* sender's uid */
-                        int _status;            /* exit code */
-                        compat_clock_t _utime;
-                        compat_clock_t _stime;
-                } _sigchld;
-
-                /* IRIX SIGCHLD */
-                struct {
-                        compat_pid_t _pid;      /* which child */
-                        compat_clock_t _utime;
-                        int _status;            /* exit code */
-                        compat_clock_t _stime;
-                } _irix_sigchld;
-
-                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
-                struct {
-                        s32 _addr; /* faulting insn/memory ref. */
-                } _sigfault;
-
-                /* SIGPOLL, SIGXFSZ (To do ...)  */
-                struct {
-                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
-                        int _fd;
-                } _sigpoll;
-
-                /* POSIX.1b timers */
-                struct {
-                        timer_t _tid;           /* timer id */
-                        int _overrun;           /* overrun count */
-                        compat_sigval_t _sigval;/* same as below */
-                        int _sys_private;       /* not to be passed to user */
-                } _timer;
-
-                /* POSIX.1b signals */
-                struct {
-                        compat_pid_t _pid;      /* sender's pid */
-                        compat_uid_t _uid;      /* sender's uid */
-                        compat_sigval_t _sigval;
-                } _rt;
-
-        } _sifields;
-} compat_siginfo_t;
-
 static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d,
         const sigset_t *s)
 {
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index b77df0366ee6..58277e0e9cd4 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -43,6 +43,7 @@ typedef s64		compat_s64;
 typedef u32             compat_uint_t;
 typedef u32             compat_ulong_t;
 typedef u64             compat_u64;
+typedef u32             compat_uptr_t;
 
 struct compat_timespec {
         compat_time_t   tv_sec;
@@ -124,6 +125,73 @@ typedef u32		compat_old_sigset_t;	/* at least 32 bits */
 
 typedef u32             compat_sigset_word;
 
+typedef union compat_sigval {
+        compat_int_t    sival_int;
+        compat_uptr_t   sival_ptr;
+} compat_sigval_t;
+
+#define SI_PAD_SIZE32   (128/sizeof(int) - 3)
+
+typedef struct compat_siginfo {
+        int si_signo;
+        int si_code;
+        int si_errno;
+
+        union {
+                int _pad[SI_PAD_SIZE32];
+
+                /* kill() */
+                struct {
+                        compat_pid_t _pid;      /* sender's pid */
+                        __compat_uid_t _uid;    /* sender's uid */
+                } _kill;
+
+                /* SIGCHLD */
+                struct {
+                        compat_pid_t _pid;      /* which child */
+                        __compat_uid_t _uid;    /* sender's uid */
+                        int _status;            /* exit code */
+                        compat_clock_t _utime;
+                        compat_clock_t _stime;
+                } _sigchld;
+
+                /* IRIX SIGCHLD */
+                struct {
+                        compat_pid_t _pid;      /* which child */
+                        compat_clock_t _utime;
+                        int _status;            /* exit code */
+                        compat_clock_t _stime;
+                } _irix_sigchld;
+
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+                struct {
+                        s32 _addr; /* faulting insn/memory ref. */
+                } _sigfault;
+
+                /* SIGPOLL, SIGXFSZ (To do ...)  */
+                struct {
+                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
+                        int _fd;
+                } _sigpoll;
+
+                /* POSIX.1b timers */
+                struct {
+                        timer_t _tid;           /* timer id */
+                        int _overrun;           /* overrun count */
+                        compat_sigval_t _sigval;/* same as below */
+                        int _sys_private;       /* not to be passed to user */
+                } _timer;
+
+                /* POSIX.1b signals */
+                struct {
+                        compat_pid_t _pid;      /* sender's pid */
+                        __compat_uid_t _uid;    /* sender's uid */
+                        compat_sigval_t _sigval;
+                } _rt;
+
+        } _sifields;
+} compat_siginfo_t;
+
 #define COMPAT_OFF_T_MAX        0x7fffffff
 #define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
 
@@ -133,7 +201,6 @@ typedef u32		compat_sigset_word;
  * as pointers because the syscall entry code will have
  * appropriately converted them already.
  */
-typedef u32             compat_uptr_t;
 
 static inline void __user *compat_ptr(compat_uptr_t uptr)
 {
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index fdaf65e1a99d..c6136cb4cd40 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -104,7 +104,7 @@ obj-$(CONFIG_MIPS_MACHINE)	+= mips_machine.o
 
 obj-$(CONFIG_OF)                += prom.o
 
-CFLAGS_cpu-bugs64.o     = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
+CFLAGS_cpu-bugs64.o     = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -x c /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
 
 obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT)   += 8250-platform.o
 
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index c5dfb2c87d44..4b0c347d7a82 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -58,7 +58,7 @@ union octeon_pci_address {
         } s;
 };
 
-int __initdata (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
+int __initconst (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
                                          u8 slot, u8 pin);
 enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
 
diff --git a/arch/mn10300/Makefile b/arch/mn10300/Makefile
index 33188b6e81e4..a3d0fef3b126 100644
--- a/arch/mn10300/Makefile
+++ b/arch/mn10300/Makefile
@@ -26,7 +26,7 @@ CHECKFLAGS	+=
 PROCESSOR       := unset
 UNIT            := unset
 
-KBUILD_CFLAGS   += -mam33 -mmem-funcs -DCPU=AM33
+KBUILD_CFLAGS   += -mam33 -DCPU=AM33 $(call cc-option,-mmem-funcs,)
 KBUILD_AFLAGS   += -mam33 -DCPU=AM33
 
 ifeq ($(CONFIG_MN10300_CURRENT_IN_E2),y)
diff --git a/arch/mn10300/include/asm/elf.h b/arch/mn10300/include/asm/elf.h
index 8157c9267f42..4ebd6b3a0a1e 100644
--- a/arch/mn10300/include/asm/elf.h
+++ b/arch/mn10300/include/asm/elf.h
@@ -151,7 +151,8 @@ do {						\
 #define ELF_PLATFORM  (NULL)
 
 #ifdef __KERNEL__
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) \
+        set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
 #endif
 
 #endif /* _ASM_ELF_H */
diff --git a/arch/openrisc/include/asm/elf.h b/arch/openrisc/include/asm/elf.h
index a8fe2c513070..225a7ff320ad 100644
--- a/arch/openrisc/include/asm/elf.h
+++ b/arch/openrisc/include/asm/elf.h
@@ -110,7 +110,8 @@ extern void dump_elf_thread(elf_greg_t *dest, struct pt_regs *pt);
 
 #define ELF_PLATFORM    (NULL)
 
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) \
+        set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
 
 #endif /* __KERNEL__ */
 #endif
diff --git a/arch/openrisc/include/asm/unistd.h b/arch/openrisc/include/asm/unistd.h
index 89af3ab5c2e9..437bdbb61b14 100644
--- a/arch/openrisc/include/asm/unistd.h
+++ b/arch/openrisc/include/asm/unistd.h
@@ -16,9 +16,6 @@
  * (at your option) any later version.
  */
 
-#if !defined(__ASM_OPENRISC_UNISTD_H) || defined(__SYSCALL)
-#define __ASM_OPENRISC_UNISTD_H
-
 #define __ARCH_HAVE_MMU
 
 #define sys_mmap2 sys_mmap_pgoff
@@ -27,5 +24,3 @@
 
 #define __NR_or1k_atomic __NR_arch_specific_syscall
 __SYSCALL(__NR_or1k_atomic, sys_or1k_atomic)
-
-#endif /* __ASM_OPENRISC_UNISTD_H */
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 3ff21b536f28..b87438bb3384 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -13,6 +13,7 @@ config PARISC
         select HAVE_PERF_EVENTS
         select GENERIC_ATOMIC64 if !64BIT
         select HAVE_GENERIC_HARDIRQS
+        select BROKEN_RODATA
         select GENERIC_IRQ_PROBE
         select GENERIC_PCI_IOMAP
         select IRQ_PER_CPU
diff --git a/arch/parisc/include/asm/compat.h b/arch/parisc/include/asm/compat.h
index 760f331d4fa3..db7a662691a8 100644
--- a/arch/parisc/include/asm/compat.h
+++ b/arch/parisc/include/asm/compat.h
@@ -36,6 +36,7 @@ typedef s64	compat_s64;
 typedef u32     compat_uint_t;
 typedef u32     compat_ulong_t;
 typedef u64     compat_u64;
+typedef u32     compat_uptr_t;
 
 struct compat_timespec {
         compat_time_t           tv_sec;
@@ -127,6 +128,63 @@ typedef u32		compat_old_sigset_t;	/* at least 32 bits */
 
 typedef u32             compat_sigset_word;
 
+typedef union compat_sigval {
+        compat_int_t    sival_int;
+        compat_uptr_t   sival_ptr;
+} compat_sigval_t;
+
+typedef struct compat_siginfo {
+        int si_signo;
+        int si_errno;
+        int si_code;
+
+        union {
+                int _pad[128/sizeof(int) - 3];
+
+                /* kill() */
+                struct {
+                        unsigned int _pid;      /* sender's pid */
+                        unsigned int _uid;      /* sender's uid */
+                } _kill;
+
+                /* POSIX.1b timers */
+                struct {
+                        compat_timer_t _tid;            /* timer id */
+                        int _overrun;           /* overrun count */
+                        char _pad[sizeof(unsigned int) - sizeof(int)];
+                        compat_sigval_t _sigval;        /* same as below */
+                        int _sys_private;       /* not to be passed to user */
+                } _timer;
+
+                /* POSIX.1b signals */
+                struct {
+                        unsigned int _pid;      /* sender's pid */
+                        unsigned int _uid;      /* sender's uid */
+                        compat_sigval_t _sigval;
+                } _rt;
+
+                /* SIGCHLD */
+                struct {
+                        unsigned int _pid;      /* which child */
+                        unsigned int _uid;      /* sender's uid */
+                        int _status;            /* exit code */
+                        compat_clock_t _utime;
+                        compat_clock_t _stime;
+                } _sigchld;
+
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+                struct {
+                        unsigned int _addr;     /* faulting insn/memory ref. */
+                } _sigfault;
+
+                /* SIGPOLL */
+                struct {
+                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
+                        int _fd;
+                } _sigpoll;
+        } _sifields;
+} compat_siginfo_t;
+
 #define COMPAT_OFF_T_MAX        0x7fffffff
 #define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
 
@@ -136,7 +194,6 @@ typedef u32		compat_sigset_word;
  * as pointers because the syscall entry code will have
  * appropriately converted them already.
  */
-typedef u32             compat_uptr_t;
 
 static inline void __user *compat_ptr(compat_uptr_t uptr)
 {
diff --git a/arch/parisc/kernel/signal32.h b/arch/parisc/kernel/signal32.h
index c7800846422c..08a88b5349a2 100644
--- a/arch/parisc/kernel/signal32.h
+++ b/arch/parisc/kernel/signal32.h
@@ -55,58 +55,6 @@ struct k_sigaction32 {
         struct compat_sigaction sa;
 };
 
-typedef struct compat_siginfo {
-        int si_signo;
-        int si_errno;
-        int si_code;
-
-        union {
-                int _pad[((128/sizeof(int)) - 3)];
-
-                /* kill() */
-                struct {
-                        unsigned int _pid;      /* sender's pid */
-                        unsigned int _uid;      /* sender's uid */
-                } _kill;
-
-                /* POSIX.1b timers */
-                struct {
-                        compat_timer_t _tid;            /* timer id */
-                        int _overrun;           /* overrun count */
-                        char _pad[sizeof(unsigned int) - sizeof(int)];
-                        compat_sigval_t _sigval;        /* same as below */
-                        int _sys_private;       /* not to be passed to user */
-                } _timer;
-
-                /* POSIX.1b signals */
-                struct {
-                        unsigned int _pid;      /* sender's pid */
-                        unsigned int _uid;      /* sender's uid */
-                        compat_sigval_t _sigval;
-                } _rt;
-
-                /* SIGCHLD */
-                struct {
-                        unsigned int _pid;      /* which child */
-                        unsigned int _uid;      /* sender's uid */
-                        int _status;            /* exit code */
-                        compat_clock_t _utime;
-                        compat_clock_t _stime;
-                } _sigchld;
-
-                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
-                struct {
-                        unsigned int _addr;     /* faulting insn/memory ref. */
-                } _sigfault;
-
-                /* SIGPOLL */
-                struct {
-                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
-                        int _fd;
-                } _sigpoll;
-        } _sifields;
-} compat_siginfo_t;
-
 int copy_siginfo_to_user32 (compat_siginfo_t __user *to, siginfo_t *from);
 int copy_siginfo_from_user32 (siginfo_t *to, compat_siginfo_t __user *from);
 
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 352f416269ce..4ce0be32d153 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -215,7 +215,8 @@ config ARCH_HIBERNATION_POSSIBLE
 config ARCH_SUSPEND_POSSIBLE
         def_bool y
         depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \
-                   (PPC_85xx && !SMP) || PPC_86xx || PPC_PSERIES || 44x || 40x
+                   (PPC_85xx && !PPC_E500MC) || PPC_86xx || PPC_PSERIES \
+                   || 44x || 40x
 
 config PPC_DCR_NATIVE
         bool
@@ -239,6 +240,9 @@ config PPC_OF_PLATFORM_PCI
 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
         def_bool y
 
+config ARCH_SUPPORTS_UPROBES
+        def_bool y
+
 config PPC_ADV_DEBUG_REGS
         bool
         depends on 40x || BOOKE
@@ -325,7 +329,8 @@ config SWIOTLB
 
 config HOTPLUG_CPU
         bool "Support for enabling/disabling CPUs"
-        depends on SMP && HOTPLUG && EXPERIMENTAL && (PPC_PSERIES || PPC_PMAC || PPC_POWERNV)
+        depends on SMP && HOTPLUG && EXPERIMENTAL && (PPC_PSERIES || \
+        PPC_PMAC || PPC_POWERNV || (PPC_85xx && !PPC_E500MC))
         ---help---
           Say Y here to be able to disable and re-enable individual
           CPUs at runtime on SMP machines.
@@ -557,6 +562,14 @@ config SCHED_SMT
           when dealing with POWER5 cpus at a cost of slightly increased
           overhead in some places. If unsure say N here.
 
+config PPC_DENORMALISATION
+        bool "PowerPC denormalisation exception handling"
+        depends on PPC_BOOK3S_64
+        default "n"
+        ---help---
+          Add support for handling denormalisation of single precision
+          values.  Useful for bare metal only.  If unsure say Y here.
+
 config CMDLINE_BOOL
         bool "Default bootloader kernel arguments"
 
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index b7d833382be4..6a15c968d214 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -107,6 +107,7 @@ src-boot := $(addprefix $(obj)/, $(src-boot))
 obj-boot := $(addsuffix .o, $(basename $(src-boot)))
 obj-wlib := $(addsuffix .o, $(basename $(addprefix $(obj)/, $(src-wlib))))
 obj-plat := $(addsuffix .o, $(basename $(addprefix $(obj)/, $(src-plat))))
+obj-plat: $(libfdt)
 
 quiet_cmd_copy_zlib = COPY    $@
       cmd_copy_zlib = sed "s@__used@@;s@<linux/\([^>]*\).*@\"\1\"@" $< > $@
diff --git a/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
new file mode 100644
index 000000000000..870c6535a053
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
@@ -0,0 +1,58 @@
+/*
+ * e500mc Power ISA Device Tree Source (include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/ {
+        cpus {
+                power-isa-version = "2.06";
+                power-isa-b;            // Base
+                power-isa-e;            // Embedded
+                power-isa-atb;          // Alternate Time Base
+                power-isa-cs;           // Cache Specification
+                power-isa-ds;           // Decorated Storage
+                power-isa-e.ed;         // Embedded.Enhanced Debug
+                power-isa-e.pd;         // Embedded.External PID
+                power-isa-e.hv;         // Embedded.Hypervisor
+                power-isa-e.le;         // Embedded.Little-Endian
+                power-isa-e.pm;         // Embedded.Performance Monitor
+                power-isa-e.pc;         // Embedded.Processor Control
+                power-isa-ecl;          // Embedded Cache Locking
+                power-isa-exp;          // External Proxy
+                power-isa-fp;           // Floating Point
+                power-isa-fp.r;         // Floating Point.Record
+                power-isa-mmc;          // Memory Coherence
+                power-isa-scpm;         // Store Conditional Page Mobility
+                power-isa-wt;           // Wait
+                mmu-type = "power-embedded";
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/e500v2_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e500v2_power_isa.dtsi
new file mode 100644
index 000000000000..f4928144d2c8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/e500v2_power_isa.dtsi
@@ -0,0 +1,52 @@
+/*
+ * e500v2 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/ {
+        cpus {
+                power-isa-version = "2.03";
+                power-isa-b;            // Base
+                power-isa-e;            // Embedded
+                power-isa-atb;          // Alternate Time Base
+                power-isa-cs;           // Cache Specification
+                power-isa-e.le;         // Embedded.Little-Endian
+                power-isa-e.pm;         // Embedded.Performance Monitor
+                power-isa-ecl;          // Embedded Cache Locking
+                power-isa-mmc;          // Memory Coherence
+                power-isa-sp;           // Signal Processing Engine
+                power-isa-sp.fd;        // SPE.Embedded Float Scalar Double
+                power-isa-sp.fs;        // SPE.Embedded Float Scalar Single
+                power-isa-sp.fv;        // SPE.Embedded Float Vector
+                mmu-type = "power-embedded";
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
new file mode 100644
index 000000000000..3230212f7ad5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
@@ -0,0 +1,59 @@
+/*
+ * e5500 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/ {
+        cpus {
+                power-isa-version = "2.06";
+                power-isa-b;            // Base
+                power-isa-e;            // Embedded
+                power-isa-atb;          // Alternate Time Base
+                power-isa-cs;           // Cache Specification
+                power-isa-ds;           // Decorated Storage
+                power-isa-e.ed;         // Embedded.Enhanced Debug
+                power-isa-e.pd;         // Embedded.External PID
+                power-isa-e.hv;         // Embedded.Hypervisor
+                power-isa-e.le;         // Embedded.Little-Endian
+                power-isa-e.pm;         // Embedded.Performance Monitor
+                power-isa-e.pc;         // Embedded.Processor Control
+                power-isa-ecl;          // Embedded Cache Locking
+                power-isa-exp;          // External Proxy
+                power-isa-fp;           // Floating Point
+                power-isa-fp.r;         // Floating Point.Record
+                power-isa-mmc;          // Memory Coherence
+                power-isa-scpm;         // Store Conditional Page Mobility
+                power-isa-wt;           // Wait
+                power-isa-64;           // 64-bit
+                mmu-type = "power-embedded";
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
index 7de45a784df6..152906f98a0f 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
@@ -33,6 +33,9 @@
  */
 
 /dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
 / {
         compatible = "fsl,MPC8536";
         #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
index 8777f9239d9e..5a69bafb652a 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
@@ -33,6 +33,9 @@
  */
 
 /dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
 / {
         compatible = "fsl,MPC8544";
         #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
index 720422d83529..fc1ce977422b 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
@@ -33,6 +33,9 @@
  */
 
 /dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
 / {
         compatible = "fsl,MPC8548";
         #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
index eacd62c5fe6c..122ca3bd0b03 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
@@ -33,6 +33,9 @@
  */
 
 /dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
 / {
         compatible = "fsl,MPC8568";
         #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
index b07064d11930..2cd15a2a0422 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
@@ -33,6 +33,9 @@
  */
 
 /dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
 / {
         compatible = "fsl,MPC8569";
         #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
index ca188326c2ca..28c2a862be96 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
@@ -33,6 +33,9 @@
  */
 
 /dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
 / {
         compatible = "fsl,MPC8572";
         #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
index 7354a8f90ea5..6e76f9b282a1 100644
--- a/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
@@ -33,6 +33,9 @@
  */
 
 /dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
 / {
         compatible = "fsl,P1010";
         #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
index 6f0376e554eb..fed9c4c8d962 100644
--- a/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
@@ -33,6 +33,9 @@
  */
 
 /dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
 / {
         compatible = "fsl,P1020";
         #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
index 4abd54bc3308..36161b500176 100644
--- a/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
@@ -33,6 +33,9 @@
  */
 
 /dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
 / {
         compatible = "fsl,P1021";
         #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
index e930f4f7ca89..1956dea040cc 100644
--- a/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
@@ -33,6 +33,9 @@
  */
 
 /dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
 / {
         compatible = "fsl,P1022";
         #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
index ac45f6d93385..132a1521921a 100644
--- a/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
@@ -33,6 +33,9 @@
  */
 
 /dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
 / {
         compatible = "fsl,P1023";
         #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
index 3213288641d1..42bf3c6d25ca 100644
--- a/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
@@ -33,6 +33,9 @@
  */
 
 /dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
 / {
         compatible = "fsl,P2020";
         #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
index 2d0a40d6b10f..7a2697d04549 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
@@ -33,6 +33,9 @@
  */
 
 /dts-v1/;
+
+/include/ "e500mc_power_isa.dtsi"
+
 / {
         compatible = "fsl,P2041";
         #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
index 136def3536b6..c9ca2c305cfe 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
@@ -33,6 +33,9 @@
  */
 
 /dts-v1/;
+
+/include/ "e500mc_power_isa.dtsi"
+
 / {
         compatible = "fsl,P3041";
         #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
index b9556ee3a639..493d9a056b5c 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -33,6 +33,9 @@
  */
 
 /dts-v1/;
+
+/include/ "e500mc_power_isa.dtsi"
+
 / {
         compatible = "fsl,P4080";
         #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
index ae823a47584e..0a198b0a77e5 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -33,6 +33,9 @@
  */
 
 /dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
 / {
         compatible = "fsl,P5020";
         #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
new file mode 100644
index 000000000000..db2c9a7b3a0e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -0,0 +1,320 @@
+/*
+ * P5040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of this
+ * software, even if advised of the possibility of such damage.
+ */
+
+&lbc {
+        compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
+        interrupts = <25 2 0 0>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+};
+
+/* controller at 0x200000 */
+&pci0 {
+        compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 15>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 15>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 40 1 0 0
+                        0000 0 0 2 &mpic 1 1 0 0
+                        0000 0 0 3 &mpic 2 1 0 0
+                        0000 0 0 4 &mpic 3 1 0 0
+                        >;
+        };
+};
+
+/* controller at 0x201000 */
+&pci1 {
+        compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 14>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 14>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 41 1 0 0
+                        0000 0 0 2 &mpic 5 1 0 0
+                        0000 0 0 3 &mpic 6 1 0 0
+                        0000 0 0 4 &mpic 7 1 0 0
+                        >;
+        };
+};
+
+/* controller at 0x202000 */
+&pci2 {
+        compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 13>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 13>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 42 1 0 0
+                        0000 0 0 2 &mpic 9 1 0 0
+                        0000 0 0 3 &mpic 10 1 0 0
+                        0000 0 0 4 &mpic 11 1 0 0
+                        >;
+        };
+};
+
+&dcsr {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,dcsr", "simple-bus";
+
+        dcsr-epu@0 {
+                compatible = "fsl,dcsr-epu";
+                interrupts = <52 2 0 0
+                              84 2 0 0
+                              85 2 0 0>;
+                reg = <0x0 0x1000>;
+        };
+        dcsr-npc {
+                compatible = "fsl,dcsr-npc";
+                reg = <0x1000 0x1000 0x1000000 0x8000>;
+        };
+        dcsr-nxc@2000 {
+                compatible = "fsl,dcsr-nxc";
+                reg = <0x2000 0x1000>;
+        };
+        dcsr-corenet {
+                compatible = "fsl,dcsr-corenet";
+                reg = <0x8000 0x1000 0xB0000 0x1000>;
+        };
+        dcsr-dpaa@9000 {
+                compatible = "fsl,p5040-dcsr-dpaa", "fsl,dcsr-dpaa";
+                reg = <0x9000 0x1000>;
+        };
+        dcsr-ocn@11000 {
+                compatible = "fsl,p5040-dcsr-ocn", "fsl,dcsr-ocn";
+                reg = <0x11000 0x1000>;
+        };
+        dcsr-ddr@12000 {
+                compatible = "fsl,dcsr-ddr";
+                dev-handle = <&ddr1>;
+                reg = <0x12000 0x1000>;
+        };
+        dcsr-ddr@13000 {
+                compatible = "fsl,dcsr-ddr";
+                dev-handle = <&ddr2>;
+                reg = <0x13000 0x1000>;
+        };
+        dcsr-nal@18000 {
+                compatible = "fsl,p5040-dcsr-nal", "fsl,dcsr-nal";
+                reg = <0x18000 0x1000>;
+        };
+        dcsr-rcpm@22000 {
+                compatible = "fsl,p5040-dcsr-rcpm", "fsl,dcsr-rcpm";
+                reg = <0x22000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@40000 {
+                compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu0>;
+                reg = <0x40000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@41000 {
+                compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu1>;
+                reg = <0x41000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@42000 {
+                compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu2>;
+                reg = <0x42000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@43000 {
+                compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu3>;
+                reg = <0x43000 0x1000>;
+        };
+};
+
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "simple-bus";
+
+        soc-sram-error {
+                compatible = "fsl,soc-sram-error";
+                interrupts = <16 2 1 29>;
+        };
+
+        corenet-law@0 {
+                compatible = "fsl,corenet-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <32>;
+        };
+
+        ddr1: memory-controller@8000 {
+                compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+                reg = <0x8000 0x1000>;
+                interrupts = <16 2 1 23>;
+        };
+
+        ddr2: memory-controller@9000 {
+                compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
+                reg = <0x9000 0x1000>;
+                interrupts = <16 2 1 22>;
+        };
+
+        cpc: l3-cache-controller@10000 {
+                compatible = "fsl,p5040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
+                reg = <0x10000 0x1000
+                       0x11000 0x1000>;
+                interrupts = <16 2 1 27
+                              16 2 1 26>;
+        };
+
+        corenet-cf@18000 {
+                compatible = "fsl,corenet-cf";
+                reg = <0x18000 0x1000>;
+                interrupts = <16 2 1 31>;
+                fsl,ccf-num-csdids = <32>;
+                fsl,ccf-num-snoopids = <32>;
+        };
+
+        iommu@20000 {
+                compatible = "fsl,pamu-v1.0", "fsl,pamu";
+                reg = <0x20000 0x5000>;
+                interrupts = <
+                        24 2 0 0
+                        16 2 1 30>;
+        };
+
+/include/ "qoriq-mpic.dtsi"
+
+        guts: global-utilities@e0000 {
+                compatible = "fsl,p5040-device-config", "fsl,qoriq-device-config-1.0";
+                reg = <0xe0000 0xe00>;
+                fsl,has-rstcr;
+                #sleep-cells = <1>;
+                fsl,liodn-bits = <12>;
+        };
+
+        pins: global-utilities@e0e00 {
+                compatible = "fsl,p5040-pin-control", "fsl,qoriq-pin-control-1.0";
+                reg = <0xe0e00 0x200>;
+                #sleep-cells = <2>;
+        };
+
+        clockgen: global-utilities@e1000 {
+                compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
+                reg = <0xe1000 0x1000>;
+                clock-frequency = <0>;
+        };
+
+        rcpm: global-utilities@e2000 {
+                compatible = "fsl,p5040-rcpm", "fsl,qoriq-rcpm-1.0";
+                reg = <0xe2000 0x1000>;
+                #sleep-cells = <1>;
+        };
+
+        sfp: sfp@e8000 {
+                compatible = "fsl,p5040-sfp", "fsl,qoriq-sfp-1.0";
+                reg        = <0xe8000 0x1000>;
+        };
+
+        serdes: serdes@ea000 {
+                compatible = "fsl,p5040-serdes";
+                reg        = <0xea000 0x1000>;
+        };
+
+/include/ "qoriq-dma-0.dtsi"
+/include/ "qoriq-dma-1.dtsi"
+/include/ "qoriq-espi-0.dtsi"
+        spi@110000 {
+                fsl,espi-num-chipselects = <4>;
+        };
+
+/include/ "qoriq-esdhc-0.dtsi"
+        sdhc@114000 {
+                sdhci,auto-cmd12;
+        };
+
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-usb2-mph-0.dtsi"
+                usb0: usb@210000 {
+                        compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
+                        phy_type = "utmi";
+                        port0;
+                };
+
+/include/ "qoriq-usb2-dr-0.dtsi"
+                usb1: usb@211000 {
+                        compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
+                        dr_mode = "host";
+                        phy_type = "utmi";
+                };
+
+/include/ "qoriq-sata2-0.dtsi"
+/include/ "qoriq-sata2-1.dtsi"
+/include/ "qoriq-sec5.2-0.dtsi"
+};
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
new file mode 100644
index 000000000000..40ca943f5d1c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
@@ -0,0 +1,114 @@
+/*
+ * P5040 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of this
+ * software, even if advised of the possibility of such damage.
+ */
+
+/dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
+/ {
+        compatible = "fsl,P5040";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+
+        aliases {
+                ccsr = &soc;
+                dcsr = &dcsr;
+
+                serial0 = &serial0;
+                serial1 = &serial1;
+                serial2 = &serial2;
+                serial3 = &serial3;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+                usb0 = &usb0;
+                usb1 = &usb1;
+                dma0 = &dma0;
+                dma1 = &dma1;
+                sdhc = &sdhc;
+                msi0 = &msi0;
+                msi1 = &msi1;
+                msi2 = &msi2;
+
+                crypto = &crypto;
+                sec_jr0 = &sec_jr0;
+                sec_jr1 = &sec_jr1;
+                sec_jr2 = &sec_jr2;
+                sec_jr3 = &sec_jr3;
+                rtic_a = &rtic_a;
+                rtic_b = &rtic_b;
+                rtic_c = &rtic_c;
+                rtic_d = &rtic_d;
+                sec_mon = &sec_mon;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: PowerPC,e5500@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2_0>;
+                        L2_0: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu1: PowerPC,e5500@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2_1>;
+                        L2_1: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu2: PowerPC,e5500@2 {
+                        device_type = "cpu";
+                        reg = <2>;
+                        next-level-cache = <&L2_2>;
+                        L2_2: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu3: PowerPC,e5500@3 {
+                        device_type = "cpu";
+                        reg = <3>;
+                        next-level-cache = <&L2_3>;
+                        L2_3: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
new file mode 100644
index 000000000000..7b2ab8a8c1f4
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
@@ -0,0 +1,118 @@
+/*
+ * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+crypto: crypto@300000 {
+        compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        reg              = <0x300000 0x10000>;
+        ranges           = <0 0x300000 0x10000>;
+        interrupts       = <92 2 0 0>;
+
+        sec_jr0: jr@1000 {
+                compatible = "fsl,sec-v5.2-job-ring",
+                             "fsl,sec-v5.0-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg = <0x1000 0x1000>;
+                interrupts = <88 2 0 0>;
+        };
+
+        sec_jr1: jr@2000 {
+                compatible = "fsl,sec-v5.2-job-ring",
+                             "fsl,sec-v5.0-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg = <0x2000 0x1000>;
+                interrupts = <89 2 0 0>;
+        };
+
+        sec_jr2: jr@3000 {
+                compatible = "fsl,sec-v5.2-job-ring",
+                             "fsl,sec-v5.0-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg = <0x3000 0x1000>;
+                interrupts = <90 2 0 0>;
+        };
+
+        sec_jr3: jr@4000 {
+                compatible = "fsl,sec-v5.2-job-ring",
+                             "fsl,sec-v5.0-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg = <0x4000 0x1000>;
+                interrupts = <91 2 0 0>;
+        };
+
+        rtic@6000 {
+                compatible = "fsl,sec-v5.2-rtic",
+                             "fsl,sec-v5.0-rtic",
+                             "fsl,sec-v4.0-rtic";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x6000 0x100>;
+                ranges = <0x0 0x6100 0xe00>;
+
+                rtic_a: rtic-a@0 {
+                        compatible = "fsl,sec-v5.2-rtic-memory",
+                                     "fsl,sec-v5.0-rtic-memory",
+                                     "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x00 0x20 0x100 0x80>;
+                };
+
+                rtic_b: rtic-b@20 {
+                        compatible = "fsl,sec-v5.2-rtic-memory",
+                                     "fsl,sec-v5.0-rtic-memory",
+                                     "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x20 0x20 0x200 0x80>;
+                };
+
+                rtic_c: rtic-c@40 {
+                        compatible = "fsl,sec-v5.2-rtic-memory",
+                                     "fsl,sec-v5.0-rtic-memory",
+                                     "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x40 0x20 0x300 0x80>;
+                };
+
+                rtic_d: rtic-d@60 {
+                        compatible = "fsl,sec-v5.2-rtic-memory",
+                                     "fsl,sec-v5.0-rtic-memory",
+                                     "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x60 0x20 0x500 0x80>;
+                };
+        };
+};
+
+sec_mon: sec_mon@314000 {
+        compatible = "fsl,sec-v5.2-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
+        reg = <0x314000 0x1000>;
+        interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dtsi b/arch/powerpc/boot/dts/mpc8536ds.dtsi
index d304a2d68c62..7c3dde84d193 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8536ds.dtsi
@@ -132,6 +132,10 @@
                         reg = <0x68>;
                         interrupts = <0 0x1 0 0>;
                 };
+                adt7461@4c {
+                        compatible = "adi,adt7461";
+                        reg = <0x4c>;
+                };
         };
 
         spi@7000 {
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index f99fb110c97f..2d31863accf5 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -11,6 +11,8 @@
 
 /dts-v1/;
 
+/include/ "fsl/e500v2_power_isa.dtsi"
+
 / {
         model = "MPC8540ADS";
         compatible = "MPC8540ADS", "MPC85xxADS";
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 0f5e93912799..1c03c2667373 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -11,6 +11,8 @@
 
 /dts-v1/;
 
+/include/ "fsl/e500v2_power_isa.dtsi"
+
 / {
         model = "MPC8541CDS";
         compatible = "MPC8541CDS", "MPC85xxCDS";
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index e934987e882b..ed38874c3a36 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -20,8 +20,10 @@
                 reg = <0 0 0 0>;        // Filled by U-Boot
         };
 
-        lbc: localbus@e0005000 {
+        board_lbc: lbc: localbus@e0005000 {
                 reg = <0 0xe0005000 0 0x1000>;
+
+                ranges = <0x0 0x0 0x0 0xff800000 0x800000>;
         };
 
         board_soc: soc: soc8544@e0000000 {
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dtsi b/arch/powerpc/boot/dts/mpc8544ds.dtsi
index 77ebc9f1d37c..b219d035d794 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8544ds.dtsi
@@ -32,6 +32,45 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+&board_lbc {
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x800000>;
+                bank-width = <2>;
+                device-width = <1>;
+
+                partition@0 {
+                        reg = <0x0 0x10000>;
+                        label = "dtb-nor";
+                };
+
+                partition@20000 {
+                        reg = <0x20000 0x30000>;
+                        label = "diagnostic-nor";
+                        read-only;
+                };
+
+                partition@200000 {
+                        reg = <0x200000 0x200000>;
+                        label = "dink-nor";
+                        read-only;
+                };
+
+                partition@400000 {
+                        reg = <0x400000 0x380000>;
+                        label = "kernel-nor";
+                };
+
+                partition@780000 {
+                        reg = <0x780000 0x80000>;
+                        label = "u-boot-nor";
+                        read-only;
+                };
+        };
+};
+
 &board_soc {
         enet0: ethernet@24000 {
                 phy-handle = <&phy0>;
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index fe10438613d6..36a7ea138c2f 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -11,6 +11,8 @@
 
 /dts-v1/;
 
+/include/ "fsl/e500v2_power_isa.dtsi"
+
 / {
         model = "MPC8555CDS";
         compatible = "MPC8555CDS", "MPC85xxCDS";
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 6e85e1ba0851..1a43f5a968f5 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -11,6 +11,8 @@
 
 /dts-v1/;
 
+/include/ "fsl/e500v2_power_isa.dtsi"
+
 / {
         model = "MPC8560ADS";
         compatible = "MPC8560ADS", "MPC85xxADS";
diff --git a/arch/powerpc/boot/dts/o2d.dts b/arch/powerpc/boot/dts/o2d.dts
new file mode 100644
index 000000000000..9f6dd4d889b3
--- /dev/null
+++ b/arch/powerpc/boot/dts/o2d.dts
@@ -0,0 +1,47 @@
+/*
+ * O2D Device Tree Source
+ *
+ * Copyright (C) 2012 DENX Software Engineering
+ * Anatolij Gustschin <agust@denx.de>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ "o2d.dtsi"
+
+/ {
+        model = "ifm,o2d";
+        compatible = "ifm,o2d";
+
+        memory {
+                reg = <0x00000000 0x08000000>;  // 128MB
+        };
+
+        localbus {
+                ranges = <0 0 0xfc000000 0x02000000
+                          3 0 0xe3000000 0x00100000>;
+
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x02000000>;
+                        bank-width = <2>;
+                        device-width = <2>;
+                        #size-cells = <1>;
+                        #address-cells = <1>;
+
+                        partition@60000 {
+                                label = "kernel";
+                                reg = <0x00060000 0x00260000>;
+                                read-only;
+                        };
+                        /* o2d specific partitions */
+                        partition@2c0000 {
+                                label = "o2d user defined";
+                                reg = <0x002c0000 0x01d40000>;
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/o2d.dtsi b/arch/powerpc/boot/dts/o2d.dtsi
new file mode 100644
index 000000000000..3444eb8f0ade
--- /dev/null
+++ b/arch/powerpc/boot/dts/o2d.dtsi
@@ -0,0 +1,139 @@
+/*
+ * O2D base Device Tree Source
+ *
+ * Copyright (C) 2012 DENX Software Engineering
+ * Anatolij Gustschin <agust@denx.de>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ "mpc5200b.dtsi"
+
+/ {
+        model = "ifm,o2d";
+        compatible = "ifm,o2d";
+
+        memory {
+                reg = <0x00000000 0x04000000>;  // 64MB
+        };
+
+        soc5200@f0000000 {
+
+                gpio_simple: gpio@b00 {
+                };
+
+                timer@600 {     // General Purpose Timer
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        fsl,has-wdt;
+                        fsl,wdt-on-boot = <0>;
+                };
+
+                timer@610 {
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                };
+
+                timer7: timer@670 {
+                };
+
+                rtc@800 {
+                        status = "disabled";
+                };
+
+                psc@2000 {              // PSC1
+                        compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+
+                        spidev@0 {
+                                compatible = "spidev";
+                                spi-max-frequency = <250000>;
+                                reg = <0>;
+                        };
+                };
+
+                psc@2200 {              // PSC2
+                        status = "disabled";
+                };
+
+                psc@2400 {              // PSC3
+                        status = "disabled";
+                };
+
+                psc@2600 {              // PSC4
+                        compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+                };
+
+                psc@2800 {              // PSC5
+                        compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+                };
+
+                psc@2c00 {              // PSC6
+                        status = "disabled";
+                };
+
+                ethernet@3000 {
+                        phy-handle = <&phy0>;
+                };
+
+                mdio@3000 {
+                        phy0: ethernet-phy@0 {
+                                reg = <0>;
+                        };
+                };
+
+                sclpc@3c00 {
+                        compatible = "fsl,mpc5200-lpbfifo";
+                        reg = <0x3c00 0x60>;
+                        interrupts = <3 23 0>;
+                };
+        };
+
+        localbus {
+                ranges = <0 0 0xff000000 0x01000000
+                          3 0 0xe3000000 0x00100000>;
+
+                // flash device at LocalPlus Bus CS0
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x01000000>;
+                        bank-width = <1>;
+                        device-width = <2>;
+                        #size-cells = <1>;
+                        #address-cells = <1>;
+                        no-unaligned-direct-access;
+
+                        /* common layout for all machines */
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x00000000 0x00040000>;
+                                read-only;
+                        };
+                        partition@40000 {
+                                label = "env";
+                                reg = <0x00040000 0x00020000>;
+                                read-only;
+                        };
+                };
+
+                csi@3,0 {
+                        compatible = "ifm,o2d-csi";
+                        reg = <3 0 0x00100000>;
+                        ifm,csi-clk-handle = <&timer7>;
+                        gpios = <&gpio_simple 23 0      /* imag_capture */
+                                 &gpio_simple 26 0      /* imag_reset */
+                                 &gpio_simple 29 0>;    /* imag_master_en */
+
+                        interrupts = <1 1 2>;           /* IRQ1, edge falling */
+
+                        ifm,csi-addr-bus-width = <24>;
+                        ifm,csi-data-bus-width = <8>;
+                        ifm,csi-wait-cycles = <0>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/o2d300.dts b/arch/powerpc/boot/dts/o2d300.dts
new file mode 100644
index 000000000000..29affe0f0da3
--- /dev/null
+++ b/arch/powerpc/boot/dts/o2d300.dts
@@ -0,0 +1,52 @@
+/*
+ * O2D300 Device Tree Source
+ *
+ * Copyright (C) 2012 DENX Software Engineering
+ * Anatolij Gustschin <agust@denx.de>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ "o2d.dtsi"
+
+/ {
+        model = "ifm,o2d300";
+        compatible = "ifm,o2d";
+
+        localbus {
+                ranges = <0 0 0xfc000000 0x02000000
+                          3 0 0xe3000000 0x00100000>;
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x02000000>;
+                        bank-width = <2>;
+                        device-width = <2>;
+                        #size-cells = <1>;
+                        #address-cells = <1>;
+
+                        partition@40000 {
+                                label = "env_1";
+                                reg = <0x00040000 0x00020000>;
+                                read-only;
+                        };
+                        partition@60000 {
+                                label = "env_2";
+                                reg = <0x00060000 0x00020000>;
+                                read-only;
+                        };
+                        partition@80000 {
+                                label = "kernel";
+                                reg = <0x00080000 0x00260000>;
+                                read-only;
+                        };
+                        /* o2d300 specific partitions */
+                        partition@2e0000 {
+                                label = "o2d300 user defined";
+                                reg = <0x002e0000 0x01d20000>;
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/o2dnt2.dts b/arch/powerpc/boot/dts/o2dnt2.dts
new file mode 100644
index 000000000000..a0f5b97a4f06
--- /dev/null
+++ b/arch/powerpc/boot/dts/o2dnt2.dts
@@ -0,0 +1,48 @@
+/*
+ * O2DNT2 Device Tree Source
+ *
+ * Copyright (C) 2012 DENX Software Engineering
+ * Anatolij Gustschin <agust@denx.de>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ "o2d.dtsi"
+
+/ {
+        model = "ifm,o2dnt2";
+        compatible = "ifm,o2d";
+
+        memory {
+                reg = <0x00000000 0x08000000>;  // 128MB
+        };
+
+        localbus {
+                ranges = <0 0 0xfc000000 0x02000000
+                          3 0 0xe3000000 0x00100000>;
+
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x02000000>;
+                        bank-width = <2>;
+                        device-width = <2>;
+                        #size-cells = <1>;
+                        #address-cells = <1>;
+
+                        partition@60000 {
+                                label = "kernel";
+                                reg = <0x00060000 0x00260000>;
+                                read-only;
+                        };
+
+                        /* o2dnt2 specific partitions */
+                        partition@2c0000 {
+                                label = "o2dnt2 user defined";
+                                reg = <0x002c0000 0x01d40000>;
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/o2i.dts b/arch/powerpc/boot/dts/o2i.dts
new file mode 100644
index 000000000000..e3cc99d1360b
--- /dev/null
+++ b/arch/powerpc/boot/dts/o2i.dts
@@ -0,0 +1,33 @@
+/*
+ * O2I Device Tree Source
+ *
+ * Copyright (C) 2012 DENX Software Engineering
+ * Anatolij Gustschin <agust@denx.de>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ "o2d.dtsi"
+
+/ {
+        model = "ifm,o2i";
+        compatible = "ifm,o2d";
+
+        localbus {
+                flash@0,0 {
+                        partition@60000 {
+                                label = "kernel";
+                                reg = <0x00060000 0x00260000>;
+                                read-only;
+                        };
+                        /* o2i specific partitions */
+                        partition@2c0000 {
+                                label = "o2i user defined";
+                                reg = <0x002c0000 0x00d40000>;
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/o2mnt.dts b/arch/powerpc/boot/dts/o2mnt.dts
new file mode 100644
index 000000000000..d91859a9e940
--- /dev/null
+++ b/arch/powerpc/boot/dts/o2mnt.dts
@@ -0,0 +1,33 @@
+/*
+ * O2MNT Device Tree Source
+ *
+ * Copyright (C) 2012 DENX Software Engineering
+ * Anatolij Gustschin <agust@denx.de>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ "o2d.dtsi"
+
+/ {
+        model = "ifm,o2mnt";
+        compatible = "ifm,o2d";
+
+        localbus {
+                flash@0,0 {
+                        partition@60000 {
+                                label = "kernel";
+                                reg = <0x00060000 0x00260000>;
+                                read-only;
+                        };
+                        /* add o2mnt specific partitions */
+                        partition@2c0000 {
+                                label = "o2mnt user defined";
+                                reg = <0x002c0000 0x00d40000>;
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/o3dnt.dts b/arch/powerpc/boot/dts/o3dnt.dts
new file mode 100644
index 000000000000..acce49326491
--- /dev/null
+++ b/arch/powerpc/boot/dts/o3dnt.dts
@@ -0,0 +1,48 @@
+/*
+ * O3DNT Device Tree Source
+ *
+ * Copyright (C) 2012 DENX Software Engineering
+ * Anatolij Gustschin <agust@denx.de>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ "o2d.dtsi"
+
+/ {
+        model = "ifm,o3dnt";
+        compatible = "ifm,o2d";
+
+        memory {
+                reg = <0x00000000 0x04000000>;  // 64MB
+        };
+
+        localbus {
+                ranges = <0 0 0xfc000000 0x01000000
+                          3 0 0xe3000000 0x00100000>;
+
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x01000000>;
+                        bank-width = <2>;
+                        device-width = <2>;
+                        #size-cells = <1>;
+                        #address-cells = <1>;
+
+                        partition@60000 {
+                                label = "kernel";
+                                reg = <0x00060000 0x00260000>;
+                                read-only;
+                        };
+
+                        /* o3dnt specific partitions */
+                        partition@2c0000 {
+                                label = "o3dnt user defined";
+                                reg = <0x002c0000 0x00d40000>;
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
deleted file mode 100644
index 41b4585c5da8..000000000000
--- a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * P1020 RDB  Core0 Device Tree Source in CAMP mode.
- *
- * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
- * can be shared, all the other devices must be assigned to one core only.
- * This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb,
- * eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi.
- *
- * Please note to add "-b 0" for core0's dts compiling.
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-/include/ "p1020rdb.dts"
-
-/ {
-        model = "fsl,P1020RDB";
-        compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
-
-        aliases {
-                ethernet1 = &enet1;
-                ethernet2 = &enet2;
-                serial0 = &serial0;
-                pci0 = &pci0;
-                pci1 = &pci1;
-        };
-
-        cpus {
-                PowerPC,P1020@1 {
-                        status = "disabled";
-                };
-        };
-
-        memory {
-                device_type = "memory";
-        };
-
-        localbus@ffe05000 {
-                status = "disabled";
-        };
-
-        soc@ffe00000 {
-                serial1: serial@4600 {
-                        status = "disabled";
-                };
-
-                enet0: ethernet@b0000 {
-                        status = "disabled";
-                };
-
-                mpic: pic@40000 {
-                        protected-sources = <
-                        42 29 30 34     /* serial1, enet0-queue-group0 */
-                        17 18 24 45     /* enet0-queue-group1, crypto */
-                        >;
-                };
-        };
-};
diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
deleted file mode 100644
index 517453821884..000000000000
--- a/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * P1020 RDB Core1 Device Tree Source in CAMP mode.
- *
- * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
- * can be shared, all the other devices must be assigned to one core only.
- * This dts allows core1 to have l2, eth0, crypto.
- *
- * Please note to add "-b 1" for core1's dts compiling.
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-/include/ "p1020rdb.dts"
-
-/ {
-        model = "fsl,P1020RDB";
-        compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
-
-        aliases {
-                ethernet0 = &enet0;
-                serial0 = &serial1;
-                };
-
-        cpus {
-                PowerPC,P1020@0 {
-                        status = "disabled";
-                };
-        };
-
-        memory {
-                device_type = "memory";
-        };
-
-        localbus@ffe05000 {
-                status = "disabled";
-        };
-
-        soc@ffe00000 {
-                ecm-law@0 {
-                        status = "disabled";
-                };
-
-                ecm@1000 {
-                        status = "disabled";
-                };
-
-                memory-controller@2000 {
-                        status = "disabled";
-                };
-
-                i2c@3000 {
-                        status = "disabled";
-                };
-
-                i2c@3100 {
-                        status = "disabled";
-                };
-
-                serial0: serial@4500 {
-                        status = "disabled";
-                };
-
-                spi@7000 {
-                        status = "disabled";
-                };
-
-                gpio: gpio-controller@f000 {
-                        status = "disabled";
-                };
-
-                dma@21300 {
-                        status = "disabled";
-                };
-
-                mdio@24000 {
-                        status = "disabled";
-                };
-
-                mdio@25000 {
-                        status = "disabled";
-                };
-
-                enet1: ethernet@b1000 {
-                        status = "disabled";
-                };
-
-                enet2: ethernet@b2000 {
-                        status = "disabled";
-                };
-
-                usb@22000 {
-                        status = "disabled";
-                };
-
-                sdhci@2e000 {
-                        status = "disabled";
-                };
-
-                mpic: pic@40000 {
-                        protected-sources = <
-                        16              /* ecm, mem, L2, pci0, pci1 */
-                        43 42 59        /* i2c, serial0, spi */
-                        47 63 62        /* gpio, tdm */
-                        20 21 22 23     /* dma */
-                        03 02           /* mdio */
-                        35 36 40        /* enet1-queue-group0 */
-                        51 52 67        /* enet1-queue-group1 */
-                        31 32 33        /* enet2-queue-group0 */
-                        25 26 27        /* enet2-queue-group1 */
-                        28 72 58        /* usb, sdhci, crypto */
-                        0xb0 0xb1 0xb2  /* message */
-                        0xb3 0xb4 0xb5
-                        0xb6 0xb7
-                        0xe0 0xe1 0xe2  /* msi */
-                        0xe3 0xe4 0xe5
-                        0xe6 0xe7               /* sdhci, crypto , pci */
-                        >;
-                };
-
-                msi@41600 {
-                        status = "disabled";
-                };
-
-                global-utilities@e0000 {        //global utilities block
-                        status = "disabled";
-                };
-        };
-
-        pci0: pcie@ffe09000 {
-                status = "disabled";
-        };
-
-        pci1: pcie@ffe0a000 {
-                status = "disabled";
-        };
-};
diff --git a/arch/powerpc/boot/dts/p1022ds.dtsi b/arch/powerpc/boot/dts/p1022ds.dtsi
index c3344b04d8ff..873da350d01b 100644
--- a/arch/powerpc/boot/dts/p1022ds.dtsi
+++ b/arch/powerpc/boot/dts/p1022ds.dtsi
@@ -149,6 +149,10 @@
                         compatible = "dallas,ds1339";
                         reg = <0x68>;
                 };
+                adt7461@4c {
+                        compatible = "adi,adt7461";
+                        reg = <0x4c>;
+                };
         };
 
         spi@7000 {
diff --git a/arch/powerpc/boot/dts/p1022rdk.dts b/arch/powerpc/boot/dts/p1022rdk.dts
new file mode 100644
index 000000000000..51d82de223f3
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022rdk.dts
@@ -0,0 +1,188 @@
+/*
+ * P1022 RDK 32-bit Physical Address Map Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1022si-pre.dtsi"
+/ {
+        model = "fsl,P1022RDK";
+        compatible = "fsl,P1022RDK";
+
+        memory {
+                device_type = "memory";
+        };
+
+        board_lbc: lbc: localbus@ffe05000 {
+                /* The P1022 RDK does not have any localbus devices */
+                status = "disabled";
+        };
+
+        board_soc: soc: soc@ffe00000 {
+                ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+                i2c@3100 {
+                        wm8960:codec@1a {
+                                compatible = "wlf,wm8960";
+                                reg = <0x1a>;
+                                /* MCLK source is a stand-alone oscillator */
+                                clock-frequency = <12288000>;
+                        };
+                        rtc@68 {
+                                compatible = "stm,m41t62";
+                                reg = <0x68>;
+                        };
+                        adt7461@4c{
+                                compatible = "adi,adt7461";
+                                reg = <0x4c>;
+                        };
+                        zl6100@21{
+                                compatible = "isil,zl6100";
+                                reg = <0x21>;
+                        };
+                        zl6100@24{
+                                compatible = "isil,zl6100";
+                                reg = <0x24>;
+                        };
+                        zl6100@26{
+                                compatible = "isil,zl6100";
+                                reg = <0x26>;
+                        };
+                        zl6100@29{
+                                compatible = "isil,zl6100";
+                                reg = <0x29>;
+                        };
+                };
+
+                spi@7000 {
+                        flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "spansion,m25p80";
+                                reg = <0>;
+                                spi-max-frequency = <1000000>;
+                                partition@0 {
+                                        label = "full-spi-flash";
+                                        reg = <0x00000000 0x00100000>;
+                                };
+                        };
+                };
+
+                ssi@15000 {
+                        fsl,mode = "i2s-slave";
+                        codec-handle = <&wm8960>;
+                };
+
+                usb@22000 {
+                        phy_type = "ulpi";
+                };
+
+                usb@23000 {
+                        phy_type = "ulpi";
+                };
+
+                mdio@24000 {
+                        phy0: ethernet-phy@0 {
+                                interrupts = <3 1 0 0>;
+                                reg = <0x1>;
+                        };
+                        phy1: ethernet-phy@1 {
+                                interrupts = <9 1 0 0>;
+                                reg = <0x2>;
+                        };
+                };
+
+                mdio@25000 {
+                        tbi0: tbi-phy@11 {
+                                reg = <0x11>;
+                                device_type = "tbi-phy";
+                        };
+                };
+
+                ethernet@b0000 {
+                        phy-handle = <&phy0>;
+                        phy-connection-type = "rgmii-id";
+                };
+
+                ethernet@b1000 {
+                        phy-handle = <&phy1>;
+                        tbi-handle = <&tbi0>;
+                        phy-connection-type = "sgmii";
+                };
+        };
+
+        pci0: pcie@ffe09000 {
+                ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+                reg = <0x0 0xffe09000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@ffe0a000 {
+                ranges = <0x2000000 0x0 0xe0000000 0 0xc0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+                reg = <0 0xffe0a000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci2: pcie@ffe0b000 {
+                ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+                reg = <0 0xffe0b000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+
+/include/ "fsl/p1022si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
deleted file mode 100644
index 66aac864c4cc..000000000000
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * P2020 RDB  Core0 Device Tree Source in CAMP mode.
- *
- * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
- * can be shared, all the other devices must be assigned to one core only.
- * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb,
- * eth1, eth2, sdhc, crypto, global-util, pci0.
- *
- * Copyright 2009-2011 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-/include/ "p2020rdb.dts"
-
-/ {
-        model = "fsl,P2020RDB";
-        compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
-
-        cpus {
-                PowerPC,P2020@1 {
-                        status = "disabled";
-                };
-        };
-
-        localbus@ffe05000 {
-                status = "disabled";
-        };
-
-        soc@ffe00000 {
-                serial1: serial@4600 {
-                        status = "disabled";
-                };
-
-                dma@c300 {
-                        status = "disabled";
-                };
-
-                enet0: ethernet@24000 {
-                        status = "disabled";
-                };
-
-                mpic: pic@40000 {
-                        protected-sources = <
-                        42 76 77 78 79 /* serial1 , dma2 */
-                        29 30 34 26 /* enet0, pci1 */
-                        0xe0 0xe1 0xe2 0xe3 /* msi */
-                        0xe4 0xe5 0xe6 0xe7
-                        >;
-                };
-
-                msi@41600 {
-                        status = "disabled";
-                };
-        };
-
-        pci0: pcie@ffe08000 {
-                status = "disabled";
-        };
-
-        pci2: pcie@ffe0a000 {
-                status = "disabled";
-        };
-};
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
deleted file mode 100644
index 9bd8ef493dd2..000000000000
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * P2020 RDB Core1 Device Tree Source in CAMP mode.
- *
- * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
- * can be shared, all the other devices must be assigned to one core only.
- * This dts allows core1 to have l2, dma2, eth0, pci1, msi.
- *
- * Please note to add "-b 1" for core1's dts compiling.
- *
- * Copyright 2009-2011 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-/include/ "p2020rdb.dts"
-
-/ {
-        model = "fsl,P2020RDB";
-        compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
-
-        cpus {
-                PowerPC,P2020@0 {
-                        status = "disabled";
-                };
-        };
-
-        localbus@ffe05000 {
-                status = "disabled";
-        };
-
-        soc@ffe00000 {
-                ecm-law@0 {
-                        status = "disabled";
-                };
-
-                ecm@1000 {
-                        status = "disabled";
-                };
-
-                memory-controller@2000 {
-                        status = "disabled";
-                };
-
-                i2c@3000 {
-                        status = "disabled";
-                };
-
-                i2c@3100 {
-                        status = "disabled";
-                };
-
-                serial0: serial@4500 {
-                        status = "disabled";
-                };
-
-                spi@7000 {
-                        status = "disabled";
-                };
-
-                gpio: gpio-controller@f000 {
-                        status = "disabled";
-                };
-
-                dma@21300 {
-                        status = "disabled";
-                };
-
-                usb@22000 {
-                        status = "disabled";
-                };
-
-                mdio@24520 {
-                        status = "disabled";
-                };
-
-                mdio@25520 {
-                        status = "disabled";
-                };
-
-                mdio@26520 {
-                        status = "disabled";
-                };
-
-                enet1: ethernet@25000 {
-                        status = "disabled";
-                };
-
-                enet2: ethernet@26000 {
-                        status = "disabled";
-                };
-
-                sdhci@2e000 {
-                        status = "disabled";
-                };
-
-                crypto@30000 {
-                        status = "disabled";
-                };
-
-                mpic: pic@40000 {
-                        protected-sources = <
-                        17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */
-                        16 20 21 22 23 28       /* L2, dma1, USB */
-                        03 35 36 40 31 32 33    /* mdio, enet1, enet2 */
-                        72 45 58 25             /* sdhci, crypto , pci */
-                        >;
-                };
-
-                global-utilities@e0000 {        //global utilities block
-                        status = "disabled";
-                };
-
-        };
-
-        pci0: pcie@ffe08000 {
-                status = "disabled";
-        };
-
-        pci1: pcie@ffe09000 {
-                status = "disabled";
-        };
-};
diff --git a/arch/powerpc/boot/dts/p2041rdb.dts b/arch/powerpc/boot/dts/p2041rdb.dts
index baab0347dab0..d97ad74c7279 100644
--- a/arch/powerpc/boot/dts/p2041rdb.dts
+++ b/arch/powerpc/boot/dts/p2041rdb.dts
@@ -94,6 +94,10 @@
                                 compatible = "pericom,pt7c4338";
                                 reg = <0x68>;
                         };
+                        adt7461@4c {
+                                compatible = "adi,adt7461";
+                                reg = <0x4c>;
+                        };
                 };
 
                 i2c@118100 {
diff --git a/arch/powerpc/boot/dts/p3041ds.dts b/arch/powerpc/boot/dts/p3041ds.dts
index 6cdcadc80c30..2fed3bc0b990 100644
--- a/arch/powerpc/boot/dts/p3041ds.dts
+++ b/arch/powerpc/boot/dts/p3041ds.dts
@@ -98,6 +98,10 @@
                                 reg = <0x68>;
                                 interrupts = <0x1 0x1 0 0>;
                         };
+                        adt7461@4c {
+                                compatible = "adi,adt7461";
+                                reg = <0x4c>;
+                        };
                 };
         };
 
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index 3e204609d02e..1cf6148b8b05 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -96,6 +96,10 @@
                                 reg = <0x68>;
                                 interrupts = <0x1 0x1 0 0>;
                         };
+                        adt7461@4c {
+                                compatible = "adi,adt7461";
+                                reg = <0x4c>;
+                        };
                 };
 
                 usb0: usb@210000 {
diff --git a/arch/powerpc/boot/dts/p5020ds.dts b/arch/powerpc/boot/dts/p5020ds.dts
index 27c07ed6adc1..2869fea717dd 100644
--- a/arch/powerpc/boot/dts/p5020ds.dts
+++ b/arch/powerpc/boot/dts/p5020ds.dts
@@ -98,6 +98,10 @@
                                 reg = <0x68>;
                                 interrupts = <0x1 0x1 0 0>;
                         };
+                        adt7461@4c {
+                                compatible = "adi,adt7461";
+                                reg = <0x4c>;
+                        };
                 };
         };
 
diff --git a/arch/powerpc/boot/dts/p5040ds.dts b/arch/powerpc/boot/dts/p5040ds.dts
new file mode 100644
index 000000000000..860b5ccf76c0
--- /dev/null
+++ b/arch/powerpc/boot/dts/p5040ds.dts
@@ -0,0 +1,207 @@
+/*
+ * P5040DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of this
+ * software, even if advised of the possibility of such damage.
+ */
+
+/include/ "fsl/p5040si-pre.dtsi"
+
+/ {
+        model = "fsl,P5040DS";
+        compatible = "fsl,P5040DS";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+
+        memory {
+                device_type = "memory";
+        };
+
+        dcsr: dcsr@f00000000 {
+                ranges = <0x00000000 0xf 0x00000000 0x01008000>;
+        };
+
+        soc: soc@ffe000000 {
+                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+                reg = <0xf 0xfe000000 0 0x00001000>;
+                spi@110000 {
+                        flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "spansion,s25sl12801";
+                                reg = <0>;
+                                spi-max-frequency = <40000000>; /* input clock */
+                                partition@u-boot {
+                                        label = "u-boot";
+                                        reg = <0x00000000 0x00100000>;
+                                };
+                                partition@kernel {
+                                        label = "kernel";
+                                        reg = <0x00100000 0x00500000>;
+                                };
+                                partition@dtb {
+                                        label = "dtb";
+                                        reg = <0x00600000 0x00100000>;
+                                };
+                                partition@fs {
+                                        label = "file system";
+                                        reg = <0x00700000 0x00900000>;
+                                };
+                        };
+                };
+
+                i2c@118100 {
+                        eeprom@51 {
+                                compatible = "at24,24c256";
+                                reg = <0x51>;
+                        };
+                        eeprom@52 {
+                                compatible = "at24,24c256";
+                                reg = <0x52>;
+                        };
+                };
+
+                i2c@119100 {
+                        rtc@68 {
+                                compatible = "dallas,ds3232";
+                                reg = <0x68>;
+                                interrupts = <0x1 0x1 0 0>;
+                        };
+                        adt7461@4c {
+                                compatible = "adi,adt7461";
+                                reg = <0x4c>;
+                        };
+                };
+        };
+
+        lbc: localbus@ffe124000 {
+                reg = <0xf 0xfe124000 0 0x1000>;
+                ranges = <0 0 0xf 0xe8000000 0x08000000
+                          2 0 0xf 0xffa00000 0x00040000
+                          3 0 0xf 0xffdf0000 0x00008000>;
+
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x08000000>;
+                        bank-width = <2>;
+                        device-width = <2>;
+                };
+
+                nand@2,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,elbc-fcm-nand";
+                        reg = <0x2 0x0 0x40000>;
+
+                        partition@0 {
+                                label = "NAND U-Boot Image";
+                                reg = <0x0 0x02000000>;
+                        };
+
+                        partition@2000000 {
+                                label = "NAND Root File System";
+                                reg = <0x02000000 0x10000000>;
+                        };
+
+                        partition@12000000 {
+                                label = "NAND Compressed RFS Image";
+                                reg = <0x12000000 0x08000000>;
+                        };
+
+                        partition@1a000000 {
+                                label = "NAND Linux Kernel Image";
+                                reg = <0x1a000000 0x04000000>;
+                        };
+
+                        partition@1e000000 {
+                                label = "NAND DTB Image";
+                                reg = <0x1e000000 0x01000000>;
+                        };
+
+                        partition@1f000000 {
+                                label = "NAND Writable User area";
+                                reg = <0x1f000000 0x01000000>;
+                        };
+                };
+
+                board-control@3,0 {
+                        compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
+                        reg = <3 0 0x40>;
+                };
+        };
+
+        pci0: pcie@ffe200000 {
+                reg = <0xf 0xfe200000 0 0x1000>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+                          0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+
+        pci1: pcie@ffe201000 {
+                reg = <0xf 0xfe201000 0 0x1000>;
+                ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+                          0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+
+        pci2: pcie@ffe202000 {
+                reg = <0xf 0xfe202000 0 0x1000>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
+                          0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+};
+
+/include/ "fsl/p5040si-post.dtsi"
diff --git a/arch/powerpc/configs/85xx/p1023rds_defconfig b/arch/powerpc/configs/85xx/p1023rds_defconfig
index 26e541c4662b..b80bcc69d1f7 100644
--- a/arch/powerpc/configs/85xx/p1023rds_defconfig
+++ b/arch/powerpc/configs/85xx/p1023rds_defconfig
@@ -112,6 +112,12 @@ CONFIG_SND=y
 CONFIG_SND_MIXER_OSS=y
 CONFIG_SND_PCM_OSS=y
 # CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_FSL=y
+CONFIG_USB_STORAGE=y
 CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_RTC_CLASS=y
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index 8b3d57c1ebe8..1c0f2432ecdb 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -27,6 +27,7 @@ CONFIG_P2041_RDB=y
 CONFIG_P3041_DS=y
 CONFIG_P4080_DS=y
 CONFIG_P5020_DS=y
+CONFIG_P5040_DS=y
 CONFIG_HIGHMEM=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_MISC=m
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 0516e22ca3de..88fa5c46f66f 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -23,6 +23,7 @@ CONFIG_MODVERSIONS=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_MAC_PARTITION=y
 CONFIG_P5020_DS=y
+CONFIG_P5040_DS=y
 # CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
 CONFIG_BINFMT_MISC=m
 CONFIG_IRQ_ALL_CPUS=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 8b5bda27d248..cf815e847cdc 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -30,6 +30,7 @@ CONFIG_MPC85xx_DS=y
 CONFIG_MPC85xx_RDB=y
 CONFIG_P1010_RDB=y
 CONFIG_P1022_DS=y
+CONFIG_P1022_RDK=y
 CONFIG_P1023_RDS=y
 CONFIG_SOCRATES=y
 CONFIG_KSI8560=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index b0974e7e98ae..502cd9e027e4 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -32,6 +32,7 @@ CONFIG_MPC85xx_DS=y
 CONFIG_MPC85xx_RDB=y
 CONFIG_P1010_RDB=y
 CONFIG_P1022_DS=y
+CONFIG_P1022_RDK=y
 CONFIG_P1023_RDS=y
 CONFIG_SOCRATES=y
 CONFIG_KSI8560=y
diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig
index de7c4c53f5cf..6d03530b7506 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -51,6 +51,7 @@ CONFIG_KEXEC=y
 CONFIG_IRQ_ALL_CPUS=y
 CONFIG_MEMORY_HOTREMOVE=y
 CONFIG_SCHED_SMT=y
+CONFIG_PPC_DENORMALISATION=y
 CONFIG_PCCARD=y
 CONFIG_ELECTRA_CF=y
 CONFIG_HOTPLUG_PCI=m
diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig
index 9f4a9368f51b..1f710a32ffae 100644
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -48,6 +48,7 @@ CONFIG_MEMORY_HOTREMOVE=y
 CONFIG_PPC_64K_PAGES=y
 CONFIG_PPC_SUBPAGE_PROT=y
 CONFIG_SCHED_SMT=y
+CONFIG_PPC_DENORMALISATION=y
 CONFIG_HOTPLUG_PCI=m
 CONFIG_HOTPLUG_PCI_RPA=m
 CONFIG_HOTPLUG_PCI_RPA_DLPAR=m
diff --git a/arch/powerpc/include/asm/abs_addr.h b/arch/powerpc/include/asm/abs_addr.h
deleted file mode 100644
index 9d92ba04b033..000000000000
--- a/arch/powerpc/include/asm/abs_addr.h
+++ /dev/null
@@ -1,56 +0,0 @@
-#ifndef _ASM_POWERPC_ABS_ADDR_H
-#define _ASM_POWERPC_ABS_ADDR_H
-#ifdef __KERNEL__
-
-
-/*
- * c 2001 PPC 64 Team, IBM Corp
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/memblock.h>
-
-#include <asm/types.h>
-#include <asm/page.h>
-#include <asm/prom.h>
-
-struct mschunks_map {
-        unsigned long num_chunks;
-        unsigned long chunk_size;
-        unsigned long chunk_shift;
-        unsigned long chunk_mask;
-        u32 *mapping;
-};
-
-extern struct mschunks_map mschunks_map;
-
-/* Chunks are 256 KB */
-#define MSCHUNKS_CHUNK_SHIFT    (18)
-#define MSCHUNKS_CHUNK_SIZE     (1UL << MSCHUNKS_CHUNK_SHIFT)
-#define MSCHUNKS_OFFSET_MASK    (MSCHUNKS_CHUNK_SIZE - 1)
-
-static inline unsigned long chunk_to_addr(unsigned long chunk)
-{
-        return chunk << MSCHUNKS_CHUNK_SHIFT;
-}
-
-static inline unsigned long addr_to_chunk(unsigned long addr)
-{
-        return addr >> MSCHUNKS_CHUNK_SHIFT;
-}
-
-static inline unsigned long phys_to_abs(unsigned long pa)
-{
-        return pa;
-}
-
-/* Convenience macros */
-#define virt_to_abs(va) phys_to_abs(__pa(va))
-#define abs_to_virt(aa) __va(aa)
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_ABS_ADDR_H */
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index efdc92618b38..dc2cf9c6d9e6 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -288,6 +288,16 @@ static __inline__ int test_bit_le(unsigned long nr,
         return (tmp[nr >> 3] >> (nr & 7)) & 1;
 }
 
+static inline void set_bit_le(int nr, void *addr)
+{
+        set_bit(nr ^ BITOP_LE_SWIZZLE, addr);
+}
+
+static inline void clear_bit_le(int nr, void *addr)
+{
+        clear_bit(nr ^ BITOP_LE_SWIZZLE, addr);
+}
+
 static inline void __set_bit_le(int nr, void *addr)
 {
         __set_bit(nr ^ BITOP_LE_SWIZZLE, addr);
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index ab9e402518e8..b843e35122e8 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -30,6 +30,8 @@ extern void flush_dcache_page(struct page *page);
 #define flush_dcache_mmap_lock(mapping)         do { } while (0)
 #define flush_dcache_mmap_unlock(mapping)       do { } while (0)
 
+extern void __flush_disable_L1(void);
+
 extern void __flush_icache_range(unsigned long, unsigned long);
 static inline void flush_icache_range(unsigned long start, unsigned long stop)
 {
diff --git a/arch/powerpc/include/asm/compat.h b/arch/powerpc/include/asm/compat.h
index 88e602f6430d..84fdf6857c31 100644
--- a/arch/powerpc/include/asm/compat.h
+++ b/arch/powerpc/include/asm/compat.h
@@ -38,6 +38,7 @@ typedef s64		compat_s64;
 typedef u32             compat_uint_t;
 typedef u32             compat_ulong_t;
 typedef u64             compat_u64;
+typedef u32             compat_uptr_t;
 
 struct compat_timespec {
         compat_time_t   tv_sec;
@@ -114,6 +115,64 @@ typedef u32		compat_old_sigset_t;
 
 typedef u32             compat_sigset_word;
 
+typedef union compat_sigval {
+        compat_int_t    sival_int;
+        compat_uptr_t   sival_ptr;
+} compat_sigval_t;
+
+#define SI_PAD_SIZE32   (128/sizeof(int) - 3)
+
+typedef struct compat_siginfo {
+        int si_signo;
+        int si_errno;
+        int si_code;
+
+        union {
+                int _pad[SI_PAD_SIZE32];
+
+                /* kill() */
+                struct {
+                        compat_pid_t _pid;              /* sender's pid */
+                        __compat_uid_t _uid;            /* sender's uid */
+                } _kill;
+
+                /* POSIX.1b timers */
+                struct {
+                        compat_timer_t _tid;            /* timer id */
+                        int _overrun;                   /* overrun count */
+                        compat_sigval_t _sigval;        /* same as below */
+                        int _sys_private;       /* not to be passed to user */
+                } _timer;
+
+                /* POSIX.1b signals */
+                struct {
+                        compat_pid_t _pid;              /* sender's pid */
+                        __compat_uid_t _uid;            /* sender's uid */
+                        compat_sigval_t _sigval;
+                } _rt;
+
+                /* SIGCHLD */
+                struct {
+                        compat_pid_t _pid;              /* which child */
+                        __compat_uid_t _uid;            /* sender's uid */
+                        int _status;                    /* exit code */
+                        compat_clock_t _utime;
+                        compat_clock_t _stime;
+                } _sigchld;
+
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS, SIGEMT */
+                struct {
+                        unsigned int _addr; /* faulting insn/memory ref. */
+                } _sigfault;
+
+                /* SIGPOLL */
+                struct {
+                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
+                        int _fd;
+                } _sigpoll;
+        } _sifields;
+} compat_siginfo_t;
+
 #define COMPAT_OFF_T_MAX        0x7fffffff
 #define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
 
@@ -123,7 +182,6 @@ typedef u32		compat_sigset_word;
  * as pointers because the syscall entry code will have
  * appropriately converted them already.
  */
-typedef u32             compat_uptr_t;
 
 static inline void __user *compat_ptr(compat_uptr_t uptr)
 {
diff --git a/arch/powerpc/include/asm/debug.h b/arch/powerpc/include/asm/debug.h
index 716d2f089eb6..32de2577bb6d 100644
--- a/arch/powerpc/include/asm/debug.h
+++ b/arch/powerpc/include/asm/debug.h
@@ -44,7 +44,7 @@ static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
 static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
 #endif
 
-extern int set_dabr(unsigned long dabr);
+extern int set_dabr(unsigned long dabr, unsigned long dabrx);
 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 extern void do_send_trap(struct pt_regs *regs, unsigned long address,
                          unsigned long error_code, int signal_code, int brkpt);
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index d60f99814ffb..b0ef73882b38 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -32,27 +32,62 @@ struct device_node;
 #ifdef CONFIG_EEH
 
 /*
+ * The struct is used to trace PE related EEH functionality.
+ * In theory, there will have one instance of the struct to
+ * be created against particular PE. In nature, PEs corelate
+ * to each other. the struct has to reflect that hierarchy in
+ * order to easily pick up those affected PEs when one particular
+ * PE has EEH errors.
+ *
+ * Also, one particular PE might be composed of PCI device, PCI
+ * bus and its subordinate components. The struct also need ship
+ * the information. Further more, one particular PE is only meaingful
+ * in the corresponding PHB. Therefore, the root PEs should be created
+ * against existing PHBs in on-to-one fashion.
+ */
+#define EEH_PE_INVALID  (1 << 0)        /* Invalid   */
+#define EEH_PE_PHB      (1 << 1)        /* PHB PE    */
+#define EEH_PE_DEVICE   (1 << 2)        /* Device PE */
+#define EEH_PE_BUS      (1 << 3)        /* Bus PE    */
+
+#define EEH_PE_ISOLATED         (1 << 0)        /* Isolated PE          */
+#define EEH_PE_RECOVERING       (1 << 1)        /* Recovering PE        */
+
+struct eeh_pe {
+        int type;                       /* PE type: PHB/Bus/Device      */
+        int state;                      /* PE EEH dependent mode        */
+        int config_addr;                /* Traditional PCI address      */
+        int addr;                       /* PE configuration address     */
+        struct pci_controller *phb;     /* Associated PHB               */
+        int check_count;                /* Times of ignored error       */
+        int freeze_count;               /* Times of froze up            */
+        int false_positives;            /* Times of reported #ff's      */
+        struct eeh_pe *parent;          /* Parent PE                    */
+        struct list_head child_list;    /* Link PE to the child list    */
+        struct list_head edevs;         /* Link list of EEH devices     */
+        struct list_head child;         /* Child PEs                    */
+};
+
+#define eeh_pe_for_each_dev(pe, edev) \
+                list_for_each_entry(edev, &pe->edevs, list)
+
+/*
  * The struct is used to trace EEH state for the associated
  * PCI device node or PCI device. In future, it might
  * represent PE as well so that the EEH device to form
  * another tree except the currently existing tree of PCI
  * buses and PCI devices
  */
-#define EEH_MODE_SUPPORTED      (1<<0)  /* EEH supported on the device  */
-#define EEH_MODE_NOCHECK        (1<<1)  /* EEH check should be skipped  */
-#define EEH_MODE_ISOLATED       (1<<2)  /* The device has been isolated */
-#define EEH_MODE_RECOVERING     (1<<3)  /* Recovering the device        */
-#define EEH_MODE_IRQ_DISABLED   (1<<4)  /* Interrupt disabled           */
+#define EEH_DEV_IRQ_DISABLED    (1<<0)  /* Interrupt disabled           */
 
 struct eeh_dev {
         int mode;                       /* EEH mode                     */
         int class_code;                 /* Class code of the device     */
         int config_addr;                /* Config address               */
         int pe_config_addr;             /* PE config address            */
-        int check_count;                /* Times of ignored error       */
-        int freeze_count;               /* Times of froze up            */
-        int false_positives;            /* Times of reported #ff's      */
         u32 config_space[16];           /* Saved PCI config space       */
+        struct eeh_pe *pe;              /* Associated PE                */
+        struct list_head list;          /* Form link list in the PE     */
         struct pci_controller *phb;     /* Associated PHB               */
         struct device_node *dn;         /* Associated device node       */
         struct pci_dev *pdev;           /* Associated PCI device        */
@@ -95,19 +130,51 @@ static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
 struct eeh_ops {
         char *name;
         int (*init)(void);
-        int (*set_option)(struct device_node *dn, int option);
-        int (*get_pe_addr)(struct device_node *dn);
-        int (*get_state)(struct device_node *dn, int *state);
-        int (*reset)(struct device_node *dn, int option);
-        int (*wait_state)(struct device_node *dn, int max_wait);
-        int (*get_log)(struct device_node *dn, int severity, char *drv_log, unsigned long len);
-        int (*configure_bridge)(struct device_node *dn);
+        void* (*of_probe)(struct device_node *dn, void *flag);
+        void* (*dev_probe)(struct pci_dev *dev, void *flag);
+        int (*set_option)(struct eeh_pe *pe, int option);
+        int (*get_pe_addr)(struct eeh_pe *pe);
+        int (*get_state)(struct eeh_pe *pe, int *state);
+        int (*reset)(struct eeh_pe *pe, int option);
+        int (*wait_state)(struct eeh_pe *pe, int max_wait);
+        int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
+        int (*configure_bridge)(struct eeh_pe *pe);
         int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
         int (*write_config)(struct device_node *dn, int where, int size, u32 val);
 };
 
 extern struct eeh_ops *eeh_ops;
 extern int eeh_subsystem_enabled;
+extern struct mutex eeh_mutex;
+extern int eeh_probe_mode;
+
+#define EEH_PROBE_MODE_DEV      (1<<0)  /* From PCI device      */
+#define EEH_PROBE_MODE_DEVTREE  (1<<1)  /* From device tree     */
+
+static inline void eeh_probe_mode_set(int flag)
+{
+        eeh_probe_mode = flag;
+}
+
+static inline int eeh_probe_mode_devtree(void)
+{
+        return (eeh_probe_mode == EEH_PROBE_MODE_DEVTREE);
+}
+
+static inline int eeh_probe_mode_dev(void)
+{
+        return (eeh_probe_mode == EEH_PROBE_MODE_DEV);
+}
+
+static inline void eeh_lock(void)
+{
+        mutex_lock(&eeh_mutex);
+}
+
+static inline void eeh_unlock(void)
+{
+        mutex_unlock(&eeh_mutex);
+}
 
 /*
  * Max number of EEH freezes allowed before we consider the device
@@ -115,22 +182,26 @@ extern int eeh_subsystem_enabled;
  */
 #define EEH_MAX_ALLOWED_FREEZES 5
 
+typedef void *(*eeh_traverse_func)(void *data, void *flag);
+int __devinit eeh_phb_pe_create(struct pci_controller *phb);
+int eeh_add_to_parent_pe(struct eeh_dev *edev);
+int eeh_rmv_from_parent_pe(struct eeh_dev *edev, int purge_pe);
+void *eeh_pe_dev_traverse(struct eeh_pe *root,
+                eeh_traverse_func fn, void *flag);
+void eeh_pe_restore_bars(struct eeh_pe *pe);
+struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
+
 void * __devinit eeh_dev_init(struct device_node *dn, void *data);
 void __devinit eeh_dev_phb_init_dynamic(struct pci_controller *phb);
-void __init eeh_dev_phb_init(void);
-void __init eeh_init(void);
-#ifdef CONFIG_PPC_PSERIES
-int __init eeh_pseries_init(void);
-#endif
 int __init eeh_ops_register(struct eeh_ops *ops);
 int __exit eeh_ops_unregister(const char *name);
 unsigned long eeh_check_failure(const volatile void __iomem *token,
                                 unsigned long val);
-int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev);
-void __init pci_addr_cache_build(void);
+int eeh_dev_check_failure(struct eeh_dev *edev);
+void __init eeh_addr_cache_build(void);
 void eeh_add_device_tree_early(struct device_node *);
 void eeh_add_device_tree_late(struct pci_bus *);
-void eeh_remove_bus_device(struct pci_dev *);
+void eeh_remove_bus_device(struct pci_dev *, int);
 
 /**
  * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
@@ -156,34 +227,24 @@ static inline void *eeh_dev_init(struct device_node *dn, void *data)
 
 static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
 
-static inline void eeh_dev_phb_init(void) { }
-
-static inline void eeh_init(void) { }
-
-#ifdef CONFIG_PPC_PSERIES
-static inline int eeh_pseries_init(void)
-{
-        return 0;
-}
-#endif /* CONFIG_PPC_PSERIES */
-
 static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
 {
         return val;
 }
 
-static inline int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
-{
-        return 0;
-}
+#define eeh_dev_check_failure(x) (0)
 
-static inline void pci_addr_cache_build(void) { }
+static inline void eeh_addr_cache_build(void) { }
 
 static inline void eeh_add_device_tree_early(struct device_node *dn) { }
 
 static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
 
-static inline void eeh_remove_bus_device(struct pci_dev *dev) { }
+static inline void eeh_remove_bus_device(struct pci_dev *dev, int purge_pe) { }
+
+static inline void eeh_lock(void) { }
+static inline void eeh_unlock(void) { }
+
 #define EEH_POSSIBLE_ERROR(val, type) (0)
 #define EEH_IO_ERROR_VALUE(size) (-1UL)
 #endif /* CONFIG_EEH */
diff --git a/arch/powerpc/include/asm/eeh_event.h b/arch/powerpc/include/asm/eeh_event.h
index c68b012b7797..de67d830151b 100644
--- a/arch/powerpc/include/asm/eeh_event.h
+++ b/arch/powerpc/include/asm/eeh_event.h
@@ -28,11 +28,11 @@
  */
 struct eeh_event {
         struct list_head        list;   /* to form event queue  */
-        struct eeh_dev          *edev;  /* EEH device           */
+        struct eeh_pe           *pe;    /* EEH PE               */
 };
 
-int eeh_send_failure_event(struct eeh_dev *edev);
-struct eeh_dev *handle_eeh_events(struct eeh_event *);
+int eeh_send_failure_event(struct eeh_pe *pe);
+void eeh_handle_event(struct eeh_pe *pe);
 
 #endif /* __KERNEL__ */
 #endif /* ASM_POWERPC_EEH_EVENT_H */
diff --git a/arch/powerpc/include/asm/exception-64e.h b/arch/powerpc/include/asm/exception-64e.h
index ac13addb8495..51fa43e536b9 100644
--- a/arch/powerpc/include/asm/exception-64e.h
+++ b/arch/powerpc/include/asm/exception-64e.h
@@ -37,6 +37,7 @@
  * critical data
  */
 
+#define PACA_EXGDBELL PACA_EXGEN
 
 /* We are out of SPRGs so we save some things in the PACA. The normal
  * exception frame is smaller than the CRIT or MC one though
@@ -45,8 +46,9 @@
 #define EX_CR           (1 * 8)
 #define EX_R10          (2 * 8)
 #define EX_R11          (3 * 8)
-#define EX_R14          (4 * 8)
-#define EX_R15          (5 * 8)
+#define EX_R13          (4 * 8)
+#define EX_R14          (5 * 8)
+#define EX_R15          (6 * 8)
 
 /*
  * The TLB miss exception uses different slots.
diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h
index aa4c488589ce..dd5ba2c22771 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -48,6 +48,8 @@ struct ccsr_guts {
         __be32  dmuxcr;         /* 0x.0068 - DMA Mux Control Register */
         u8      res06c[0x70 - 0x6c];
         __be32  devdisr;        /* 0x.0070 - Device Disable Control */
+#define CCSR_GUTS_DEVDISR_TB1   0x00001000
+#define CCSR_GUTS_DEVDISR_TB0   0x00004000
         __be32  devdisr2;       /* 0x.0074 - Device Disable Control 2 */
         u8      res078[0x7c - 0x78];
         __be32  pmjcr;          /* 0x.007c - 4 Power Management Jog Control Register */
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
index b955012939a2..b8a4b9bc50b3 100644
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -768,22 +768,24 @@ struct fsl_ifc_gpcm {
  */
 struct fsl_ifc_regs {
         __be32 ifc_rev;
-        u32 res1[0x3];
+        u32 res1[0x2];
         struct {
+                __be32 cspr_ext;
                 __be32 cspr;
-                u32 res2[0x2];
+                u32 res2;
         } cspr_cs[FSL_IFC_BANK_COUNT];
-        u32 res3[0x18];
+        u32 res3[0x19];
         struct {
                 __be32 amask;
                 u32 res4[0x2];
         } amask_cs[FSL_IFC_BANK_COUNT];
-        u32 res5[0x18];
+        u32 res5[0x17];
         struct {
+                __be32 csor_ext;
                 __be32 csor;
-                u32 res6[0x2];
+                u32 res6;
         } csor_cs[FSL_IFC_BANK_COUNT];
-        u32 res7[0x18];
+        u32 res7[0x19];
         struct {
                 __be32 ftim[4];
                 u32 res8[0x8];
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index 423cf9eaf4a4..7a867065db79 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -152,11 +152,6 @@
 #define H_VASI_RESUMED          5
 #define H_VASI_COMPLETED        6
 
-/* DABRX flags */
-#define H_DABRX_HYPERVISOR      (1UL<<(63-61))
-#define H_DABRX_KERNEL          (1UL<<(63-62))
-#define H_DABRX_USER            (1UL<<(63-63))
-
 /* Each control block has to be on a 4K boundary */
 #define H_CB_ALIGNMENT          4096
 
diff --git a/arch/powerpc/include/asm/hw_breakpoint.h b/arch/powerpc/include/asm/hw_breakpoint.h
index be04330af751..423424599dad 100644
--- a/arch/powerpc/include/asm/hw_breakpoint.h
+++ b/arch/powerpc/include/asm/hw_breakpoint.h
@@ -27,10 +27,11 @@
 #ifdef CONFIG_HAVE_HW_BREAKPOINT
 
 struct arch_hw_breakpoint {
-        bool            extraneous_interrupt;
-        u8              len; /* length of the target data symbol */
-        int             type;
         unsigned long   address;
+        unsigned long   dabrx;
+        int             type;
+        u8              len; /* length of the target data symbol */
+        bool            extraneous_interrupt;
 };
 
 #include <linux/kdebug.h>
@@ -61,7 +62,7 @@ extern void ptrace_triggered(struct perf_event *bp,
                         struct perf_sample_data *data, struct pt_regs *regs);
 static inline void hw_breakpoint_disable(void)
 {
-        set_dabr(0);
+        set_dabr(0, 0);
 }
 extern void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs);
 
diff --git a/arch/powerpc/include/asm/kprobes.h b/arch/powerpc/include/asm/kprobes.h
index be0171afdc0f..7b6feab6fd26 100644
--- a/arch/powerpc/include/asm/kprobes.h
+++ b/arch/powerpc/include/asm/kprobes.h
@@ -29,21 +29,16 @@
 #include <linux/types.h>
 #include <linux/ptrace.h>
 #include <linux/percpu.h>
+#include <asm/probes.h>
 
 #define  __ARCH_WANT_KPROBES_INSN_SLOT
 
 struct pt_regs;
 struct kprobe;
 
-typedef unsigned int kprobe_opcode_t;
-#define BREAKPOINT_INSTRUCTION  0x7fe00008      /* trap */
+typedef ppc_opcode_t kprobe_opcode_t;
 #define MAX_INSN_SIZE 1
 
-#define IS_TW(instr)            (((instr) & 0xfc0007fe) == 0x7c000008)
-#define IS_TD(instr)            (((instr) & 0xfc0007fe) == 0x7c000088)
-#define IS_TDI(instr)           (((instr) & 0xfc000000) == 0x08000000)
-#define IS_TWI(instr)           (((instr) & 0xfc000000) == 0x0c000000)
-
 #ifdef CONFIG_PPC64
 /*
  * 64bit powerpc uses function descriptors.
@@ -72,12 +67,6 @@ typedef unsigned int kprobe_opcode_t;
                 addr = (kprobe_opcode_t *)kallsyms_lookup_name(dot_name); \
         }                                                               \
 }
-
-#define is_trap(instr)  (IS_TW(instr) || IS_TD(instr) || \
-                        IS_TWI(instr) || IS_TDI(instr))
-#else
-/* Use stock kprobe_lookup_name since ppc32 doesn't use function descriptors */
-#define is_trap(instr)  (IS_TW(instr) || IS_TWI(instr))
 #endif
 
 #define flush_insn_slot(p)      do { } while (0)
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
index f0e0c6a66d97..7aefdb3e1ce4 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -59,7 +59,7 @@ struct hpte_cache {
         struct hlist_node list_vpte;
         struct hlist_node list_vpte_long;
         struct rcu_head rcu_head;
-        u64 host_va;
+        u64 host_vpn;
         u64 pfn;
         ulong slot;
         struct kvmppc_pte pte;
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h b/arch/powerpc/include/asm/kvm_book3s_asm.h
index bfcd00c1485d..88609b23b775 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -74,7 +74,6 @@ struct kvmppc_host_state {
         ulong vmhandler;
         ulong scratch0;
         ulong scratch1;
-        ulong sprg3;
         u8 in_guest;
         u8 restore_hid5;
         u8 napping;
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index f7706d722b39..c4231973edd3 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -34,19 +34,19 @@ struct machdep_calls {
         char            *name;
 #ifdef CONFIG_PPC64
         void            (*hpte_invalidate)(unsigned long slot,
-                                           unsigned long va,
+                                           unsigned long vpn,
                                            int psize, int ssize,
                                            int local);
         long            (*hpte_updatepp)(unsigned long slot, 
                                          unsigned long newpp, 
-                                         unsigned long va,
+                                         unsigned long vpn,
                                          int psize, int ssize,
                                          int local);
         void            (*hpte_updateboltedpp)(unsigned long newpp, 
                                                unsigned long ea,
                                                int psize, int ssize);
         long            (*hpte_insert)(unsigned long hpte_group,
-                                       unsigned long va,
+                                       unsigned long vpn,
                                        unsigned long prpn,
                                        unsigned long rflags,
                                        unsigned long vflags,
@@ -180,7 +180,8 @@ struct machdep_calls {
         void            (*enable_pmcs)(void);
 
         /* Set DABR for this platform, leave empty for default implemenation */
-        int             (*set_dabr)(unsigned long dabr);
+        int             (*set_dabr)(unsigned long dabr,
+                                    unsigned long dabrx);
 
 #ifdef CONFIG_PPC32     /* XXX for now */
         /* A general init function, called by ppc_init in init/main.c.
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index 1c65a59881ea..9673f73eb8db 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -16,6 +16,13 @@
 #include <asm/page.h>
 
 /*
+ * This is necessary to get the definition of PGTABLE_RANGE which we
+ * need for various slices related matters. Note that this isn't the
+ * complete pgtable.h but only a portion of it.
+ */
+#include <asm/pgtable-ppc64.h>
+
+/*
  * Segment table
  */
 
@@ -154,9 +161,25 @@ struct mmu_psize_def
 #define MMU_SEGSIZE_256M        0
 #define MMU_SEGSIZE_1T          1
 
+/*
+ * encode page number shift.
+ * in order to fit the 78 bit va in a 64 bit variable we shift the va by
+ * 12 bits. This enable us to address upto 76 bit va.
+ * For hpt hash from a va we can ignore the page size bits of va and for
+ * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
+ * we work in all cases including 4k page size.
+ */
+#define VPN_SHIFT       12
 
 #ifndef __ASSEMBLY__
 
+static inline int segment_shift(int ssize)
+{
+        if (ssize == MMU_SEGSIZE_256M)
+                return SID_SHIFT;
+        return SID_SHIFT_1T;
+}
+
 /*
  * The current system page and segment sizes
  */
@@ -180,18 +203,39 @@ extern unsigned long tce_alloc_start, tce_alloc_end;
 extern int mmu_ci_restrictions;
 
 /*
+ * This computes the AVPN and B fields of the first dword of a HPTE,
+ * for use when we want to match an existing PTE.  The bottom 7 bits
+ * of the returned value are zero.
+ */
+static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
+                                             int ssize)
+{
+        unsigned long v;
+        /*
+         * The AVA field omits the low-order 23 bits of the 78 bits VA.
+         * These bits are not needed in the PTE, because the
+         * low-order b of these bits are part of the byte offset
+         * into the virtual page and, if b < 23, the high-order
+         * 23-b of these bits are always used in selecting the
+         * PTEGs to be searched
+         */
+        v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
+        v <<= HPTE_V_AVPN_SHIFT;
+        v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
+        return v;
+}
+
+/*
  * This function sets the AVPN and L fields of the HPTE  appropriately
  * for the page size
  */
-static inline unsigned long hpte_encode_v(unsigned long va, int psize,
-                                          int ssize)
+static inline unsigned long hpte_encode_v(unsigned long vpn,
+                                          int psize, int ssize)
 {
         unsigned long v;
-        v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
-        v <<= HPTE_V_AVPN_SHIFT;
+        v = hpte_encode_avpn(vpn, psize, ssize);
         if (psize != MMU_PAGE_4K)
                 v |= HPTE_V_LARGE;
-        v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
         return v;
 }
 
@@ -216,30 +260,37 @@ static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
 }
 
 /*
- * Build a VA given VSID, EA and segment size
+ * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
  */
-static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
-                                   int ssize)
+static inline unsigned long hpt_vpn(unsigned long ea,
+                                    unsigned long vsid, int ssize)
 {
-        if (ssize == MMU_SEGSIZE_256M)
-                return (vsid << 28) | (ea & 0xfffffffUL);
-        return (vsid << 40) | (ea & 0xffffffffffUL);
+        unsigned long mask;
+        int s_shift = segment_shift(ssize);
+
+        mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
+        return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
 }
 
 /*
  * This hashes a virtual address
  */
-
-static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
-                                     int ssize)
+static inline unsigned long hpt_hash(unsigned long vpn,
+                                     unsigned int shift, int ssize)
 {
+        int mask;
         unsigned long hash, vsid;
 
+        /* VPN_SHIFT can be atmost 12 */
         if (ssize == MMU_SEGSIZE_256M) {
-                hash = (va >> 28) ^ ((va & 0x0fffffffUL) >> shift);
+                mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
+                hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
+                        ((vpn & mask) >> (shift - VPN_SHIFT));
         } else {
-                vsid = va >> 40;
-                hash = vsid ^ (vsid << 25) ^ ((va & 0xffffffffffUL) >> shift);
+                mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
+                vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
+                hash = vsid ^ (vsid << 25) ^
+                        ((vpn & mask) >> (shift - VPN_SHIFT)) ;
         }
         return hash & 0x7fffffffffUL;
 }
@@ -280,63 +331,61 @@ extern void slb_set_size(u16 size);
 #endif /* __ASSEMBLY__ */
 
 /*
- * VSID allocation
+ * VSID allocation (256MB segment)
+ *
+ * We first generate a 38-bit "proto-VSID".  For kernel addresses this
+ * is equal to the ESID | 1 << 37, for user addresses it is:
+ *      (context << USER_ESID_BITS) | (esid & ((1U << USER_ESID_BITS) - 1)
  *
- * We first generate a 36-bit "proto-VSID".  For kernel addresses this
- * is equal to the ESID, for user addresses it is:
- *      (context << 15) | (esid & 0x7fff)
+ * This splits the proto-VSID into the below range
+ *  0 - (2^(CONTEXT_BITS + USER_ESID_BITS) - 1) : User proto-VSID range
+ *  2^(CONTEXT_BITS + USER_ESID_BITS) - 2^(VSID_BITS) : Kernel proto-VSID range
  *
- * The two forms are distinguishable because the top bit is 0 for user
- * addresses, whereas the top two bits are 1 for kernel addresses.
- * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
- * now.
+ * We also have CONTEXT_BITS + USER_ESID_BITS = VSID_BITS - 1
+ * That is, we assign half of the space to user processes and half
+ * to the kernel.
  *
  * The proto-VSIDs are then scrambled into real VSIDs with the
  * multiplicative hash:
  *
  *      VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
- *      where   VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
- *              VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
  *
- * This scramble is only well defined for proto-VSIDs below
- * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
- * reserved.  VSID_MULTIPLIER is prime, so in particular it is
+ * VSID_MULTIPLIER is prime, so in particular it is
  * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
  * Because the modulus is 2^n-1 we can compute it efficiently without
  * a divide or extra multiply (see below).
  *
  * This scheme has several advantages over older methods:
  *
- *      - We have VSIDs allocated for every kernel address
+ *      - We have VSIDs allocated for every kernel address
  * (i.e. everything above 0xC000000000000000), except the very top
  * segment, which simplifies several things.
  *
- *      - We allow for 16 significant bits of ESID and 19 bits of
- * context for user addresses.  i.e. 16T (44 bits) of address space for
- * up to half a million contexts.
+ *      - We allow for USER_ESID_BITS significant bits of ESID and
+ * CONTEXT_BITS  bits of context for user addresses.
+ *  i.e. 64T (46 bits) of address space for up to half a million contexts.
  *
- *      - The scramble function gives robust scattering in the hash
+ *      - The scramble function gives robust scattering in the hash
  * table (at least based on some initial results).  The previous
  * method was more susceptible to pathological cases giving excessive
  * hash collisions.
  */
+
 /*
- * WARNING - If you change these you must make sure the asm
- * implementations in slb_allocate (slb_low.S), do_stab_bolted
- * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
+ * This should be computed such that protovosid * vsid_mulitplier
+ * doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
  */
-
-#define VSID_MULTIPLIER_256M    ASM_CONST(200730139)    /* 28-bit prime */
-#define VSID_BITS_256M          36
+#define VSID_MULTIPLIER_256M    ASM_CONST(12538073)     /* 24-bit prime */
+#define VSID_BITS_256M          38
 #define VSID_MODULUS_256M       ((1UL<<VSID_BITS_256M)-1)
 
 #define VSID_MULTIPLIER_1T      ASM_CONST(12538073)     /* 24-bit prime */
-#define VSID_BITS_1T            24
+#define VSID_BITS_1T            26
 #define VSID_MODULUS_1T         ((1UL<<VSID_BITS_1T)-1)
 
 #define CONTEXT_BITS            19
-#define USER_ESID_BITS          16
-#define USER_ESID_BITS_1T       4
+#define USER_ESID_BITS          18
+#define USER_ESID_BITS_1T       6
 
 #define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
 
@@ -372,6 +421,8 @@ extern void slb_set_size(u16 size);
         srdi    rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */   \
         add     rt,rt,rx
 
+/* 4 bits per slice and we have one slice per 1TB */
+#define SLICE_ARRAY_SIZE  (PGTABLE_RANGE >> 41)
 
 #ifndef __ASSEMBLY__
 
@@ -416,7 +467,7 @@ typedef struct {
 
 #ifdef CONFIG_PPC_MM_SLICES
         u64 low_slices_psize;   /* SLB page size encodings */
-        u64 high_slices_psize;  /* 4 bits per slice for now */
+        unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
 #else
         u16 sllp;               /* SLB page size encoding */
 #endif
@@ -452,12 +503,32 @@ typedef struct {
         })
 #endif /* 1 */
 
-/* This is only valid for addresses >= PAGE_OFFSET */
+/*
+ * This is only valid for addresses >= PAGE_OFFSET
+ * The proto-VSID space is divided into two class
+ * User:   0 to 2^(CONTEXT_BITS + USER_ESID_BITS) -1
+ * kernel: 2^(CONTEXT_BITS + USER_ESID_BITS) to 2^(VSID_BITS) - 1
+ *
+ * With KERNEL_START at 0xc000000000000000, the proto vsid for
+ * the kernel ends up with 0xc00000000 (36 bits). With 64TB
+ * support we need to have kernel proto-VSID in the
+ * [2^37 to 2^38 - 1] range due to the increased USER_ESID_BITS.
+ */
 static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
 {
-        if (ssize == MMU_SEGSIZE_256M)
-                return vsid_scramble(ea >> SID_SHIFT, 256M);
-        return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
+        unsigned long proto_vsid;
+        /*
+         * We need to make sure proto_vsid for the kernel is
+         * >= 2^(CONTEXT_BITS + USER_ESID_BITS[_1T])
+         */
+        if (ssize == MMU_SEGSIZE_256M) {
+                proto_vsid = ea >> SID_SHIFT;
+                proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS));
+                return vsid_scramble(proto_vsid, 256M);
+        }
+        proto_vsid = ea >> SID_SHIFT_1T;
+        proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS_1T));
+        return vsid_scramble(proto_vsid, 1T);
 }
 
 /* Returns the segment size indicator for a user address */
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index e8a26db2e8f3..5e38eedea218 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -146,6 +146,15 @@ extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 extern u64 ppc64_rma_size;
 #endif /* CONFIG_PPC64 */
 
+struct mm_struct;
+#ifdef CONFIG_DEBUG_VM
+extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
+#else /* CONFIG_DEBUG_VM */
+static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
+{
+}
+#endif /* !CONFIG_DEBUG_VM */
+
 #endif /* !__ASSEMBLY__ */
 
 /* The kernel use the constants below to index in the page sizes array.
diff --git a/arch/powerpc/include/asm/mpc52xx.h b/arch/powerpc/include/asm/mpc52xx.h
index 1f41382eda38..0acc7c7c28d1 100644
--- a/arch/powerpc/include/asm/mpc52xx.h
+++ b/arch/powerpc/include/asm/mpc52xx.h
@@ -307,6 +307,7 @@ struct mpc52xx_lpbfifo_request {
         size_t size;
         size_t pos;     /* current position of transfer */
         int flags;
+        int defer_xfer_start;
 
         /* What to do when finished */
         void (*callback)(struct mpc52xx_lpbfifo_request *);
@@ -323,6 +324,7 @@ struct mpc52xx_lpbfifo_request {
 extern int mpc52xx_lpbfifo_submit(struct mpc52xx_lpbfifo_request *req);
 extern void mpc52xx_lpbfifo_abort(struct mpc52xx_lpbfifo_request *req);
 extern void mpc52xx_lpbfifo_poll(void);
+extern int mpc52xx_lpbfifo_start_xfer(struct mpc52xx_lpbfifo_request *req);
 
 /* mpc52xx_pic.c */
 extern void mpc52xx_init_irq(void);
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c9f698a994be..c0f9ef90f0b8 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -63,6 +63,7 @@
  */
 #define MPIC_TIMER_BASE                 0x01100
 #define MPIC_TIMER_STRIDE               0x40
+#define MPIC_TIMER_GROUP_STRIDE         0x1000
 
 #define MPIC_TIMER_CURRENT_CNT          0x00000
 #define MPIC_TIMER_BASE_CNT             0x00010
@@ -110,10 +111,16 @@
 #define         MPIC_VECPRI_SENSE_MASK                  0x00400000
 #define MPIC_IRQ_DESTINATION            0x00010
 
+#define MPIC_FSL_BRR1                   0x00000
+#define         MPIC_FSL_BRR1_VER                       0x0000ffff
+
 #define MPIC_MAX_IRQ_SOURCES    2048
 #define MPIC_MAX_CPUS           32
 #define MPIC_MAX_ISU            32
 
+#define MPIC_MAX_ERR      32
+#define MPIC_FSL_ERR_INT  16
+
 /*
  * Tsi108 implementation of MPIC has many differences from the original one
  */
@@ -266,6 +273,7 @@ struct mpic
         struct irq_chip         hc_ipi;
 #endif
         struct irq_chip         hc_tm;
+        struct irq_chip         hc_err;
         const char              *name;
         /* Flags */
         unsigned int            flags;
@@ -279,6 +287,8 @@ struct mpic
         /* vector numbers used for internal sources (ipi/timers) */
         unsigned int            ipi_vecs[4];
         unsigned int            timer_vecs[8];
+        /* vector numbers used for FSL MPIC error interrupts */
+        unsigned int            err_int_vecs[MPIC_MAX_ERR];
 
         /* Spurious vector to program into unused sources */
         unsigned int            spurious_vec;
@@ -296,11 +306,15 @@ struct mpic
         phys_addr_t paddr;
 
         /* The various ioremap'ed bases */
+        struct mpic_reg_bank    thiscpuregs;
         struct mpic_reg_bank    gregs;
         struct mpic_reg_bank    tmregs;
         struct mpic_reg_bank    cpuregs[MPIC_MAX_CPUS];
         struct mpic_reg_bank    isus[MPIC_MAX_ISU];
 
+        /* ioremap'ed base for error interrupt registers */
+        u32 __iomem     *err_regs;
+
         /* Protected sources */
         unsigned long           *protected;
 
@@ -365,6 +379,11 @@ struct mpic
 #define MPIC_NO_RESET                   0x00004000
 /* Freescale MPIC (compatible includes "fsl,mpic") */
 #define MPIC_FSL                        0x00008000
+/* Freescale MPIC supports EIMR (error interrupt mask register).
+ * This flag is set for MPIC version >= 4.1 (version determined
+ * from the BRR1 register).
+*/
+#define MPIC_FSL_HAS_EIMR               0x00010000
 
 /* MPIC HW modification ID */
 #define MPIC_REGSET_MASK                0xf0000000
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index daf813fea91f..e9e7a6999bb8 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -100,7 +100,7 @@ struct paca_struct {
         /* SLB related definitions */
         u16 vmalloc_sllp;
         u16 slb_cache_ptr;
-        u16 slb_cache[SLB_CACHE_ENTRIES];
+        u32 slb_cache[SLB_CACHE_ENTRIES];
 #endif /* CONFIG_PPC_STD_MMU_64 */
 
 #ifdef CONFIG_PPC_BOOK3E
@@ -136,6 +136,7 @@ struct paca_struct {
         u8 io_sync;                     /* writel() needs spin_unlock sync */
         u8 irq_work_pending;            /* IRQ_WORK interrupt while soft-disable */
         u8 nap_state_lost;              /* NV GPR values lost in power7_idle */
+        u64 sprg3;                      /* Saved user-visible sprg */
 
 #ifdef CONFIG_PPC_POWERNV
         /* Pointer to OPAL machine check event structure set by the
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index fed85e6290e1..cd915d6b093d 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -78,11 +78,19 @@ extern u64 ppc64_pft_size;
 #define GET_LOW_SLICE_INDEX(addr)       ((addr) >> SLICE_LOW_SHIFT)
 #define GET_HIGH_SLICE_INDEX(addr)      ((addr) >> SLICE_HIGH_SHIFT)
 
+/*
+ * 1 bit per slice and we have one slice per 1TB
+ * Right now we support only 64TB.
+ * IF we change this we will have to change the type
+ * of high_slices
+ */
+#define SLICE_MASK_SIZE 8
+
 #ifndef __ASSEMBLY__
 
 struct slice_mask {
         u16 low_slices;
-        u16 high_slices;
+        u64 high_slices;
 };
 
 struct mm_struct;
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index 8cccbee61519..025a130729bc 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -182,14 +182,25 @@ static inline int pci_device_from_OF_node(struct device_node *np,
 #if defined(CONFIG_EEH)
 static inline struct eeh_dev *of_node_to_eeh_dev(struct device_node *dn)
 {
+        /*
+         * For those OF nodes whose parent isn't PCI bridge, they
+         * don't have PCI_DN actually. So we have to skip them for
+         * any EEH operations.
+         */
+        if (!dn || !PCI_DN(dn))
+                return NULL;
+
         return PCI_DN(dn)->edev;
 }
+#else
+#define of_node_to_eeh_dev(x) (NULL)
 #endif
 
 /** Find the bus corresponding to the indicated device node */
 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
 
 /** Remove all of the PCI devices under this bus */
+extern void __pcibios_remove_pci_devices(struct pci_bus *bus, int purge_pe);
 extern void pcibios_remove_pci_devices(struct pci_bus *bus);
 
 /** Discover new pci devices under this bus, and add them */
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index 078019b5b353..9710be3a2d17 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -49,6 +49,7 @@ struct power_pmu {
 #define PPMU_ALT_SIPR           2       /* uses alternate posn for SIPR/HV */
 #define PPMU_NO_SIPR            4       /* no SIPR/HV in MMCRA at all */
 #define PPMU_NO_CONT_SAMPLING   8       /* no continuous sampling */
+#define PPMU_SIAR_VALID         16      /* Processor has SIAR Valid bit */
 
 /*
  * Values for flags to get_alternatives()
diff --git a/arch/powerpc/include/asm/pgtable-ppc64-4k.h b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
index 6eefdcffa359..12798c9d4b4b 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64-4k.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
@@ -7,7 +7,7 @@
  */
 #define PTE_INDEX_SIZE  9
 #define PMD_INDEX_SIZE  7
-#define PUD_INDEX_SIZE  7
+#define PUD_INDEX_SIZE  9
 #define PGD_INDEX_SIZE  9
 
 #ifndef __ASSEMBLY__
@@ -19,7 +19,7 @@
 
 #define PTRS_PER_PTE    (1 << PTE_INDEX_SIZE)
 #define PTRS_PER_PMD    (1 << PMD_INDEX_SIZE)
-#define PTRS_PER_PUD    (1 << PMD_INDEX_SIZE)
+#define PTRS_PER_PUD    (1 << PUD_INDEX_SIZE)
 #define PTRS_PER_PGD    (1 << PGD_INDEX_SIZE)
 
 /* PMD_SHIFT determines what a second-level page table entry can map */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64-64k.h b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
index 90533ddcd703..be4e2878fbc0 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64-64k.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
@@ -7,7 +7,7 @@
 #define PTE_INDEX_SIZE  12
 #define PMD_INDEX_SIZE  12
 #define PUD_INDEX_SIZE  0
-#define PGD_INDEX_SIZE  4
+#define PGD_INDEX_SIZE  6
 
 #ifndef __ASSEMBLY__
 #define PTE_TABLE_SIZE  (sizeof(real_pte_t) << PTE_INDEX_SIZE)
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index c4205616dfb5..0182c203e411 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -21,17 +21,6 @@
 #define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
 
 
-/* Some sanity checking */
-#if TASK_SIZE_USER64 > PGTABLE_RANGE
-#error TASK_SIZE_USER64 exceeds pagetable range
-#endif
-
-#ifdef CONFIG_PPC_STD_MMU_64
-#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
-#error TASK_SIZE_USER64 exceeds user VSID range
-#endif
-#endif
-
 /*
  * Define the address range of the kernel non-linear virtual area
  */
@@ -41,7 +30,7 @@
 #else
 #define KERN_VIRT_START ASM_CONST(0xD000000000000000)
 #endif
-#define KERN_VIRT_SIZE  PGTABLE_RANGE
+#define KERN_VIRT_SIZE  ASM_CONST(0x0000100000000000)
 
 /*
  * The vmalloc space starts at the beginning of that region, and
@@ -117,9 +106,6 @@
 
 #ifndef __ASSEMBLY__
 
-#include <linux/stddef.h>
-#include <asm/tlbflush.h>
-
 /*
  * This is the default implementation of various PTE accessors, it's
  * used in all cases except Book3S with 64K pages where we have a
@@ -198,7 +184,8 @@
 /* to find an entry in a kernel page-table-directory */
 /* This now only contains the vmalloc pages */
 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
+extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
+                            pte_t *ptep, unsigned long pte, int huge);
 
 /* Atomic PTE updates */
 static inline unsigned long pte_update(struct mm_struct *mm,
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 2e0e4110f7ae..a9cbd3ba5c33 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -9,14 +9,6 @@
 
 struct mm_struct;
 
-#ifdef CONFIG_DEBUG_VM
-extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
-#else /* CONFIG_DEBUG_VM */
-static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
-{
-}
-#endif /* !CONFIG_DEBUG_VM */
-
 #endif /* !__ASSEMBLY__ */
 
 #if defined(CONFIG_PPC64)
@@ -27,6 +19,8 @@ static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
 
 #ifndef __ASSEMBLY__
 
+#include <asm/tlbflush.h>
+
 /* Generic accessors to PTE bits */
 static inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_RW; }
 static inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 4c25319f2fbc..5f73ce63fcae 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -126,6 +126,7 @@
 #define PPC_INST_TLBIVAX                0x7c000624
 #define PPC_INST_TLBSRX_DOT             0x7c0006a5
 #define PPC_INST_XXLOR                  0xf0000510
+#define PPC_INST_XVCPSGNDP              0xf0000780
 
 #define PPC_INST_NAP                    0x4c000364
 #define PPC_INST_SLEEP                  0x4c0003a4
@@ -277,6 +278,8 @@
                                                VSX_XX1((s), a, b))
 #define XXLOR(t, a, b)          stringify_in_c(.long PPC_INST_XXLOR | \
                                                VSX_XX3((t), a, b))
+#define XVCPSGNDP(t, a, b)      stringify_in_c(.long (PPC_INST_XVCPSGNDP | \
+                                               VSX_XX3((t), (a), (b))))
 
 #define PPC_NAP                 stringify_in_c(.long PPC_INST_NAP)
 #define PPC_SLEEP               stringify_in_c(.long PPC_INST_SLEEP)
diff --git a/arch/powerpc/include/asm/ppc-pci.h b/arch/powerpc/include/asm/ppc-pci.h
index 80fa704d410f..ed57fa7920c8 100644
--- a/arch/powerpc/include/asm/ppc-pci.h
+++ b/arch/powerpc/include/asm/ppc-pci.h
@@ -47,19 +47,17 @@ extern int rtas_setup_phb(struct pci_controller *phb);
 
 #ifdef CONFIG_EEH
 
-void pci_addr_cache_build(void);
-void pci_addr_cache_insert_device(struct pci_dev *dev);
-void pci_addr_cache_remove_device(struct pci_dev *dev);
-struct pci_dev *pci_addr_cache_get_device(unsigned long addr);
-void eeh_slot_error_detail(struct eeh_dev *edev, int severity);
-int eeh_pci_enable(struct eeh_dev *edev, int function);
-int eeh_reset_pe(struct eeh_dev *);
-void eeh_restore_bars(struct eeh_dev *);
+void eeh_addr_cache_insert_dev(struct pci_dev *dev);
+void eeh_addr_cache_rmv_dev(struct pci_dev *dev);
+struct eeh_dev *eeh_addr_cache_get_dev(unsigned long addr);
+void eeh_slot_error_detail(struct eeh_pe *pe, int severity);
+int eeh_pci_enable(struct eeh_pe *pe, int function);
+int eeh_reset_pe(struct eeh_pe *);
+void eeh_save_bars(struct eeh_dev *edev);
 int rtas_write_config(struct pci_dn *, int where, int size, u32 val);
 int rtas_read_config(struct pci_dn *, int where, int size, u32 *val);
-void eeh_mark_slot(struct device_node *dn, int mode_flag);
-void eeh_clear_slot(struct device_node *dn, int mode_flag);
-struct device_node *eeh_find_device_pe(struct device_node *dn);
+void eeh_pe_state_mark(struct eeh_pe *pe, int state);
+void eeh_pe_state_clear(struct eeh_pe *pe, int state);
 
 void eeh_sysfs_add_device(struct pci_dev *pdev);
 void eeh_sysfs_remove_device(struct pci_dev *pdev);
diff --git a/arch/powerpc/include/asm/probes.h b/arch/powerpc/include/asm/probes.h
new file mode 100644
index 000000000000..5f1e15b68704
--- /dev/null
+++ b/arch/powerpc/include/asm/probes.h
@@ -0,0 +1,42 @@
+#ifndef _ASM_POWERPC_PROBES_H
+#define _ASM_POWERPC_PROBES_H
+#ifdef __KERNEL__
+/*
+ * Definitions common to probes files
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright IBM Corporation, 2012
+ */
+#include <linux/types.h>
+
+typedef u32 ppc_opcode_t;
+#define BREAKPOINT_INSTRUCTION  0x7fe00008      /* trap */
+
+/* Trap definitions per ISA */
+#define IS_TW(instr)            (((instr) & 0xfc0007fe) == 0x7c000008)
+#define IS_TD(instr)            (((instr) & 0xfc0007fe) == 0x7c000088)
+#define IS_TDI(instr)           (((instr) & 0xfc000000) == 0x08000000)
+#define IS_TWI(instr)           (((instr) & 0xfc000000) == 0x0c000000)
+
+#ifdef CONFIG_PPC64
+#define is_trap(instr)          (IS_TW(instr) || IS_TD(instr) || \
+                                IS_TWI(instr) || IS_TDI(instr))
+#else
+#define is_trap(instr)          (IS_TW(instr) || IS_TWI(instr))
+#endif /* CONFIG_PPC64 */
+
+#endif /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_PROBES_H */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 54b73a28c205..9dc5cd1fde1a 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -97,8 +97,8 @@ extern struct task_struct *last_task_used_spe;
 #endif
 
 #ifdef CONFIG_PPC64
-/* 64-bit user address space is 44-bits (16TB user VM) */
-#define TASK_SIZE_USER64 (0x0000100000000000UL)
+/* 64-bit user address space is 46-bits (64TB user VM) */
+#define TASK_SIZE_USER64 (0x0000400000000000UL)
 
 /* 
  * 32-bit user address space is 4GB - 1 page 
@@ -219,6 +219,8 @@ struct thread_struct {
 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
 #endif
         unsigned long   dabr;           /* Data address breakpoint register */
+        unsigned long   dabrx;          /*      ... extension  */
+        unsigned long   trap_nr;        /* last trap # on this thread */
 #ifdef CONFIG_ALTIVEC
         /* Complete AltiVec register set */
         vector128       vr[32] __attribute__((aligned(16)));
diff --git a/arch/powerpc/include/asm/pte-hash64-64k.h b/arch/powerpc/include/asm/pte-hash64-64k.h
index 59247e816ac5..eedf427c9124 100644
--- a/arch/powerpc/include/asm/pte-hash64-64k.h
+++ b/arch/powerpc/include/asm/pte-hash64-64k.h
@@ -58,14 +58,16 @@
 /* Trick: we set __end to va + 64k, which happens works for
  * a 16M page as well as we want only one iteration
  */
-#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift)          \
-        do {                                                                \
-                unsigned long __end = va + PAGE_SIZE;                       \
-                unsigned __split = (psize == MMU_PAGE_4K ||                 \
-                                    psize == MMU_PAGE_64K_AP);              \
-                shift = mmu_psize_defs[psize].shift;                        \
-                for (index = 0; va < __end; index++, va += (1L << shift)) { \
-                        if (!__split || __rpte_sub_valid(rpte, index)) do { \
+#define pte_iterate_hashed_subpages(rpte, psize, vpn, index, shift)     \
+        do {                                                            \
+                unsigned long __end = vpn + (1UL << (PAGE_SHIFT - VPN_SHIFT));  \
+                unsigned __split = (psize == MMU_PAGE_4K ||             \
+                                    psize == MMU_PAGE_64K_AP);          \
+                shift = mmu_psize_defs[psize].shift;                    \
+                for (index = 0; vpn < __end; index++,                   \
+                             vpn += (1L << (shift - VPN_SHIFT))) {      \
+                        if (!__split || __rpte_sub_valid(rpte, index))  \
+                                do {
 
 #define pte_iterate_hashed_end() } while(0); } } while(0)
 
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 638608677e2a..d24c14163966 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -208,6 +208,9 @@
 #define SPRN_DABRX      0x3F7   /* Data Address Breakpoint Register Extension */
 #define   DABRX_USER    (1UL << 0)
 #define   DABRX_KERNEL  (1UL << 1)
+#define   DABRX_HYP     (1UL << 2)
+#define   DABRX_BTI     (1UL << 3)
+#define   DABRX_ALL     (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER)
 #define SPRN_DAR        0x013   /* Data Address Register */
 #define SPRN_DBCR       0x136   /* e300 Data Breakpoint Control Reg */
 #define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
@@ -521,6 +524,7 @@
 
 #define SPRN_HSRR0      0x13A   /* Save/Restore Register 0 */
 #define SPRN_HSRR1      0x13B   /* Save/Restore Register 1 */
+#define   HSRR1_DENORM          0x00100000 /* Denorm exception */
 
 #define SPRN_TBCTL      0x35f   /* PA6T Timebase control register */
 #define   TBCTL_FREEZE          0x0000000000000000ull /* Freeze all tbs */
@@ -602,6 +606,10 @@
 #define   POWER6_MMCRA_SIPR   0x0000020000000000ULL
 #define   POWER6_MMCRA_THRM     0x00000020UL
 #define   POWER6_MMCRA_OTHER    0x0000000EUL
+
+#define   POWER7P_MMCRA_SIAR_VALID 0x10000000   /* P7+ SIAR contents valid */
+#define   POWER7P_MMCRA_SDAR_VALID 0x08000000   /* P7+ SDAR contents valid */
+
 #define SPRN_PMC1       787
 #define SPRN_PMC2       788
 #define SPRN_PMC3       789
@@ -761,7 +769,8 @@
  * 64-bit embedded
  *      - SPRG0 generic exception scratch
  *      - SPRG2 TLB exception stack
- *      - SPRG3 CPU and NUMA node for VDSO getcpu (user visible)
+ *      - SPRG3 critical exception scratch and
+ *        CPU and NUMA node for VDSO getcpu (user visible)
  *      - SPRG4 unused (user visible)
  *      - SPRG6 TLB miss scratch (user visible, sorry !)
  *      - SPRG7 critical exception scratch
@@ -858,11 +867,12 @@
 
 #ifdef CONFIG_PPC_BOOK3E_64
 #define SPRN_SPRG_MC_SCRATCH    SPRN_SPRG8
-#define SPRN_SPRG_CRIT_SCRATCH  SPRN_SPRG7
+#define SPRN_SPRG_CRIT_SCRATCH  SPRN_SPRG3
 #define SPRN_SPRG_DBG_SCRATCH   SPRN_SPRG9
 #define SPRN_SPRG_TLB_EXFRAME   SPRN_SPRG2
 #define SPRN_SPRG_TLB_SCRATCH   SPRN_SPRG6
 #define SPRN_SPRG_GEN_SCRATCH   SPRN_SPRG0
+#define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH
 
 #define SET_PACA(rX)    mtspr   SPRN_SPRG_PACA,rX
 #define GET_PACA(rX)    mfspr   rX,SPRN_SPRG_PACA
@@ -937,7 +947,7 @@
 #define PVR_VER(pvr)    (((pvr) >>  16) & 0xFFFF)       /* Version field */
 #define PVR_REV(pvr)    (((pvr) >>   0) & 0xFFFF)       /* Revison field */
 
-#define __is_processor(pv)      (PVR_VER(mfspr(SPRN_PVR)) == (pv))
+#define pvr_version_is(pvr)     (PVR_VER(mfspr(SPRN_PVR)) == (pvr))
 
 /*
  * IBM has further subdivided the standard PowerPC 16-bit version and
@@ -1002,25 +1012,25 @@
 #define PVR_476_ISS     0x00052000
 
 /* 64-bit processors */
-/* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */
-#define PV_NORTHSTAR    0x0033
-#define PV_PULSAR       0x0034
-#define PV_POWER4       0x0035
-#define PV_ICESTAR      0x0036
-#define PV_SSTAR        0x0037
-#define PV_POWER4p      0x0038
-#define PV_970          0x0039
-#define PV_POWER5       0x003A
-#define PV_POWER5p      0x003B
-#define PV_970FX        0x003C
-#define PV_POWER6       0x003E
-#define PV_POWER7       0x003F
-#define PV_630          0x0040
-#define PV_630p 0x0041
-#define PV_970MP        0x0044
-#define PV_970GX        0x0045
-#define PV_BE           0x0070
-#define PV_PA6T         0x0090
+#define PVR_NORTHSTAR   0x0033
+#define PVR_PULSAR      0x0034
+#define PVR_POWER4      0x0035
+#define PVR_ICESTAR     0x0036
+#define PVR_SSTAR       0x0037
+#define PVR_POWER4p     0x0038
+#define PVR_970         0x0039
+#define PVR_POWER5      0x003A
+#define PVR_POWER5p     0x003B
+#define PVR_970FX       0x003C
+#define PVR_POWER6      0x003E
+#define PVR_POWER7      0x003F
+#define PVR_630         0x0040
+#define PVR_630p        0x0041
+#define PVR_970MP       0x0044
+#define PVR_970GX       0x0045
+#define PVR_POWER7p     0x004A
+#define PVR_BE          0x0070
+#define PVR_PA6T        0x0090
 
 /* Macros for setting and retrieving special purpose registers */
 #ifndef __ASSEMBLY__
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index d084ce195fc3..8b9a306260b2 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -9,7 +9,7 @@ extern void ppc_printk_progress(char *s, unsigned short hex);
 extern unsigned int rtas_data;
 extern int mem_init_done;       /* set on boot once kmalloc can be called */
 extern int init_bootmem_done;   /* set once bootmem is available */
-extern phys_addr_t memory_limit;
+extern unsigned long long memory_limit;
 extern unsigned long klimit;
 extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
 
diff --git a/arch/powerpc/include/asm/siginfo.h b/arch/powerpc/include/asm/siginfo.h
index 49495b0534ed..ccce3ef5cd86 100644
--- a/arch/powerpc/include/asm/siginfo.h
+++ b/arch/powerpc/include/asm/siginfo.h
@@ -10,7 +10,6 @@
 
 #ifdef __powerpc64__
 #    define __ARCH_SI_PREAMBLE_SIZE     (4 * sizeof(int))
-#    define SI_PAD_SIZE32               ((SI_MAX_SIZE/sizeof(int)) - 3)
 #endif
 
 #include <asm-generic/siginfo.h>
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index ebc24dc5b1a1..e807e9d8e3f7 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -65,6 +65,7 @@ int generic_cpu_disable(void);
 void generic_cpu_die(unsigned int cpu);
 void generic_mach_cpu_die(void);
 void generic_set_cpu_dead(unsigned int cpu);
+void generic_set_cpu_up(unsigned int cpu);
 int generic_check_cpu_restart(unsigned int cpu);
 #endif
 
@@ -190,6 +191,7 @@ extern unsigned long __secondary_hold_spinloop;
 extern unsigned long __secondary_hold_acknowledge;
 extern char __secondary_hold;
 
+extern void __early_start(void);
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/sparsemem.h b/arch/powerpc/include/asm/sparsemem.h
index 0c5fa3145615..f6fc0ee813d7 100644
--- a/arch/powerpc/include/asm/sparsemem.h
+++ b/arch/powerpc/include/asm/sparsemem.h
@@ -10,8 +10,8 @@
  */
 #define SECTION_SIZE_BITS       24
 
-#define MAX_PHYSADDR_BITS       44
-#define MAX_PHYSMEM_BITS        44
+#define MAX_PHYSADDR_BITS       46
+#define MAX_PHYSMEM_BITS        46
 
 #endif /* CONFIG_SPARSEMEM */
 
diff --git a/arch/powerpc/include/asm/swiotlb.h b/arch/powerpc/include/asm/swiotlb.h
index 8979d4cd3d70..de99d6e29430 100644
--- a/arch/powerpc/include/asm/swiotlb.h
+++ b/arch/powerpc/include/asm/swiotlb.h
@@ -22,4 +22,10 @@ int __init swiotlb_setup_bus_notifier(void);
 
 extern void pci_dma_dev_setup_swiotlb(struct pci_dev *pdev);
 
+#ifdef CONFIG_SWIOTLB
+void swiotlb_detect_4g(void);
+#else
+static inline void swiotlb_detect_4g(void) {}
+#endif
+
 #endif /* __ASM_SWIOTLB_H */
diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h
index faf93529cbf0..8ceea14d6fe4 100644
--- a/arch/powerpc/include/asm/thread_info.h
+++ b/arch/powerpc/include/asm/thread_info.h
@@ -102,7 +102,10 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_RESTOREALL          11      /* Restore all regs (implies NOERROR) */
 #define TIF_NOERROR             12      /* Force successful syscall return */
 #define TIF_NOTIFY_RESUME       13      /* callback before returning to user */
+#define TIF_UPROBE              14      /* breakpointed or single-stepping */
 #define TIF_SYSCALL_TRACEPOINT  15      /* syscall tracepoint instrumentation */
+#define TIF_EMULATE_STACK_STORE 16      /* Is an instruction emulation
+                                                for stack store? */
 
 /* as above, but as bit values */
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
@@ -118,12 +121,14 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_RESTOREALL         (1<<TIF_RESTOREALL)
 #define _TIF_NOERROR            (1<<TIF_NOERROR)
 #define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
+#define _TIF_UPROBE             (1<<TIF_UPROBE)
 #define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
+#define _TIF_EMULATE_STACK_STORE        (1<<TIF_EMULATE_STACK_STORE)
 #define _TIF_SYSCALL_T_OR_A     (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \
                                  _TIF_SECCOMP | _TIF_SYSCALL_TRACEPOINT)
 
 #define _TIF_USER_WORK_MASK     (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
-                                 _TIF_NOTIFY_RESUME)
+                                 _TIF_NOTIFY_RESUME | _TIF_UPROBE)
 #define _TIF_PERSYSCALL_MASK    (_TIF_RESTOREALL|_TIF_NOERROR)
 
 /* Bits in local_flags */
diff --git a/arch/powerpc/include/asm/tlbflush.h b/arch/powerpc/include/asm/tlbflush.h
index 81143fcbd113..61a59271665b 100644
--- a/arch/powerpc/include/asm/tlbflush.h
+++ b/arch/powerpc/include/asm/tlbflush.h
@@ -95,7 +95,7 @@ struct ppc64_tlb_batch {
         unsigned long           index;
         struct mm_struct        *mm;
         real_pte_t              pte[PPC64_TLB_BATCH_NR];
-        unsigned long           vaddr[PPC64_TLB_BATCH_NR];
+        unsigned long           vpn[PPC64_TLB_BATCH_NR];
         unsigned int            psize;
         int                     ssize;
 };
@@ -103,9 +103,6 @@ DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
 
 extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
 
-extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
-                            pte_t *ptep, unsigned long pte, int huge);
-
 #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
 
 static inline void arch_enter_lazy_mmu_mode(void)
@@ -127,7 +124,7 @@ static inline void arch_leave_lazy_mmu_mode(void)
 #define arch_flush_lazy_mmu_mode()      do {} while (0)
 
 
-extern void flush_hash_page(unsigned long va, real_pte_t pte, int psize,
+extern void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize,
                             int ssize, int local);
 extern void flush_hash_range(unsigned long number, int local);
 
diff --git a/arch/powerpc/include/asm/uaccess.h b/arch/powerpc/include/asm/uaccess.h
index 17bb40cad5bf..4db49590acf5 100644
--- a/arch/powerpc/include/asm/uaccess.h
+++ b/arch/powerpc/include/asm/uaccess.h
@@ -98,11 +98,6 @@ struct exception_table_entry {
  * PowerPC, we can just do these as direct assignments.  (Of course, the
  * exception handling means that it's no longer "just"...)
  *
- * The "user64" versions of the user access functions are versions that
- * allow access of 64-bit data. The "get_user" functions do not
- * properly handle 64-bit data because the value gets down cast to a long.
- * The "put_user" functions already handle 64-bit data properly but we add
- * "user64" versions for completeness
  */
 #define get_user(x, ptr) \
         __get_user_check((x), (ptr), sizeof(*(ptr)))
@@ -114,12 +109,6 @@ struct exception_table_entry {
 #define __put_user(x, ptr) \
         __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
 
-#ifndef __powerpc64__
-#define __get_user64(x, ptr) \
-        __get_user64_nocheck((x), (ptr), sizeof(*(ptr)))
-#define __put_user64(x, ptr) __put_user(x, ptr)
-#endif
-
 #define __get_user_inatomic(x, ptr) \
         __get_user_nosleep((x), (ptr), sizeof(*(ptr)))
 #define __put_user_inatomic(x, ptr) \
diff --git a/arch/powerpc/include/asm/uprobes.h b/arch/powerpc/include/asm/uprobes.h
new file mode 100644
index 000000000000..b532060d0916
--- /dev/null
+++ b/arch/powerpc/include/asm/uprobes.h
@@ -0,0 +1,54 @@
+#ifndef _ASM_UPROBES_H
+#define _ASM_UPROBES_H
+/*
+ * User-space Probes (UProbes) for powerpc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright IBM Corporation, 2007-2012
+ *
+ * Adapted from the x86 port by Ananth N Mavinakayanahalli <ananth@in.ibm.com>
+ */
+
+#include <linux/notifier.h>
+#include <asm/probes.h>
+
+typedef ppc_opcode_t uprobe_opcode_t;
+
+#define MAX_UINSN_BYTES         4
+#define UPROBE_XOL_SLOT_BYTES   (MAX_UINSN_BYTES)
+
+/* The following alias is needed for reference from arch-agnostic code */
+#define UPROBE_SWBP_INSN        BREAKPOINT_INSTRUCTION
+#define UPROBE_SWBP_INSN_SIZE   4 /* swbp insn size in bytes */
+
+struct arch_uprobe {
+        union {
+                u8      insn[MAX_UINSN_BYTES];
+                u32     ainsn;
+        };
+};
+
+struct arch_uprobe_task {
+        unsigned long   saved_trap_nr;
+};
+
+extern int  arch_uprobe_analyze_insn(struct arch_uprobe *aup, struct mm_struct *mm, unsigned long addr);
+extern int  arch_uprobe_pre_xol(struct arch_uprobe *aup, struct pt_regs *regs);
+extern int  arch_uprobe_post_xol(struct arch_uprobe *aup, struct pt_regs *regs);
+extern bool arch_uprobe_xol_was_trapped(struct task_struct *tsk);
+extern int  arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data);
+extern void arch_uprobe_abort_xol(struct arch_uprobe *aup, struct pt_regs *regs);
+#endif  /* _ASM_UPROBES_H */
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index bb282dd81612..cde12f8a4ebc 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -96,6 +96,7 @@ obj-$(CONFIG_MODULES)		+= ppc_ksyms.o
 obj-$(CONFIG_BOOTX_TEXT)        += btext.o
 obj-$(CONFIG_SMP)               += smp.o
 obj-$(CONFIG_KPROBES)           += kprobes.o
+obj-$(CONFIG_UPROBES)           += uprobes.o
 obj-$(CONFIG_PPC_UDBG_16550)    += legacy_serial.o udbg_16550.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
 obj-$(CONFIG_SWIOTLB)           += dma-swiotlb.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index e8995727b1c1..7523539cfe9f 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -206,6 +206,7 @@ int main(void)
         DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time));
         DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
         DEFINE(PACA_NAPSTATELOST, offsetof(struct paca_struct, nap_state_lost));
+        DEFINE(PACA_SPRG3, offsetof(struct paca_struct, sprg3));
 #endif /* CONFIG_PPC64 */
 
         /* RTAS */
@@ -534,7 +535,6 @@ int main(void)
         HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
         HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
         HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
-        HSTATE_FIELD(HSTATE_SPRG3, sprg3);
         HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
         HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
         HSTATE_FIELD(HSTATE_NAPPING, napping);
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 69fdd2322a66..dcd881937f7a 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -16,6 +16,8 @@
 #include <asm/processor.h>
 #include <asm/cputable.h>
 #include <asm/ppc_asm.h>
+#include <asm/mmu-book3e.h>
+#include <asm/asm-offsets.h>
 
 _GLOBAL(__e500_icache_setup)
         mfspr   r0, SPRN_L1CSR1
@@ -73,27 +75,81 @@ _GLOBAL(__setup_cpu_e500v2)
         mtlr    r4
         blr
 _GLOBAL(__setup_cpu_e500mc)
-        mr      r5, r4
-        mflr    r4
+_GLOBAL(__setup_cpu_e5500)
+        mflr    r5
         bl      __e500_icache_setup
         bl      __e500_dcache_setup
         bl      __setup_e500mc_ivors
-        mtlr    r4
+        /*
+         * We only want to touch IVOR38-41 if we're running on hardware
+         * that supports category E.HV.  The architectural way to determine
+         * this is MMUCFG[LPIDSIZE].
+         */
+        mfspr   r3, SPRN_MMUCFG
+        rlwinm. r3, r3, 0, MMUCFG_LPIDSIZE
+        beq     1f
+        bl      __setup_ehv_ivors
+        b       2f
+1:
+        lwz     r3, CPU_SPEC_FEATURES(r4)
+        /* We need this check as cpu_setup is also called for
+         * the secondary cores. So, if we have already cleared
+         * the feature on the primary core, avoid doing it on the
+         * secondary core.
+         */
+        andis.  r6, r3, CPU_FTR_EMB_HV@h
+        beq     2f
+        rlwinm  r3, r3, 0, ~CPU_FTR_EMB_HV
+        stw     r3, CPU_SPEC_FEATURES(r4)
+2:
+        mtlr    r5
         blr
 #endif
-/* Right now, restore and setup are the same thing */
+
+#ifdef CONFIG_PPC_BOOK3E_64
 _GLOBAL(__restore_cpu_e5500)
-_GLOBAL(__setup_cpu_e5500)
         mflr    r4
         bl      __e500_icache_setup
         bl      __e500_dcache_setup
-#ifdef CONFIG_PPC_BOOK3E_64
         bl      .__setup_base_ivors
         bl      .setup_perfmon_ivor
         bl      .setup_doorbell_ivors
+        /*
+         * We only want to touch IVOR38-41 if we're running on hardware
+         * that supports category E.HV.  The architectural way to determine
+         * this is MMUCFG[LPIDSIZE].
+         */
+        mfspr   r10,SPRN_MMUCFG
+        rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
+        beq     1f
         bl      .setup_ehv_ivors
-#else
-        bl      __setup_e500mc_ivors
-#endif
+1:
         mtlr    r4
         blr
+
+_GLOBAL(__setup_cpu_e5500)
+        mflr    r5
+        bl      __e500_icache_setup
+        bl      __e500_dcache_setup
+        bl      .__setup_base_ivors
+        bl      .setup_perfmon_ivor
+        bl      .setup_doorbell_ivors
+        /*
+         * We only want to touch IVOR38-41 if we're running on hardware
+         * that supports category E.HV.  The architectural way to determine
+         * this is MMUCFG[LPIDSIZE].
+         */
+        mfspr   r10,SPRN_MMUCFG
+        rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
+        beq     1f
+        bl      .setup_ehv_ivors
+        b       2f
+1:
+        ld      r10,CPU_SPEC_FEATURES(r4)
+        LOAD_REG_IMMEDIATE(r9,CPU_FTR_EMB_HV)
+        andc    r10,r10,r9
+        std     r10,CPU_SPEC_FEATURES(r4)
+2:
+        mtlr    r5
+        blr
+#endif
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 455faa389876..0514c21f138b 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -2016,7 +2016,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .oprofile_cpu_type      = "ppc/e500mc",
                 .oprofile_type          = PPC_OPROFILE_FSL_EMB,
                 .cpu_setup              = __setup_cpu_e5500,
+#ifndef CONFIG_PPC32
                 .cpu_restore            = __restore_cpu_e5500,
+#endif
                 .machine_check          = machine_check_e500mc,
                 .platform               = "ppce5500",
         },
@@ -2034,7 +2036,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .oprofile_cpu_type      = "ppc/e6500",
                 .oprofile_type          = PPC_OPROFILE_FSL_EMB,
                 .cpu_setup              = __setup_cpu_e5500,
+#ifndef CONFIG_PPC32
                 .cpu_restore            = __restore_cpu_e5500,
+#endif
                 .machine_check          = machine_check_e500mc,
                 .platform               = "ppce6500",
         },
diff --git a/arch/powerpc/kernel/dma-swiotlb.c b/arch/powerpc/kernel/dma-swiotlb.c
index 46943651da23..bd1a2aba599f 100644
--- a/arch/powerpc/kernel/dma-swiotlb.c
+++ b/arch/powerpc/kernel/dma-swiotlb.c
@@ -12,6 +12,7 @@
  */
 
 #include <linux/dma-mapping.h>
+#include <linux/memblock.h>
 #include <linux/pfn.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
@@ -20,7 +21,6 @@
 #include <asm/machdep.h>
 #include <asm/swiotlb.h>
 #include <asm/dma.h>
-#include <asm/abs_addr.h>
 
 unsigned int ppc_swiotlb_enable;
 
@@ -105,3 +105,23 @@ int __init swiotlb_setup_bus_notifier(void)
                               &ppc_swiotlb_plat_bus_notifier);
         return 0;
 }
+
+void swiotlb_detect_4g(void)
+{
+        if ((memblock_end_of_DRAM() - 1) > 0xffffffff)
+                ppc_swiotlb_enable = 1;
+}
+
+static int __init swiotlb_late_init(void)
+{
+        if (ppc_swiotlb_enable) {
+                swiotlb_print_info();
+                set_pci_dma_ops(&swiotlb_dma_ops);
+                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
+        } else {
+                swiotlb_free();
+        }
+
+        return 0;
+}
+subsys_initcall(swiotlb_late_init);
diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c
index 355b9d84b0f8..8032b97ccdcb 100644
--- a/arch/powerpc/kernel/dma.c
+++ b/arch/powerpc/kernel/dma.c
@@ -14,7 +14,6 @@
 #include <linux/pci.h>
 #include <asm/vio.h>
 #include <asm/bug.h>
-#include <asm/abs_addr.h>
 #include <asm/machdep.h>
 
 /*
@@ -50,7 +49,7 @@ void *dma_direct_alloc_coherent(struct device *dev, size_t size,
                 return NULL;
         ret = page_address(page);
         memset(ret, 0, size);
-        *dma_handle = virt_to_abs(ret) + get_dma_offset(dev);
+        *dma_handle = __pa(ret) + get_dma_offset(dev);
 
         return ret;
 #endif
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index ead5016b02d0..af37528da49f 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -831,19 +831,56 @@ restore_user:
         bnel-   load_dbcr0
 #endif
 
-#ifdef CONFIG_PREEMPT
         b       restore
 
 /* N.B. the only way to get here is from the beq following ret_from_except. */
 resume_kernel:
-        /* check current_thread_info->preempt_count */
+        /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
         CURRENT_THREAD_INFO(r9, r1)
+        lwz     r8,TI_FLAGS(r9)
+        andis.  r8,r8,_TIF_EMULATE_STACK_STORE@h
+        beq+    1f
+
+        addi    r8,r1,INT_FRAME_SIZE    /* Get the kprobed function entry */
+
+        lwz     r3,GPR1(r1)
+        subi    r3,r3,INT_FRAME_SIZE    /* dst: Allocate a trampoline exception frame */
+        mr      r4,r1                   /* src:  current exception frame */
+        mr      r1,r3                   /* Reroute the trampoline frame to r1 */
+
+        /* Copy from the original to the trampoline. */
+        li      r5,INT_FRAME_SIZE/4     /* size: INT_FRAME_SIZE */
+        li      r6,0                    /* start offset: 0 */
+        mtctr   r5
+2:      lwzx    r0,r6,r4
+        stwx    r0,r6,r3
+        addi    r6,r6,4
+        bdnz    2b
+
+        /* Do real store operation to complete stwu */
+        lwz     r5,GPR1(r1)
+        stw     r8,0(r5)
+
+        /* Clear _TIF_EMULATE_STACK_STORE flag */
+        lis     r11,_TIF_EMULATE_STACK_STORE@h
+        addi    r5,r9,TI_FLAGS
+0:      lwarx   r8,0,r5
+        andc    r8,r8,r11
+#ifdef CONFIG_IBM405_ERR77
+        dcbt    0,r5
+#endif
+        stwcx.  r8,0,r5
+        bne-    0b
+1:
+
+#ifdef CONFIG_PREEMPT
+        /* check current_thread_info->preempt_count */
         lwz     r0,TI_PREEMPT(r9)
         cmpwi   0,r0,0          /* if non-zero, just restore regs and return */
         bne     restore
-        lwz     r0,TI_FLAGS(r9)
-        andi.   r0,r0,_TIF_NEED_RESCHED
+        andi.   r8,r8,_TIF_NEED_RESCHED
         beq+    restore
+        lwz     r3,_MSR(r1)
         andi.   r0,r3,MSR_EE    /* interrupts off? */
         beq     restore         /* don't schedule if so */
 #ifdef CONFIG_TRACE_IRQFLAGS
@@ -864,8 +901,6 @@ resume_kernel:
          */
         bl      trace_hardirqs_on
 #endif
-#else
-resume_kernel:
 #endif /* CONFIG_PREEMPT */
 
         /* interrupts are hard-disabled at this point */
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index b40e0b4815b3..0e931aaffca2 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -593,6 +593,41 @@ _GLOBAL(ret_from_except_lite)
         b       .ret_from_except
 
 resume_kernel:
+        /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
+        CURRENT_THREAD_INFO(r9, r1)
+        ld      r8,TI_FLAGS(r9)
+        andis.  r8,r8,_TIF_EMULATE_STACK_STORE@h
+        beq+    1f
+
+        addi    r8,r1,INT_FRAME_SIZE    /* Get the kprobed function entry */
+
+        lwz     r3,GPR1(r1)
+        subi    r3,r3,INT_FRAME_SIZE    /* dst: Allocate a trampoline exception frame */
+        mr      r4,r1                   /* src:  current exception frame */
+        mr      r1,r3                   /* Reroute the trampoline frame to r1 */
+
+        /* Copy from the original to the trampoline. */
+        li      r5,INT_FRAME_SIZE/8     /* size: INT_FRAME_SIZE */
+        li      r6,0                    /* start offset: 0 */
+        mtctr   r5
+2:      ldx     r0,r6,r4
+        stdx    r0,r6,r3
+        addi    r6,r6,8
+        bdnz    2b
+
+        /* Do real store operation to complete stwu */
+        lwz     r5,GPR1(r1)
+        std     r8,0(r5)
+
+        /* Clear _TIF_EMULATE_STACK_STORE flag */
+        lis     r11,_TIF_EMULATE_STACK_STORE@h
+        addi    r5,r9,TI_FLAGS
+        ldarx   r4,0,r5
+        andc    r4,r4,r11
+        stdcx.  r4,0,r5
+        bne-    0b
+1:
+
 #ifdef CONFIG_PREEMPT
         /* Check if we need to preempt */
         andi.   r0,r4,_TIF_NEED_RESCHED
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 98be7f0cd227..4684e33a26c3 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -25,6 +25,8 @@
 #include <asm/ppc-opcode.h>
 #include <asm/mmu.h>
 #include <asm/hw_irq.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_booke_hv_asm.h>
 
 /* XXX This will ultimately add space for a special exception save
  *     structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
@@ -35,16 +37,18 @@
 #define SPECIAL_EXC_FRAME_SIZE  INT_FRAME_SIZE
 
 /* Exception prolog code for all exceptions */
-#define EXCEPTION_PROLOG(n, type, addition)                                 \
+#define EXCEPTION_PROLOG(n, intnum, type, addition)                         \
         mtspr   SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */   \
         mfspr   r13,SPRN_SPRG_PACA;     /* get PACA */                      \
         std     r10,PACA_EX##type+EX_R10(r13);                              \
         std     r11,PACA_EX##type+EX_R11(r13);                              \
+        PROLOG_STORE_RESTORE_SCRATCH_##type;                                \
         mfcr    r10;                    /* save CR */                       \
+        mfspr   r11,SPRN_##type##_SRR1;/* what are we coming from */        \
+        DO_KVM  intnum,SPRN_##type##_SRR1;    /* KVM hook */                \
+        stw     r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
         addition;                       /* additional code for that exc. */ \
         std     r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */  \
-        stw     r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
-        mfspr   r11,SPRN_##type##_SRR1;/* what are we coming from */        \
         type##_SET_KSTACK;              /* get special stack if necessary */\
         andi.   r10,r11,MSR_PR;         /* save stack pointer */            \
         beq     1f;                     /* branch around if supervisor */   \
@@ -59,6 +63,10 @@
 #define SPRN_GEN_SRR0   SPRN_SRR0
 #define SPRN_GEN_SRR1   SPRN_SRR1
 
+#define GDBELL_SET_KSTACK       GEN_SET_KSTACK
+#define SPRN_GDBELL_SRR0        SPRN_GSRR0
+#define SPRN_GDBELL_SRR1        SPRN_GSRR1
+
 #define CRIT_SET_KSTACK                                                     \
         ld      r1,PACA_CRIT_STACK(r13);                                    \
         subi    r1,r1,SPECIAL_EXC_FRAME_SIZE;
@@ -77,29 +85,46 @@
 #define SPRN_MC_SRR0    SPRN_MCSRR0
 #define SPRN_MC_SRR1    SPRN_MCSRR1
 
-#define NORMAL_EXCEPTION_PROLOG(n, addition)                                \
-        EXCEPTION_PROLOG(n, GEN, addition##_GEN(n))
+#define NORMAL_EXCEPTION_PROLOG(n, intnum, addition)                        \
+        EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n))
+
+#define CRIT_EXCEPTION_PROLOG(n, intnum, addition)                          \
+        EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n))
 
-#define CRIT_EXCEPTION_PROLOG(n, addition)                                  \
-        EXCEPTION_PROLOG(n, CRIT, addition##_CRIT(n))
+#define DBG_EXCEPTION_PROLOG(n, intnum, addition)                           \
+        EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n))
 
-#define DBG_EXCEPTION_PROLOG(n, addition)                                   \
-        EXCEPTION_PROLOG(n, DBG, addition##_DBG(n))
+#define MC_EXCEPTION_PROLOG(n, intnum, addition)                            \
+        EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n))
 
-#define MC_EXCEPTION_PROLOG(n, addition)                                    \
-        EXCEPTION_PROLOG(n, MC, addition##_MC(n))
+#define GDBELL_EXCEPTION_PROLOG(n, intnum, addition)                        \
+        EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n))
 
+/*
+ * Store user-visible scratch in PACA exception slots and restore proper value
+ */
+#define PROLOG_STORE_RESTORE_SCRATCH_GEN
+#define PROLOG_STORE_RESTORE_SCRATCH_GDBELL
+#define PROLOG_STORE_RESTORE_SCRATCH_DBG
+#define PROLOG_STORE_RESTORE_SCRATCH_MC
+
+#define PROLOG_STORE_RESTORE_SCRATCH_CRIT                                   \
+        mfspr   r10,SPRN_SPRG_CRIT_SCRATCH;     /* get r13 */               \
+        std     r10,PACA_EXCRIT+EX_R13(r13);                                \
+        ld      r11,PACA_SPRG3(r13);                                        \
+        mtspr   SPRN_SPRG_CRIT_SCRATCH,r11;
 
 /* Variants of the "addition" argument for the prolog
  */
 #define PROLOG_ADDITION_NONE_GEN(n)
+#define PROLOG_ADDITION_NONE_GDBELL(n)
 #define PROLOG_ADDITION_NONE_CRIT(n)
 #define PROLOG_ADDITION_NONE_DBG(n)
 #define PROLOG_ADDITION_NONE_MC(n)
 
 #define PROLOG_ADDITION_MASKABLE_GEN(n)                                     \
-        lbz     r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */      \
-        cmpwi   cr0,r11,0;              /* yes -> go out of line */         \
+        lbz     r10,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */      \
+        cmpwi   cr0,r10,0;              /* yes -> go out of line */         \
         beq     masked_interrupt_book3e_##n
 
 #define PROLOG_ADDITION_2REGS_GEN(n)                                        \
@@ -233,9 +258,9 @@ exc_##n##_bad_stack:							    \
 1:
 
 
-#define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack)                   \
+#define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack)           \
         START_EXCEPTION(label);                                         \
-        NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE)      \
+        NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\
         EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE)             \
         ack(r8);                                                        \
         CHECK_NAPPING();                                                \
@@ -286,7 +311,8 @@ interrupt_end_book3e:
 
 /* Critical Input Interrupt */
         START_EXCEPTION(critical_input);
-        CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE)
+        CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
+                              PROLOG_ADDITION_NONE)
 //      EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE)
 //      bl      special_reg_save_crit
 //      CHECK_NAPPING();
@@ -297,7 +323,8 @@ interrupt_end_book3e:
 
 /* Machine Check Interrupt */
         START_EXCEPTION(machine_check);
-        CRIT_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
+        MC_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_MACHINE_CHECK,
+                            PROLOG_ADDITION_NONE)
 //      EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE)
 //      bl      special_reg_save_mc
 //      addi    r3,r1,STACK_FRAME_OVERHEAD
@@ -308,7 +335,8 @@ interrupt_end_book3e:
 
 /* Data Storage Interrupt */
         START_EXCEPTION(data_storage)
-        NORMAL_EXCEPTION_PROLOG(0x300, PROLOG_ADDITION_2REGS)
+        NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE,
+                                PROLOG_ADDITION_2REGS)
         mfspr   r14,SPRN_DEAR
         mfspr   r15,SPRN_ESR
         EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_DISABLE)
@@ -316,18 +344,21 @@ interrupt_end_book3e:
 
 /* Instruction Storage Interrupt */
         START_EXCEPTION(instruction_storage);
-        NORMAL_EXCEPTION_PROLOG(0x400, PROLOG_ADDITION_2REGS)
+        NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE,
+                                PROLOG_ADDITION_2REGS)
         li      r15,0
         mr      r14,r10
         EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_DISABLE)
         b       storage_fault_common
 
 /* External Input Interrupt */
-        MASKABLE_EXCEPTION(0x500, external_input, .do_IRQ, ACK_NONE)
+        MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
+                           external_input, .do_IRQ, ACK_NONE)
 
 /* Alignment */
         START_EXCEPTION(alignment);
-        NORMAL_EXCEPTION_PROLOG(0x600, PROLOG_ADDITION_2REGS)
+        NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT,
+                                PROLOG_ADDITION_2REGS)
         mfspr   r14,SPRN_DEAR
         mfspr   r15,SPRN_ESR
         EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP)
@@ -335,7 +366,8 @@ interrupt_end_book3e:
 
 /* Program Interrupt */
         START_EXCEPTION(program);
-        NORMAL_EXCEPTION_PROLOG(0x700, PROLOG_ADDITION_1REG)
+        NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
+                                PROLOG_ADDITION_1REG)
         mfspr   r14,SPRN_ESR
         EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE)
         std     r14,_DSISR(r1)
@@ -347,7 +379,8 @@ interrupt_end_book3e:
 
 /* Floating Point Unavailable Interrupt */
         START_EXCEPTION(fp_unavailable);
-        NORMAL_EXCEPTION_PROLOG(0x800, PROLOG_ADDITION_NONE)
+        NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
+                                PROLOG_ADDITION_NONE)
         /* we can probably do a shorter exception entry for that one... */
         EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
         ld      r12,_MSR(r1)
@@ -362,14 +395,17 @@ interrupt_end_book3e:
         b       .ret_from_except
 
 /* Decrementer Interrupt */
-        MASKABLE_EXCEPTION(0x900, decrementer, .timer_interrupt, ACK_DEC)
+        MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
+                           decrementer, .timer_interrupt, ACK_DEC)
 
 /* Fixed Interval Timer Interrupt */
-        MASKABLE_EXCEPTION(0x980, fixed_interval, .unknown_exception, ACK_FIT)
+        MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
+                           fixed_interval, .unknown_exception, ACK_FIT)
 
 /* Watchdog Timer Interrupt */
         START_EXCEPTION(watchdog);
-        CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE)
+        CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
+                              PROLOG_ADDITION_NONE)
 //      EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE)
 //      bl      special_reg_save_crit
 //      CHECK_NAPPING();
@@ -388,7 +424,8 @@ interrupt_end_book3e:
 
 /* Auxiliary Processor Unavailable Interrupt */
         START_EXCEPTION(ap_unavailable);
-        NORMAL_EXCEPTION_PROLOG(0xf20, PROLOG_ADDITION_NONE)
+        NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
+                                PROLOG_ADDITION_NONE)
         EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_DISABLE)
         bl      .save_nvgprs
         addi    r3,r1,STACK_FRAME_OVERHEAD
@@ -397,7 +434,8 @@ interrupt_end_book3e:
 
 /* Debug exception as a critical interrupt*/
         START_EXCEPTION(debug_crit);
-        CRIT_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
+        CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
+                              PROLOG_ADDITION_2REGS)
 
         /*
          * If there is a single step or branch-taken exception in an
@@ -431,7 +469,7 @@ interrupt_end_book3e:
         mtcr    r10
         ld      r10,PACA_EXCRIT+EX_R10(r13)     /* restore registers */
         ld      r11,PACA_EXCRIT+EX_R11(r13)
-        mfspr   r13,SPRN_SPRG_CRIT_SCRATCH
+        ld      r13,PACA_EXCRIT+EX_R13(r13)
         rfci
 
         /* Normal debug exception */
@@ -444,7 +482,7 @@ interrupt_end_book3e:
         /* Now we mash up things to make it look like we are coming on a
          * normal exception
          */
-        mfspr   r15,SPRN_SPRG_CRIT_SCRATCH
+        ld      r15,PACA_EXCRIT+EX_R13(r13)
         mtspr   SPRN_SPRG_GEN_SCRATCH,r15
         mfspr   r14,SPRN_DBSR
         EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE)
@@ -462,7 +500,8 @@ kernel_dbg_exc:
 
 /* Debug exception as a debug interrupt*/
         START_EXCEPTION(debug_debug);
-        DBG_EXCEPTION_PROLOG(0xd08, PROLOG_ADDITION_2REGS)
+        DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
+                                                 PROLOG_ADDITION_2REGS)
 
         /*
          * If there is a single step or branch-taken exception in an
@@ -523,18 +562,21 @@ kernel_dbg_exc:
         b       .ret_from_except
 
         START_EXCEPTION(perfmon);
-        NORMAL_EXCEPTION_PROLOG(0x260, PROLOG_ADDITION_NONE)
+        NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
+                                PROLOG_ADDITION_NONE)
         EXCEPTION_COMMON(0x260, PACA_EXGEN, INTS_DISABLE)
         addi    r3,r1,STACK_FRAME_OVERHEAD
         bl      .performance_monitor_exception
         b       .ret_from_except_lite
 
 /* Doorbell interrupt */
-        MASKABLE_EXCEPTION(0x280, doorbell, .doorbell_exception, ACK_NONE)
+        MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
+                           doorbell, .doorbell_exception, ACK_NONE)
 
 /* Doorbell critical Interrupt */
         START_EXCEPTION(doorbell_crit);
-        CRIT_EXCEPTION_PROLOG(0x2a0, PROLOG_ADDITION_NONE)
+        CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
+                              PROLOG_ADDITION_NONE)
 //      EXCEPTION_COMMON(0x2a0, PACA_EXCRIT, INTS_DISABLE)
 //      bl      special_reg_save_crit
 //      CHECK_NAPPING();
@@ -543,12 +585,24 @@ kernel_dbg_exc:
 //      b       ret_from_crit_except
         b       .
 
-/* Guest Doorbell */
-        MASKABLE_EXCEPTION(0x2c0, guest_doorbell, .unknown_exception, ACK_NONE)
+/*
+ *      Guest doorbell interrupt
+ *      This general exception use GSRRx save/restore registers
+ */
+        START_EXCEPTION(guest_doorbell);
+        GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL,
+                                PROLOG_ADDITION_NONE)
+        EXCEPTION_COMMON(0x2c0, PACA_EXGEN, INTS_KEEP)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .save_nvgprs
+        INTS_RESTORE_HARD
+        bl      .unknown_exception
+        b       .ret_from_except
 
 /* Guest Doorbell critical Interrupt */
         START_EXCEPTION(guest_doorbell_crit);
-        CRIT_EXCEPTION_PROLOG(0x2e0, PROLOG_ADDITION_NONE)
+        CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
+                              PROLOG_ADDITION_NONE)
 //      EXCEPTION_COMMON(0x2e0, PACA_EXCRIT, INTS_DISABLE)
 //      bl      special_reg_save_crit
 //      CHECK_NAPPING();
@@ -559,7 +613,8 @@ kernel_dbg_exc:
 
 /* Hypervisor call */
         START_EXCEPTION(hypercall);
-        NORMAL_EXCEPTION_PROLOG(0x310, PROLOG_ADDITION_NONE)
+        NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
+                                PROLOG_ADDITION_NONE)
         EXCEPTION_COMMON(0x310, PACA_EXGEN, INTS_KEEP)
         addi    r3,r1,STACK_FRAME_OVERHEAD
         bl      .save_nvgprs
@@ -569,7 +624,8 @@ kernel_dbg_exc:
 
 /* Embedded Hypervisor priviledged  */
         START_EXCEPTION(ehpriv);
-        NORMAL_EXCEPTION_PROLOG(0x320, PROLOG_ADDITION_NONE)
+        NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
+                                PROLOG_ADDITION_NONE)
         EXCEPTION_COMMON(0x320, PACA_EXGEN, INTS_KEEP)
         addi    r3,r1,STACK_FRAME_OVERHEAD
         bl      .save_nvgprs
@@ -582,44 +638,42 @@ kernel_dbg_exc:
  * accordingly and if the interrupt is level sensitive, we hard disable
  */
 
+.macro masked_interrupt_book3e paca_irq full_mask
+        lbz     r10,PACAIRQHAPPENED(r13)
+        ori     r10,r10,\paca_irq
+        stb     r10,PACAIRQHAPPENED(r13)
+
+        .if \full_mask == 1
+        rldicl  r10,r11,48,1            /* clear MSR_EE */
+        rotldi  r11,r10,16
+        mtspr   SPRN_SRR1,r11
+        .endif
+
+        lwz     r11,PACA_EXGEN+EX_CR(r13)
+        mtcr    r11
+        ld      r10,PACA_EXGEN+EX_R10(r13)
+        ld      r11,PACA_EXGEN+EX_R11(r13)
+        mfspr   r13,SPRN_SPRG_GEN_SCRATCH
+        rfi
+        b       .
+.endm
+
 masked_interrupt_book3e_0x500:
-        /* XXX When adding support for EPR, use PACA_IRQ_EE_EDGE */
-        li      r11,PACA_IRQ_EE
-        b       masked_interrupt_book3e_full_mask
+        // XXX When adding support for EPR, use PACA_IRQ_EE_EDGE
+        masked_interrupt_book3e PACA_IRQ_EE 1
 
 masked_interrupt_book3e_0x900:
-        ACK_DEC(r11);
-        li      r11,PACA_IRQ_DEC
-        b       masked_interrupt_book3e_no_mask
+        ACK_DEC(r10);
+        masked_interrupt_book3e PACA_IRQ_DEC 0
+
 masked_interrupt_book3e_0x980:
-        ACK_FIT(r11);
-        li      r11,PACA_IRQ_DEC
-        b       masked_interrupt_book3e_no_mask
+        ACK_FIT(r10);
+        masked_interrupt_book3e PACA_IRQ_DEC 0
+
 masked_interrupt_book3e_0x280:
 masked_interrupt_book3e_0x2c0:
-        li      r11,PACA_IRQ_DBELL
-        b       masked_interrupt_book3e_no_mask
+        masked_interrupt_book3e PACA_IRQ_DBELL 0
 
-masked_interrupt_book3e_no_mask:
-        mtcr    r10
-        lbz     r10,PACAIRQHAPPENED(r13)
-        or      r10,r10,r11
-        stb     r10,PACAIRQHAPPENED(r13)
-        b       1f
-masked_interrupt_book3e_full_mask:
-        mtcr    r10
-        lbz     r10,PACAIRQHAPPENED(r13)
-        or      r10,r10,r11
-        stb     r10,PACAIRQHAPPENED(r13)
-        mfspr   r10,SPRN_SRR1
-        rldicl  r11,r10,48,1            /* clear MSR_EE */
-        rotldi  r10,r11,16
-        mtspr   SPRN_SRR1,r10
-1:      ld      r10,PACA_EXGEN+EX_R10(r13);
-        ld      r11,PACA_EXGEN+EX_R11(r13);
-        mfspr   r13,SPRN_SPRG_GEN_SCRATCH;
-        rfi
-        b       .
 /*
  * Called from arch_local_irq_enable when an interrupt needs
  * to be resent. r3 contains either 0x500,0x900,0x260 or 0x280
@@ -1302,25 +1356,11 @@ _GLOBAL(setup_perfmon_ivor)
 _GLOBAL(setup_doorbell_ivors)
         SET_IVOR(36, 0x280) /* Processor Doorbell */
         SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
-
-        /* Check MMUCFG[LPIDSIZE] to determine if we have category E.HV */
-        mfspr   r10,SPRN_MMUCFG
-        rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
-        beqlr
-
-        SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
-        SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
         blr
 
 _GLOBAL(setup_ehv_ivors)
-        /*
-         * We may be running as a guest and lack E.HV even on a chip
-         * that normally has it.
-         */
-        mfspr   r10,SPRN_MMUCFG
-        rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
-        beqlr
-
         SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
         SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
+        SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
+        SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
         blr
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 39aa97d3ff88..10b658ad65e1 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -275,6 +275,31 @@ vsx_unavailable_pSeries_1:
         STD_EXCEPTION_PSERIES(0x1300, 0x1300, instruction_breakpoint)
         KVM_HANDLER_PR_SKIP(PACA_EXGEN, EXC_STD, 0x1300)
 
+        . = 0x1500
+        .global denorm_Hypervisor
+denorm_exception_hv:
+        HMT_MEDIUM
+        mtspr   SPRN_SPRG_HSCRATCH0,r13
+        mfspr   r13,SPRN_SPRG_HPACA
+        std     r9,PACA_EXGEN+EX_R9(r13)
+        std     r10,PACA_EXGEN+EX_R10(r13)
+        std     r11,PACA_EXGEN+EX_R11(r13)
+        std     r12,PACA_EXGEN+EX_R12(r13)
+        mfspr   r9,SPRN_SPRG_HSCRATCH0
+        std     r9,PACA_EXGEN+EX_R13(r13)
+        mfcr    r9
+
+#ifdef CONFIG_PPC_DENORMALISATION
+        mfspr   r10,SPRN_HSRR1
+        mfspr   r11,SPRN_HSRR0          /* save HSRR0 */
+        andis.  r10,r10,(HSRR1_DENORM)@h /* denorm? */
+        addi    r11,r11,-4              /* HSRR0 is next instruction */
+        bne+    denorm_assist
+#endif
+
+        EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
+        KVM_HANDLER_SKIP(PACA_EXGEN, EXC_STD, 0x1500)
+
 #ifdef CONFIG_CBE_RAS
         STD_EXCEPTION_HV(0x1600, 0x1602, cbe_maintenance)
         KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1602)
@@ -336,6 +361,103 @@ do_stab_bolted_pSeries:
         KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x900)
         KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x982)
 
+#ifdef CONFIG_PPC_DENORMALISATION
+denorm_assist:
+BEGIN_FTR_SECTION
+/*
+ * To denormalise we need to move a copy of the register to itself.
+ * For POWER6 do that here for all FP regs.
+ */
+        mfmsr   r10
+        ori     r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
+        xori    r10,r10,(MSR_FE0|MSR_FE1)
+        mtmsrd  r10
+        sync
+        fmr     0,0
+        fmr     1,1
+        fmr     2,2
+        fmr     3,3
+        fmr     4,4
+        fmr     5,5
+        fmr     6,6
+        fmr     7,7
+        fmr     8,8
+        fmr     9,9
+        fmr     10,10
+        fmr     11,11
+        fmr     12,12
+        fmr     13,13
+        fmr     14,14
+        fmr     15,15
+        fmr     16,16
+        fmr     17,17
+        fmr     18,18
+        fmr     19,19
+        fmr     20,20
+        fmr     21,21
+        fmr     22,22
+        fmr     23,23
+        fmr     24,24
+        fmr     25,25
+        fmr     26,26
+        fmr     27,27
+        fmr     28,28
+        fmr     29,29
+        fmr     30,30
+        fmr     31,31
+FTR_SECTION_ELSE
+/*
+ * To denormalise we need to move a copy of the register to itself.
+ * For POWER7 do that here for the first 32 VSX registers only.
+ */
+        mfmsr   r10
+        oris    r10,r10,MSR_VSX@h
+        mtmsrd  r10
+        sync
+        XVCPSGNDP(0,0,0)
+        XVCPSGNDP(1,1,1)
+        XVCPSGNDP(2,2,2)
+        XVCPSGNDP(3,3,3)
+        XVCPSGNDP(4,4,4)
+        XVCPSGNDP(5,5,5)
+        XVCPSGNDP(6,6,6)
+        XVCPSGNDP(7,7,7)
+        XVCPSGNDP(8,8,8)
+        XVCPSGNDP(9,9,9)
+        XVCPSGNDP(10,10,10)
+        XVCPSGNDP(11,11,11)
+        XVCPSGNDP(12,12,12)
+        XVCPSGNDP(13,13,13)
+        XVCPSGNDP(14,14,14)
+        XVCPSGNDP(15,15,15)
+        XVCPSGNDP(16,16,16)
+        XVCPSGNDP(17,17,17)
+        XVCPSGNDP(18,18,18)
+        XVCPSGNDP(19,19,19)
+        XVCPSGNDP(20,20,20)
+        XVCPSGNDP(21,21,21)
+        XVCPSGNDP(22,22,22)
+        XVCPSGNDP(23,23,23)
+        XVCPSGNDP(24,24,24)
+        XVCPSGNDP(25,25,25)
+        XVCPSGNDP(26,26,26)
+        XVCPSGNDP(27,27,27)
+        XVCPSGNDP(28,28,28)
+        XVCPSGNDP(29,29,29)
+        XVCPSGNDP(30,30,30)
+        XVCPSGNDP(31,31,31)
+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
+        mtspr   SPRN_HSRR0,r11
+        mtcrf   0x80,r9
+        ld      r9,PACA_EXGEN+EX_R9(r13)
+        ld      r10,PACA_EXGEN+EX_R10(r13)
+        ld      r11,PACA_EXGEN+EX_R11(r13)
+        ld      r12,PACA_EXGEN+EX_R12(r13)
+        ld      r13,PACA_EXGEN+EX_R13(r13)
+        HRFID
+        b       .
+#endif
+
         .align  7
         /* moved from 0xe00 */
         STD_EXCEPTION_HV(., 0xe02, h_data_storage)
@@ -495,6 +617,7 @@ machine_check_common:
         STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception)
         STD_EXCEPTION_COMMON_ASYNC(0xf00, performance_monitor, .performance_monitor_exception)
         STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
+        STD_EXCEPTION_COMMON(0x1502, denorm, .unknown_exception)
 #ifdef CONFIG_ALTIVEC
         STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
 #else
@@ -960,7 +1083,9 @@ _GLOBAL(do_stab_bolted)
         rldimi  r10,r11,7,52    /* r10 = first ste of the group */
 
         /* Calculate VSID */
-        /* This is a kernel address, so protovsid = ESID */
+        /* This is a kernel address, so protovsid = ESID | 1 << 37 */
+        li      r9,0x1
+        rldimi  r11,r9,(CONTEXT_BITS + USER_ESID_BITS),0
         ASM_VSID_SCRAMBLE(r11, r9, 256M)
         rldic   r9,r11,12,16    /* r9 = vsid << 12 */
 
diff --git a/arch/powerpc/kernel/fadump.c b/arch/powerpc/kernel/fadump.c
index 18bdf74fa164..06c8202a69cf 100644
--- a/arch/powerpc/kernel/fadump.c
+++ b/arch/powerpc/kernel/fadump.c
@@ -289,8 +289,7 @@ int __init fadump_reserve_mem(void)
                 else
                         memory_limit = memblock_end_of_DRAM();
                 printk(KERN_INFO "Adjusted memory_limit for firmware-assisted"
-                                " dump, now %#016llx\n",
-                                (unsigned long long)memory_limit);
+                                " dump, now %#016llx\n", memory_limit);
         }
         if (memory_limit)
                 memory_boundary = memory_limit;
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 0f59863c3ade..6f62a737f607 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -895,15 +895,11 @@ _GLOBAL(__setup_e500mc_ivors)
         mtspr   SPRN_IVOR36,r3
         li      r3,CriticalDoorbell@l
         mtspr   SPRN_IVOR37,r3
+        sync
+        blr
 
-        /*
-         * We only want to touch IVOR38-41 if we're running on hardware
-         * that supports category E.HV.  The architectural way to determine
-         * this is MMUCFG[LPIDSIZE].
-         */
-        mfspr   r3, SPRN_MMUCFG
-        andis.  r3, r3, MMUCFG_LPIDSIZE@h
-        beq     no_hv
+/* setup ehv ivors for */
+_GLOBAL(__setup_ehv_ivors)
         li      r3,GuestDoorbell@l
         mtspr   SPRN_IVOR38,r3
         li      r3,CriticalGuestDoorbell@l
@@ -912,14 +908,8 @@ _GLOBAL(__setup_e500mc_ivors)
         mtspr   SPRN_IVOR40,r3
         li      r3,Ehvpriv@l
         mtspr   SPRN_IVOR41,r3
-skip_hv_ivors:
         sync
         blr
-no_hv:
-        lwz     r3, CPU_SPEC_FEATURES(r5)
-        rlwinm  r3, r3, 0, ~CPU_FTR_EMB_HV
-        stw     r3, CPU_SPEC_FEATURES(r5)
-        b       skip_hv_ivors
 
 #ifdef CONFIG_SPE
 /*
@@ -1043,6 +1033,34 @@ _GLOBAL(flush_dcache_L1)
 
         blr
 
+/* Flush L1 d-cache, invalidate and disable d-cache and i-cache */
+_GLOBAL(__flush_disable_L1)
+        mflr    r10
+        bl      flush_dcache_L1 /* Flush L1 d-cache */
+        mtlr    r10
+
+        mfspr   r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */
+        li      r5, 2
+        rlwimi  r4, r5, 0, 3
+
+        msync
+        isync
+        mtspr   SPRN_L1CSR0, r4
+        isync
+
+1:      mfspr   r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */
+        andi.   r4, r4, 2
+        bne     1b
+
+        mfspr   r4, SPRN_L1CSR1 /* Invalidate and disable i-cache */
+        li      r5, 2
+        rlwimi  r4, r5, 0, 3
+
+        mtspr   SPRN_L1CSR1, r4
+        isync
+
+        blr
+
 #ifdef CONFIG_SMP
 /* When we get here, r24 needs to hold the CPU # */
         .globl __secondary_start
diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c
index 956a4c496de9..a89cae481b04 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -73,7 +73,7 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
          * If so, DABR will be populated in single_step_dabr_instruction().
          */
         if (current->thread.last_hit_ubp != bp)
-                set_dabr(info->address | info->type | DABR_TRANSLATION);
+                set_dabr(info->address | info->type | DABR_TRANSLATION, info->dabrx);
 
         return 0;
 }
@@ -97,7 +97,7 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
         }
 
         *slot = NULL;
-        set_dabr(0);
+        set_dabr(0, 0);
 }
 
 /*
@@ -170,6 +170,13 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
 
         info->address = bp->attr.bp_addr;
         info->len = bp->attr.bp_len;
+        info->dabrx = DABRX_ALL;
+        if (bp->attr.exclude_user)
+                info->dabrx &= ~DABRX_USER;
+        if (bp->attr.exclude_kernel)
+                info->dabrx &= ~DABRX_KERNEL;
+        if (bp->attr.exclude_hv)
+                info->dabrx &= ~DABRX_HYP;
 
         /*
          * Since breakpoint length can be a maximum of HW_BREAKPOINT_LEN(8)
@@ -197,7 +204,7 @@ void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs)
 
         info = counter_arch_bp(tsk->thread.last_hit_ubp);
         regs->msr &= ~MSR_SE;
-        set_dabr(info->address | info->type | DABR_TRANSLATION);
+        set_dabr(info->address | info->type | DABR_TRANSLATION, info->dabrx);
         tsk->thread.last_hit_ubp = NULL;
 }
 
@@ -215,7 +222,7 @@ int __kprobes hw_breakpoint_handler(struct die_args *args)
         unsigned long dar = regs->dar;
 
         /* Disable breakpoints during exception handling */
-        set_dabr(0);
+        set_dabr(0, 0);
 
         /*
          * The counter may be concurrently released but that can only
@@ -281,7 +288,7 @@ int __kprobes hw_breakpoint_handler(struct die_args *args)
         if (!info->extraneous_interrupt)
                 perf_bp_event(bp, regs);
 
-        set_dabr(info->address | info->type | DABR_TRANSLATION);
+        set_dabr(info->address | info->type | DABR_TRANSLATION, info->dabrx);
 out:
         rcu_read_unlock();
         return rc;
@@ -294,7 +301,7 @@ int __kprobes single_step_dabr_instruction(struct die_args *args)
 {
         struct pt_regs *regs = args->regs;
         struct perf_event *bp = NULL;
-        struct arch_hw_breakpoint *bp_info;
+        struct arch_hw_breakpoint *info;
 
         bp = current->thread.last_hit_ubp;
         /*
@@ -304,16 +311,16 @@ int __kprobes single_step_dabr_instruction(struct die_args *args)
         if (!bp)
                 return NOTIFY_DONE;
 
-        bp_info = counter_arch_bp(bp);
+        info = counter_arch_bp(bp);
 
         /*
          * We shall invoke the user-defined callback function in the single
          * stepping handler to confirm to 'trigger-after-execute' semantics
          */
-        if (!bp_info->extraneous_interrupt)
+        if (!info->extraneous_interrupt)
                 perf_bp_event(bp, regs);
 
-        set_dabr(bp_info->address | bp_info->type | DABR_TRANSLATION);
+        set_dabr(info->address | info->type | DABR_TRANSLATION, info->dabrx);
         current->thread.last_hit_ubp = NULL;
 
         /*
diff --git a/arch/powerpc/kernel/ibmebus.c b/arch/powerpc/kernel/ibmebus.c
index b01d14eeca8d..8220baa46faf 100644
--- a/arch/powerpc/kernel/ibmebus.c
+++ b/arch/powerpc/kernel/ibmebus.c
@@ -47,7 +47,6 @@
 #include <linux/stat.h>
 #include <linux/of_platform.h>
 #include <asm/ibmebus.h>
-#include <asm/abs_addr.h>
 
 static struct device ibmebus_bus_device = { /* fake "parent" device */
         .init_name = "ibmebus",
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index ff5a6ce027b8..8226c6cb348a 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -215,7 +215,8 @@ static unsigned long iommu_range_alloc(struct device *dev,
         spin_lock_irqsave(&(pool->lock), flags);
 
 again:
-        if ((pass == 0) && handle && *handle)
+        if ((pass == 0) && handle && *handle &&
+            (*handle >= pool->start) && (*handle < pool->end))
                 start = *handle;
         else
                 start = pool->hint;
@@ -236,7 +237,9 @@ again:
                  * but on second pass, start at 0 in pool 0.
                  */
                 if ((start & mask) >= limit || pass > 0) {
+                        spin_unlock(&(pool->lock));
                         pool = &(tbl->pools[0]);
+                        spin_lock(&(pool->lock));
                         start = pool->start;
                 } else {
                         start &= mask;
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 1f017bb7a7ce..71413f41278f 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -489,10 +489,10 @@ void do_IRQ(struct pt_regs *regs)
         struct pt_regs *old_regs = set_irq_regs(regs);
         unsigned int irq;
 
-        trace_irq_entry(regs);
-
         irq_enter();
 
+        trace_irq_entry(regs);
+
         check_stack_overflow();
 
         /*
@@ -511,10 +511,10 @@ void do_IRQ(struct pt_regs *regs)
         else
                 __get_cpu_var(irq_stat).spurious_irqs++;
 
+        trace_irq_exit(regs);
+
         irq_exit();
         set_irq_regs(old_regs);
-
-        trace_irq_exit(regs);
 }
 
 void __init init_IRQ(void)
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index 5df777794403..fa9f6c72f557 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -165,7 +165,7 @@ void __init reserve_crashkernel(void)
         if (memory_limit && memory_limit <= crashk_res.end) {
                 memory_limit = crashk_res.end + 1;
                 printk("Adjusted memory limit for crashkernel, now 0x%llx\n",
-                       (unsigned long long)memory_limit);
+                       memory_limit);
         }
 
         printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
@@ -204,6 +204,12 @@ static struct property crashk_size_prop = {
         .value = &crashk_size,
 };
 
+static struct property memory_limit_prop = {
+        .name = "linux,memory-limit",
+        .length = sizeof(unsigned long long),
+        .value = &memory_limit,
+};
+
 static void __init export_crashk_values(struct device_node *node)
 {
         struct property *prop;
@@ -223,6 +229,12 @@ static void __init export_crashk_values(struct device_node *node)
                 crashk_size = resource_size(&crashk_res);
                 prom_add_property(node, &crashk_size_prop);
         }
+
+        /*
+         * memory_limit is required by the kexec-tools to limit the
+         * crash regions to the actual memory used.
+         */
+        prom_update_property(node, &memory_limit_prop);
 }
 
 static int __init kexec_setup(void)
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index fbe1a12dc7f1..cd6da855090c 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -142,6 +142,7 @@ void __init initialise_paca(struct paca_struct *new_paca, int cpu)
         new_paca->hw_cpu_id = 0xffff;
         new_paca->kexec_state = KEXEC_STATE_NONE;
         new_paca->__current = &init_task;
+        new_paca->data_offset = 0xfeeeeeeeeeeeeeeeULL;
 #ifdef CONFIG_PPC_STD_MMU_64
         new_paca->slb_shadow_ptr = &slb_shadow[cpu];
 #endif /* CONFIG_PPC_STD_MMU_64 */
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 43fea543d686..7f94f760dd0c 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -980,13 +980,14 @@ static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
                 if (i >= 3 && bus->self->transparent)
                         continue;
 
-                /* If we are going to re-assign everything, mark the resource
-                 * as unset and move it down to 0
+                /* If we're going to reassign everything, we can
+                 * shrink the P2P resource to have size as being
+                 * of 0 in order to save space.
                  */
                 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
                         res->flags |= IORESOURCE_UNSET;
-                        res->end -= res->start;
                         res->start = 0;
+                        res->end = -1;
                         continue;
                 }
 
@@ -1248,7 +1249,14 @@ void pcibios_allocate_bus_resources(struct pci_bus *bus)
                 pr_warning("PCI: Cannot allocate resource region "
                            "%d of PCI bridge %d, will remap\n", i, bus->number);
         clear_resource:
-                res->start = res->end = 0;
+                /* The resource might be figured out when doing
+                 * reassignment based on the resources required
+                 * by the downstream PCI devices. Here we set
+                 * the size of the resource to be 0 in order to
+                 * save more space.
+                 */
+                res->start = 0;
+                res->end = -1;
                 res->flags = 0;
         }
 
diff --git a/arch/powerpc/kernel/ppc32.h b/arch/powerpc/kernel/ppc32.h
index dc16aefe1dd0..02fb0ee26093 100644
--- a/arch/powerpc/kernel/ppc32.h
+++ b/arch/powerpc/kernel/ppc32.h
@@ -16,57 +16,6 @@
 
 /* These are here to support 32-bit syscalls on a 64-bit kernel. */
 
-typedef struct compat_siginfo {
-        int si_signo;
-        int si_errno;
-        int si_code;
-
-        union {
-                int _pad[SI_PAD_SIZE32];
-
-                /* kill() */
-                struct {
-                        compat_pid_t _pid;              /* sender's pid */
-                        compat_uid_t _uid;              /* sender's uid */
-                } _kill;
-
-                /* POSIX.1b timers */
-                struct {
-                        compat_timer_t _tid;                    /* timer id */
-                        int _overrun;                   /* overrun count */
-                        compat_sigval_t _sigval;                /* same as below */
-                        int _sys_private;               /* not to be passed to user */
-                } _timer;
-
-                /* POSIX.1b signals */
-                struct {
-                        compat_pid_t _pid;              /* sender's pid */
-                        compat_uid_t _uid;              /* sender's uid */
-                        compat_sigval_t _sigval;
-                } _rt;
-
-                /* SIGCHLD */
-                struct {
-                        compat_pid_t _pid;              /* which child */
-                        compat_uid_t _uid;              /* sender's uid */
-                        int _status;                    /* exit code */
-                        compat_clock_t _utime;
-                        compat_clock_t _stime;
-                } _sigchld;
-
-                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS, SIGEMT */
-                struct {
-                        unsigned int _addr; /* faulting insn/memory ref. */
-                } _sigfault;
-
-                /* SIGPOLL */
-                struct {
-                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
-                        int _fd;
-                } _sigpoll;
-        } _sifields;
-} compat_siginfo_t;
-
 #define __old_sigaction32       old_sigaction32
 
 struct __old_sigaction32 {
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index e9cb51f5f801..d5ad666efd8b 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -258,6 +258,7 @@ void do_send_trap(struct pt_regs *regs, unsigned long address,
 {
         siginfo_t info;
 
+        current->thread.trap_nr = signal_code;
         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
                         11, SIGSEGV) == NOTIFY_STOP)
                 return;
@@ -275,6 +276,7 @@ void do_dabr(struct pt_regs *regs, unsigned long address,
 {
         siginfo_t info;
 
+        current->thread.trap_nr = TRAP_HWBKPT;
         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
                         11, SIGSEGV) == NOTIFY_STOP)
                 return;
@@ -283,7 +285,7 @@ void do_dabr(struct pt_regs *regs, unsigned long address,
                 return;
 
         /* Clear the DABR */
-        set_dabr(0);
+        set_dabr(0, 0);
 
         /* Deliver the signal to userspace */
         info.si_signo = SIGTRAP;
@@ -364,18 +366,19 @@ static void set_debug_reg_defaults(struct thread_struct *thread)
 {
         if (thread->dabr) {
                 thread->dabr = 0;
-                set_dabr(0);
+                thread->dabrx = 0;
+                set_dabr(0, 0);
         }
 }
 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 
-int set_dabr(unsigned long dabr)
+int set_dabr(unsigned long dabr, unsigned long dabrx)
 {
         __get_cpu_var(current_dabr) = dabr;
 
         if (ppc_md.set_dabr)
-                return ppc_md.set_dabr(dabr);
+                return ppc_md.set_dabr(dabr, dabrx);
 
         /* XXX should we have a CPU_FTR_HAS_DABR ? */
 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
@@ -385,9 +388,8 @@ int set_dabr(unsigned long dabr)
 #endif
 #elif defined(CONFIG_PPC_BOOK3S)
         mtspr(SPRN_DABR, dabr);
+        mtspr(SPRN_DABRX, dabrx);
 #endif
-
-
         return 0;
 }
 
@@ -480,7 +482,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
  */
 #ifndef CONFIG_HAVE_HW_BREAKPOINT
         if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
-                set_dabr(new->thread.dabr);
+                set_dabr(new->thread.dabr, new->thread.dabrx);
 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
 #endif
 
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index f191bf02943a..37725e86651e 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -78,7 +78,7 @@ static int __init early_parse_mem(char *p)
                 return 1;
 
         memory_limit = PAGE_ALIGN(memparse(p, &p));
-        DBG("memory limit = 0x%llx\n", (unsigned long long)memory_limit);
+        DBG("memory limit = 0x%llx\n", memory_limit);
 
         return 0;
 }
@@ -661,7 +661,7 @@ void __init early_init_devtree(void *params)
 
         /* make sure we've parsed cmdline for mem= before this */
         if (memory_limit)
-                first_memblock_size = min(first_memblock_size, memory_limit);
+                first_memblock_size = min_t(u64, first_memblock_size, memory_limit);
         setup_initial_memory_limit(memstart_addr, first_memblock_size);
         /* Reserve MEMBLOCK regions used by kernel, initrd, dt, etc... */
         memblock_reserve(PHYSICAL_START, __pa(klimit) - PHYSICAL_START);
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 47834a3f4938..cb6c123722a2 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -1748,7 +1748,7 @@ static void __init prom_initialize_tce_table(void)
                  * else will impact performance, so we always allocate 8MB.
                  * Anton
                  */
-                if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p))
+                if (pvr_version_is(PVR_POWER4) || pvr_version_is(PVR_POWER4p))
                         minsize = 8UL << 20;
                 else
                         minsize = 4UL << 20;
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index c10fc28b9092..79d8e56470df 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -960,6 +960,7 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
                 thread->ptrace_bps[0] = bp;
                 ptrace_put_breakpoints(task);
                 thread->dabr = data;
+                thread->dabrx = DABRX_ALL;
                 return 0;
         }
 
@@ -983,6 +984,7 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
 
         /* Move contents to the DABR register */
         task->thread.dabr = data;
+        task->thread.dabrx = DABRX_ALL;
 #else /* CONFIG_PPC_ADV_DEBUG_REGS */
         /* As described above, it was assumed 3 bits were passed with the data
          *  address, but we will assume only the mode bits will be passed
@@ -1397,6 +1399,7 @@ static long ppc_set_hwdebug(struct task_struct *child,
                 dabr |= DABR_DATA_WRITE;
 
         child->thread.dabr = dabr;
+        child->thread.dabrx = DABRX_ALL;
 
         return 1;
 #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c
index 2c0ee6405633..20b0120db0c3 100644
--- a/arch/powerpc/kernel/rtas_flash.c
+++ b/arch/powerpc/kernel/rtas_flash.c
@@ -21,7 +21,6 @@
 #include <asm/delay.h>
 #include <asm/uaccess.h>
 #include <asm/rtas.h>
-#include <asm/abs_addr.h>
 
 #define MODULE_VERS "1.0"
 #define MODULE_NAME "rtas_flash"
@@ -582,7 +581,7 @@ static void rtas_flash_firmware(int reboot_type)
         flist = (struct flash_block_list *)&rtas_data_buf[0];
         flist->num_blocks = 0;
         flist->next = rtas_firmware_flash_list;
-        rtas_block_list = virt_to_abs(flist);
+        rtas_block_list = __pa(flist);
         if (rtas_block_list >= 4UL*1024*1024*1024) {
                 printk(KERN_ALERT "FLASH: kernel bug...flash list header addr above 4GB\n");
                 spin_unlock(&rtas_data_buf_lock);
@@ -596,13 +595,13 @@ static void rtas_flash_firmware(int reboot_type)
         for (f = flist; f; f = next) {
                 /* Translate data addrs to absolute */
                 for (i = 0; i < f->num_blocks; i++) {
-                        f->blocks[i].data = (char *)virt_to_abs(f->blocks[i].data);
+                        f->blocks[i].data = (char *)__pa(f->blocks[i].data);
                         image_size += f->blocks[i].length;
                 }
                 next = f->next;
                 /* Don't translate NULL pointer for last entry */
                 if (f->next)
-                        f->next = (struct flash_block_list *)virt_to_abs(f->next);
+                        f->next = (struct flash_block_list *)__pa(f->next);
                 else
                         f->next = NULL;
                 /* make num_blocks into the version/length field */
diff --git a/arch/powerpc/kernel/rtas_pci.c b/arch/powerpc/kernel/rtas_pci.c
index 179af906dcda..6de63e3250bb 100644
--- a/arch/powerpc/kernel/rtas_pci.c
+++ b/arch/powerpc/kernel/rtas_pci.c
@@ -81,7 +81,7 @@ int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
         if (returnval == EEH_IO_ERROR_VALUE(size) &&
-            eeh_dn_check_failure (pdn->node, NULL))
+            eeh_dev_check_failure(of_node_to_eeh_dev(pdn->node)))
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
         return PCIBIOS_SUCCESSFUL;
@@ -275,9 +275,6 @@ void __init find_and_init_phbs(void)
         of_node_put(root);
         pci_devs_phb_init();
 
-        /* Create EEH devices for all PHBs */
-        eeh_dev_phb_init();
-
         /*
          * PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties
          * in chosen.
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 389bd4f0cdb1..efb6a41b3131 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -208,6 +208,8 @@ void __init early_setup(unsigned long dt_ptr)
 
         /* Fix up paca fields required for the boot cpu */
         get_paca()->cpu_start = 1;
+        /* Allow percpu accesses to "work" until we setup percpu data */
+        get_paca()->data_offset = 0;
 
         /* Probe the machine type */
         probe_machine();
diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c
index 5c023c9cf16e..a2dc75793bd5 100644
--- a/arch/powerpc/kernel/signal.c
+++ b/arch/powerpc/kernel/signal.c
@@ -11,6 +11,7 @@
 
 #include <linux/tracehook.h>
 #include <linux/signal.h>
+#include <linux/uprobes.h>
 #include <linux/key.h>
 #include <asm/hw_breakpoint.h>
 #include <asm/uaccess.h>
@@ -130,7 +131,7 @@ static int do_signal(struct pt_regs *regs)
          * triggered inside the kernel.
          */
         if (current->thread.dabr)
-                set_dabr(current->thread.dabr);
+                set_dabr(current->thread.dabr, current->thread.dabrx);
 #endif
         /* Re-enable the breakpoints for the signal stack */
         thread_change_pc(current, regs);
@@ -157,6 +158,11 @@ static int do_signal(struct pt_regs *regs)
 
 void do_notify_resume(struct pt_regs *regs, unsigned long thread_info_flags)
 {
+        if (thread_info_flags & _TIF_UPROBE) {
+                clear_thread_flag(TIF_UPROBE);
+                uprobe_notify_resume(regs);
+        }
+
         if (thread_info_flags & _TIF_SIGPENDING)
                 do_signal(regs);
 
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 8d4214afc21d..2b952b5386fd 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -102,7 +102,7 @@ int __devinit smp_generic_kick_cpu(int nr)
          * Ok it's not there, so it might be soft-unplugged, let's
          * try to bring it back
          */
-        per_cpu(cpu_state, nr) = CPU_UP_PREPARE;
+        generic_set_cpu_up(nr);
         smp_wmb();
         smp_send_reschedule(nr);
 #endif /* CONFIG_HOTPLUG_CPU */
@@ -171,7 +171,7 @@ int smp_request_message_ipi(int virq, int msg)
         }
 #endif
         err = request_irq(virq, smp_ipi_action[msg],
-                          IRQF_PERCPU | IRQF_NO_THREAD,
+                          IRQF_PERCPU | IRQF_NO_THREAD | IRQF_NO_SUSPEND,
                           smp_ipi_name[msg], 0);
         WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n",
                 virq, smp_ipi_name[msg], err);
@@ -413,6 +413,16 @@ void generic_set_cpu_dead(unsigned int cpu)
         per_cpu(cpu_state, cpu) = CPU_DEAD;
 }
 
+/*
+ * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise
+ * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(),
+ * which makes the delay in generic_cpu_die() not happen.
+ */
+void generic_set_cpu_up(unsigned int cpu)
+{
+        per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
+}
+
 int generic_check_cpu_restart(unsigned int cpu)
 {
         return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE;
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index eaa9d0e6abca..c9986fd400d8 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -508,8 +508,6 @@ void timer_interrupt(struct pt_regs * regs)
          */
         may_hard_irq_enable();
 
-        trace_timer_interrupt_entry(regs);
-
         __get_cpu_var(irq_stat).timer_irqs++;
 
 #if defined(CONFIG_PPC32) && defined(CONFIG_PMAC)
@@ -520,6 +518,8 @@ void timer_interrupt(struct pt_regs * regs)
         old_regs = set_irq_regs(regs);
         irq_enter();
 
+        trace_timer_interrupt_entry(regs);
+
         if (test_irq_work_pending()) {
                 clear_irq_work_pending();
                 irq_work_run();
@@ -544,10 +544,10 @@ void timer_interrupt(struct pt_regs * regs)
         }
 #endif
 
+        trace_timer_interrupt_exit(regs);
+
         irq_exit();
         set_irq_regs(old_regs);
-
-        trace_timer_interrupt_exit(regs);
 }
 
 /*
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index ae0843fa7a61..32518401af68 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -251,6 +251,7 @@ void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
         if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
                 local_irq_enable();
 
+        current->thread.trap_nr = code;
         memset(&info, 0, sizeof(info));
         info.si_signo = signr;
         info.si_code = code;
diff --git a/arch/powerpc/kernel/uprobes.c b/arch/powerpc/kernel/uprobes.c
new file mode 100644
index 000000000000..d2d46d1014f8
--- /dev/null
+++ b/arch/powerpc/kernel/uprobes.c
@@ -0,0 +1,184 @@
+/*
+ * User-space Probes (UProbes) for powerpc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright IBM Corporation, 2007-2012
+ *
+ * Adapted from the x86 port by Ananth N Mavinakayanahalli <ananth@in.ibm.com>
+ */
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/uprobes.h>
+#include <linux/uaccess.h>
+#include <linux/kdebug.h>
+
+#include <asm/sstep.h>
+
+#define UPROBE_TRAP_NR  UINT_MAX
+
+/**
+ * arch_uprobe_analyze_insn
+ * @mm: the probed address space.
+ * @arch_uprobe: the probepoint information.
+ * @addr: vaddr to probe.
+ * Return 0 on success or a -ve number on error.
+ */
+int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe,
+                struct mm_struct *mm, unsigned long addr)
+{
+        if (addr & 0x03)
+                return -EINVAL;
+
+        /*
+         * We currently don't support a uprobe on an already
+         * existing breakpoint instruction underneath
+         */
+        if (is_trap(auprobe->ainsn))
+                return -ENOTSUPP;
+        return 0;
+}
+
+/*
+ * arch_uprobe_pre_xol - prepare to execute out of line.
+ * @auprobe: the probepoint information.
+ * @regs: reflects the saved user state of current task.
+ */
+int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
+{
+        struct arch_uprobe_task *autask = &current->utask->autask;
+
+        autask->saved_trap_nr = current->thread.trap_nr;
+        current->thread.trap_nr = UPROBE_TRAP_NR;
+        regs->nip = current->utask->xol_vaddr;
+        return 0;
+}
+
+/**
+ * uprobe_get_swbp_addr - compute address of swbp given post-swbp regs
+ * @regs: Reflects the saved state of the task after it has hit a breakpoint
+ * instruction.
+ * Return the address of the breakpoint instruction.
+ */
+unsigned long uprobe_get_swbp_addr(struct pt_regs *regs)
+{
+        return instruction_pointer(regs);
+}
+
+/*
+ * If xol insn itself traps and generates a signal (SIGILL/SIGSEGV/etc),
+ * then detect the case where a singlestepped instruction jumps back to its
+ * own address. It is assumed that anything like do_page_fault/do_trap/etc
+ * sets thread.trap_nr != UINT_MAX.
+ *
+ * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr,
+ * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to
+ * UPROBE_TRAP_NR == UINT_MAX set by arch_uprobe_pre_xol().
+ */
+bool arch_uprobe_xol_was_trapped(struct task_struct *t)
+{
+        if (t->thread.trap_nr != UPROBE_TRAP_NR)
+                return true;
+
+        return false;
+}
+
+/*
+ * Called after single-stepping. To avoid the SMP problems that can
+ * occur when we temporarily put back the original opcode to
+ * single-step, we single-stepped a copy of the instruction.
+ *
+ * This function prepares to resume execution after the single-step.
+ */
+int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
+{
+        struct uprobe_task *utask = current->utask;
+
+        WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR);
+
+        current->thread.trap_nr = utask->autask.saved_trap_nr;
+
+        /*
+         * On powerpc, except for loads and stores, most instructions
+         * including ones that alter code flow (branches, calls, returns)
+         * are emulated in the kernel. We get here only if the emulation
+         * support doesn't exist and have to fix-up the next instruction
+         * to be executed.
+         */
+        regs->nip = utask->vaddr + MAX_UINSN_BYTES;
+        return 0;
+}
+
+/* callback routine for handling exceptions. */
+int arch_uprobe_exception_notify(struct notifier_block *self,
+                                unsigned long val, void *data)
+{
+        struct die_args *args = data;
+        struct pt_regs *regs = args->regs;
+
+        /* regs == NULL is a kernel bug */
+        if (WARN_ON(!regs))
+                return NOTIFY_DONE;
+
+        /* We are only interested in userspace traps */
+        if (!user_mode(regs))
+                return NOTIFY_DONE;
+
+        switch (val) {
+        case DIE_BPT:
+                if (uprobe_pre_sstep_notifier(regs))
+                        return NOTIFY_STOP;
+                break;
+        case DIE_SSTEP:
+                if (uprobe_post_sstep_notifier(regs))
+                        return NOTIFY_STOP;
+        default:
+                break;
+        }
+        return NOTIFY_DONE;
+}
+
+/*
+ * This function gets called when XOL instruction either gets trapped or
+ * the thread has a fatal signal, so reset the instruction pointer to its
+ * probed address.
+ */
+void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
+{
+        struct uprobe_task *utask = current->utask;
+
+        current->thread.trap_nr = utask->autask.saved_trap_nr;
+        instruction_pointer_set(regs, utask->vaddr);
+}
+
+/*
+ * See if the instruction can be emulated.
+ * Returns true if instruction was emulated, false otherwise.
+ */
+bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
+{
+        int ret;
+
+        /*
+         * emulate_step() returns 1 if the insn was successfully emulated.
+         * For all other cases, we need to single-step in hardware.
+         */
+        ret = emulate_step(regs, auprobe->ainsn);
+        if (ret > 0)
+                return true;
+
+        return false;
+}
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index b67db22e102d..1b2076f049ce 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -723,9 +723,7 @@ int __cpuinit vdso_getcpu_init(void)
 
         val = (cpu & 0xfff) | ((node & 0xffff) << 16);
         mtspr(SPRN_SPRG3, val);
-#ifdef CONFIG_KVM_BOOK3S_HANDLER
-        get_paca()->kvm_hstate.sprg3 = val;
-#endif
+        get_paca()->sprg3 = val;
 
         put_cpu();
 
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index 02b32216bbc3..201ba59738be 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -33,7 +33,6 @@
 #include <asm/prom.h>
 #include <asm/firmware.h>
 #include <asm/tce.h>
-#include <asm/abs_addr.h>
 #include <asm/page.h>
 #include <asm/hvcall.h>
 
diff --git a/arch/powerpc/kvm/book3s_32_mmu_host.c b/arch/powerpc/kvm/book3s_32_mmu_host.c
index 837f13e7b6bf..00aa61268e0d 100644
--- a/arch/powerpc/kvm/book3s_32_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_32_mmu_host.c
@@ -141,7 +141,7 @@ extern char etext[];
 int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
 {
         pfn_t hpaddr;
-        u64 va;
+        u64 vpn;
         u64 vsid;
         struct kvmppc_sid_map *map;
         volatile u32 *pteg;
@@ -173,7 +173,7 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
         BUG_ON(!map);
 
         vsid = map->host_vsid;
-        va = (vsid << SID_SHIFT) | (eaddr & ~ESID_MASK);
+        vpn = (vsid << (SID_SHIFT - VPN_SHIFT)) | ((eaddr & ~ESID_MASK) >> VPN_SHIFT)
 
 next_pteg:
         if (rr == 16) {
@@ -244,11 +244,11 @@ next_pteg:
         dprintk_mmu("KVM: %c%c Map 0x%llx: [%lx] 0x%llx (0x%llx) -> %lx\n",
                     orig_pte->may_write ? 'w' : '-',
                     orig_pte->may_execute ? 'x' : '-',
-                    orig_pte->eaddr, (ulong)pteg, va,
+                    orig_pte->eaddr, (ulong)pteg, vpn,
                     orig_pte->vpage, hpaddr);
 
         pte->slot = (ulong)&pteg[rr];
-        pte->host_va = va;
+        pte->host_vpn = vpn;
         pte->pte = *orig_pte;
         pte->pfn = hpaddr >> PAGE_SHIFT;
 
diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c b/arch/powerpc/kvm/book3s_64_mmu_host.c
index 0688b6b39585..4d72f9ebc554 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_host.c
@@ -33,7 +33,7 @@
 
 void kvmppc_mmu_invalidate_pte(struct kvm_vcpu *vcpu, struct hpte_cache *pte)
 {
-        ppc_md.hpte_invalidate(pte->slot, pte->host_va,
+        ppc_md.hpte_invalidate(pte->slot, pte->host_vpn,
                                MMU_PAGE_4K, MMU_SEGSIZE_256M,
                                false);
 }
@@ -80,8 +80,9 @@ static struct kvmppc_sid_map *find_sid_vsid(struct kvm_vcpu *vcpu, u64 gvsid)
 
 int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
 {
+        unsigned long vpn;
         pfn_t hpaddr;
-        ulong hash, hpteg, va;
+        ulong hash, hpteg;
         u64 vsid;
         int ret;
         int rflags = 0x192;
@@ -117,7 +118,7 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
         }
 
         vsid = map->host_vsid;
-        va = hpt_va(orig_pte->eaddr, vsid, MMU_SEGSIZE_256M);
+        vpn = hpt_vpn(orig_pte->eaddr, vsid, MMU_SEGSIZE_256M);
 
         if (!orig_pte->may_write)
                 rflags |= HPTE_R_PP;
@@ -129,7 +130,7 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
         else
                 kvmppc_mmu_flush_icache(hpaddr >> PAGE_SHIFT);
 
-        hash = hpt_hash(va, PTE_SIZE, MMU_SEGSIZE_256M);
+        hash = hpt_hash(vpn, PTE_SIZE, MMU_SEGSIZE_256M);
 
 map_again:
         hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
@@ -141,7 +142,8 @@ map_again:
                         goto out;
                 }
 
-        ret = ppc_md.hpte_insert(hpteg, va, hpaddr, rflags, vflags, MMU_PAGE_4K, MMU_SEGSIZE_256M);
+        ret = ppc_md.hpte_insert(hpteg, vpn, hpaddr, rflags, vflags,
+                                 MMU_PAGE_4K, MMU_SEGSIZE_256M);
 
         if (ret < 0) {
                 /* If we couldn't map a primary PTE, try a secondary */
@@ -152,7 +154,8 @@ map_again:
         } else {
                 struct hpte_cache *pte = kvmppc_mmu_hpte_cache_next(vcpu);
 
-                trace_kvm_book3s_64_mmu_map(rflags, hpteg, va, hpaddr, orig_pte);
+                trace_kvm_book3s_64_mmu_map(rflags, hpteg,
+                                            vpn, hpaddr, orig_pte);
 
                 /* The ppc_md code may give us a secondary entry even though we
                    asked for a primary. Fix up. */
@@ -162,7 +165,7 @@ map_again:
                 }
 
                 pte->slot = hpteg + (ret & 7);
-                pte->host_va = va;
+                pte->host_vpn = vpn;
                 pte->pte = *orig_pte;
                 pte->pfn = hpaddr >> PAGE_SHIFT;
 
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 44b72feaff7d..74a24bbb9637 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -1065,7 +1065,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
         mtspr   SPRN_DABRX,r6
 
         /* Restore SPRG3 */
-        ld      r3,HSTATE_SPRG3(r13)
+        ld      r3,PACA_SPRG3(r13)
         mtspr   SPRN_SPRG3,r3
 
         /*
diff --git a/arch/powerpc/kvm/trace.h b/arch/powerpc/kvm/trace.h
index 877186b7b1c3..ddb6a2149d44 100644
--- a/arch/powerpc/kvm/trace.h
+++ b/arch/powerpc/kvm/trace.h
@@ -189,7 +189,7 @@ TRACE_EVENT(kvm_book3s_mmu_map,
         TP_ARGS(pte),
 
         TP_STRUCT__entry(
-                __field(        u64,            host_va         )
+                __field(        u64,            host_vpn        )
                 __field(        u64,            pfn             )
                 __field(        ulong,          eaddr           )
                 __field(        u64,            vpage           )
@@ -198,7 +198,7 @@ TRACE_EVENT(kvm_book3s_mmu_map,
         ),
 
         TP_fast_assign(
-                __entry->host_va        = pte->host_va;
+                __entry->host_vpn       = pte->host_vpn;
                 __entry->pfn            = pte->pfn;
                 __entry->eaddr          = pte->pte.eaddr;
                 __entry->vpage          = pte->pte.vpage;
@@ -208,8 +208,8 @@ TRACE_EVENT(kvm_book3s_mmu_map,
                                           (pte->pte.may_execute ? 0x1 : 0);
         ),
 
-        TP_printk("Map: hva=%llx pfn=%llx ea=%lx vp=%llx ra=%lx [%x]",
-                  __entry->host_va, __entry->pfn, __entry->eaddr,
+        TP_printk("Map: hvpn=%llx pfn=%llx ea=%lx vp=%llx ra=%lx [%x]",
+                  __entry->host_vpn, __entry->pfn, __entry->eaddr,
                   __entry->vpage, __entry->raddr, __entry->flags)
 );
 
@@ -218,7 +218,7 @@ TRACE_EVENT(kvm_book3s_mmu_invalidate,
         TP_ARGS(pte),
 
         TP_STRUCT__entry(
-                __field(        u64,            host_va         )
+                __field(        u64,            host_vpn        )
                 __field(        u64,            pfn             )
                 __field(        ulong,          eaddr           )
                 __field(        u64,            vpage           )
@@ -227,7 +227,7 @@ TRACE_EVENT(kvm_book3s_mmu_invalidate,
         ),
 
         TP_fast_assign(
-                __entry->host_va        = pte->host_va;
+                __entry->host_vpn       = pte->host_vpn;
                 __entry->pfn            = pte->pfn;
                 __entry->eaddr          = pte->pte.eaddr;
                 __entry->vpage          = pte->pte.vpage;
@@ -238,7 +238,7 @@ TRACE_EVENT(kvm_book3s_mmu_invalidate,
         ),
 
         TP_printk("Flush: hva=%llx pfn=%llx ea=%lx vp=%llx ra=%lx [%x]",
-                  __entry->host_va, __entry->pfn, __entry->eaddr,
+                  __entry->host_vpn, __entry->pfn, __entry->eaddr,
                   __entry->vpage, __entry->raddr, __entry->flags)
 );
 
diff --git a/arch/powerpc/lib/memcpy_power7.S b/arch/powerpc/lib/memcpy_power7.S
index 7ba6c96de778..0663630baf3b 100644
--- a/arch/powerpc/lib/memcpy_power7.S
+++ b/arch/powerpc/lib/memcpy_power7.S
@@ -239,8 +239,8 @@ _GLOBAL(memcpy_power7)
         ori     r9,r9,1         /* stream=1 */
 
         srdi    r7,r5,7         /* length in cachelines, capped at 0x3FF */
-        cmpldi  cr1,r7,0x3FF
-        ble     cr1,1f
+        cmpldi  r7,0x3FF
+        ble     1f
         li      r7,0x3FF
 1:      lis     r0,0x0E00       /* depth=7 */
         sldi    r7,r7,7
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 9a52349874ee..e15c521846ca 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -566,7 +566,7 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
         unsigned long int ea;
         unsigned int cr, mb, me, sh;
         int err;
-        unsigned long old_ra;
+        unsigned long old_ra, val3;
         long ival;
 
         opcode = instr >> 26;
@@ -1486,11 +1486,43 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
                 goto ldst_done;
 
         case 36:        /* stw */
-        case 37:        /* stwu */
                 val = regs->gpr[rd];
                 err = write_mem(val, dform_ea(instr, regs), 4, regs);
                 goto ldst_done;
 
+        case 37:        /* stwu */
+                val = regs->gpr[rd];
+                val3 = dform_ea(instr, regs);
+                /*
+                 * For PPC32 we always use stwu to change stack point with r1. So
+                 * this emulated store may corrupt the exception frame, now we
+                 * have to provide the exception frame trampoline, which is pushed
+                 * below the kprobed function stack. So we only update gpr[1] but
+                 * don't emulate the real store operation. We will do real store
+                 * operation safely in exception return code by checking this flag.
+                 */
+                if ((ra == 1) && !(regs->msr & MSR_PR) \
+                        && (val3 >= (regs->gpr[1] - STACK_INT_FRAME_SIZE))) {
+                        /*
+                         * Check if we will touch kernel sack overflow
+                         */
+                        if (val3 - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
+                                printk(KERN_CRIT "Can't kprobe this since Kernel stack overflow.\n");
+                                err = -EINVAL;
+                                break;
+                        }
+
+                        /*
+                         * Check if we already set since that means we'll
+                         * lose the previous value.
+                         */
+                        WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
+                        set_thread_flag(TIF_EMULATE_STACK_STORE);
+                        err = 0;
+                } else
+                        err = write_mem(val, val3, 4, regs);
+                goto ldst_done;
+
         case 38:        /* stb */
         case 39:        /* stbu */
                 val = regs->gpr[rd];
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index e5f028b5794e..5495ebe983a2 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -133,6 +133,7 @@ static int do_sigbus(struct pt_regs *regs, unsigned long address)
         up_read(&current->mm->mmap_sem);
 
         if (user_mode(regs)) {
+                current->thread.trap_nr = BUS_ADRERR;
                 info.si_signo = SIGBUS;
                 info.si_errno = 0;
                 info.si_code = BUS_ADRERR;
diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index 602aeb06d298..56585086413a 100644
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -63,7 +63,7 @@ _GLOBAL(__hash_page_4K)
         /* Save non-volatile registers.
          * r31 will hold "old PTE"
          * r30 is "new PTE"
-         * r29 is "va"
+         * r29 is vpn
          * r28 is a hash value
          * r27 is hashtab mask (maybe dynamic patched instead ?)
          */
@@ -111,10 +111,10 @@ BEGIN_FTR_SECTION
         cmpdi   r9,0                    /* check segment size */
         bne     3f
 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
-        /* Calc va and put it in r29 */
-        rldicr  r29,r5,28,63-28
-        rldicl  r3,r3,0,36
-        or      r29,r3,r29
+        /* Calc vpn and put it in r29 */
+        sldi    r29,r5,SID_SHIFT - VPN_SHIFT
+        rldicl  r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
+        or      r29,r28,r29
 
         /* Calculate hash value for primary slot and store it in r28 */
         rldicl  r5,r5,0,25              /* vsid & 0x0000007fffffffff */
@@ -122,14 +122,19 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
         xor     r28,r5,r0
         b       4f
 
-3:      /* Calc VA and hash in r29 and r28 for 1T segment */
-        sldi    r29,r5,40               /* vsid << 40 */
-        clrldi  r3,r3,24                /* ea & 0xffffffffff */
+3:      /* Calc vpn and put it in r29 */
+        sldi    r29,r5,SID_SHIFT_1T - VPN_SHIFT
+        rldicl  r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT_1T - VPN_SHIFT)
+        or      r29,r28,r29
+
+        /*
+         * calculate hash value for primary slot and
+         * store it in r28 for 1T segment
+         */
         rldic   r28,r5,25,25            /* (vsid << 25) & 0x7fffffffff */
         clrldi  r5,r5,40                /* vsid & 0xffffff */
         rldicl  r0,r3,64-12,36          /* (ea >> 12) & 0xfffffff */
         xor     r28,r28,r5
-        or      r29,r3,r29              /* VA */
         xor     r28,r28,r0              /* hash */
 
         /* Convert linux PTE bits into HW equivalents */
@@ -185,7 +190,7 @@ htab_insert_pte:
 
         /* Call ppc_md.hpte_insert */
         ld      r6,STK_PARAM(R4)(r1)    /* Retrieve new pp bits */
-        mr      r4,r29                  /* Retrieve va */
+        mr      r4,r29                  /* Retrieve vpn */
         li      r7,0                    /* !bolted, !secondary */
         li      r8,MMU_PAGE_4K          /* page size */
         ld      r9,STK_PARAM(R9)(r1)    /* segment size */
@@ -208,7 +213,7 @@ _GLOBAL(htab_call_hpte_insert1)
         
         /* Call ppc_md.hpte_insert */
         ld      r6,STK_PARAM(R4)(r1)    /* Retrieve new pp bits */
-        mr      r4,r29                  /* Retrieve va */
+        mr      r4,r29                  /* Retrieve vpn */
         li      r7,HPTE_V_SECONDARY     /* !bolted, secondary */
         li      r8,MMU_PAGE_4K          /* page size */
         ld      r9,STK_PARAM(R9)(r1)    /* segment size */
@@ -278,7 +283,7 @@ htab_modify_pte:
         add     r3,r0,r3        /* add slot idx */
 
         /* Call ppc_md.hpte_updatepp */
-        mr      r5,r29                  /* va */
+        mr      r5,r29                  /* vpn */
         li      r6,MMU_PAGE_4K          /* page size */
         ld      r7,STK_PARAM(R9)(r1)    /* segment size */
         ld      r8,STK_PARAM(R8)(r1)    /* get "local" param */
@@ -339,7 +344,7 @@ _GLOBAL(__hash_page_4K)
         /* Save non-volatile registers.
          * r31 will hold "old PTE"
          * r30 is "new PTE"
-         * r29 is "va"
+         * r29 is vpn
          * r28 is a hash value
          * r27 is hashtab mask (maybe dynamic patched instead ?)
          * r26 is the hidx mask
@@ -394,10 +399,14 @@ BEGIN_FTR_SECTION
         cmpdi   r9,0                    /* check segment size */
         bne     3f
 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
-        /* Calc va and put it in r29 */
-        rldicr  r29,r5,28,63-28         /* r29 = (vsid << 28) */
-        rldicl  r3,r3,0,36              /* r3 = (ea & 0x0fffffff) */
-        or      r29,r3,r29              /* r29 = va */
+        /* Calc vpn and put it in r29 */
+        sldi    r29,r5,SID_SHIFT - VPN_SHIFT
+        /*
+         * clrldi r3,r3,64 - SID_SHIFT -->  ea & 0xfffffff
+         * srdi  r28,r3,VPN_SHIFT
+         */
+        rldicl  r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
+        or      r29,r28,r29
 
         /* Calculate hash value for primary slot and store it in r28 */
         rldicl  r5,r5,0,25              /* vsid & 0x0000007fffffffff */
@@ -405,14 +414,23 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
         xor     r28,r5,r0
         b       4f
 
-3:      /* Calc VA and hash in r29 and r28 for 1T segment */
-        sldi    r29,r5,40               /* vsid << 40 */
-        clrldi  r3,r3,24                /* ea & 0xffffffffff */
+3:      /* Calc vpn and put it in r29 */
+        sldi    r29,r5,SID_SHIFT_1T - VPN_SHIFT
+        /*
+         * clrldi r3,r3,64 - SID_SHIFT_1T -->  ea & 0xffffffffff
+         * srdi r28,r3,VPN_SHIFT
+         */
+        rldicl  r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT_1T - VPN_SHIFT)
+        or      r29,r28,r29
+
+        /*
+         * Calculate hash value for primary slot and
+         * store it in r28  for 1T segment
+         */
         rldic   r28,r5,25,25            /* (vsid << 25) & 0x7fffffffff */
         clrldi  r5,r5,40                /* vsid & 0xffffff */
         rldicl  r0,r3,64-12,36          /* (ea >> 12) & 0xfffffff */
         xor     r28,r28,r5
-        or      r29,r3,r29              /* VA */
         xor     r28,r28,r0              /* hash */
 
         /* Convert linux PTE bits into HW equivalents */
@@ -488,7 +506,7 @@ htab_special_pfn:
 
         /* Call ppc_md.hpte_insert */
         ld      r6,STK_PARAM(R4)(r1)    /* Retrieve new pp bits */
-        mr      r4,r29                  /* Retrieve va */
+        mr      r4,r29                  /* Retrieve vpn */
         li      r7,0                    /* !bolted, !secondary */
         li      r8,MMU_PAGE_4K          /* page size */
         ld      r9,STK_PARAM(R9)(r1)    /* segment size */
@@ -515,7 +533,7 @@ _GLOBAL(htab_call_hpte_insert1)
 
         /* Call ppc_md.hpte_insert */
         ld      r6,STK_PARAM(R4)(r1)    /* Retrieve new pp bits */
-        mr      r4,r29                  /* Retrieve va */
+        mr      r4,r29                  /* Retrieve vpn */
         li      r7,HPTE_V_SECONDARY     /* !bolted, secondary */
         li      r8,MMU_PAGE_4K          /* page size */
         ld      r9,STK_PARAM(R9)(r1)    /* segment size */
@@ -547,7 +565,7 @@ _GLOBAL(htab_call_hpte_remove)
          * useless now that the segment has been switched to 4k pages.
          */
 htab_inval_old_hpte:
-        mr      r3,r29                  /* virtual addr */
+        mr      r3,r29                  /* vpn */
         mr      r4,r31                  /* PTE.pte */
         li      r5,0                    /* PTE.hidx */
         li      r6,MMU_PAGE_64K         /* psize */
@@ -620,7 +638,7 @@ htab_modify_pte:
         add     r3,r0,r3        /* add slot idx */
 
         /* Call ppc_md.hpte_updatepp */
-        mr      r5,r29                  /* va */
+        mr      r5,r29                  /* vpn */
         li      r6,MMU_PAGE_4K          /* page size */
         ld      r7,STK_PARAM(R9)(r1)    /* segment size */
         ld      r8,STK_PARAM(R8)(r1)    /* get "local" param */
@@ -676,7 +694,7 @@ _GLOBAL(__hash_page_64K)
         /* Save non-volatile registers.
          * r31 will hold "old PTE"
          * r30 is "new PTE"
-         * r29 is "va"
+         * r29 is vpn
          * r28 is a hash value
          * r27 is hashtab mask (maybe dynamic patched instead ?)
          */
@@ -729,10 +747,10 @@ BEGIN_FTR_SECTION
         cmpdi   r9,0                    /* check segment size */
         bne     3f
 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
-        /* Calc va and put it in r29 */
-        rldicr  r29,r5,28,63-28
-        rldicl  r3,r3,0,36
-        or      r29,r3,r29
+        /* Calc vpn and put it in r29 */
+        sldi    r29,r5,SID_SHIFT - VPN_SHIFT
+        rldicl  r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
+        or      r29,r28,r29
 
         /* Calculate hash value for primary slot and store it in r28 */
         rldicl  r5,r5,0,25              /* vsid & 0x0000007fffffffff */
@@ -740,14 +758,19 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
         xor     r28,r5,r0
         b       4f
 
-3:      /* Calc VA and hash in r29 and r28 for 1T segment */
-        sldi    r29,r5,40               /* vsid << 40 */
-        clrldi  r3,r3,24                /* ea & 0xffffffffff */
+3:      /* Calc vpn and put it in r29 */
+        sldi    r29,r5,SID_SHIFT_1T - VPN_SHIFT
+        rldicl  r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT_1T - VPN_SHIFT)
+        or      r29,r28,r29
+
+        /*
+         * calculate hash value for primary slot and
+         * store it in r28 for 1T segment
+         */
         rldic   r28,r5,25,25            /* (vsid << 25) & 0x7fffffffff */
         clrldi  r5,r5,40                /* vsid & 0xffffff */
         rldicl  r0,r3,64-16,40          /* (ea >> 16) & 0xffffff */
         xor     r28,r28,r5
-        or      r29,r3,r29              /* VA */
         xor     r28,r28,r0              /* hash */
 
         /* Convert linux PTE bits into HW equivalents */
@@ -806,7 +829,7 @@ ht64_insert_pte:
 
         /* Call ppc_md.hpte_insert */
         ld      r6,STK_PARAM(R4)(r1)    /* Retrieve new pp bits */
-        mr      r4,r29                  /* Retrieve va */
+        mr      r4,r29                  /* Retrieve vpn */
         li      r7,0                    /* !bolted, !secondary */
         li      r8,MMU_PAGE_64K
         ld      r9,STK_PARAM(R9)(r1)    /* segment size */
@@ -829,7 +852,7 @@ _GLOBAL(ht64_call_hpte_insert1)
 
         /* Call ppc_md.hpte_insert */
         ld      r6,STK_PARAM(R4)(r1)    /* Retrieve new pp bits */
-        mr      r4,r29                  /* Retrieve va */
+        mr      r4,r29                  /* Retrieve vpn */
         li      r7,HPTE_V_SECONDARY     /* !bolted, secondary */
         li      r8,MMU_PAGE_64K
         ld      r9,STK_PARAM(R9)(r1)    /* segment size */
@@ -899,7 +922,7 @@ ht64_modify_pte:
         add     r3,r0,r3        /* add slot idx */
 
         /* Call ppc_md.hpte_updatepp */
-        mr      r5,r29                  /* va */
+        mr      r5,r29                  /* vpn */
         li      r6,MMU_PAGE_64K
         ld      r7,STK_PARAM(R9)(r1)    /* segment size */
         ld      r8,STK_PARAM(R8)(r1)    /* get "local" param */
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 90039bc64119..ffc1e00f7a22 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -14,10 +14,10 @@
 
 #include <linux/spinlock.h>
 #include <linux/bitops.h>
+#include <linux/of.h>
 #include <linux/threads.h>
 #include <linux/smp.h>
 
-#include <asm/abs_addr.h>
 #include <asm/machdep.h>
 #include <asm/mmu.h>
 #include <asm/mmu_context.h>
@@ -39,22 +39,35 @@
 
 DEFINE_RAW_SPINLOCK(native_tlbie_lock);
 
-static inline void __tlbie(unsigned long va, int psize, int ssize)
+static inline void __tlbie(unsigned long vpn, int psize, int ssize)
 {
+        unsigned long va;
         unsigned int penc;
 
-        /* clear top 16 bits, non SLS segment */
+        /*
+         * We need 14 to 65 bits of va for a tlibe of 4K page
+         * With vpn we ignore the lower VPN_SHIFT bits already.
+         * And top two bits are already ignored because we can
+         * only accomadate 76 bits in a 64 bit vpn with a VPN_SHIFT
+         * of 12.
+         */
+        va = vpn << VPN_SHIFT;
+        /*
+         * clear top 16 bits of 64bit va, non SLS segment
+         * Older versions of the architecture (2.02 and earler) require the
+         * masking of the top 16 bits.
+         */
         va &= ~(0xffffULL << 48);
 
         switch (psize) {
         case MMU_PAGE_4K:
-                va &= ~0xffful;
                 va |= ssize << 8;
                 asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
                              : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
                              : "memory");
                 break;
         default:
+                /* We need 14 to 14 + i bits of va */
                 penc = mmu_psize_defs[psize].penc;
                 va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
                 va |= penc << 12;
@@ -67,21 +80,28 @@ static inline void __tlbie(unsigned long va, int psize, int ssize)
         }
 }
 
-static inline void __tlbiel(unsigned long va, int psize, int ssize)
+static inline void __tlbiel(unsigned long vpn, int psize, int ssize)
 {
+        unsigned long va;
         unsigned int penc;
 
-        /* clear top 16 bits, non SLS segment */
+        /* VPN_SHIFT can be atmost 12 */
+        va = vpn << VPN_SHIFT;
+        /*
+         * clear top 16 bits of 64 bit va, non SLS segment
+         * Older versions of the architecture (2.02 and earler) require the
+         * masking of the top 16 bits.
+         */
         va &= ~(0xffffULL << 48);
 
         switch (psize) {
         case MMU_PAGE_4K:
-                va &= ~0xffful;
                 va |= ssize << 8;
                 asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
                              : : "r"(va) : "memory");
                 break;
         default:
+                /* We need 14 to 14 + i bits of va */
                 penc = mmu_psize_defs[psize].penc;
                 va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
                 va |= penc << 12;
@@ -94,7 +114,7 @@ static inline void __tlbiel(unsigned long va, int psize, int ssize)
 
 }
 
-static inline void tlbie(unsigned long va, int psize, int ssize, int local)
+static inline void tlbie(unsigned long vpn, int psize, int ssize, int local)
 {
         unsigned int use_local = local && mmu_has_feature(MMU_FTR_TLBIEL);
         int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
@@ -105,10 +125,10 @@ static inline void tlbie(unsigned long va, int psize, int ssize, int local)
                 raw_spin_lock(&native_tlbie_lock);
         asm volatile("ptesync": : :"memory");
         if (use_local) {
-                __tlbiel(va, psize, ssize);
+                __tlbiel(vpn, psize, ssize);
                 asm volatile("ptesync": : :"memory");
         } else {
-                __tlbie(va, psize, ssize);
+                __tlbie(vpn, psize, ssize);
                 asm volatile("eieio; tlbsync; ptesync": : :"memory");
         }
         if (lock_tlbie && !use_local)
@@ -134,7 +154,7 @@ static inline void native_unlock_hpte(struct hash_pte *hptep)
         clear_bit_unlock(HPTE_LOCK_BIT, word);
 }
 
-static long native_hpte_insert(unsigned long hpte_group, unsigned long va,
+static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn,
                         unsigned long pa, unsigned long rflags,
                         unsigned long vflags, int psize, int ssize)
 {
@@ -143,9 +163,9 @@ static long native_hpte_insert(unsigned long hpte_group, unsigned long va,
         int i;
 
         if (!(vflags & HPTE_V_BOLTED)) {
-                DBG_LOW("    insert(group=%lx, va=%016lx, pa=%016lx,"
+                DBG_LOW("    insert(group=%lx, vpn=%016lx, pa=%016lx,"
                         " rflags=%lx, vflags=%lx, psize=%d)\n",
-                        hpte_group, va, pa, rflags, vflags, psize);
+                        hpte_group, vpn, pa, rflags, vflags, psize);
         }
 
         for (i = 0; i < HPTES_PER_GROUP; i++) {
@@ -163,7 +183,7 @@ static long native_hpte_insert(unsigned long hpte_group, unsigned long va,
         if (i == HPTES_PER_GROUP)
                 return -1;
 
-        hpte_v = hpte_encode_v(va, psize, ssize) | vflags | HPTE_V_VALID;
+        hpte_v = hpte_encode_v(vpn, psize, ssize) | vflags | HPTE_V_VALID;
         hpte_r = hpte_encode_r(pa, psize) | rflags;
 
         if (!(vflags & HPTE_V_BOLTED)) {
@@ -225,17 +245,17 @@ static long native_hpte_remove(unsigned long hpte_group)
 }
 
 static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
-                                 unsigned long va, int psize, int ssize,
+                                 unsigned long vpn, int psize, int ssize,
                                  int local)
 {
         struct hash_pte *hptep = htab_address + slot;
         unsigned long hpte_v, want_v;
         int ret = 0;
 
-        want_v = hpte_encode_v(va, psize, ssize);
+        want_v = hpte_encode_v(vpn, psize, ssize);
 
-        DBG_LOW("    update(va=%016lx, avpnv=%016lx, hash=%016lx, newpp=%x)",
-                va, want_v & HPTE_V_AVPN, slot, newpp);
+        DBG_LOW("    update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
+                vpn, want_v & HPTE_V_AVPN, slot, newpp);
 
         native_lock_hpte(hptep);
 
@@ -254,12 +274,12 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
         native_unlock_hpte(hptep);
 
         /* Ensure it is out of the tlb too. */
-        tlbie(va, psize, ssize, local);
+        tlbie(vpn, psize, ssize, local);
 
         return ret;
 }
 
-static long native_hpte_find(unsigned long va, int psize, int ssize)
+static long native_hpte_find(unsigned long vpn, int psize, int ssize)
 {
         struct hash_pte *hptep;
         unsigned long hash;
@@ -267,8 +287,8 @@ static long native_hpte_find(unsigned long va, int psize, int ssize)
         long slot;
         unsigned long want_v, hpte_v;
 
-        hash = hpt_hash(va, mmu_psize_defs[psize].shift, ssize);
-        want_v = hpte_encode_v(va, psize, ssize);
+        hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize);
+        want_v = hpte_encode_v(vpn, psize, ssize);
 
         /* Bolted mappings are only ever in the primary group */
         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
@@ -295,14 +315,15 @@ static long native_hpte_find(unsigned long va, int psize, int ssize)
 static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
                                        int psize, int ssize)
 {
-        unsigned long vsid, va;
+        unsigned long vpn;
+        unsigned long vsid;
         long slot;
         struct hash_pte *hptep;
 
         vsid = get_kernel_vsid(ea, ssize);
-        va = hpt_va(ea, vsid, ssize);
+        vpn = hpt_vpn(ea, vsid, ssize);
 
-        slot = native_hpte_find(va, psize, ssize);
+        slot = native_hpte_find(vpn, psize, ssize);
         if (slot == -1)
                 panic("could not find page to bolt\n");
         hptep = htab_address + slot;
@@ -312,10 +333,10 @@ static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
                 (newpp & (HPTE_R_PP | HPTE_R_N));
 
         /* Ensure it is out of the tlb too. */
-        tlbie(va, psize, ssize, 0);
+        tlbie(vpn, psize, ssize, 0);
 }
 
-static void native_hpte_invalidate(unsigned long slot, unsigned long va,
+static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,
                                    int psize, int ssize, int local)
 {
         struct hash_pte *hptep = htab_address + slot;
@@ -325,9 +346,9 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long va,
 
         local_irq_save(flags);
 
-        DBG_LOW("    invalidate(va=%016lx, hash: %x)\n", va, slot);
+        DBG_LOW("    invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot);
 
-        want_v = hpte_encode_v(va, psize, ssize);
+        want_v = hpte_encode_v(vpn, psize, ssize);
         native_lock_hpte(hptep);
         hpte_v = hptep->v;
 
@@ -339,7 +360,7 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long va,
                 hptep->v = 0;
 
         /* Invalidate the TLB */
-        tlbie(va, psize, ssize, local);
+        tlbie(vpn, psize, ssize, local);
 
         local_irq_restore(flags);
 }
@@ -349,11 +370,12 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long va,
 #define LP_MASK(i)      ((0xFF >> (i)) << LP_SHIFT)
 
 static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
-                        int *psize, int *ssize, unsigned long *va)
+                        int *psize, int *ssize, unsigned long *vpn)
 {
+        unsigned long avpn, pteg, vpi;
         unsigned long hpte_r = hpte->r;
         unsigned long hpte_v = hpte->v;
-        unsigned long avpn;
+        unsigned long vsid, seg_off;
         int i, size, shift, penc;
 
         if (!(hpte_v & HPTE_V_LARGE))
@@ -380,32 +402,38 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
         }
 
         /* This works for all page sizes, and for 256M and 1T segments */
+        *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
         shift = mmu_psize_defs[size].shift;
-        avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm) << 23;
-
-        if (shift < 23) {
-                unsigned long vpi, vsid, pteg;
 
-                pteg = slot / HPTES_PER_GROUP;
-                if (hpte_v & HPTE_V_SECONDARY)
-                        pteg = ~pteg;
-                switch (hpte_v >> HPTE_V_SSIZE_SHIFT) {
-                case MMU_SEGSIZE_256M:
-                        vpi = ((avpn >> 28) ^ pteg) & htab_hash_mask;
-                        break;
-                case MMU_SEGSIZE_1T:
-                        vsid = avpn >> 40;
+        avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm);
+        pteg = slot / HPTES_PER_GROUP;
+        if (hpte_v & HPTE_V_SECONDARY)
+                pteg = ~pteg;
+
+        switch (*ssize) {
+        case MMU_SEGSIZE_256M:
+                /* We only have 28 - 23 bits of seg_off in avpn */
+                seg_off = (avpn & 0x1f) << 23;
+                vsid    =  avpn >> 5;
+                /* We can find more bits from the pteg value */
+                if (shift < 23) {
+                        vpi = (vsid ^ pteg) & htab_hash_mask;
+                        seg_off |= vpi << shift;
+                }
+                *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT;
+        case MMU_SEGSIZE_1T:
+                /* We only have 40 - 23 bits of seg_off in avpn */
+                seg_off = (avpn & 0x1ffff) << 23;
+                vsid    = avpn >> 17;
+                if (shift < 23) {
                         vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
-                        break;
-                default:
-                        avpn = vpi = size = 0;
+                        seg_off |= vpi << shift;
                 }
-                avpn |= (vpi << mmu_psize_defs[size].shift);
+                *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT;
+        default:
+                *vpn = size = 0;
         }
-
-        *va = avpn;
         *psize = size;
-        *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
 }
 
 /*
@@ -418,9 +446,10 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
  */
 static void native_hpte_clear(void)
 {
+        unsigned long vpn = 0;
         unsigned long slot, slots, flags;
         struct hash_pte *hptep = htab_address;
-        unsigned long hpte_v, va;
+        unsigned long hpte_v;
         unsigned long pteg_count;
         int psize, ssize;
 
@@ -448,9 +477,9 @@ static void native_hpte_clear(void)
                  * already hold the native_tlbie_lock.
                  */
                 if (hpte_v & HPTE_V_VALID) {
-                        hpte_decode(hptep, slot, &psize, &ssize, &va);
+                        hpte_decode(hptep, slot, &psize, &ssize, &vpn);
                         hptep->v = 0;
-                        __tlbie(va, psize, ssize);
+                        __tlbie(vpn, psize, ssize);
                 }
         }
 
@@ -465,7 +494,8 @@ static void native_hpte_clear(void)
  */
 static void native_flush_hash_range(unsigned long number, int local)
 {
-        unsigned long va, hash, index, hidx, shift, slot;
+        unsigned long vpn;
+        unsigned long hash, index, hidx, shift, slot;
         struct hash_pte *hptep;
         unsigned long hpte_v;
         unsigned long want_v;
@@ -479,18 +509,18 @@ static void native_flush_hash_range(unsigned long number, int local)
         local_irq_save(flags);
 
         for (i = 0; i < number; i++) {
-                va = batch->vaddr[i];
+                vpn = batch->vpn[i];
                 pte = batch->pte[i];
 
-                pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
-                        hash = hpt_hash(va, shift, ssize);
+                pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
+                        hash = hpt_hash(vpn, shift, ssize);
                         hidx = __rpte_to_hidx(pte, index);
                         if (hidx & _PTEIDX_SECONDARY)
                                 hash = ~hash;
                         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
                         slot += hidx & _PTEIDX_GROUP_IX;
                         hptep = htab_address + slot;
-                        want_v = hpte_encode_v(va, psize, ssize);
+                        want_v = hpte_encode_v(vpn, psize, ssize);
                         native_lock_hpte(hptep);
                         hpte_v = hptep->v;
                         if (!HPTE_V_COMPARE(hpte_v, want_v) ||
@@ -505,12 +535,12 @@ static void native_flush_hash_range(unsigned long number, int local)
             mmu_psize_defs[psize].tlbiel && local) {
                 asm volatile("ptesync":::"memory");
                 for (i = 0; i < number; i++) {
-                        va = batch->vaddr[i];
+                        vpn = batch->vpn[i];
                         pte = batch->pte[i];
 
-                        pte_iterate_hashed_subpages(pte, psize, va, index,
-                                                    shift) {
-                                __tlbiel(va, psize, ssize);
+                        pte_iterate_hashed_subpages(pte, psize,
+                                                    vpn, index, shift) {
+                                __tlbiel(vpn, psize, ssize);
                         } pte_iterate_hashed_end();
                 }
                 asm volatile("ptesync":::"memory");
@@ -522,12 +552,12 @@ static void native_flush_hash_range(unsigned long number, int local)
 
                 asm volatile("ptesync":::"memory");
                 for (i = 0; i < number; i++) {
-                        va = batch->vaddr[i];
+                        vpn = batch->vpn[i];
                         pte = batch->pte[i];
 
-                        pte_iterate_hashed_subpages(pte, psize, va, index,
-                                                    shift) {
-                                __tlbie(va, psize, ssize);
+                        pte_iterate_hashed_subpages(pte, psize,
+                                                    vpn, index, shift) {
+                                __tlbie(vpn, psize, ssize);
                         } pte_iterate_hashed_end();
                 }
                 asm volatile("eieio; tlbsync; ptesync":::"memory");
@@ -539,29 +569,6 @@ static void native_flush_hash_range(unsigned long number, int local)
         local_irq_restore(flags);
 }
 
-#ifdef CONFIG_PPC_PSERIES
-/* Disable TLB batching on nighthawk */
-static inline int tlb_batching_enabled(void)
-{
-        struct device_node *root = of_find_node_by_path("/");
-        int enabled = 1;
-
-        if (root) {
-                const char *model = of_get_property(root, "model", NULL);
-                if (model && !strcmp(model, "IBM,9076-N81"))
-                        enabled = 0;
-                of_node_put(root);
-        }
-
-        return enabled;
-}
-#else
-static inline int tlb_batching_enabled(void)
-{
-        return 1;
-}
-#endif
-
 void __init hpte_init_native(void)
 {
         ppc_md.hpte_invalidate  = native_hpte_invalidate;
@@ -570,6 +577,5 @@ void __init hpte_init_native(void)
         ppc_md.hpte_insert      = native_hpte_insert;
         ppc_md.hpte_remove      = native_hpte_remove;
         ppc_md.hpte_clear_all   = native_hpte_clear;
-        if (tlb_batching_enabled())
-                ppc_md.flush_hash_range = native_flush_hash_range;
+        ppc_md.flush_hash_range = native_flush_hash_range;
 }
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 377e5cbedbbb..3a292be2e079 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -43,7 +43,6 @@
 #include <asm/uaccess.h>
 #include <asm/machdep.h>
 #include <asm/prom.h>
-#include <asm/abs_addr.h>
 #include <asm/tlbflush.h>
 #include <asm/io.h>
 #include <asm/eeh.h>
@@ -192,18 +191,18 @@ int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
              vaddr += step, paddr += step) {
                 unsigned long hash, hpteg;
                 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
-                unsigned long va = hpt_va(vaddr, vsid, ssize);
+                unsigned long vpn  = hpt_vpn(vaddr, vsid, ssize);
                 unsigned long tprot = prot;
 
                 /* Make kernel text executable */
                 if (overlaps_kernel_text(vaddr, vaddr + step))
                         tprot &= ~HPTE_R_N;
 
-                hash = hpt_hash(va, shift, ssize);
+                hash = hpt_hash(vpn, shift, ssize);
                 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
 
                 BUG_ON(!ppc_md.hpte_insert);
-                ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot,
+                ret = ppc_md.hpte_insert(hpteg, vpn, paddr, tprot,
                                          HPTE_V_BOLTED, psize, ssize);
 
                 if (ret < 0)
@@ -651,7 +650,7 @@ static void __init htab_initialize(void)
                 DBG("Hash table allocated at %lx, size: %lx\n", table,
                     htab_size_bytes);
 
-                htab_address = abs_to_virt(table);
+                htab_address = __va(table);
 
                 /* htab absolute addr + encoded htabsize */
                 _SDR1 = table + __ilog2(pteg_count) - 11;
@@ -804,16 +803,19 @@ unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
 #ifdef CONFIG_PPC_MM_SLICES
 unsigned int get_paca_psize(unsigned long addr)
 {
-        unsigned long index, slices;
+        u64 lpsizes;
+        unsigned char *hpsizes;
+        unsigned long index, mask_index;
 
         if (addr < SLICE_LOW_TOP) {
-                slices = get_paca()->context.low_slices_psize;
+                lpsizes = get_paca()->context.low_slices_psize;
                 index = GET_LOW_SLICE_INDEX(addr);
-        } else {
-                slices = get_paca()->context.high_slices_psize;
-                index = GET_HIGH_SLICE_INDEX(addr);
+                return (lpsizes >> (index * 4)) & 0xF;
         }
-        return (slices >> (index * 4)) & 0xF;
+        hpsizes = get_paca()->context.high_slices_psize;
+        index = GET_HIGH_SLICE_INDEX(addr);
+        mask_index = index & 0x1;
+        return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
 }
 
 #else
@@ -1153,21 +1155,21 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
  *          do not forget to update the assembly call site !
  */
-void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
+void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
                      int local)
 {
         unsigned long hash, index, shift, hidx, slot;
 
-        DBG_LOW("flush_hash_page(va=%016lx)\n", va);
-        pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
-                hash = hpt_hash(va, shift, ssize);
+        DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
+        pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
+                hash = hpt_hash(vpn, shift, ssize);
                 hidx = __rpte_to_hidx(pte, index);
                 if (hidx & _PTEIDX_SECONDARY)
                         hash = ~hash;
                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
                 slot += hidx & _PTEIDX_GROUP_IX;
                 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
-                ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
+                ppc_md.hpte_invalidate(slot, vpn, psize, ssize, local);
         } pte_iterate_hashed_end();
 }
 
@@ -1181,7 +1183,7 @@ void flush_hash_range(unsigned long number, int local)
                         &__get_cpu_var(ppc64_tlb_batch);
 
                 for (i = 0; i < number; i++)
-                        flush_hash_page(batch->vaddr[i], batch->pte[i],
+                        flush_hash_page(batch->vpn[i], batch->pte[i],
                                         batch->psize, batch->ssize, local);
         }
 }
@@ -1208,14 +1210,14 @@ static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
 {
         unsigned long hash, hpteg;
         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
-        unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
+        unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
         unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
         int ret;
 
-        hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
+        hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
         hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
 
-        ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
+        ret = ppc_md.hpte_insert(hpteg, vpn, __pa(vaddr),
                                  mode, HPTE_V_BOLTED,
                                  mmu_linear_psize, mmu_kernel_ssize);
         BUG_ON (ret < 0);
@@ -1229,9 +1231,9 @@ static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
 {
         unsigned long hash, hidx, slot;
         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
-        unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
+        unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
 
-        hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
+        hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
         spin_lock(&linear_map_hash_lock);
         BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
         hidx = linear_map_hash_slots[lmi] & 0x7f;
@@ -1241,7 +1243,7 @@ static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
                 hash = ~hash;
         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
         slot += hidx & _PTEIDX_GROUP_IX;
-        ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
+        ppc_md.hpte_invalidate(slot, vpn, mmu_linear_psize, mmu_kernel_ssize, 0);
 }
 
 void kernel_map_pages(struct page *page, int numpages, int enable)
diff --git a/arch/powerpc/mm/hugetlbpage-hash64.c b/arch/powerpc/mm/hugetlbpage-hash64.c
index cc5c273086cf..cecad348f604 100644
--- a/arch/powerpc/mm/hugetlbpage-hash64.c
+++ b/arch/powerpc/mm/hugetlbpage-hash64.c
@@ -18,14 +18,15 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
                      pte_t *ptep, unsigned long trap, int local, int ssize,
                      unsigned int shift, unsigned int mmu_psize)
 {
+        unsigned long vpn;
         unsigned long old_pte, new_pte;
-        unsigned long va, rflags, pa, sz;
+        unsigned long rflags, pa, sz;
         long slot;
 
         BUG_ON(shift != mmu_psize_defs[mmu_psize].shift);
 
         /* Search the Linux page table for a match with va */
-        va = hpt_va(ea, vsid, ssize);
+        vpn = hpt_vpn(ea, vsid, ssize);
 
         /* At this point, we have a pte (old_pte) which can be used to build
          * or update an HPTE. There are 2 cases:
@@ -69,19 +70,19 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
                 /* There MIGHT be an HPTE for this pte */
                 unsigned long hash, slot;
 
-                hash = hpt_hash(va, shift, ssize);
+                hash = hpt_hash(vpn, shift, ssize);
                 if (old_pte & _PAGE_F_SECOND)
                         hash = ~hash;
                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
                 slot += (old_pte & _PAGE_F_GIX) >> 12;
 
-                if (ppc_md.hpte_updatepp(slot, rflags, va, mmu_psize,
+                if (ppc_md.hpte_updatepp(slot, rflags, vpn, mmu_psize,
                                          ssize, local) == -1)
                         old_pte &= ~_PAGE_HPTEFLAGS;
         }
 
         if (likely(!(old_pte & _PAGE_HASHPTE))) {
-                unsigned long hash = hpt_hash(va, shift, ssize);
+                unsigned long hash = hpt_hash(vpn, shift, ssize);
                 unsigned long hpte_group;
 
                 pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT;
@@ -101,14 +102,14 @@ repeat:
                                       _PAGE_COHERENT | _PAGE_GUARDED));
 
                 /* Insert into the hash table, primary slot */
-                slot = ppc_md.hpte_insert(hpte_group, va, pa, rflags, 0,
+                slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, 0,
                                           mmu_psize, ssize);
 
                 /* Primary is full, try the secondary */
                 if (unlikely(slot == -1)) {
                         hpte_group = ((~hash & htab_hash_mask) *
                                       HPTES_PER_GROUP) & ~0x7UL;
-                        slot = ppc_md.hpte_insert(hpte_group, va, pa, rflags,
+                        slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags,
                                                   HPTE_V_SECONDARY,
                                                   mmu_psize, ssize);
                         if (slot == -1) {
diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
index 620b7acd2fdf..95a45293e5ac 100644
--- a/arch/powerpc/mm/init_64.c
+++ b/arch/powerpc/mm/init_64.c
@@ -62,7 +62,6 @@
 #include <asm/cputable.h>
 #include <asm/sections.h>
 #include <asm/iommu.h>
-#include <asm/abs_addr.h>
 #include <asm/vdso.h>
 
 #include "mmu_decl.h"
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index fbdad0e3929a..0dba5066c22a 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -62,7 +62,7 @@
 
 int init_bootmem_done;
 int mem_init_done;
-phys_addr_t memory_limit;
+unsigned long long memory_limit;
 
 #ifdef CONFIG_HIGHMEM
 pte_t *kmap_pte;
@@ -300,8 +300,7 @@ void __init mem_init(void)
         unsigned long reservedpages = 0, codesize, initsize, datasize, bsssize;
 
 #ifdef CONFIG_SWIOTLB
-        if (ppc_swiotlb_enable)
-                swiotlb_init(1);
+        swiotlb_init(0);
 #endif
 
         num_physpages = memblock_phys_mem_size() >> PAGE_SHIFT;
diff --git a/arch/powerpc/mm/mmu_context_hash64.c b/arch/powerpc/mm/mmu_context_hash64.c
index 40677aa0190e..40bc5b0ace54 100644
--- a/arch/powerpc/mm/mmu_context_hash64.c
+++ b/arch/powerpc/mm/mmu_context_hash64.c
@@ -30,11 +30,13 @@ static DEFINE_SPINLOCK(mmu_context_lock);
 static DEFINE_IDA(mmu_context_ida);
 
 /*
- * The proto-VSID space has 2^35 - 1 segments available for user mappings.
- * Each segment contains 2^28 bytes.  Each context maps 2^44 bytes,
- * so we can support 2^19-1 contexts (19 == 35 + 28 - 44).
+ * 256MB segment
+ * The proto-VSID space has 2^(CONTEX_BITS + USER_ESID_BITS) - 1 segments
+ * available for user mappings. Each segment contains 2^28 bytes. Each
+ * context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts
+ * (19 == 37 + 28 - 46).
  */
-#define MAX_CONTEXT     ((1UL << 19) - 1)
+#define MAX_CONTEXT     ((1UL << CONTEXT_BITS) - 1)
 
 int __init_new_context(void)
 {
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 249a0631c4db..e212a271c7a4 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -51,13 +51,22 @@
 #include <asm/processor.h>
 #include <asm/cputable.h>
 #include <asm/sections.h>
-#include <asm/abs_addr.h>
 #include <asm/firmware.h>
 
 #include "mmu_decl.h"
 
-unsigned long ioremap_bot = IOREMAP_BASE;
+/* Some sanity checking */
+#if TASK_SIZE_USER64 > PGTABLE_RANGE
+#error TASK_SIZE_USER64 exceeds pagetable range
+#endif
+
+#ifdef CONFIG_PPC_STD_MMU_64
+#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
+#error TASK_SIZE_USER64 exceeds user VSID range
+#endif
+#endif
 
+unsigned long ioremap_bot = IOREMAP_BASE;
 
 #ifdef CONFIG_PPC_MMU_NOHASH
 static void *early_alloc_pgtable(unsigned long size)
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index b9ee79ce2200..1a16ca227757 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -56,6 +56,12 @@ _GLOBAL(slb_allocate_realmode)
          */
 _GLOBAL(slb_miss_kernel_load_linear)
         li      r11,0
+        li      r9,0x1
+        /*
+         * for 1T we shift 12 bits more.  slb_finish_load_1T will do
+         * the necessary adjustment
+         */
+        rldimi  r10,r9,(CONTEXT_BITS + USER_ESID_BITS),0
 BEGIN_FTR_SECTION
         b       slb_finish_load
 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
@@ -85,6 +91,12 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
         _GLOBAL(slb_miss_kernel_load_io)
         li      r11,0
 6:
+        li      r9,0x1
+        /*
+         * for 1T we shift 12 bits more.  slb_finish_load_1T will do
+         * the necessary adjustment
+         */
+        rldimi  r10,r9,(CONTEXT_BITS + USER_ESID_BITS),0
 BEGIN_FTR_SECTION
         b       slb_finish_load
 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
@@ -108,17 +120,31 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
          * between 4k and 64k standard page size
          */
 #ifdef CONFIG_PPC_MM_SLICES
+        /* r10 have esid */
         cmpldi  r10,16
-
-        /* Get the slice index * 4 in r11 and matching slice size mask in r9 */
-        ld      r9,PACALOWSLICESPSIZE(r13)
-        sldi    r11,r10,2
+        /* below SLICE_LOW_TOP */
         blt     5f
-        ld      r9,PACAHIGHSLICEPSIZE(r13)
-        srdi    r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT - 2)
-        andi.   r11,r11,0x3c
+        /*
+         * Handle hpsizes,
+         * r9 is get_paca()->context.high_slices_psize[index], r11 is mask_index
+         */
+        srdi    r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT + 1) /* index */
+        addi    r9,r11,PACAHIGHSLICEPSIZE
+        lbzx    r9,r13,r9               /* r9 is hpsizes[r11] */
+        /* r11 = (r10 >> (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)) & 0x1 */
+        rldicl  r11,r10,(64 - (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)),63
+        b       6f
 
-5:      /* Extract the psize and multiply to get an array offset */
+5:
+        /*
+         * Handle lpsizes
+         * r9 is get_paca()->context.low_slices_psize, r11 is index
+         */
+        ld      r9,PACALOWSLICESPSIZE(r13)
+        mr      r11,r10
+6:
+        sldi    r11,r11,2  /* index * 4 */
+        /* Extract the psize and multiply to get an array offset */
         srd     r9,r9,r11
         andi.   r9,r9,0xf
         mulli   r9,r9,MMUPSIZEDEFSIZE
@@ -209,7 +235,11 @@ _GLOBAL(slb_allocate_user)
  */
 slb_finish_load:
         ASM_VSID_SCRAMBLE(r10,r9,256M)
-        rldimi  r11,r10,SLB_VSID_SHIFT,16       /* combine VSID and flags */
+        /*
+         * bits above VSID_BITS_256M need to be ignored from r10
+         * also combine VSID and flags
+         */
+        rldimi  r11,r10,SLB_VSID_SHIFT,(64 - (SLB_VSID_SHIFT + VSID_BITS_256M))
 
         /* r3 = EA, r11 = VSID data */
         /*
@@ -252,10 +282,10 @@ _GLOBAL(slb_compare_rr_to_size)
         bge     1f
 
         /* still room in the slb cache */
-        sldi    r11,r3,1                /* r11 = offset * sizeof(u16) */
-        rldicl  r10,r10,36,28           /* get low 16 bits of the ESID */
-        add     r11,r11,r13             /* r11 = (u16 *)paca + offset */
-        sth     r10,PACASLBCACHE(r11)   /* paca->slb_cache[offset] = esid */
+        sldi    r11,r3,2                /* r11 = offset * sizeof(u32) */
+        srdi    r10,r10,28              /* get the 36 bits of the ESID */
+        add     r11,r11,r13             /* r11 = (u32 *)paca + offset */
+        stw     r10,PACASLBCACHE(r11)   /* paca->slb_cache[offset] = esid */
         addi    r3,r3,1                 /* offset++ */
         b       2f
 1:                                      /* offset >= SLB_CACHE_ENTRIES */
@@ -273,7 +303,11 @@ _GLOBAL(slb_compare_rr_to_size)
 slb_finish_load_1T:
         srdi    r10,r10,40-28           /* get 1T ESID */
         ASM_VSID_SCRAMBLE(r10,r9,1T)
-        rldimi  r11,r10,SLB_VSID_SHIFT_1T,16    /* combine VSID and flags */
+        /*
+         * bits above VSID_BITS_1T need to be ignored from r10
+         * also combine VSID and flags
+         */
+        rldimi  r11,r10,SLB_VSID_SHIFT_1T,(64 - (SLB_VSID_SHIFT_1T + VSID_BITS_1T))
         li      r10,MMU_SEGSIZE_1T
         rldimi  r11,r10,SLB_VSID_SSIZE_SHIFT,0  /* insert segment size */
 
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
index 73709f7ce92c..5829d2a950d4 100644
--- a/arch/powerpc/mm/slice.c
+++ b/arch/powerpc/mm/slice.c
@@ -34,6 +34,11 @@
 #include <asm/mmu.h>
 #include <asm/spu.h>
 
+/* some sanity checks */
+#if (PGTABLE_RANGE >> 43) > SLICE_MASK_SIZE
+#error PGTABLE_RANGE exceeds slice_mask high_slices size
+#endif
+
 static DEFINE_SPINLOCK(slice_convert_lock);
 
 
@@ -42,7 +47,7 @@ int _slice_debug = 1;
 
 static void slice_print_mask(const char *label, struct slice_mask mask)
 {
-        char    *p, buf[16 + 3 + 16 + 1];
+        char    *p, buf[16 + 3 + 64 + 1];
         int     i;
 
         if (!_slice_debug)
@@ -54,7 +59,7 @@ static void slice_print_mask(const char *label, struct slice_mask mask)
         *(p++) = '-';
         *(p++) = ' ';
         for (i = 0; i < SLICE_NUM_HIGH; i++)
-                *(p++) = (mask.high_slices & (1 << i)) ? '1' : '0';
+                *(p++) = (mask.high_slices & (1ul << i)) ? '1' : '0';
         *(p++) = 0;
 
         printk(KERN_DEBUG "%s:%s\n", label, buf);
@@ -84,8 +89,8 @@ static struct slice_mask slice_range_to_mask(unsigned long start,
         }
 
         if ((start + len) > SLICE_LOW_TOP)
-                ret.high_slices = (1u << (GET_HIGH_SLICE_INDEX(end) + 1))
-                        - (1u << GET_HIGH_SLICE_INDEX(start));
+                ret.high_slices = (1ul << (GET_HIGH_SLICE_INDEX(end) + 1))
+                        - (1ul << GET_HIGH_SLICE_INDEX(start));
 
         return ret;
 }
@@ -135,26 +140,31 @@ static struct slice_mask slice_mask_for_free(struct mm_struct *mm)
 
         for (i = 0; i < SLICE_NUM_HIGH; i++)
                 if (!slice_high_has_vma(mm, i))
-                        ret.high_slices |= 1u << i;
+                        ret.high_slices |= 1ul << i;
 
         return ret;
 }
 
 static struct slice_mask slice_mask_for_size(struct mm_struct *mm, int psize)
 {
+        unsigned char *hpsizes;
+        int index, mask_index;
         struct slice_mask ret = { 0, 0 };
         unsigned long i;
-        u64 psizes;
+        u64 lpsizes;
 
-        psizes = mm->context.low_slices_psize;
+        lpsizes = mm->context.low_slices_psize;
         for (i = 0; i < SLICE_NUM_LOW; i++)
-                if (((psizes >> (i * 4)) & 0xf) == psize)
+                if (((lpsizes >> (i * 4)) & 0xf) == psize)
                         ret.low_slices |= 1u << i;
 
-        psizes = mm->context.high_slices_psize;
-        for (i = 0; i < SLICE_NUM_HIGH; i++)
-                if (((psizes >> (i * 4)) & 0xf) == psize)
-                        ret.high_slices |= 1u << i;
+        hpsizes = mm->context.high_slices_psize;
+        for (i = 0; i < SLICE_NUM_HIGH; i++) {
+                mask_index = i & 0x1;
+                index = i >> 1;
+                if (((hpsizes[index] >> (mask_index * 4)) & 0xf) == psize)
+                        ret.high_slices |= 1ul << i;
+        }
 
         return ret;
 }
@@ -183,8 +193,10 @@ static void slice_flush_segments(void *parm)
 
 static void slice_convert(struct mm_struct *mm, struct slice_mask mask, int psize)
 {
+        int index, mask_index;
         /* Write the new slice psize bits */
-        u64 lpsizes, hpsizes;
+        unsigned char *hpsizes;
+        u64 lpsizes;
         unsigned long i, flags;
 
         slice_dbg("slice_convert(mm=%p, psize=%d)\n", mm, psize);
@@ -201,14 +213,18 @@ static void slice_convert(struct mm_struct *mm, struct slice_mask mask, int psiz
                         lpsizes = (lpsizes & ~(0xful << (i * 4))) |
                                 (((unsigned long)psize) << (i * 4));
 
-        hpsizes = mm->context.high_slices_psize;
-        for (i = 0; i < SLICE_NUM_HIGH; i++)
-                if (mask.high_slices & (1u << i))
-                        hpsizes = (hpsizes & ~(0xful << (i * 4))) |
-                                (((unsigned long)psize) << (i * 4));
-
+        /* Assign the value back */
         mm->context.low_slices_psize = lpsizes;
-        mm->context.high_slices_psize = hpsizes;
+
+        hpsizes = mm->context.high_slices_psize;
+        for (i = 0; i < SLICE_NUM_HIGH; i++) {
+                mask_index = i & 0x1;
+                index = i >> 1;
+                if (mask.high_slices & (1ul << i))
+                        hpsizes[index] = (hpsizes[index] &
+                                          ~(0xf << (mask_index * 4))) |
+                                (((unsigned long)psize) << (mask_index * 4));
+        }
 
         slice_dbg(" lsps=%lx, hsps=%lx\n",
                   mm->context.low_slices_psize,
@@ -587,18 +603,19 @@ unsigned long arch_get_unmapped_area_topdown(struct file *filp,
 
 unsigned int get_slice_psize(struct mm_struct *mm, unsigned long addr)
 {
-        u64 psizes;
-        int index;
+        unsigned char *hpsizes;
+        int index, mask_index;
 
         if (addr < SLICE_LOW_TOP) {
-                psizes = mm->context.low_slices_psize;
+                u64 lpsizes;
+                lpsizes = mm->context.low_slices_psize;
                 index = GET_LOW_SLICE_INDEX(addr);
-        } else {
-                psizes = mm->context.high_slices_psize;
-                index = GET_HIGH_SLICE_INDEX(addr);
+                return (lpsizes >> (index * 4)) & 0xf;
         }
-
-        return (psizes >> (index * 4)) & 0xf;
+        hpsizes = mm->context.high_slices_psize;
+        index = GET_HIGH_SLICE_INDEX(addr);
+        mask_index = index & 0x1;
+        return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xf;
 }
 EXPORT_SYMBOL_GPL(get_slice_psize);
 
@@ -618,7 +635,9 @@ EXPORT_SYMBOL_GPL(get_slice_psize);
  */
 void slice_set_user_psize(struct mm_struct *mm, unsigned int psize)
 {
-        unsigned long flags, lpsizes, hpsizes;
+        int index, mask_index;
+        unsigned char *hpsizes;
+        unsigned long flags, lpsizes;
         unsigned int old_psize;
         int i;
 
@@ -639,15 +658,21 @@ void slice_set_user_psize(struct mm_struct *mm, unsigned int psize)
                 if (((lpsizes >> (i * 4)) & 0xf) == old_psize)
                         lpsizes = (lpsizes & ~(0xful << (i * 4))) |
                                 (((unsigned long)psize) << (i * 4));
+        /* Assign the value back */
+        mm->context.low_slices_psize = lpsizes;
 
         hpsizes = mm->context.high_slices_psize;
-        for (i = 0; i < SLICE_NUM_HIGH; i++)
-                if (((hpsizes >> (i * 4)) & 0xf) == old_psize)
-                        hpsizes = (hpsizes & ~(0xful << (i * 4))) |
-                                (((unsigned long)psize) << (i * 4));
+        for (i = 0; i < SLICE_NUM_HIGH; i++) {
+                mask_index = i & 0x1;
+                index = i >> 1;
+                if (((hpsizes[index] >> (mask_index * 4)) & 0xf) == old_psize)
+                        hpsizes[index] = (hpsizes[index] &
+                                          ~(0xf << (mask_index * 4))) |
+                                (((unsigned long)psize) << (mask_index * 4));
+        }
+
+
 
-        mm->context.low_slices_psize = lpsizes;
-        mm->context.high_slices_psize = hpsizes;
 
         slice_dbg(" lsps=%lx, hsps=%lx\n",
                   mm->context.low_slices_psize,
@@ -660,18 +685,27 @@ void slice_set_user_psize(struct mm_struct *mm, unsigned int psize)
 void slice_set_psize(struct mm_struct *mm, unsigned long address,
                      unsigned int psize)
 {
+        unsigned char *hpsizes;
         unsigned long i, flags;
-        u64 *p;
+        u64 *lpsizes;
 
         spin_lock_irqsave(&slice_convert_lock, flags);
         if (address < SLICE_LOW_TOP) {
                 i = GET_LOW_SLICE_INDEX(address);
-                p = &mm->context.low_slices_psize;
+                lpsizes = &mm->context.low_slices_psize;
+                *lpsizes = (*lpsizes & ~(0xful << (i * 4))) |
+                        ((unsigned long) psize << (i * 4));
         } else {
+                int index, mask_index;
                 i = GET_HIGH_SLICE_INDEX(address);
-                p = &mm->context.high_slices_psize;
+                hpsizes = mm->context.high_slices_psize;
+                mask_index = i & 0x1;
+                index = i >> 1;
+                hpsizes[index] = (hpsizes[index] &
+                                  ~(0xf << (mask_index * 4))) |
+                        (((unsigned long)psize) << (mask_index * 4));
         }
-        *p = (*p & ~(0xful << (i * 4))) | ((unsigned long) psize << (i * 4));
+
         spin_unlock_irqrestore(&slice_convert_lock, flags);
 
 #ifdef CONFIG_SPU_BASE
diff --git a/arch/powerpc/mm/stab.c b/arch/powerpc/mm/stab.c
index 9106ebb118f5..3f8efa6f2997 100644
--- a/arch/powerpc/mm/stab.c
+++ b/arch/powerpc/mm/stab.c
@@ -20,7 +20,6 @@
 #include <asm/paca.h>
 #include <asm/cputable.h>
 #include <asm/prom.h>
-#include <asm/abs_addr.h>
 
 struct stab_entry {
         unsigned long esid_data;
@@ -257,7 +256,7 @@ void __init stabs_alloc(void)
                 memset((void *)newstab, 0, HW_PAGE_SIZE);
 
                 paca[cpu].stab_addr = newstab;
-                paca[cpu].stab_real = virt_to_abs(newstab);
+                paca[cpu].stab_real = __pa(newstab);
                 printk(KERN_INFO "Segment table for CPU %d at 0x%llx "
                        "virtual, 0x%llx absolute\n",
                        cpu, paca[cpu].stab_addr, paca[cpu].stab_real);
diff --git a/arch/powerpc/mm/subpage-prot.c b/arch/powerpc/mm/subpage-prot.c
index e4f8f1fc81a5..7c415ddde948 100644
--- a/arch/powerpc/mm/subpage-prot.c
+++ b/arch/powerpc/mm/subpage-prot.c
@@ -95,7 +95,8 @@ static void subpage_prot_clear(unsigned long addr, unsigned long len)
         struct mm_struct *mm = current->mm;
         struct subpage_prot_table *spt = &mm->context.spt;
         u32 **spm, *spp;
-        int i, nw;
+        unsigned long i;
+        size_t nw;
         unsigned long next, limit;
 
         down_write(&mm->mmap_sem);
@@ -144,7 +145,8 @@ long sys_subpage_prot(unsigned long addr, unsigned long len, u32 __user *map)
         struct mm_struct *mm = current->mm;
         struct subpage_prot_table *spt = &mm->context.spt;
         u32 **spm, *spp;
-        int i, nw;
+        unsigned long i;
+        size_t nw;
         unsigned long next, limit;
         int err;
 
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index 31f18207970b..ae758b3ff72c 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -42,8 +42,9 @@ DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
 void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
                      pte_t *ptep, unsigned long pte, int huge)
 {
+        unsigned long vpn;
         struct ppc64_tlb_batch *batch = &get_cpu_var(ppc64_tlb_batch);
-        unsigned long vsid, vaddr;
+        unsigned long vsid;
         unsigned int psize;
         int ssize;
         real_pte_t rpte;
@@ -86,7 +87,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
                 vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
                 ssize = mmu_kernel_ssize;
         }
-        vaddr = hpt_va(addr, vsid, ssize);
+        vpn = hpt_vpn(addr, vsid, ssize);
         rpte = __real_pte(__pte(pte), ptep);
 
         /*
@@ -96,7 +97,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
          * and decide to use local invalidates instead...
          */
         if (!batch->active) {
-                flush_hash_page(vaddr, rpte, psize, ssize, 0);
+                flush_hash_page(vpn, rpte, psize, ssize, 0);
                 put_cpu_var(ppc64_tlb_batch);
                 return;
         }
@@ -122,7 +123,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
                 batch->ssize = ssize;
         }
         batch->pte[i] = rpte;
-        batch->vaddr[i] = vaddr;
+        batch->vpn[i] = vpn;
         batch->index = ++i;
         if (i >= PPC64_TLB_BATCH_NR)
                 __flush_tlb_pending(batch);
@@ -146,7 +147,7 @@ void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
         if (cpumask_equal(mm_cpumask(batch->mm), tmp))
                 local = 1;
         if (i == 1)
-                flush_hash_page(batch->vaddr[0], batch->pte[0],
+                flush_hash_page(batch->vpn[0], batch->pte[0],
                                 batch->psize, batch->ssize, local);
         else
                 flush_hash_range(i, local);
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index f09d48e3268d..b4113bf86353 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -20,6 +20,8 @@
 #include <asm/pgtable.h>
 #include <asm/exception-64e.h>
 #include <asm/ppc-opcode.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_booke_hv_asm.h>
 
 #ifdef CONFIG_PPC_64K_PAGES
 #define VPTE_PMD_SHIFT  (PTE_INDEX_SIZE+1)
@@ -37,12 +39,18 @@
  *                                                                    *
  **********************************************************************/
 
-.macro tlb_prolog_bolted addr
-        mtspr   SPRN_SPRG_TLB_SCRATCH,r13
+.macro tlb_prolog_bolted intnum addr
+        mtspr   SPRN_SPRG_GEN_SCRATCH,r13
         mfspr   r13,SPRN_SPRG_PACA
         std     r10,PACA_EXTLB+EX_TLB_R10(r13)
         mfcr    r10
         std     r11,PACA_EXTLB+EX_TLB_R11(r13)
+#ifdef CONFIG_KVM_BOOKE_HV
+BEGIN_FTR_SECTION
+        mfspr   r11, SPRN_SRR1
+END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
+#endif
+        DO_KVM  \intnum, SPRN_SRR1
         std     r16,PACA_EXTLB+EX_TLB_R16(r13)
         mfspr   r16,\addr               /* get faulting address */
         std     r14,PACA_EXTLB+EX_TLB_R14(r13)
@@ -61,12 +69,12 @@
         ld      r15,PACA_EXTLB+EX_TLB_R15(r13)
         TLB_MISS_RESTORE_STATS_BOLTED
         ld      r16,PACA_EXTLB+EX_TLB_R16(r13)
-        mfspr   r13,SPRN_SPRG_TLB_SCRATCH
+        mfspr   r13,SPRN_SPRG_GEN_SCRATCH
 .endm
 
 /* Data TLB miss */
         START_EXCEPTION(data_tlb_miss_bolted)
-        tlb_prolog_bolted SPRN_DEAR
+        tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR
 
         /* We need _PAGE_PRESENT and  _PAGE_ACCESSED set */
 
@@ -214,7 +222,7 @@ itlb_miss_fault_bolted:
 
 /* Instruction TLB miss */
         START_EXCEPTION(instruction_tlb_miss_bolted)
-        tlb_prolog_bolted SPRN_SRR0
+        tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0
 
         rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
         srdi    r15,r16,60              /* get region */
diff --git a/arch/powerpc/oprofile/op_model_power4.c b/arch/powerpc/oprofile/op_model_power4.c
index 95ae77dec3f6..315f9495e9b2 100644
--- a/arch/powerpc/oprofile/op_model_power4.c
+++ b/arch/powerpc/oprofile/op_model_power4.c
@@ -21,6 +21,13 @@
 #include <asm/reg.h>
 
 #define dbg(args...)
+#define OPROFILE_PM_PMCSEL_MSK      0xffULL
+#define OPROFILE_PM_UNIT_SHIFT      60
+#define OPROFILE_PM_UNIT_MSK        0xfULL
+#define OPROFILE_MAX_PMC_NUM        3
+#define OPROFILE_PMSEL_FIELD_WIDTH  8
+#define OPROFILE_UNIT_FIELD_WIDTH   4
+#define MMCRA_SIAR_VALID_MASK       0x10000000ULL
 
 static unsigned long reset_value[OP_MAX_COUNTER];
 
@@ -31,6 +38,61 @@ static int use_slot_nums;
 static u32 mmcr0_val;
 static u64 mmcr1_val;
 static u64 mmcra_val;
+static u32 cntr_marked_events;
+
+static int power7_marked_instr_event(u64 mmcr1)
+{
+        u64 psel, unit;
+        int pmc, cntr_marked_events = 0;
+
+        /* Given the MMCR1 value, look at the field for each counter to
+         * determine if it is a marked event.  Code based on the function
+         * power7_marked_instr_event() in file arch/powerpc/perf/power7-pmu.c.
+         */
+        for (pmc = 0; pmc < 4; pmc++) {
+                psel = mmcr1 & (OPROFILE_PM_PMCSEL_MSK
+                                << (OPROFILE_MAX_PMC_NUM - pmc)
+                                * OPROFILE_MAX_PMC_NUM);
+                psel = (psel >> ((OPROFILE_MAX_PMC_NUM - pmc)
+                                 * OPROFILE_PMSEL_FIELD_WIDTH)) & ~1ULL;
+                unit = mmcr1 & (OPROFILE_PM_UNIT_MSK
+                                << (OPROFILE_PM_UNIT_SHIFT
+                                    - (pmc * OPROFILE_PMSEL_FIELD_WIDTH )));
+                unit = unit >> (OPROFILE_PM_UNIT_SHIFT
+                                - (pmc * OPROFILE_PMSEL_FIELD_WIDTH));
+
+                switch (psel >> 4) {
+                case 2:
+                        cntr_marked_events |= (pmc == 1 || pmc == 3) << pmc;
+                        break;
+                case 3:
+                        if (psel == 0x3c) {
+                                cntr_marked_events |= (pmc == 0) << pmc;
+                                break;
+                        }
+
+                        if (psel == 0x3e) {
+                                cntr_marked_events |= (pmc != 1) << pmc;
+                                break;
+                        }
+
+                        cntr_marked_events |= 1 << pmc;
+                        break;
+                case 4:
+                case 5:
+                        cntr_marked_events |= (unit == 0xd) << pmc;
+                        break;
+                case 6:
+                        if (psel == 0x64)
+                                cntr_marked_events |= (pmc >= 2) << pmc;
+                        break;
+                case 8:
+                        cntr_marked_events |= (unit == 0xd) << pmc;
+                        break;
+                }
+        }
+        return cntr_marked_events;
+}
 
 static int power4_reg_setup(struct op_counter_config *ctr,
                              struct op_system_config *sys,
@@ -47,6 +109,23 @@ static int power4_reg_setup(struct op_counter_config *ctr,
         mmcr1_val = sys->mmcr1;
         mmcra_val = sys->mmcra;
 
+        /* Power 7+ and newer architectures:
+         * Determine which counter events in the group (the group of events is
+         * specified by the bit settings in the MMCR1 register) are marked
+         * events for use in the interrupt handler.  Do the calculation once
+         * before OProfile starts.  Information is used in the interrupt
+         * handler.  Starting with Power 7+ we only record the sample for
+         * marked events if the SIAR valid bit is set.  For non marked events
+         * the sample is always recorded.
+         */
+        if (pvr_version_is(PVR_POWER7p))
+                cntr_marked_events = power7_marked_instr_event(mmcr1_val);
+        else
+                cntr_marked_events = 0; /* For older processors, set the bit map
+                                         * to zero so the sample will always be
+                                         * be recorded.
+                                         */
+
         for (i = 0; i < cur_cpu_spec->num_pmcs; ++i)
                 reset_value[i] = 0x80000000UL - ctr[i].count;
 
@@ -61,10 +140,10 @@ static int power4_reg_setup(struct op_counter_config *ctr,
         else
                 mmcr0_val |= MMCR0_PROBLEM_DISABLE;
 
-        if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p) ||
-            __is_processor(PV_970) || __is_processor(PV_970FX) ||
-            __is_processor(PV_970MP) || __is_processor(PV_970GX) ||
-            __is_processor(PV_POWER5) || __is_processor(PV_POWER5p))
+        if (pvr_version_is(PVR_POWER4) || pvr_version_is(PVR_POWER4p) ||
+            pvr_version_is(PVR_970) || pvr_version_is(PVR_970FX) ||
+            pvr_version_is(PVR_970MP) || pvr_version_is(PVR_970GX) ||
+            pvr_version_is(PVR_POWER5) || pvr_version_is(PVR_POWER5p))
                 use_slot_nums = 1;
 
         return 0;
@@ -84,9 +163,9 @@ extern void ppc_enable_pmcs(void);
  */
 static inline int mmcra_must_set_sample(void)
 {
-        if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p) ||
-            __is_processor(PV_970) || __is_processor(PV_970FX) ||
-            __is_processor(PV_970MP) || __is_processor(PV_970GX))
+        if (pvr_version_is(PVR_POWER4) || pvr_version_is(PVR_POWER4p) ||
+            pvr_version_is(PVR_970) || pvr_version_is(PVR_970FX) ||
+            pvr_version_is(PVR_970MP) || pvr_version_is(PVR_970GX))
                 return 1;
 
         return 0;
@@ -276,7 +355,7 @@ static bool pmc_overflow(unsigned long val)
          * PMCs because a user might set a period of less than 256 and we
          * don't want to mistakenly reset them.
          */
-        if (__is_processor(PV_POWER7) && ((0x80000000 - val) <= 256))
+        if (pvr_version_is(PVR_POWER7) && ((0x80000000 - val) <= 256))
                 return true;
 
         return false;
@@ -291,6 +370,7 @@ static void power4_handle_interrupt(struct pt_regs *regs,
         int i;
         unsigned int mmcr0;
         unsigned long mmcra;
+        bool siar_valid = false;
 
         mmcra = mfspr(SPRN_MMCRA);
 
@@ -300,11 +380,29 @@ static void power4_handle_interrupt(struct pt_regs *regs,
         /* set the PMM bit (see comment below) */
         mtmsrd(mfmsr() | MSR_PMM);
 
+        /* Check that the SIAR  valid bit in MMCRA is set to 1. */
+        if ((mmcra & MMCRA_SIAR_VALID_MASK) == MMCRA_SIAR_VALID_MASK)
+                siar_valid = true;
+
         for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
                 val = classic_ctr_read(i);
                 if (pmc_overflow(val)) {
                         if (oprofile_running && ctr[i].enabled) {
-                                oprofile_add_ext_sample(pc, regs, i, is_kernel);
+                                /* Power 7+ and newer architectures:
+                                 * If the event is a marked event, then only
+                                 * save the sample if the SIAR valid bit is
+                                 * set.  If the event is not marked, then
+                                 * always save the sample.
+                                 * Note, the Sample enable bit in the MMCRA
+                                 * register must be set to 1 if the group
+                                 * contains a marked event.
+                                 */
+                                if ((siar_valid &&
+                                     (cntr_marked_events & (1 << i)))
+                                    || !(cntr_marked_events & (1 << i)))
+                                        oprofile_add_ext_sample(pc, regs, i,
+                                                                is_kernel);
+
                                 classic_ctr_write(i, reset_value[i]);
                         } else {
                                 classic_ctr_write(i, 0);
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 7cd2dbd6e4c4..0db88f501f91 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -82,6 +82,11 @@ static inline int perf_intr_is_nmi(struct pt_regs *regs)
         return 0;
 }
 
+static inline int siar_valid(struct pt_regs *regs)
+{
+        return 1;
+}
+
 #endif /* CONFIG_PPC32 */
 
 /*
@@ -106,14 +111,20 @@ static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
  * If we're not doing instruction sampling, give them the SDAR
  * (sampled data address).  If we are doing instruction sampling, then
  * only give them the SDAR if it corresponds to the instruction
- * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC
- * bit in MMCRA.
+ * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC or
+ * the [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA.
  */
 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
 {
         unsigned long mmcra = regs->dsisr;
-        unsigned long sdsync = (ppmu->flags & PPMU_ALT_SIPR) ?
-                POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC;
+        unsigned long sdsync;
+
+        if (ppmu->flags & PPMU_SIAR_VALID)
+                sdsync = POWER7P_MMCRA_SDAR_VALID;
+        else if (ppmu->flags & PPMU_ALT_SIPR)
+                sdsync = POWER6_MMCRA_SDSYNC;
+        else
+                sdsync = MMCRA_SDSYNC;
 
         if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync))
                 *addrp = mfspr(SPRN_SDAR);
@@ -230,6 +241,24 @@ static inline int perf_intr_is_nmi(struct pt_regs *regs)
         return !regs->softe;
 }
 
+/*
+ * On processors like P7+ that have the SIAR-Valid bit, marked instructions
+ * must be sampled only if the SIAR-valid bit is set.
+ *
+ * For unmarked instructions and for processors that don't have the SIAR-Valid
+ * bit, assume that SIAR is valid.
+ */
+static inline int siar_valid(struct pt_regs *regs)
+{
+        unsigned long mmcra = regs->dsisr;
+        int marked = mmcra & MMCRA_SAMPLE_ENABLE;
+
+        if ((ppmu->flags & PPMU_SIAR_VALID) && marked)
+                return mmcra & POWER7P_MMCRA_SIAR_VALID;
+
+        return 1;
+}
+
 #endif /* CONFIG_PPC64 */
 
 static void perf_event_interrupt(struct pt_regs *regs);
@@ -1291,6 +1320,7 @@ struct pmu power_pmu = {
         .event_idx      = power_pmu_event_idx,
 };
 
+
 /*
  * A counter has overflowed; update its count and record
  * things if requested.  Note that interrupts are hard-disabled
@@ -1324,7 +1354,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
                         left += period;
                         if (left <= 0)
                                 left = period;
-                        record = 1;
+                        record = siar_valid(regs);
                         event->hw.last_period = event->hw.sample_period;
                 }
                 if (left < 0x80000000LL)
@@ -1374,8 +1404,10 @@ unsigned long perf_instruction_pointer(struct pt_regs *regs)
 {
         unsigned long use_siar = regs->result;
 
-        if (use_siar)
+        if (use_siar && siar_valid(regs))
                 return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
+        else if (use_siar)
+                return 0;               // no valid instruction pointer
         else
                 return regs->nip;
 }
@@ -1396,7 +1428,7 @@ static bool pmc_overflow(unsigned long val)
          * PMCs because a user might set a period of less than 256 and we
          * don't want to mistakenly reset them.
          */
-        if (__is_processor(PV_POWER7) && ((0x80000000 - val) <= 256))
+        if (pvr_version_is(PVR_POWER7) && ((0x80000000 - val) <= 256))
                 return true;
 
         return false;
diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c
index 1251e4d7e262..441af08edf43 100644
--- a/arch/powerpc/perf/power7-pmu.c
+++ b/arch/powerpc/perf/power7-pmu.c
@@ -373,6 +373,9 @@ static int __init init_power7_pmu(void)
             strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7"))
                 return -ENODEV;
 
+        if (pvr_version_is(PVR_POWER7p))
+                power7_pmu.flags |= PPMU_SIAR_VALID;
+
         return register_power_pmu(&power7_pmu);
 }
 
diff --git a/arch/powerpc/platforms/40x/ppc40x_simple.c b/arch/powerpc/platforms/40x/ppc40x_simple.c
index 97612068fae3..969dddcf3320 100644
--- a/arch/powerpc/platforms/40x/ppc40x_simple.c
+++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
@@ -50,7 +50,7 @@ machine_device_initcall(ppc40x_simple, ppc40x_device_probe);
  * Again, if your board needs to do things differently then create a
  * board.c file for it rather than adding it to this list.
  */
-static const char *board[] __initdata = {
+static const char * const board[] __initconst = {
         "amcc,acadia",
         "amcc,haleakala",
         "amcc,kilauea",
diff --git a/arch/powerpc/platforms/44x/currituck.c b/arch/powerpc/platforms/44x/currituck.c
index 9f6c33d63a42..6bd89a0e0dea 100644
--- a/arch/powerpc/platforms/44x/currituck.c
+++ b/arch/powerpc/platforms/44x/currituck.c
@@ -21,7 +21,6 @@
  */
 
 #include <linux/init.h>
-#include <linux/memblock.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/rtc.h>
@@ -159,13 +158,8 @@ static void __init ppc47x_setup_arch(void)
 
         /* No need to check the DMA config as we /know/ our windows are all of
          * RAM.  Lets hope that doesn't change */
-#ifdef CONFIG_SWIOTLB
-        if ((memblock_end_of_DRAM() - 1) > 0xffffffff) {
-                ppc_swiotlb_enable = 1;
-                set_pci_dma_ops(&swiotlb_dma_ops);
-                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
-        }
-#endif
+        swiotlb_detect_4g();
+
         ppc47x_smp_init();
 }
 
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index c16999802ecf..b62508b113db 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -2,6 +2,7 @@ config PPC_MPC512x
         bool "512x-based boards"
         depends on 6xx
         select FSL_SOC
+        select FB_FSL_DIU
         select IPIC
         select PPC_CLOCK
         select PPC_PCI_CHOICE
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
index 1d8700ff60b0..9f771e05457c 100644
--- a/arch/powerpc/platforms/512x/clock.c
+++ b/arch/powerpc/platforms/512x/clock.c
@@ -54,14 +54,16 @@ static DEFINE_MUTEX(clocks_mutex);
 static struct clk *mpc5121_clk_get(struct device *dev, const char *id)
 {
         struct clk *p, *clk = ERR_PTR(-ENOENT);
-        int dev_match = 0;
-        int id_match = 0;
+        int dev_match;
+        int id_match;
 
         if (dev == NULL || id == NULL)
                 return clk;
 
         mutex_lock(&clocks_mutex);
         list_for_each_entry(p, &clocks, node) {
+                dev_match = id_match = 0;
+
                 if (dev == p->dev)
                         dev_match++;
                 if (strcmp(id, p->name) == 0)
diff --git a/arch/powerpc/platforms/512x/mpc5121_generic.c b/arch/powerpc/platforms/512x/mpc5121_generic.c
index 926731f1ff01..ca1ca6669990 100644
--- a/arch/powerpc/platforms/512x/mpc5121_generic.c
+++ b/arch/powerpc/platforms/512x/mpc5121_generic.c
@@ -26,7 +26,7 @@
 /*
  * list of supported boards
  */
-static const char *board[] __initdata = {
+static const char * const board[] __initconst = {
         "prt,prtlvt",
         NULL
 };
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index cfe958e94e1e..1650e090ef3a 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -191,8 +191,6 @@ mpc512x_valid_monitor_port(enum fsl_diu_monitor_port port)
 
 static struct fsl_diu_shared_fb __attribute__ ((__aligned__(8))) diu_shared_fb;
 
-#if defined(CONFIG_FB_FSL_DIU) || \
-    defined(CONFIG_FB_FSL_DIU_MODULE)
 static inline void mpc512x_free_bootmem(struct page *page)
 {
         __ClearPageReserved(page);
@@ -220,7 +218,6 @@ void mpc512x_release_bootmem(void)
         }
         diu_ops.release_bootmem = NULL;
 }
-#endif
 
 /*
  * Check if DIU was pre-initialized. If so, perform steps
@@ -323,15 +320,12 @@ void __init mpc512x_setup_diu(void)
                 }
         }
 
-#if defined(CONFIG_FB_FSL_DIU) || \
-    defined(CONFIG_FB_FSL_DIU_MODULE)
         diu_ops.get_pixel_format        = mpc512x_get_pixel_format;
         diu_ops.set_gamma_table         = mpc512x_set_gamma_table;
         diu_ops.set_monitor_port        = mpc512x_set_monitor_port;
         diu_ops.set_pixel_clock         = mpc512x_set_pixel_clock;
         diu_ops.valid_monitor_port      = mpc512x_valid_monitor_port;
         diu_ops.release_bootmem         = mpc512x_release_bootmem;
-#endif
 }
 
 void __init mpc512x_init_IRQ(void)
diff --git a/arch/powerpc/platforms/52xx/lite5200.c b/arch/powerpc/platforms/52xx/lite5200.c
index 01ffa64d2aa7..448d862bcf3d 100644
--- a/arch/powerpc/platforms/52xx/lite5200.c
+++ b/arch/powerpc/platforms/52xx/lite5200.c
@@ -172,7 +172,7 @@ static void __init lite5200_setup_arch(void)
         mpc52xx_setup_pci();
 }
 
-static const char *board[] __initdata = {
+static const char * const board[] __initconst = {
         "fsl,lite5200",
         "fsl,lite5200b",
         NULL,
diff --git a/arch/powerpc/platforms/52xx/media5200.c b/arch/powerpc/platforms/52xx/media5200.c
index 17d91b7da315..070d315dd6cd 100644
--- a/arch/powerpc/platforms/52xx/media5200.c
+++ b/arch/powerpc/platforms/52xx/media5200.c
@@ -232,7 +232,7 @@ static void __init media5200_setup_arch(void)
 }
 
 /* list of the supported boards */
-static const char *board[] __initdata = {
+static const char * const board[] __initconst = {
         "fsl,media5200",
         NULL
 };
diff --git a/arch/powerpc/platforms/52xx/mpc5200_simple.c b/arch/powerpc/platforms/52xx/mpc5200_simple.c
index c0aa04068d69..9cf36020cf0d 100644
--- a/arch/powerpc/platforms/52xx/mpc5200_simple.c
+++ b/arch/powerpc/platforms/52xx/mpc5200_simple.c
@@ -52,6 +52,7 @@ static void __init mpc5200_simple_setup_arch(void)
 static const char *board[] __initdata = {
         "anonymous,a4m072",
         "anon,charon",
+        "ifm,o2d",
         "intercontrol,digsy-mtc",
         "manroland,mucmc52",
         "manroland,uc101",
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
index d61fb1c0c1a0..2351f9e0fb6f 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
@@ -170,7 +170,8 @@ static void mpc52xx_lpbfifo_kick(struct mpc52xx_lpbfifo_request *req)
         out_be32(lpbfifo.regs + LPBFIFO_REG_CONTROL, bit_fields);
 
         /* Kick it off */
-        out_8(lpbfifo.regs + LPBFIFO_REG_PACKET_SIZE, 0x01);
+        if (!lpbfifo.req->defer_xfer_start)
+                out_8(lpbfifo.regs + LPBFIFO_REG_PACKET_SIZE, 0x01);
         if (dma)
                 bcom_enable(lpbfifo.bcom_cur_task);
 }
@@ -421,6 +422,38 @@ int mpc52xx_lpbfifo_submit(struct mpc52xx_lpbfifo_request *req)
 }
 EXPORT_SYMBOL(mpc52xx_lpbfifo_submit);
 
+int mpc52xx_lpbfifo_start_xfer(struct mpc52xx_lpbfifo_request *req)
+{
+        unsigned long flags;
+
+        if (!lpbfifo.regs)
+                return -ENODEV;
+
+        spin_lock_irqsave(&lpbfifo.lock, flags);
+
+        /*
+         * If the req pointer is already set and a transfer was
+         * started on submit, then this transfer is in progress
+         */
+        if (lpbfifo.req && !lpbfifo.req->defer_xfer_start) {
+                spin_unlock_irqrestore(&lpbfifo.lock, flags);
+                return -EBUSY;
+        }
+
+        /*
+         * If the req was previously submitted but not
+         * started, start it now
+         */
+        if (lpbfifo.req && lpbfifo.req == req &&
+            lpbfifo.req->defer_xfer_start) {
+                out_8(lpbfifo.regs + LPBFIFO_REG_PACKET_SIZE, 0x01);
+        }
+
+        spin_unlock_irqrestore(&lpbfifo.lock, flags);
+        return 0;
+}
+EXPORT_SYMBOL(mpc52xx_lpbfifo_start_xfer);
+
 void mpc52xx_lpbfifo_abort(struct mpc52xx_lpbfifo_request *req)
 {
         unsigned long flags;
diff --git a/arch/powerpc/platforms/83xx/mpc837x_rdb.c b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
index 16c9c9cbbb7f..eca1f0960fff 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
@@ -60,7 +60,7 @@ static void __init mpc837x_rdb_setup_arch(void)
 
 machine_device_initcall(mpc837x_rdb, mpc83xx_declare_of_platform_devices);
 
-static const char *board[] __initdata = {
+static const char * const board[] __initconst = {
         "fsl,mpc8377rdb",
         "fsl,mpc8378rdb",
         "fsl,mpc8379rdb",
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 159c01e91463..02d02a09942d 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -104,6 +104,13 @@ config P1022_DS
         help
           This option enables support for the Freescale P1022DS reference board.
 
+config P1022_RDK
+        bool "Freescale / iVeia P1022 RDK"
+        select DEFAULT_UIMAGE
+        help
+          This option enables support for the Freescale / iVeia P1022RDK
+          reference board.
+
 config P1023_RDS
         bool "Freescale P1023 RDS"
         select DEFAULT_UIMAGE
@@ -254,6 +261,20 @@ config P5020_DS
         help
           This option enables support for the P5020 DS board
 
+config P5040_DS
+        bool "Freescale P5040 DS"
+        select DEFAULT_UIMAGE
+        select E500
+        select PPC_E500MC
+        select PHYS_64BIT
+        select SWIOTLB
+        select ARCH_REQUIRE_GPIOLIB
+        select GPIO_MPC8XXX
+        select HAS_RAPIDIO
+        select PPC_EPAPR_HV_PIC
+        help
+          This option enables support for the P5040 DS board
+
 config PPC_QEMU_E500
         bool "QEMU generic e500 platform"
         depends on EXPERIMENTAL
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 3dfe81175036..76f679cb04a0 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -15,11 +15,13 @@ obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
 obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
 obj-$(CONFIG_P1010_RDB)   += p1010rdb.o
 obj-$(CONFIG_P1022_DS)    += p1022_ds.o
+obj-$(CONFIG_P1022_RDK)   += p1022_rdk.o
 obj-$(CONFIG_P1023_RDS)   += p1023_rds.o
 obj-$(CONFIG_P2041_RDB)   += p2041_rdb.o corenet_ds.o
 obj-$(CONFIG_P3041_DS)    += p3041_ds.o corenet_ds.o
 obj-$(CONFIG_P4080_DS)    += p4080_ds.o corenet_ds.o
 obj-$(CONFIG_P5020_DS)    += p5020_ds.o corenet_ds.o
+obj-$(CONFIG_P5040_DS)    += p5040_ds.o corenet_ds.o
 obj-$(CONFIG_STX_GP3)     += stx_gp3.o
 obj-$(CONFIG_TQM85xx)     += tqm85xx.o
 obj-$(CONFIG_SBC8548)     += sbc8548.o
diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
index 67dac22b4363..d0861a0d8360 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -27,6 +27,16 @@ static struct of_device_id __initdata mpc85xx_common_ids[] = {
         { .compatible = "fsl,mpc8548-guts", },
         /* Probably unnecessary? */
         { .compatible = "gpio-leds", },
+        /* For all PCI controllers */
+        { .compatible = "fsl,mpc8540-pci", },
+        { .compatible = "fsl,mpc8548-pcie", },
+        { .compatible = "fsl,p1022-pcie", },
+        { .compatible = "fsl,p1010-pcie", },
+        { .compatible = "fsl,p1023-pcie", },
+        { .compatible = "fsl,p4080-pcie", },
+        { .compatible = "fsl,qoriq-pcie-v2.4", },
+        { .compatible = "fsl,qoriq-pcie-v2.3", },
+        { .compatible = "fsl,qoriq-pcie-v2.2", },
         {},
 };
 
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
index 925b02874233..ed69c9250717 100644
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -16,7 +16,6 @@
 #include <linux/kdev_t.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
-#include <linux/memblock.h>
 
 #include <asm/time.h>
 #include <asm/machdep.h>
@@ -52,37 +51,16 @@ void __init corenet_ds_pic_init(void)
  */
 void __init corenet_ds_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-        struct pci_controller *hose;
-#endif
-        dma_addr_t max = 0xffffffff;
-
         mpc85xx_smp_init();
 
-#ifdef CONFIG_PCI
-        for_each_node_by_type(np, "pci") {
-                if (of_device_is_compatible(np, "fsl,p4080-pcie") ||
-                    of_device_is_compatible(np, "fsl,qoriq-pcie-v2.2")) {
-                        fsl_add_bridge(np, 0);
-                        hose = pci_find_hose_for_OF_device(np);
-                        max = min(max, hose->dma_window_base_cur +
-                                        hose->dma_window_size);
-                }
-        }
-
-#ifdef CONFIG_PPC64
+#if defined(CONFIG_PCI) && defined(CONFIG_PPC64)
         pci_devs_phb_init();
 #endif
-#endif
 
-#ifdef CONFIG_SWIOTLB
-        if ((memblock_end_of_DRAM() - 1) > max) {
-                ppc_swiotlb_enable = 1;
-                set_pci_dma_ops(&swiotlb_dma_ops);
-                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
-        }
-#endif
+        fsl_pci_assign_primary();
+
+        swiotlb_detect_4g();
+
         pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
 }
 
@@ -99,6 +77,12 @@ static const struct of_device_id of_device_ids[] __devinitconst = {
         {
                 .compatible     = "fsl,qoriq-pcie-v2.2",
         },
+        {
+                .compatible     = "fsl,qoriq-pcie-v2.3",
+        },
+        {
+                .compatible     = "fsl,qoriq-pcie-v2.4",
+        },
         /* The following two are for the Freescale hypervisor */
         {
                 .name           = "hypervisor",
diff --git a/arch/powerpc/platforms/85xx/ge_imp3a.c b/arch/powerpc/platforms/85xx/ge_imp3a.c
index b6a728b0a8ca..e6285ae6f423 100644
--- a/arch/powerpc/platforms/85xx/ge_imp3a.c
+++ b/arch/powerpc/platforms/85xx/ge_imp3a.c
@@ -22,7 +22,6 @@
 #include <linux/seq_file.h>
 #include <linux/interrupt.h>
 #include <linux/of_platform.h>
-#include <linux/memblock.h>
 
 #include <asm/time.h>
 #include <asm/machdep.h>
@@ -84,53 +83,39 @@ void __init ge_imp3a_pic_init(void)
         of_node_put(cascade_node);
 }
 
-#ifdef CONFIG_PCI
-static int primary_phb_addr;
-#endif  /* CONFIG_PCI */
-
-/*
- * Setup the architecture
- */
-static void __init ge_imp3a_setup_arch(void)
+static void ge_imp3a_pci_assign_primary(void)
 {
-        struct device_node *regs;
 #ifdef CONFIG_PCI
         struct device_node *np;
-        struct pci_controller *hose;
-#endif
-        dma_addr_t max = 0xffffffff;
+        struct resource rsrc;
 
-        if (ppc_md.progress)
-                ppc_md.progress("ge_imp3a_setup_arch()", 0);
-
-#ifdef CONFIG_PCI
         for_each_node_by_type(np, "pci") {
                 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
                     of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
                     of_device_is_compatible(np, "fsl,p2020-pcie")) {
-                        struct resource rsrc;
                         of_address_to_resource(np, 0, &rsrc);
-                        if ((rsrc.start & 0xfffff) == primary_phb_addr)
-                                fsl_add_bridge(np, 1);
-                        else
-                                fsl_add_bridge(np, 0);
-
-                        hose = pci_find_hose_for_OF_device(np);
-                        max = min(max, hose->dma_window_base_cur +
-                                        hose->dma_window_size);
+                        if ((rsrc.start & 0xfffff) == 0x9000)
+                                fsl_pci_primary = np;
                 }
         }
 #endif
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init ge_imp3a_setup_arch(void)
+{
+        struct device_node *regs;
+
+        if (ppc_md.progress)
+                ppc_md.progress("ge_imp3a_setup_arch()", 0);
 
         mpc85xx_smp_init();
 
-#ifdef CONFIG_SWIOTLB
-        if ((memblock_end_of_DRAM() - 1) > max) {
-                ppc_swiotlb_enable = 1;
-                set_pci_dma_ops(&swiotlb_dma_ops);
-                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
-        }
-#endif
+        ge_imp3a_pci_assign_primary();
+
+        swiotlb_detect_4g();
 
         /* Remap basic board registers */
         regs = of_find_compatible_node(NULL, NULL, "ge,imp3a-fpga-regs");
@@ -215,17 +200,10 @@ static int __init ge_imp3a_probe(void)
 {
         unsigned long root = of_get_flat_dt_root();
 
-        if (of_flat_dt_is_compatible(root, "ge,IMP3A")) {
-#ifdef CONFIG_PCI
-                primary_phb_addr = 0x9000;
-#endif
-                return 1;
-        }
-
-        return 0;
+        return of_flat_dt_is_compatible(root, "ge,IMP3A");
 }
 
-machine_device_initcall(ge_imp3a, mpc85xx_common_publish_devices);
+machine_arch_initcall(ge_imp3a, mpc85xx_common_publish_devices);
 
 machine_arch_initcall(ge_imp3a, swiotlb_setup_bus_notifier);
 
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c b/arch/powerpc/platforms/85xx/mpc8536_ds.c
index 767c7cf18a9c..15ce4b55f117 100644
--- a/arch/powerpc/platforms/85xx/mpc8536_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c
@@ -17,7 +17,6 @@
 #include <linux/seq_file.h>
 #include <linux/interrupt.h>
 #include <linux/of_platform.h>
-#include <linux/memblock.h>
 
 #include <asm/time.h>
 #include <asm/machdep.h>
@@ -46,46 +45,17 @@ void __init mpc8536_ds_pic_init(void)
  */
 static void __init mpc8536_ds_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-        struct pci_controller *hose;
-#endif
-        dma_addr_t max = 0xffffffff;
-
         if (ppc_md.progress)
                 ppc_md.progress("mpc8536_ds_setup_arch()", 0);
 
-#ifdef CONFIG_PCI
-        for_each_node_by_type(np, "pci") {
-                if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
-                    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
-                        struct resource rsrc;
-                        of_address_to_resource(np, 0, &rsrc);
-                        if ((rsrc.start & 0xfffff) == 0x8000)
-                                fsl_add_bridge(np, 1);
-                        else
-                                fsl_add_bridge(np, 0);
-
-                        hose = pci_find_hose_for_OF_device(np);
-                        max = min(max, hose->dma_window_base_cur +
-                                        hose->dma_window_size);
-                }
-        }
-
-#endif
+        fsl_pci_assign_primary();
 
-#ifdef CONFIG_SWIOTLB
-        if ((memblock_end_of_DRAM() - 1) > max) {
-                ppc_swiotlb_enable = 1;
-                set_pci_dma_ops(&swiotlb_dma_ops);
-                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
-        }
-#endif
+        swiotlb_detect_4g();
 
         printk("MPC8536 DS board from Freescale Semiconductor\n");
 }
 
-machine_device_initcall(mpc8536_ds, mpc85xx_common_publish_devices);
+machine_arch_initcall(mpc8536_ds, mpc85xx_common_publish_devices);
 
 machine_arch_initcall(mpc8536_ds, swiotlb_setup_bus_notifier);
 
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index 29ee8fcd75a2..7d12a19aa7ee 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -137,10 +137,6 @@ static void __init init_ioports(void)
 
 static void __init mpc85xx_ads_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
-
         if (ppc_md.progress)
                 ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
 
@@ -150,11 +146,10 @@ static void __init mpc85xx_ads_setup_arch(void)
 #endif
 
 #ifdef CONFIG_PCI
-        for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
-                fsl_add_bridge(np, 1);
-
         ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 #endif
+
+        fsl_pci_assign_primary();
 }
 
 static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
@@ -173,7 +168,7 @@ static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 }
 
-machine_device_initcall(mpc85xx_ads, mpc85xx_common_publish_devices);
+machine_arch_initcall(mpc85xx_ads, mpc85xx_common_publish_devices);
 
 /*
  * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 11156fb53d83..c474505ad0d0 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -276,6 +276,33 @@ machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
 
 #endif /* CONFIG_PPC_I8259 */
 
+static void mpc85xx_cds_pci_assign_primary(void)
+{
+#ifdef CONFIG_PCI
+        struct device_node *np;
+
+        if (fsl_pci_primary)
+                return;
+
+        /*
+         * MPC85xx_CDS has ISA bridge but unfortunately there is no
+         * isa node in device tree. We now looking for i8259 node as
+         * a workaround for such a broken device tree. This routine
+         * is for complying to all device trees.
+         */
+        np = of_find_node_by_name(NULL, "i8259");
+        while ((fsl_pci_primary = of_get_parent(np))) {
+                of_node_put(np);
+                np = fsl_pci_primary;
+
+                if ((of_device_is_compatible(np, "fsl,mpc8540-pci") ||
+                    of_device_is_compatible(np, "fsl,mpc8548-pcie")) &&
+                    of_device_is_available(np))
+                        return;
+        }
+#endif
+}
+
 /*
  * Setup the architecture
  */
@@ -309,21 +336,12 @@ static void __init mpc85xx_cds_setup_arch(void)
         }
 
 #ifdef CONFIG_PCI
-        for_each_node_by_type(np, "pci") {
-                if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
-                    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
-                        struct resource rsrc;
-                        of_address_to_resource(np, 0, &rsrc);
-                        if ((rsrc.start & 0xfffff) == 0x8000)
-                                fsl_add_bridge(np, 1);
-                        else
-                                fsl_add_bridge(np, 0);
-                }
-        }
-
         ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
         ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 #endif
+
+        mpc85xx_cds_pci_assign_primary();
+        fsl_pci_assign_primary();
 }
 
 static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
@@ -355,7 +373,7 @@ static int __init mpc85xx_cds_probe(void)
         return of_flat_dt_is_compatible(root, "MPC85xxCDS");
 }
 
-machine_device_initcall(mpc85xx_cds, mpc85xx_common_publish_devices);
+machine_arch_initcall(mpc85xx_cds, mpc85xx_common_publish_devices);
 
 define_machine(mpc85xx_cds) {
         .name           = "MPC85xx CDS",
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 6d3265fe7718..9ebb91ed96a3 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -20,7 +20,6 @@
 #include <linux/seq_file.h>
 #include <linux/interrupt.h>
 #include <linux/of_platform.h>
-#include <linux/memblock.h>
 
 #include <asm/time.h>
 #include <asm/machdep.h>
@@ -129,13 +128,11 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
 }
 #endif  /* CONFIG_PCI */
 
-static void __init mpc85xx_ds_pci_init(void)
+static void __init mpc85xx_ds_uli_init(void)
 {
 #ifdef CONFIG_PCI
         struct device_node *node;
 
-        fsl_pci_init();
-
         /* See if we have a ULI under the primary */
 
         node = of_find_node_by_name(NULL, "uli1575");
@@ -159,7 +156,9 @@ static void __init mpc85xx_ds_setup_arch(void)
         if (ppc_md.progress)
                 ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
 
-        mpc85xx_ds_pci_init();
+        swiotlb_detect_4g();
+        fsl_pci_assign_primary();
+        mpc85xx_ds_uli_init();
         mpc85xx_smp_init();
 
         printk("MPC85xx DS board from Freescale Semiconductor\n");
@@ -175,9 +174,9 @@ static int __init mpc8544_ds_probe(void)
         return !!of_flat_dt_is_compatible(root, "MPC8544DS");
 }
 
-machine_device_initcall(mpc8544_ds, mpc85xx_common_publish_devices);
-machine_device_initcall(mpc8572_ds, mpc85xx_common_publish_devices);
-machine_device_initcall(p2020_ds, mpc85xx_common_publish_devices);
+machine_arch_initcall(mpc8544_ds, mpc85xx_common_publish_devices);
+machine_arch_initcall(mpc8572_ds, mpc85xx_common_publish_devices);
+machine_arch_initcall(p2020_ds, mpc85xx_common_publish_devices);
 
 machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier);
 machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 8e4b094c553b..8498f7323470 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -327,44 +327,16 @@ static void __init mpc85xx_mds_qeic_init(void) { }
 
 static void __init mpc85xx_mds_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct pci_controller *hose;
-        struct device_node *np;
-#endif
-        dma_addr_t max = 0xffffffff;
-
         if (ppc_md.progress)
                 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
 
-#ifdef CONFIG_PCI
-        for_each_node_by_type(np, "pci") {
-                if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
-                    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
-                        struct resource rsrc;
-                        of_address_to_resource(np, 0, &rsrc);
-                        if ((rsrc.start & 0xfffff) == 0x8000)
-                                fsl_add_bridge(np, 1);
-                        else
-                                fsl_add_bridge(np, 0);
-
-                        hose = pci_find_hose_for_OF_device(np);
-                        max = min(max, hose->dma_window_base_cur +
-                                        hose->dma_window_size);
-                }
-        }
-#endif
-
         mpc85xx_smp_init();
 
         mpc85xx_mds_qe_init();
 
-#ifdef CONFIG_SWIOTLB
-        if ((memblock_end_of_DRAM() - 1) > max) {
-                ppc_swiotlb_enable = 1;
-                set_pci_dma_ops(&swiotlb_dma_ops);
-                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
-        }
-#endif
+        fsl_pci_assign_primary();
+
+        swiotlb_detect_4g();
 }
 
 
@@ -409,9 +381,9 @@ static int __init mpc85xx_publish_devices(void)
         return mpc85xx_common_publish_devices();
 }
 
-machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
-machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
-machine_device_initcall(p1021_mds, mpc85xx_common_publish_devices);
+machine_arch_initcall(mpc8568_mds, mpc85xx_publish_devices);
+machine_arch_initcall(mpc8569_mds, mpc85xx_publish_devices);
+machine_arch_initcall(p1021_mds, mpc85xx_common_publish_devices);
 
 machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
 machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 1910fdcb75b2..ede8771d6f02 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -86,23 +86,17 @@ void __init mpc85xx_rdb_pic_init(void)
  */
 static void __init mpc85xx_rdb_setup_arch(void)
 {
-#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
+#ifdef CONFIG_QUICC_ENGINE
         struct device_node *np;
 #endif
 
         if (ppc_md.progress)
                 ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);
 
-#ifdef CONFIG_PCI
-        for_each_node_by_type(np, "pci") {
-                if (of_device_is_compatible(np, "fsl,mpc8548-pcie"))
-                        fsl_add_bridge(np, 0);
-        }
-
-#endif
-
         mpc85xx_smp_init();
 
+        fsl_pci_assign_primary();
+
 #ifdef CONFIG_QUICC_ENGINE
         np = of_find_compatible_node(NULL, NULL, "fsl,qe");
         if (!np) {
@@ -161,15 +155,15 @@ qe_fail:
         printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
 }
 
-machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
-machine_device_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices);
-machine_device_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices);
-machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
-machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
-machine_device_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
-machine_device_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
-machine_device_initcall(p1025_rdb, mpc85xx_common_publish_devices);
-machine_device_initcall(p1024_rdb, mpc85xx_common_publish_devices);
+machine_arch_initcall(p2020_rdb, mpc85xx_common_publish_devices);
+machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices);
+machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices);
+machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices);
+machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
+machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
+machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
+machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices);
+machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices);
 
 /*
  * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/p1010rdb.c b/arch/powerpc/platforms/85xx/p1010rdb.c
index dbaf44354f0d..0252961392d5 100644
--- a/arch/powerpc/platforms/85xx/p1010rdb.c
+++ b/arch/powerpc/platforms/85xx/p1010rdb.c
@@ -46,25 +46,15 @@ void __init p1010_rdb_pic_init(void)
  */
 static void __init p1010_rdb_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
-
         if (ppc_md.progress)
                 ppc_md.progress("p1010_rdb_setup_arch()", 0);
 
-#ifdef CONFIG_PCI
-        for_each_node_by_type(np, "pci") {
-                if (of_device_is_compatible(np, "fsl,p1010-pcie"))
-                        fsl_add_bridge(np, 0);
-        }
-
-#endif
+        fsl_pci_assign_primary();
 
         printk(KERN_INFO "P1010 RDB board from Freescale Semiconductor\n");
 }
 
-machine_device_initcall(p1010_rdb, mpc85xx_common_publish_devices);
+machine_arch_initcall(p1010_rdb, mpc85xx_common_publish_devices);
 machine_arch_initcall(p1010_rdb, swiotlb_setup_bus_notifier);
 
 /*
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index 3c732acf331d..848a3e98e1c1 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -18,7 +18,6 @@
 
 #include <linux/pci.h>
 #include <linux/of_platform.h>
-#include <linux/memblock.h>
 #include <asm/div64.h>
 #include <asm/mpic.h>
 #include <asm/swiotlb.h>
@@ -507,32 +506,9 @@ early_param("video", early_video_setup);
  */
 static void __init p1022_ds_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
-        dma_addr_t max = 0xffffffff;
-
         if (ppc_md.progress)
                 ppc_md.progress("p1022_ds_setup_arch()", 0);
 
-#ifdef CONFIG_PCI
-        for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
-                struct resource rsrc;
-                struct pci_controller *hose;
-
-                of_address_to_resource(np, 0, &rsrc);
-
-                if ((rsrc.start & 0xfffff) == 0x8000)
-                        fsl_add_bridge(np, 1);
-                else
-                        fsl_add_bridge(np, 0);
-
-                hose = pci_find_hose_for_OF_device(np);
-                max = min(max, hose->dma_window_base_cur +
-                          hose->dma_window_size);
-        }
-#endif
-
 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
         diu_ops.get_pixel_format        = p1022ds_get_pixel_format;
         diu_ops.set_gamma_table         = p1022ds_set_gamma_table;
@@ -601,18 +577,14 @@ static void __init p1022_ds_setup_arch(void)
 
         mpc85xx_smp_init();
 
-#ifdef CONFIG_SWIOTLB
-        if ((memblock_end_of_DRAM() - 1) > max) {
-                ppc_swiotlb_enable = 1;
-                set_pci_dma_ops(&swiotlb_dma_ops);
-                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
-        }
-#endif
+        fsl_pci_assign_primary();
+
+        swiotlb_detect_4g();
 
         pr_info("Freescale P1022 DS reference board\n");
 }
 
-machine_device_initcall(p1022_ds, mpc85xx_common_publish_devices);
+machine_arch_initcall(p1022_ds, mpc85xx_common_publish_devices);
 
 machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
 
diff --git a/arch/powerpc/platforms/85xx/p1022_rdk.c b/arch/powerpc/platforms/85xx/p1022_rdk.c
new file mode 100644
index 000000000000..55ffa1cc380c
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p1022_rdk.c
@@ -0,0 +1,167 @@
+/*
+ * P1022 RDK board specific routines
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * Based on p1022_ds.c
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/pci.h>
+#include <linux/of_platform.h>
+#include <asm/div64.h>
+#include <asm/mpic.h>
+#include <asm/swiotlb.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include <asm/udbg.h>
+#include <asm/fsl_guts.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+
+/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
+#define CLKDVDR_PXCKEN          0x80000000
+#define CLKDVDR_PXCKINV         0x10000000
+#define CLKDVDR_PXCKDLY         0x06000000
+#define CLKDVDR_PXCLK_MASK      0x00FF0000
+
+/**
+ * p1022rdk_set_monitor_port: switch the output to a different monitor port
+ */
+static void p1022rdk_set_monitor_port(enum fsl_diu_monitor_port port)
+{
+        if (port != FSL_DIU_PORT_DVI) {
+                pr_err("p1022rdk: unsupported monitor port %i\n", port);
+                return;
+        }
+}
+
+/**
+ * p1022rdk_set_pixel_clock: program the DIU's clock
+ *
+ * @pixclock: the wavelength, in picoseconds, of the clock
+ */
+void p1022rdk_set_pixel_clock(unsigned int pixclock)
+{
+        struct device_node *guts_np = NULL;
+        struct ccsr_guts __iomem *guts;
+        unsigned long freq;
+        u64 temp;
+        u32 pxclk;
+
+        /* Map the global utilities registers. */
+        guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
+        if (!guts_np) {
+                pr_err("p1022rdk: missing global utilties device node\n");
+                return;
+        }
+
+        guts = of_iomap(guts_np, 0);
+        of_node_put(guts_np);
+        if (!guts) {
+                pr_err("p1022rdk: could not map global utilties device\n");
+                return;
+        }
+
+        /* Convert pixclock from a wavelength to a frequency */
+        temp = 1000000000000ULL;
+        do_div(temp, pixclock);
+        freq = temp;
+
+        /*
+         * 'pxclk' is the ratio of the platform clock to the pixel clock.
+         * This number is programmed into the CLKDVDR register, and the valid
+         * range of values is 2-255.
+         */
+        pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
+        pxclk = clamp_t(u32, pxclk, 2, 255);
+
+        /* Disable the pixel clock, and set it to non-inverted and no delay */
+        clrbits32(&guts->clkdvdr,
+                  CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
+
+        /* Enable the clock and set the pxclk */
+        setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
+
+        iounmap(guts);
+}
+
+/**
+ * p1022rdk_valid_monitor_port: set the monitor port for sysfs
+ */
+enum fsl_diu_monitor_port
+p1022rdk_valid_monitor_port(enum fsl_diu_monitor_port port)
+{
+        return FSL_DIU_PORT_DVI;
+}
+
+#endif
+
+void __init p1022_rdk_pic_init(void)
+{
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+                MPIC_SINGLE_DEST_CPU,
+                0, 256, " OpenPIC  ");
+        BUG_ON(mpic == NULL);
+        mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init p1022_rdk_setup_arch(void)
+{
+        if (ppc_md.progress)
+                ppc_md.progress("p1022_rdk_setup_arch()", 0);
+
+#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+        diu_ops.set_monitor_port        = p1022rdk_set_monitor_port;
+        diu_ops.set_pixel_clock         = p1022rdk_set_pixel_clock;
+        diu_ops.valid_monitor_port      = p1022rdk_valid_monitor_port;
+#endif
+
+        mpc85xx_smp_init();
+
+        fsl_pci_assign_primary();
+
+        swiotlb_detect_4g();
+
+        pr_info("Freescale / iVeia P1022 RDK reference board\n");
+}
+
+machine_arch_initcall(p1022_rdk, mpc85xx_common_publish_devices);
+
+machine_arch_initcall(p1022_rdk, swiotlb_setup_bus_notifier);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p1022_rdk_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,p1022rdk");
+}
+
+define_machine(p1022_rdk) {
+        .name                   = "P1022 RDK",
+        .probe                  = p1022_rdk_probe,
+        .setup_arch             = p1022_rdk_setup_arch,
+        .init_IRQ               = p1022_rdk_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/p1023_rds.c b/arch/powerpc/platforms/85xx/p1023_rds.c
index 2990e8b13dc9..9cc60a738834 100644
--- a/arch/powerpc/platforms/85xx/p1023_rds.c
+++ b/arch/powerpc/platforms/85xx/p1023_rds.c
@@ -80,15 +80,12 @@ static void __init mpc85xx_rds_setup_arch(void)
                 }
         }
 
-#ifdef CONFIG_PCI
-        for_each_compatible_node(np, "pci", "fsl,p1023-pcie")
-                fsl_add_bridge(np, 0);
-#endif
-
         mpc85xx_smp_init();
+
+        fsl_pci_assign_primary();
 }
 
-machine_device_initcall(p1023_rds, mpc85xx_common_publish_devices);
+machine_arch_initcall(p1023_rds, mpc85xx_common_publish_devices);
 
 static void __init mpc85xx_rds_pic_init(void)
 {
diff --git a/arch/powerpc/platforms/85xx/p2041_rdb.c b/arch/powerpc/platforms/85xx/p2041_rdb.c
index 6541fa2630c0..000c0892fc40 100644
--- a/arch/powerpc/platforms/85xx/p2041_rdb.c
+++ b/arch/powerpc/platforms/85xx/p2041_rdb.c
@@ -80,7 +80,7 @@ define_machine(p2041_rdb) {
         .power_save             = e500_idle,
 };
 
-machine_device_initcall(p2041_rdb, corenet_ds_publish_devices);
+machine_arch_initcall(p2041_rdb, corenet_ds_publish_devices);
 
 #ifdef CONFIG_SWIOTLB
 machine_arch_initcall(p2041_rdb, swiotlb_setup_bus_notifier);
diff --git a/arch/powerpc/platforms/85xx/p3041_ds.c b/arch/powerpc/platforms/85xx/p3041_ds.c
index f238efa75891..b3edc205daa9 100644
--- a/arch/powerpc/platforms/85xx/p3041_ds.c
+++ b/arch/powerpc/platforms/85xx/p3041_ds.c
@@ -82,7 +82,7 @@ define_machine(p3041_ds) {
         .power_save             = e500_idle,
 };
 
-machine_device_initcall(p3041_ds, corenet_ds_publish_devices);
+machine_arch_initcall(p3041_ds, corenet_ds_publish_devices);
 
 #ifdef CONFIG_SWIOTLB
 machine_arch_initcall(p3041_ds, swiotlb_setup_bus_notifier);
diff --git a/arch/powerpc/platforms/85xx/p4080_ds.c b/arch/powerpc/platforms/85xx/p4080_ds.c
index c92417dc6574..54df10632aea 100644
--- a/arch/powerpc/platforms/85xx/p4080_ds.c
+++ b/arch/powerpc/platforms/85xx/p4080_ds.c
@@ -81,7 +81,7 @@ define_machine(p4080_ds) {
         .power_save             = e500_idle,
 };
 
-machine_device_initcall(p4080_ds, corenet_ds_publish_devices);
+machine_arch_initcall(p4080_ds, corenet_ds_publish_devices);
 #ifdef CONFIG_SWIOTLB
 machine_arch_initcall(p4080_ds, swiotlb_setup_bus_notifier);
 #endif
diff --git a/arch/powerpc/platforms/85xx/p5020_ds.c b/arch/powerpc/platforms/85xx/p5020_ds.c
index 17bef15a85ed..753a42c29d4d 100644
--- a/arch/powerpc/platforms/85xx/p5020_ds.c
+++ b/arch/powerpc/platforms/85xx/p5020_ds.c
@@ -91,7 +91,7 @@ define_machine(p5020_ds) {
 #endif
 };
 
-machine_device_initcall(p5020_ds, corenet_ds_publish_devices);
+machine_arch_initcall(p5020_ds, corenet_ds_publish_devices);
 
 #ifdef CONFIG_SWIOTLB
 machine_arch_initcall(p5020_ds, swiotlb_setup_bus_notifier);
diff --git a/arch/powerpc/platforms/85xx/p5040_ds.c b/arch/powerpc/platforms/85xx/p5040_ds.c
new file mode 100644
index 000000000000..11381851828e
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p5040_ds.c
@@ -0,0 +1,89 @@
+/*
+ * P5040 DS Setup
+ *
+ * Copyright 2009-2010 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+
+#include <asm/machdep.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <linux/of_fdt.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include <asm/ehv_pic.h>
+
+#include "corenet_ds.h"
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p5040_ds_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_SMP
+        extern struct smp_ops_t smp_85xx_ops;
+#endif
+
+        if (of_flat_dt_is_compatible(root, "fsl,P5040DS"))
+                return 1;
+
+        /* Check if we're running under the Freescale hypervisor */
+        if (of_flat_dt_is_compatible(root, "fsl,P5040DS-hv")) {
+                ppc_md.init_IRQ = ehv_pic_init;
+                ppc_md.get_irq = ehv_pic_get_irq;
+                ppc_md.restart = fsl_hv_restart;
+                ppc_md.power_off = fsl_hv_halt;
+                ppc_md.halt = fsl_hv_halt;
+#ifdef CONFIG_SMP
+                /*
+                 * Disable the timebase sync operations because we can't write
+                 * to the timebase registers under the hypervisor.
+                  */
+                smp_85xx_ops.give_timebase = NULL;
+                smp_85xx_ops.take_timebase = NULL;
+#endif
+                return 1;
+        }
+
+        return 0;
+}
+
+define_machine(p5040_ds) {
+        .name                   = "P5040 DS",
+        .probe                  = p5040_ds_probe,
+        .setup_arch             = corenet_ds_setup_arch,
+        .init_IRQ               = corenet_ds_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
+#ifdef CONFIG_PPC64
+        .get_irq                = mpic_get_irq,
+#else
+        .get_irq                = mpic_get_coreint_irq,
+#endif
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+#ifdef CONFIG_PPC64
+        .power_save             = book3e_idle,
+#else
+        .power_save             = e500_idle,
+#endif
+};
+
+machine_arch_initcall(p5040_ds, corenet_ds_publish_devices);
+
+#ifdef CONFIG_SWIOTLB
+machine_arch_initcall(p5040_ds, swiotlb_setup_bus_notifier);
+#endif
diff --git a/arch/powerpc/platforms/85xx/qemu_e500.c b/arch/powerpc/platforms/85xx/qemu_e500.c
index 95a2e53af71b..f6ea5618c733 100644
--- a/arch/powerpc/platforms/85xx/qemu_e500.c
+++ b/arch/powerpc/platforms/85xx/qemu_e500.c
@@ -41,7 +41,8 @@ static void __init qemu_e500_setup_arch(void)
 {
         ppc_md.progress("qemu_e500_setup_arch()", 0);
 
-        fsl_pci_init();
+        fsl_pci_assign_primary();
+        swiotlb_detect_4g();
         mpc85xx_smp_init();
 }
 
@@ -55,7 +56,7 @@ static int __init qemu_e500_probe(void)
         return !!of_flat_dt_is_compatible(root, "fsl,qemu-e500");
 }
 
-machine_device_initcall(qemu_e500, mpc85xx_common_publish_devices);
+machine_arch_initcall(qemu_e500, mpc85xx_common_publish_devices);
 
 define_machine(qemu_e500) {
         .name                   = "QEMU e500",
diff --git a/arch/powerpc/platforms/85xx/sbc8548.c b/arch/powerpc/platforms/85xx/sbc8548.c
index cd3a66bdb54b..f62121825914 100644
--- a/arch/powerpc/platforms/85xx/sbc8548.c
+++ b/arch/powerpc/platforms/85xx/sbc8548.c
@@ -88,26 +88,11 @@ static int __init sbc8548_hw_rev(void)
  */
 static void __init sbc8548_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
-
         if (ppc_md.progress)
                 ppc_md.progress("sbc8548_setup_arch()", 0);
 
-#ifdef CONFIG_PCI
-        for_each_node_by_type(np, "pci") {
-                if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
-                    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
-                        struct resource rsrc;
-                        of_address_to_resource(np, 0, &rsrc);
-                        if ((rsrc.start & 0xfffff) == 0x8000)
-                                fsl_add_bridge(np, 1);
-                        else
-                                fsl_add_bridge(np, 0);
-                }
-        }
-#endif
+        fsl_pci_assign_primary();
+
         sbc_rev = sbc8548_hw_rev();
 }
 
@@ -128,7 +113,7 @@ static void sbc8548_show_cpuinfo(struct seq_file *m)
         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 }
 
-machine_device_initcall(sbc8548, mpc85xx_common_publish_devices);
+machine_arch_initcall(sbc8548, mpc85xx_common_publish_devices);
 
 /*
  * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index ff4249044a3c..6fcfa12e5c56 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -2,7 +2,7 @@
  * Author: Andy Fleming <afleming@freescale.com>
  *         Kumar Gala <galak@kernel.crashing.org>
  *
- * Copyright 2006-2008, 2011 Freescale Semiconductor Inc.
+ * Copyright 2006-2008, 2011-2012 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -17,6 +17,7 @@
 #include <linux/of.h>
 #include <linux/kexec.h>
 #include <linux/highmem.h>
+#include <linux/cpu.h>
 
 #include <asm/machdep.h>
 #include <asm/pgtable.h>
@@ -24,33 +25,118 @@
 #include <asm/mpic.h>
 #include <asm/cacheflush.h>
 #include <asm/dbell.h>
+#include <asm/fsl_guts.h>
 
 #include <sysdev/fsl_soc.h>
 #include <sysdev/mpic.h>
 #include "smp.h"
 
-extern void __early_start(void);
-
-#define BOOT_ENTRY_ADDR_UPPER   0
-#define BOOT_ENTRY_ADDR_LOWER   1
-#define BOOT_ENTRY_R3_UPPER     2
-#define BOOT_ENTRY_R3_LOWER     3
-#define BOOT_ENTRY_RESV         4
-#define BOOT_ENTRY_PIR          5
-#define BOOT_ENTRY_R6_UPPER     6
-#define BOOT_ENTRY_R6_LOWER     7
-#define NUM_BOOT_ENTRY          8
-#define SIZE_BOOT_ENTRY         (NUM_BOOT_ENTRY * sizeof(u32))
-
-static int __init
-smp_85xx_kick_cpu(int nr)
+struct epapr_spin_table {
+        u32     addr_h;
+        u32     addr_l;
+        u32     r3_h;
+        u32     r3_l;
+        u32     reserved;
+        u32     pir;
+};
+
+static struct ccsr_guts __iomem *guts;
+static u64 timebase;
+static int tb_req;
+static int tb_valid;
+
+static void mpc85xx_timebase_freeze(int freeze)
+{
+        uint32_t mask;
+
+        mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1;
+        if (freeze)
+                setbits32(&guts->devdisr, mask);
+        else
+                clrbits32(&guts->devdisr, mask);
+
+        in_be32(&guts->devdisr);
+}
+
+static void mpc85xx_give_timebase(void)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+
+        while (!tb_req)
+                barrier();
+        tb_req = 0;
+
+        mpc85xx_timebase_freeze(1);
+        timebase = get_tb();
+        mb();
+        tb_valid = 1;
+
+        while (tb_valid)
+                barrier();
+
+        mpc85xx_timebase_freeze(0);
+
+        local_irq_restore(flags);
+}
+
+static void mpc85xx_take_timebase(void)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+
+        tb_req = 1;
+        while (!tb_valid)
+                barrier();
+
+        set_tb(timebase >> 32, timebase & 0xffffffff);
+        isync();
+        tb_valid = 0;
+
+        local_irq_restore(flags);
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+static void __cpuinit smp_85xx_mach_cpu_die(void)
+{
+        unsigned int cpu = smp_processor_id();
+        u32 tmp;
+
+        local_irq_disable();
+        idle_task_exit();
+        generic_set_cpu_dead(cpu);
+        mb();
+
+        mtspr(SPRN_TCR, 0);
+
+        __flush_disable_L1();
+        tmp = (mfspr(SPRN_HID0) & ~(HID0_DOZE|HID0_SLEEP)) | HID0_NAP;
+        mtspr(SPRN_HID0, tmp);
+        isync();
+
+        /* Enter NAP mode. */
+        tmp = mfmsr();
+        tmp |= MSR_WE;
+        mb();
+        mtmsr(tmp);
+        isync();
+
+        while (1)
+                ;
+}
+#endif
+
+static int __cpuinit smp_85xx_kick_cpu(int nr)
 {
         unsigned long flags;
         const u64 *cpu_rel_addr;
-        __iomem u32 *bptr_vaddr;
+        __iomem struct epapr_spin_table *spin_table;
         struct device_node *np;
-        int n = 0, hw_cpu = get_hard_smp_processor_id(nr);
+        int hw_cpu = get_hard_smp_processor_id(nr);
         int ioremappable;
+        int ret = 0;
 
         WARN_ON(nr < 0 || nr >= NR_CPUS);
         WARN_ON(hw_cpu < 0 || hw_cpu >= NR_CPUS);
@@ -75,46 +161,81 @@ smp_85xx_kick_cpu(int nr)
 
         /* Map the spin table */
         if (ioremappable)
-                bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY);
+                spin_table = ioremap(*cpu_rel_addr,
+                                sizeof(struct epapr_spin_table));
         else
-                bptr_vaddr = phys_to_virt(*cpu_rel_addr);
+                spin_table = phys_to_virt(*cpu_rel_addr);
 
         local_irq_save(flags);
-
-        out_be32(bptr_vaddr + BOOT_ENTRY_PIR, hw_cpu);
 #ifdef CONFIG_PPC32
-        out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start));
+#ifdef CONFIG_HOTPLUG_CPU
+        /* Corresponding to generic_set_cpu_dead() */
+        generic_set_cpu_up(nr);
+
+        if (system_state == SYSTEM_RUNNING) {
+                out_be32(&spin_table->addr_l, 0);
+
+                /*
+                 * We don't set the BPTR register here since it already points
+                 * to the boot page properly.
+                 */
+                mpic_reset_core(hw_cpu);
+
+                /* wait until core is ready... */
+                if (!spin_event_timeout(in_be32(&spin_table->addr_l) == 1,
+                                                10000, 100)) {
+                        pr_err("%s: timeout waiting for core %d to reset\n",
+                                                        __func__, hw_cpu);
+                        ret = -ENOENT;
+                        goto out;
+                }
+
+                /*  clear the acknowledge status */
+                __secondary_hold_acknowledge = -1;
+        }
+#endif
+        out_be32(&spin_table->pir, hw_cpu);
+        out_be32(&spin_table->addr_l, __pa(__early_start));
 
         if (!ioremappable)
-                flush_dcache_range((ulong)bptr_vaddr,
-                                (ulong)(bptr_vaddr + SIZE_BOOT_ENTRY));
+                flush_dcache_range((ulong)spin_table,
+                        (ulong)spin_table + sizeof(struct epapr_spin_table));
 
         /* Wait a bit for the CPU to ack. */
-        while ((__secondary_hold_acknowledge != hw_cpu) && (++n < 1000))
-                mdelay(1);
+        if (!spin_event_timeout(__secondary_hold_acknowledge == hw_cpu,
+                                        10000, 100)) {
+                pr_err("%s: timeout waiting for core %d to ack\n",
+                                                __func__, hw_cpu);
+                ret = -ENOENT;
+                goto out;
+        }
+out:
 #else
         smp_generic_kick_cpu(nr);
 
-        out_be64((u64 *)(bptr_vaddr + BOOT_ENTRY_ADDR_UPPER),
-                __pa((u64)*((unsigned long long *) generic_secondary_smp_init)));
+        out_be32(&spin_table->pir, hw_cpu);
+        out_be64((u64 *)(&spin_table->addr_h),
+          __pa((u64)*((unsigned long long *)generic_secondary_smp_init)));
 
         if (!ioremappable)
-                flush_dcache_range((ulong)bptr_vaddr,
-                                (ulong)(bptr_vaddr + SIZE_BOOT_ENTRY));
+                flush_dcache_range((ulong)spin_table,
+                        (ulong)spin_table + sizeof(struct epapr_spin_table));
 #endif
 
         local_irq_restore(flags);
 
         if (ioremappable)
-                iounmap(bptr_vaddr);
-
-        pr_debug("waited %d msecs for CPU #%d.\n", n, nr);
+                iounmap(spin_table);
 
-        return 0;
+        return ret;
 }
 
 struct smp_ops_t smp_85xx_ops = {
         .kick_cpu = smp_85xx_kick_cpu,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_disable    = generic_cpu_disable,
+        .cpu_die        = generic_cpu_die,
+#endif
 #ifdef CONFIG_KEXEC
         .give_timebase  = smp_generic_give_timebase,
         .take_timebase  = smp_generic_take_timebase,
@@ -218,8 +339,7 @@ static void mpc85xx_smp_machine_kexec(struct kimage *image)
 }
 #endif /* CONFIG_KEXEC */
 
-static void __init
-smp_85xx_setup_cpu(int cpu_nr)
+static void __cpuinit smp_85xx_setup_cpu(int cpu_nr)
 {
         if (smp_85xx_ops.probe == smp_mpic_probe)
                 mpic_setup_this_cpu();
@@ -228,6 +348,16 @@ smp_85xx_setup_cpu(int cpu_nr)
                 doorbell_setup_this_cpu();
 }
 
+static const struct of_device_id mpc85xx_smp_guts_ids[] = {
+        { .compatible = "fsl,mpc8572-guts", },
+        { .compatible = "fsl,p1020-guts", },
+        { .compatible = "fsl,p1021-guts", },
+        { .compatible = "fsl,p1022-guts", },
+        { .compatible = "fsl,p1023-guts", },
+        { .compatible = "fsl,p2020-guts", },
+        {},
+};
+
 void __init mpc85xx_smp_init(void)
 {
         struct device_node *np;
@@ -249,6 +379,22 @@ void __init mpc85xx_smp_init(void)
                 smp_85xx_ops.cause_ipi = doorbell_cause_ipi;
         }
 
+        np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids);
+        if (np) {
+                guts = of_iomap(np, 0);
+                of_node_put(np);
+                if (!guts) {
+                        pr_err("%s: Could not map guts node address\n",
+                                                                __func__);
+                        return;
+                }
+                smp_85xx_ops.give_timebase = mpc85xx_give_timebase;
+                smp_85xx_ops.take_timebase = mpc85xx_take_timebase;
+#ifdef CONFIG_HOTPLUG_CPU
+                ppc_md.cpu_die = smp_85xx_mach_cpu_die;
+#endif
+        }
+
         smp_ops = &smp_85xx_ops;
 
 #ifdef CONFIG_KEXEC
diff --git a/arch/powerpc/platforms/85xx/socrates.c b/arch/powerpc/platforms/85xx/socrates.c
index b9c6daa07b66..ae368e0e1076 100644
--- a/arch/powerpc/platforms/85xx/socrates.c
+++ b/arch/powerpc/platforms/85xx/socrates.c
@@ -66,20 +66,13 @@ static void __init socrates_pic_init(void)
  */
 static void __init socrates_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
-
         if (ppc_md.progress)
                 ppc_md.progress("socrates_setup_arch()", 0);
 
-#ifdef CONFIG_PCI
-        for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
-                fsl_add_bridge(np, 1);
-#endif
+        fsl_pci_assign_primary();
 }
 
-machine_device_initcall(socrates, mpc85xx_common_publish_devices);
+machine_arch_initcall(socrates, mpc85xx_common_publish_devices);
 
 /*
  * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/stx_gp3.c b/arch/powerpc/platforms/85xx/stx_gp3.c
index e0508002b086..6f4939b6309e 100644
--- a/arch/powerpc/platforms/85xx/stx_gp3.c
+++ b/arch/powerpc/platforms/85xx/stx_gp3.c
@@ -60,21 +60,14 @@ static void __init stx_gp3_pic_init(void)
  */
 static void __init stx_gp3_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
-
         if (ppc_md.progress)
                 ppc_md.progress("stx_gp3_setup_arch()", 0);
 
+        fsl_pci_assign_primary();
+
 #ifdef CONFIG_CPM2
         cpm2_reset();
 #endif
-
-#ifdef CONFIG_PCI
-        for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
-                fsl_add_bridge(np, 1);
-#endif
 }
 
 static void stx_gp3_show_cpuinfo(struct seq_file *m)
@@ -93,7 +86,7 @@ static void stx_gp3_show_cpuinfo(struct seq_file *m)
         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 }
 
-machine_device_initcall(stx_gp3, mpc85xx_common_publish_devices);
+machine_arch_initcall(stx_gp3, mpc85xx_common_publish_devices);
 
 /*
  * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c
index 3e70a2035e53..b4e58cdc09a5 100644
--- a/arch/powerpc/platforms/85xx/tqm85xx.c
+++ b/arch/powerpc/platforms/85xx/tqm85xx.c
@@ -59,10 +59,6 @@ static void __init tqm85xx_pic_init(void)
  */
 static void __init tqm85xx_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
-
         if (ppc_md.progress)
                 ppc_md.progress("tqm85xx_setup_arch()", 0);
 
@@ -70,20 +66,7 @@ static void __init tqm85xx_setup_arch(void)
         cpm2_reset();
 #endif
 
-#ifdef CONFIG_PCI
-        for_each_node_by_type(np, "pci") {
-                if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
-                    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
-                        struct resource rsrc;
-                        if (!of_address_to_resource(np, 0, &rsrc)) {
-                                if ((rsrc.start & 0xfffff) == 0x8000)
-                                        fsl_add_bridge(np, 1);
-                                else
-                                        fsl_add_bridge(np, 0);
-                        }
-                }
-        }
-#endif
+        fsl_pci_assign_primary();
 }
 
 static void tqm85xx_show_cpuinfo(struct seq_file *m)
@@ -123,9 +106,9 @@ static void __devinit tqm85xx_ti1520_fixup(struct pci_dev *pdev)
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1520,
                 tqm85xx_ti1520_fixup);
 
-machine_device_initcall(tqm85xx, mpc85xx_common_publish_devices);
+machine_arch_initcall(tqm85xx, mpc85xx_common_publish_devices);
 
-static const char *board[] __initdata = {
+static const char * const board[] __initconst = {
         "tqc,tqm8540",
         "tqc,tqm8541",
         "tqc,tqm8548",
diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
index 41c687550ea7..dcbf7e42dce7 100644
--- a/arch/powerpc/platforms/85xx/xes_mpc85xx.c
+++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
@@ -111,18 +111,11 @@ static void xes_mpc85xx_fixups(void)
         }
 }
 
-#ifdef CONFIG_PCI
-static int primary_phb_addr;
-#endif
-
 /*
  * Setup the architecture
  */
 static void __init xes_mpc85xx_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
         struct device_node *root;
         const char *model = "Unknown";
 
@@ -137,26 +130,14 @@ static void __init xes_mpc85xx_setup_arch(void)
 
         xes_mpc85xx_fixups();
 
-#ifdef CONFIG_PCI
-        for_each_node_by_type(np, "pci") {
-                if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
-                    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
-                        struct resource rsrc;
-                        of_address_to_resource(np, 0, &rsrc);
-                        if ((rsrc.start & 0xfffff) == primary_phb_addr)
-                                fsl_add_bridge(np, 1);
-                        else
-                                fsl_add_bridge(np, 0);
-                }
-        }
-#endif
-
         mpc85xx_smp_init();
+
+        fsl_pci_assign_primary();
 }
 
-machine_device_initcall(xes_mpc8572, mpc85xx_common_publish_devices);
-machine_device_initcall(xes_mpc8548, mpc85xx_common_publish_devices);
-machine_device_initcall(xes_mpc8540, mpc85xx_common_publish_devices);
+machine_arch_initcall(xes_mpc8572, mpc85xx_common_publish_devices);
+machine_arch_initcall(xes_mpc8548, mpc85xx_common_publish_devices);
+machine_arch_initcall(xes_mpc8540, mpc85xx_common_publish_devices);
 
 /*
  * Called very early, device-tree isn't unflattened
@@ -165,42 +146,21 @@ static int __init xes_mpc8572_probe(void)
 {
         unsigned long root = of_get_flat_dt_root();
 
-        if (of_flat_dt_is_compatible(root, "xes,MPC8572")) {
-#ifdef CONFIG_PCI
-                primary_phb_addr = 0x8000;
-#endif
-                return 1;
-        } else {
-                return 0;
-        }
+        return of_flat_dt_is_compatible(root, "xes,MPC8572");
 }
 
 static int __init xes_mpc8548_probe(void)
 {
         unsigned long root = of_get_flat_dt_root();
 
-        if (of_flat_dt_is_compatible(root, "xes,MPC8548")) {
-#ifdef CONFIG_PCI
-                primary_phb_addr = 0xb000;
-#endif
-                return 1;
-        } else {
-                return 0;
-        }
+        return of_flat_dt_is_compatible(root, "xes,MPC8548");
 }
 
 static int __init xes_mpc8540_probe(void)
 {
         unsigned long root = of_get_flat_dt_root();
 
-        if (of_flat_dt_is_compatible(root, "xes,MPC8540")) {
-#ifdef CONFIG_PCI
-                primary_phb_addr = 0xb000;
-#endif
-                return 1;
-        } else {
-                return 0;
-        }
+        return of_flat_dt_is_compatible(root, "xes,MPC8540");
 }
 
 define_machine(xes_mpc8572) {
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c b/arch/powerpc/platforms/86xx/gef_ppc9a.c
index 563aafa8629c..bf5338754c5a 100644
--- a/arch/powerpc/platforms/86xx/gef_ppc9a.c
+++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c
@@ -73,13 +73,6 @@ static void __init gef_ppc9a_init_irq(void)
 static void __init gef_ppc9a_setup_arch(void)
 {
         struct device_node *regs;
-#ifdef CONFIG_PCI
-        struct device_node *np;
-
-        for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
-                fsl_add_bridge(np, 1);
-        }
-#endif
 
         printk(KERN_INFO "GE Intelligent Platforms PPC9A 6U VME SBC\n");
 
@@ -87,6 +80,8 @@ static void __init gef_ppc9a_setup_arch(void)
         mpc86xx_smp_init();
 #endif
 
+        fsl_pci_assign_primary();
+
         /* Remap basic board registers */
         regs = of_find_compatible_node(NULL, NULL, "gef,ppc9a-fpga-regs");
         if (regs) {
@@ -221,6 +216,7 @@ static long __init mpc86xx_time_init(void)
 static __initdata struct of_device_id of_bus_ids[] = {
         { .compatible = "simple-bus", },
         { .compatible = "gianfar", },
+        { .compatible = "fsl,mpc8641-pcie", },
         {},
 };
 
@@ -231,7 +227,7 @@ static int __init declare_of_platform_devices(void)
 
         return 0;
 }
-machine_device_initcall(gef_ppc9a, declare_of_platform_devices);
+machine_arch_initcall(gef_ppc9a, declare_of_platform_devices);
 
 define_machine(gef_ppc9a) {
         .name                   = "GE PPC9A",
diff --git a/arch/powerpc/platforms/86xx/gef_sbc310.c b/arch/powerpc/platforms/86xx/gef_sbc310.c
index cc6a91ae0889..0b7851330a07 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc310.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc310.c
@@ -73,20 +73,14 @@ static void __init gef_sbc310_init_irq(void)
 static void __init gef_sbc310_setup_arch(void)
 {
         struct device_node *regs;
-#ifdef CONFIG_PCI
-        struct device_node *np;
-
-        for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
-                fsl_add_bridge(np, 1);
-        }
-#endif
-
         printk(KERN_INFO "GE Intelligent Platforms SBC310 6U VPX SBC\n");
 
 #ifdef CONFIG_SMP
         mpc86xx_smp_init();
 #endif
 
+        fsl_pci_assign_primary();
+
         /* Remap basic board registers */
         regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs");
         if (regs) {
@@ -209,6 +203,7 @@ static long __init mpc86xx_time_init(void)
 static __initdata struct of_device_id of_bus_ids[] = {
         { .compatible = "simple-bus", },
         { .compatible = "gianfar", },
+        { .compatible = "fsl,mpc8641-pcie", },
         {},
 };
 
@@ -219,7 +214,7 @@ static int __init declare_of_platform_devices(void)
 
         return 0;
 }
-machine_device_initcall(gef_sbc310, declare_of_platform_devices);
+machine_arch_initcall(gef_sbc310, declare_of_platform_devices);
 
 define_machine(gef_sbc310) {
         .name                   = "GE SBC310",
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c
index aead6b337f4a..b9eb174897b1 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -73,13 +73,6 @@ static void __init gef_sbc610_init_irq(void)
 static void __init gef_sbc610_setup_arch(void)
 {
         struct device_node *regs;
-#ifdef CONFIG_PCI
-        struct device_node *np;
-
-        for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
-                fsl_add_bridge(np, 1);
-        }
-#endif
 
         printk(KERN_INFO "GE Intelligent Platforms SBC610 6U VPX SBC\n");
 
@@ -87,6 +80,8 @@ static void __init gef_sbc610_setup_arch(void)
         mpc86xx_smp_init();
 #endif
 
+        fsl_pci_assign_primary();
+
         /* Remap basic board registers */
         regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs");
         if (regs) {
@@ -198,6 +193,7 @@ static long __init mpc86xx_time_init(void)
 static __initdata struct of_device_id of_bus_ids[] = {
         { .compatible = "simple-bus", },
         { .compatible = "gianfar", },
+        { .compatible = "fsl,mpc8641-pcie", },
         {},
 };
 
@@ -208,7 +204,7 @@ static int __init declare_of_platform_devices(void)
 
         return 0;
 }
-machine_device_initcall(gef_sbc610, declare_of_platform_devices);
+machine_arch_initcall(gef_sbc610, declare_of_platform_devices);
 
 define_machine(gef_sbc610) {
         .name                   = "GE SBC610",
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index 62cd3c555bfb..a817398a56da 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -91,6 +91,9 @@ static struct of_device_id __initdata mpc8610_ids[] = {
         { .compatible = "simple-bus", },
         /* So that the DMA channel nodes can be probed individually: */
         { .compatible = "fsl,eloplus-dma", },
+        /* PCI controllers */
+        { .compatible = "fsl,mpc8610-pci", },
+        { .compatible = "fsl,mpc8641-pcie", },
         {}
 };
 
@@ -107,7 +110,7 @@ static int __init mpc8610_declare_of_platform_devices(void)
 
         return 0;
 }
-machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
+machine_arch_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
 
 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
 
@@ -278,25 +281,13 @@ mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port)
 static void __init mpc86xx_hpcd_setup_arch(void)
 {
         struct resource r;
-        struct device_node *np;
         unsigned char *pixis;
 
         if (ppc_md.progress)
                 ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
 
-#ifdef CONFIG_PCI
-        for_each_node_by_type(np, "pci") {
-                if (of_device_is_compatible(np, "fsl,mpc8610-pci")
-                    || of_device_is_compatible(np, "fsl,mpc8641-pcie")) {
-                        struct resource rsrc;
-                        of_address_to_resource(np, 0, &rsrc);
-                        if ((rsrc.start & 0xfffff) == 0xa000)
-                                fsl_add_bridge(np, 1);
-                        else
-                                fsl_add_bridge(np, 0);
-                }
-        }
-#endif
+        fsl_pci_assign_primary();
+
 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
         diu_ops.get_pixel_format        = mpc8610hpcd_get_pixel_format;
         diu_ops.set_gamma_table         = mpc8610hpcd_set_gamma_table;
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index 817245bc0219..e8bf3fae5606 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -19,7 +19,6 @@
 #include <linux/delay.h>
 #include <linux/seq_file.h>
 #include <linux/of_platform.h>
-#include <linux/memblock.h>
 
 #include <asm/time.h>
 #include <asm/machdep.h>
@@ -51,15 +50,8 @@ extern int uli_exclude_device(struct pci_controller *hose,
 static int mpc86xx_exclude_device(struct pci_controller *hose,
                                    u_char bus, u_char devfn)
 {
-        struct device_node* node;       
-        struct resource rsrc;
-
-        node = hose->dn;
-        of_address_to_resource(node, 0, &rsrc);
-
-        if ((rsrc.start & 0xfffff) == 0x8000) {
+        if (hose->dn == fsl_pci_primary)
                 return uli_exclude_device(hose, bus, devfn);
-        }
 
         return PCIBIOS_SUCCESSFUL;
 }
@@ -69,30 +61,11 @@ static int mpc86xx_exclude_device(struct pci_controller *hose,
 static void __init
 mpc86xx_hpcn_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-        struct pci_controller *hose;
-#endif
-        dma_addr_t max = 0xffffffff;
-
         if (ppc_md.progress)
                 ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
 
 #ifdef CONFIG_PCI
-        for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
-                struct resource rsrc;
-                of_address_to_resource(np, 0, &rsrc);
-                if ((rsrc.start & 0xfffff) == 0x8000)
-                        fsl_add_bridge(np, 1);
-                else
-                        fsl_add_bridge(np, 0);
-                hose = pci_find_hose_for_OF_device(np);
-                max = min(max, hose->dma_window_base_cur +
-                          hose->dma_window_size);
-        }
-
         ppc_md.pci_exclude_device = mpc86xx_exclude_device;
-
 #endif
 
         printk("MPC86xx HPCN board from Freescale Semiconductor\n");
@@ -101,13 +74,9 @@ mpc86xx_hpcn_setup_arch(void)
         mpc86xx_smp_init();
 #endif
 
-#ifdef CONFIG_SWIOTLB
-        if ((memblock_end_of_DRAM() - 1) > max) {
-                ppc_swiotlb_enable = 1;
-                set_pci_dma_ops(&swiotlb_dma_ops);
-                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
-        }
-#endif
+        fsl_pci_assign_primary();
+
+        swiotlb_detect_4g();
 }
 
 
@@ -162,6 +131,7 @@ static __initdata struct of_device_id of_bus_ids[] = {
         { .compatible = "simple-bus", },
         { .compatible = "fsl,srio", },
         { .compatible = "gianfar", },
+        { .compatible = "fsl,mpc8641-pcie", },
         {},
 };
 
@@ -171,7 +141,7 @@ static int __init declare_of_platform_devices(void)
 
         return 0;
 }
-machine_device_initcall(mpc86xx_hpcn, declare_of_platform_devices);
+machine_arch_initcall(mpc86xx_hpcn, declare_of_platform_devices);
 machine_arch_initcall(mpc86xx_hpcn, swiotlb_setup_bus_notifier);
 
 define_machine(mpc86xx_hpcn) {
diff --git a/arch/powerpc/platforms/86xx/sbc8641d.c b/arch/powerpc/platforms/86xx/sbc8641d.c
index e7007d0d949e..b47a8fd0f3d3 100644
--- a/arch/powerpc/platforms/86xx/sbc8641d.c
+++ b/arch/powerpc/platforms/86xx/sbc8641d.c
@@ -38,23 +38,16 @@
 static void __init
 sbc8641_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
-
         if (ppc_md.progress)
                 ppc_md.progress("sbc8641_setup_arch()", 0);
 
-#ifdef CONFIG_PCI
-        for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie")
-                fsl_add_bridge(np, 0);
-#endif
-
         printk("SBC8641 board from Wind River\n");
 
 #ifdef CONFIG_SMP
         mpc86xx_smp_init();
 #endif
+
+        fsl_pci_assign_primary();
 }
 
 
@@ -102,6 +95,7 @@ mpc86xx_time_init(void)
 static __initdata struct of_device_id of_bus_ids[] = {
         { .compatible = "simple-bus", },
         { .compatible = "gianfar", },
+        { .compatible = "fsl,mpc8641-pcie", },
         {},
 };
 
@@ -111,7 +105,7 @@ static int __init declare_of_platform_devices(void)
 
         return 0;
 }
-machine_device_initcall(sbc8641, declare_of_platform_devices);
+machine_arch_initcall(sbc8641, declare_of_platform_devices);
 
 define_machine(sbc8641) {
         .name                   = "SBC8641D",
diff --git a/arch/powerpc/platforms/cell/beat.c b/arch/powerpc/platforms/cell/beat.c
index 852592b2b712..affcf566d460 100644
--- a/arch/powerpc/platforms/cell/beat.c
+++ b/arch/powerpc/platforms/cell/beat.c
@@ -136,9 +136,9 @@ ssize_t beat_nvram_get_size(void)
         return BEAT_NVRAM_SIZE;
 }
 
-int beat_set_xdabr(unsigned long dabr)
+int beat_set_xdabr(unsigned long dabr, unsigned long dabrx)
 {
-        if (beat_set_dabr(dabr, DABRX_KERNEL | DABRX_USER))
+        if (beat_set_dabr(dabr, dabrx))
                 return -1;
         return 0;
 }
diff --git a/arch/powerpc/platforms/cell/beat.h b/arch/powerpc/platforms/cell/beat.h
index 32c8efcedc80..bfcb8e351ae5 100644
--- a/arch/powerpc/platforms/cell/beat.h
+++ b/arch/powerpc/platforms/cell/beat.h
@@ -32,7 +32,7 @@ void beat_get_rtc_time(struct rtc_time *);
 ssize_t beat_nvram_get_size(void);
 ssize_t beat_nvram_read(char *, size_t, loff_t *);
 ssize_t beat_nvram_write(char *, size_t, loff_t *);
-int beat_set_xdabr(unsigned long);
+int beat_set_xdabr(unsigned long, unsigned long);
 void beat_power_save(void);
 void beat_kexec_cpu_down(int, int);
 
diff --git a/arch/powerpc/platforms/cell/beat_htab.c b/arch/powerpc/platforms/cell/beat_htab.c
index 943c9d39aa16..0f6f83988b3d 100644
--- a/arch/powerpc/platforms/cell/beat_htab.c
+++ b/arch/powerpc/platforms/cell/beat_htab.c
@@ -88,7 +88,7 @@ static inline unsigned int beat_read_mask(unsigned hpte_group)
 }
 
 static long beat_lpar_hpte_insert(unsigned long hpte_group,
-                                  unsigned long va, unsigned long pa,
+                                  unsigned long vpn, unsigned long pa,
                                   unsigned long rflags, unsigned long vflags,
                                   int psize, int ssize)
 {
@@ -103,7 +103,7 @@ static long beat_lpar_hpte_insert(unsigned long hpte_group,
                         "rflags=%lx, vflags=%lx, psize=%d)\n",
                 hpte_group, va, pa, rflags, vflags, psize);
 
-        hpte_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M) |
+        hpte_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M) |
                 vflags | HPTE_V_VALID;
         hpte_r = hpte_encode_r(pa, psize) | rflags;
 
@@ -184,14 +184,14 @@ static void beat_lpar_hptab_clear(void)
  */
 static long beat_lpar_hpte_updatepp(unsigned long slot,
                                     unsigned long newpp,
-                                    unsigned long va,
+                                    unsigned long vpn,
                                     int psize, int ssize, int local)
 {
         unsigned long lpar_rc;
         u64 dummy0, dummy1;
         unsigned long want_v;
 
-        want_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M);
+        want_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M);
 
         DBG_LOW("    update: "
                 "avpnv=%016lx, slot=%016lx, psize: %d, newpp %016lx ... ",
@@ -220,15 +220,15 @@ static long beat_lpar_hpte_updatepp(unsigned long slot,
         return 0;
 }
 
-static long beat_lpar_hpte_find(unsigned long va, int psize)
+static long beat_lpar_hpte_find(unsigned long vpn, int psize)
 {
         unsigned long hash;
         unsigned long i, j;
         long slot;
         unsigned long want_v, hpte_v;
 
-        hash = hpt_hash(va, mmu_psize_defs[psize].shift, MMU_SEGSIZE_256M);
-        want_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M);
+        hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, MMU_SEGSIZE_256M);
+        want_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M);
 
         for (j = 0; j < 2; j++) {
                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
@@ -255,14 +255,15 @@ static void beat_lpar_hpte_updateboltedpp(unsigned long newpp,
                                           unsigned long ea,
                                           int psize, int ssize)
 {
-        unsigned long lpar_rc, slot, vsid, va;
+        unsigned long vpn;
+        unsigned long lpar_rc, slot, vsid;
         u64 dummy0, dummy1;
 
         vsid = get_kernel_vsid(ea, MMU_SEGSIZE_256M);
-        va = (vsid << 28) | (ea & 0x0fffffff);
+        vpn = hpt_vpn(ea, vsid, MMU_SEGSIZE_256M);
 
         raw_spin_lock(&beat_htab_lock);
-        slot = beat_lpar_hpte_find(va, psize);
+        slot = beat_lpar_hpte_find(vpn, psize);
         BUG_ON(slot == -1);
 
         lpar_rc = beat_write_htab_entry(0, slot, 0, newpp, 0, 7,
@@ -272,7 +273,7 @@ static void beat_lpar_hpte_updateboltedpp(unsigned long newpp,
         BUG_ON(lpar_rc != 0);
 }
 
-static void beat_lpar_hpte_invalidate(unsigned long slot, unsigned long va,
+static void beat_lpar_hpte_invalidate(unsigned long slot, unsigned long vpn,
                                          int psize, int ssize, int local)
 {
         unsigned long want_v;
@@ -282,7 +283,7 @@ static void beat_lpar_hpte_invalidate(unsigned long slot, unsigned long va,
 
         DBG_LOW("    inval : slot=%lx, va=%016lx, psize: %d, local: %d\n",
                 slot, va, psize, local);
-        want_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M);
+        want_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M);
 
         raw_spin_lock_irqsave(&beat_htab_lock, flags);
         dummy1 = beat_lpar_hpte_getword0(slot);
@@ -311,7 +312,7 @@ void __init hpte_init_beat(void)
 }
 
 static long beat_lpar_hpte_insert_v3(unsigned long hpte_group,
-                                  unsigned long va, unsigned long pa,
+                                  unsigned long vpn, unsigned long pa,
                                   unsigned long rflags, unsigned long vflags,
                                   int psize, int ssize)
 {
@@ -322,11 +323,11 @@ static long beat_lpar_hpte_insert_v3(unsigned long hpte_group,
                 return -1;
 
         if (!(vflags & HPTE_V_BOLTED))
-                DBG_LOW("hpte_insert(group=%lx, va=%016lx, pa=%016lx, "
+                DBG_LOW("hpte_insert(group=%lx, vpn=%016lx, pa=%016lx, "
                         "rflags=%lx, vflags=%lx, psize=%d)\n",
-                hpte_group, va, pa, rflags, vflags, psize);
+                hpte_group, vpn, pa, rflags, vflags, psize);
 
-        hpte_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M) |
+        hpte_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M) |
                 vflags | HPTE_V_VALID;
         hpte_r = hpte_encode_r(pa, psize) | rflags;
 
@@ -364,14 +365,14 @@ static long beat_lpar_hpte_insert_v3(unsigned long hpte_group,
  */
 static long beat_lpar_hpte_updatepp_v3(unsigned long slot,
                                     unsigned long newpp,
-                                    unsigned long va,
+                                    unsigned long vpn,
                                     int psize, int ssize, int local)
 {
         unsigned long lpar_rc;
         unsigned long want_v;
         unsigned long pss;
 
-        want_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M);
+        want_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M);
         pss = (psize == MMU_PAGE_4K) ? -1UL : mmu_psize_defs[psize].penc;
 
         DBG_LOW("    update: "
@@ -392,16 +393,16 @@ static long beat_lpar_hpte_updatepp_v3(unsigned long slot,
         return 0;
 }
 
-static void beat_lpar_hpte_invalidate_v3(unsigned long slot, unsigned long va,
+static void beat_lpar_hpte_invalidate_v3(unsigned long slot, unsigned long vpn,
                                          int psize, int ssize, int local)
 {
         unsigned long want_v;
         unsigned long lpar_rc;
         unsigned long pss;
 
-        DBG_LOW("    inval : slot=%lx, va=%016lx, psize: %d, local: %d\n",
-                slot, va, psize, local);
-        want_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M);
+        DBG_LOW("    inval : slot=%lx, vpn=%016lx, psize: %d, local: %d\n",
+                slot, vpn, psize, local);
+        want_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M);
         pss = (psize == MMU_PAGE_4K) ? -1UL : mmu_psize_defs[psize].penc;
 
         lpar_rc = beat_invalidate_htab_entry3(0, slot, want_v, pss);
diff --git a/arch/powerpc/platforms/pasemi/iommu.c b/arch/powerpc/platforms/pasemi/iommu.c
index 14943ef01918..7d2d036754b5 100644
--- a/arch/powerpc/platforms/pasemi/iommu.c
+++ b/arch/powerpc/platforms/pasemi/iommu.c
@@ -19,12 +19,12 @@
 
 #undef DEBUG
 
+#include <linux/memblock.h>
 #include <linux/types.h>
 #include <linux/spinlock.h>
 #include <linux/pci.h>
 #include <asm/iommu.h>
 #include <asm/machdep.h>
-#include <asm/abs_addr.h>
 #include <asm/firmware.h>
 
 #define IOBMAP_PAGE_SHIFT       12
@@ -99,7 +99,7 @@ static int iobmap_build(struct iommu_table *tbl, long index,
         ip = ((u32 *)tbl->it_base) + index;
 
         while (npages--) {
-                rpn = virt_to_abs(uaddr) >> IOBMAP_PAGE_SHIFT;
+                rpn = __pa(uaddr) >> IOBMAP_PAGE_SHIFT;
 
                 *(ip++) = IOBMAP_L2E_V | rpn;
                 /* invalidate tlb, can be optimized more */
@@ -258,7 +258,7 @@ void __init alloc_iobmap_l2(void)
         return;
 #endif
         /* For 2G space, 8x64 pages (2^21 bytes) is max total l2 size */
-        iob_l2_base = (u32 *)abs_to_virt(memblock_alloc_base(1UL<<21, 1UL<<21, 0x80000000));
+        iob_l2_base = (u32 *)__va(memblock_alloc_base(1UL<<21, 1UL<<21, 0x80000000));
 
         printk(KERN_INFO "IOBMAP L2 allocated at: %p\n", iob_l2_base);
 }
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 0e7eccc0f88d..471aa3ccd9fd 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -30,19 +30,10 @@
 #include <asm/opal.h>
 #include <asm/iommu.h>
 #include <asm/tce.h>
-#include <asm/abs_addr.h>
 
 #include "powernv.h"
 #include "pci.h"
 
-struct resource_wrap {
-        struct list_head        link;
-        resource_size_t         size;
-        resource_size_t         align;
-        struct pci_dev          *dev;   /* Set if it's a device */
-        struct pci_bus          *bus;   /* Set if it's a bridge */
-};
-
 static int __pe_printk(const char *level, const struct pnv_ioda_pe *pe,
                        struct va_format *vaf)
 {
@@ -78,273 +69,6 @@ define_pe_printk_level(pe_err, KERN_ERR);
 define_pe_printk_level(pe_warn, KERN_WARNING);
 define_pe_printk_level(pe_info, KERN_INFO);
 
-
-/* Calculate resource usage & alignment requirement of a single
- * device. This will also assign all resources within the device
- * for a given type starting at 0 for the biggest one and then
- * assigning in decreasing order of size.
- */
-static void __devinit pnv_ioda_calc_dev(struct pci_dev *dev, unsigned int flags,
-                                        resource_size_t *size,
-                                        resource_size_t *align)
-{
-        resource_size_t start;
-        struct resource *r;
-        int i;
-
-        pr_devel("  -> CDR %s\n", pci_name(dev));
-
-        *size = *align = 0;
-
-        /* Clear the resources out and mark them all unset */
-        for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
-                r = &dev->resource[i];
-                if (!(r->flags & flags))
-                    continue;
-                if (r->start) {
-                        r->end -= r->start;
-                        r->start = 0;
-                }
-                r->flags |= IORESOURCE_UNSET;
-        }
-
-        /* We currently keep all memory resources together, we
-         * will handle prefetch & 64-bit separately in the future
-         * but for now we stick everybody in M32
-         */
-        start = 0;
-        for (;;) {
-                resource_size_t max_size = 0;
-                int max_no = -1;
-
-                /* Find next biggest resource */
-                for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
-                        r = &dev->resource[i];
-                        if (!(r->flags & IORESOURCE_UNSET) ||
-                            !(r->flags & flags))
-                                continue;
-                        if (resource_size(r) > max_size) {
-                                max_size = resource_size(r);
-                                max_no = i;
-                        }
-                }
-                if (max_no < 0)
-                        break;
-                r = &dev->resource[max_no];
-                if (max_size > *align)
-                        *align = max_size;
-                *size += max_size;
-                r->start = start;
-                start += max_size;
-                r->end = r->start + max_size - 1;
-                r->flags &= ~IORESOURCE_UNSET;
-                pr_devel("  ->     R%d %016llx..%016llx\n",
-                         max_no, r->start, r->end);
-        }
-        pr_devel("  <- CDR %s size=%llx align=%llx\n",
-                 pci_name(dev), *size, *align);
-}
-
-/* Allocate a resource "wrap" for a given device or bridge and
- * insert it at the right position in the sorted list
- */
-static void __devinit pnv_ioda_add_wrap(struct list_head *list,
-                                        struct pci_bus *bus,
-                                        struct pci_dev *dev,
-                                        resource_size_t size,
-                                        resource_size_t align)
-{
-        struct resource_wrap *w1, *w = kzalloc(sizeof(*w), GFP_KERNEL);
-
-        w->size = size;
-        w->align = align;
-        w->dev = dev;
-        w->bus = bus;
-
-        list_for_each_entry(w1, list, link) {
-                if (w1->align < align) {
-                        list_add_tail(&w->link, &w1->link);
-                        return;
-                }
-        }
-        list_add_tail(&w->link, list);
-}
-
-/* Offset device resources of a given type */
-static void __devinit pnv_ioda_offset_dev(struct pci_dev *dev,
-                                          unsigned int flags,
-                                          resource_size_t offset)
-{
-        struct resource *r;
-        int i;
-
-        pr_devel("  -> ODR %s [%x] +%016llx\n", pci_name(dev), flags, offset);
-
-        for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
-                r = &dev->resource[i];
-                if (r->flags & flags) {
-                        dev->resource[i].start += offset;
-                        dev->resource[i].end += offset;
-                }
-        }
-
-        pr_devel("  <- ODR %s [%x] +%016llx\n", pci_name(dev), flags, offset);
-}
-
-/* Offset bus resources (& all children) of a given type */
-static void __devinit pnv_ioda_offset_bus(struct pci_bus *bus,
-                                          unsigned int flags,
-                                          resource_size_t offset)
-{
-        struct resource *r;
-        struct pci_dev *dev;
-        struct pci_bus *cbus;
-        int i;
-
-        pr_devel("  -> OBR %s [%x] +%016llx\n",
-                 bus->self ? pci_name(bus->self) : "root", flags, offset);
-
-        pci_bus_for_each_resource(bus, r, i) {
-                if (r && (r->flags & flags)) {
-                        r->start += offset;
-                        r->end += offset;
-                }
-        }
-        list_for_each_entry(dev, &bus->devices, bus_list)
-                pnv_ioda_offset_dev(dev, flags, offset);
-        list_for_each_entry(cbus, &bus->children, node)
-                pnv_ioda_offset_bus(cbus, flags, offset);
-
-        pr_devel("  <- OBR %s [%x]\n",
-                 bus->self ? pci_name(bus->self) : "root", flags);
-}
-
-/* This is the guts of our IODA resource allocation. This is called
- * recursively for each bus in the system. It calculates all the
- * necessary size and requirements for children and assign them
- * resources such that:
- *
- *   - Each function fits in it's own contiguous set of IO/M32
- *     segment
- *
- *   - All segments behind a P2P bridge are contiguous and obey
- *     alignment constraints of those bridges
- */
-static void __devinit pnv_ioda_calc_bus(struct pci_bus *bus, unsigned int flags,
-                                        resource_size_t *size,
-                                        resource_size_t *align)
-{
-        struct pci_controller *hose = pci_bus_to_host(bus);
-        struct pnv_phb *phb = hose->private_data;
-        resource_size_t dev_size, dev_align, start;
-        resource_size_t min_align, min_balign;
-        struct pci_dev *cdev;
-        struct pci_bus *cbus;
-        struct list_head head;
-        struct resource_wrap *w;
-        unsigned int bres;
-
-        *size = *align = 0;
-
-        pr_devel("-> CBR %s [%x]\n",
-                 bus->self ? pci_name(bus->self) : "root", flags);
-
-        /* Calculate alignment requirements based on the type
-         * of resource we are working on
-         */
-        if (flags & IORESOURCE_IO) {
-                bres = 0;
-                min_align = phb->ioda.io_segsize;
-                min_balign = 0x1000;
-        } else {
-                bres = 1;
-                min_align = phb->ioda.m32_segsize;
-                min_balign = 0x100000;
-        }
-
-        /* Gather all our children resources ordered by alignment */
-        INIT_LIST_HEAD(&head);
-
-        /*   - Busses */
-        list_for_each_entry(cbus, &bus->children, node) {
-                pnv_ioda_calc_bus(cbus, flags, &dev_size, &dev_align);
-                pnv_ioda_add_wrap(&head, cbus, NULL, dev_size, dev_align);
-        }
-
-        /*   - Devices */
-        list_for_each_entry(cdev, &bus->devices, bus_list) {
-                pnv_ioda_calc_dev(cdev, flags, &dev_size, &dev_align);
-                /* Align them to segment size */
-                if (dev_align < min_align)
-                        dev_align = min_align;
-                pnv_ioda_add_wrap(&head, NULL, cdev, dev_size, dev_align);
-        }
-        if (list_empty(&head))
-                goto empty;
-
-        /* Now we can do two things: assign offsets to them within that
-         * level and get our total alignment & size requirements. The
-         * assignment algorithm is going to be uber-trivial for now, we
-         * can try to be smarter later at filling out holes.
-         */
-        if (bus->self) {
-                /* No offset for downstream bridges */
-                start = 0;
-        } else {
-                /* Offset from the root */
-                if (flags & IORESOURCE_IO)
-                        /* Don't hand out IO 0 */
-                        start = hose->io_resource.start + 0x1000;
-                else
-                        start = hose->mem_resources[0].start;
-        }
-        while(!list_empty(&head)) {
-                w = list_first_entry(&head, struct resource_wrap, link);
-                list_del(&w->link);
-                if (w->size) {
-                        if (start) {
-                                start = ALIGN(start, w->align);
-                                if (w->dev)
-                                        pnv_ioda_offset_dev(w->dev,flags,start);
-                                else if (w->bus)
-                                        pnv_ioda_offset_bus(w->bus,flags,start);
-                        }
-                        if (w->align > *align)
-                                *align = w->align;
-                }
-                start += w->size;
-                kfree(w);
-        }
-        *size = start;
-
-        /* Align and setup bridge resources */
-        *align = max_t(resource_size_t, *align,
-                       max_t(resource_size_t, min_align, min_balign));
-        *size = ALIGN(*size,
-                      max_t(resource_size_t, min_align, min_balign));
- empty:
-        /* Only setup P2P's, not the PHB itself */
-        if (bus->self) {
-                struct resource *res = bus->resource[bres];
-
-                if (WARN_ON(res == NULL))
-                        return;
-
-                /*
-                 * FIXME: We should probably export and call
-                 * pci_bridge_check_ranges() to properly re-initialize
-                 * the PCI portion of the flags here, and to detect
-                 * what the bridge actually supports.
-                 */
-                res->start = 0;
-                res->flags = (*size) ? flags : 0;
-                res->end = (*size) ? (*size - 1) : 0;
-        }
-
-        pr_devel("<- CBR %s [%x] *size=%016llx *align=%016llx\n",
-                 bus->self ? pci_name(bus->self) : "root", flags,*size,*align);
-}
-
 static struct pci_dn *pnv_ioda_get_pdn(struct pci_dev *dev)
 {
         struct device_node *np;
@@ -355,172 +79,6 @@ static struct pci_dn *pnv_ioda_get_pdn(struct pci_dev *dev)
         return PCI_DN(np);
 }
 
-static void __devinit pnv_ioda_setup_pe_segments(struct pci_dev *dev)
-{
-        struct pci_controller *hose = pci_bus_to_host(dev->bus);
-        struct pnv_phb *phb = hose->private_data;
-        struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
-        unsigned int pe, i;
-        resource_size_t pos;
-        struct resource io_res;
-        struct resource m32_res;
-        struct pci_bus_region region;
-        int rc;
-
-        /* Anything not referenced in the device-tree gets PE#0 */
-        pe = pdn ? pdn->pe_number : 0;
-
-        /* Calculate the device min/max */
-        io_res.start = m32_res.start = (resource_size_t)-1;
-        io_res.end = m32_res.end = 0;
-        io_res.flags = IORESOURCE_IO;
-        m32_res.flags = IORESOURCE_MEM;
-
-        for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
-                struct resource *r = NULL;
-                if (dev->resource[i].flags & IORESOURCE_IO)
-                        r = &io_res;
-                if (dev->resource[i].flags & IORESOURCE_MEM)
-                        r = &m32_res;
-                if (!r)
-                        continue;
-                if (dev->resource[i].start < r->start)
-                        r->start = dev->resource[i].start;
-                if (dev->resource[i].end > r->end)
-                        r->end = dev->resource[i].end;
-        }
-
-        /* Setup IO segments */
-        if (io_res.start < io_res.end) {
-                pcibios_resource_to_bus(dev, &region, &io_res);
-                pos = region.start;
-                i = pos / phb->ioda.io_segsize;
-                while(i < phb->ioda.total_pe && pos <= region.end) {
-                        if (phb->ioda.io_segmap[i]) {
-                                pr_err("%s: Trying to use IO seg #%d which is"
-                                       " already used by PE# %d\n",
-                                       pci_name(dev), i,
-                                       phb->ioda.io_segmap[i]);
-                                /* XXX DO SOMETHING TO DISABLE DEVICE ? */
-                                break;
-                        }
-                        phb->ioda.io_segmap[i] = pe;
-                        rc = opal_pci_map_pe_mmio_window(phb->opal_id, pe,
-                                                         OPAL_IO_WINDOW_TYPE,
-                                                         0, i);
-                        if (rc != OPAL_SUCCESS) {
-                                pr_err("%s: OPAL error %d setting up mapping"
-                                       " for IO seg# %d\n",
-                                       pci_name(dev), rc, i);
-                                /* XXX DO SOMETHING TO DISABLE DEVICE ? */
-                                break;
-                        }
-                        pos += phb->ioda.io_segsize;
-                        i++;
-                };
-        }
-
-        /* Setup M32 segments */
-        if (m32_res.start < m32_res.end) {
-                pcibios_resource_to_bus(dev, &region, &m32_res);
-                pos = region.start;
-                i = pos / phb->ioda.m32_segsize;
-                while(i < phb->ioda.total_pe && pos <= region.end) {
-                        if (phb->ioda.m32_segmap[i]) {
-                                pr_err("%s: Trying to use M32 seg #%d which is"
-                                       " already used by PE# %d\n",
-                                       pci_name(dev), i,
-                                       phb->ioda.m32_segmap[i]);
-                                /* XXX DO SOMETHING TO DISABLE DEVICE ? */
-                                break;
-                        }
-                        phb->ioda.m32_segmap[i] = pe;
-                        rc = opal_pci_map_pe_mmio_window(phb->opal_id, pe,
-                                                         OPAL_M32_WINDOW_TYPE,
-                                                         0, i);
-                        if (rc != OPAL_SUCCESS) {
-                                pr_err("%s: OPAL error %d setting up mapping"
-                                       " for M32 seg# %d\n",
-                                       pci_name(dev), rc, i);
-                                /* XXX DO SOMETHING TO DISABLE DEVICE ? */
-                                break;
-                        }
-                        pos += phb->ioda.m32_segsize;
-                        i++;
-                }
-        }
-}
-
-/* Check if a resource still fits in the total IO or M32 range
- * for a given PHB
- */
-static int __devinit pnv_ioda_resource_fit(struct pci_controller *hose,
-                                           struct resource *r)
-{
-        struct resource *bounds;
-
-        if (r->flags & IORESOURCE_IO)
-                bounds = &hose->io_resource;
-        else if (r->flags & IORESOURCE_MEM)
-                bounds = &hose->mem_resources[0];
-        else
-                return 1;
-
-        if (r->start >= bounds->start && r->end <= bounds->end)
-                return 1;
-        r->flags = 0;
-        return 0;
-}
-
-static void __devinit pnv_ioda_update_resources(struct pci_bus *bus)
-{
-        struct pci_controller *hose = pci_bus_to_host(bus);
-        struct pci_bus *cbus;
-        struct pci_dev *cdev;
-        unsigned int i;
-
-        /* We used to clear all device enables here. However it looks like
-         * clearing MEM enable causes Obsidian (IPR SCS) to go bonkers,
-         * and shoot fatal errors to the PHB which in turns fences itself
-         * and we can't recover from that ... yet. So for now, let's leave
-         * the enables as-is and hope for the best.
-         */
-
-        /* Check if bus resources fit in our IO or M32 range */
-        for (i = 0; bus->self && (i < 2); i++) {
-                struct resource *r = bus->resource[i];
-                if (r && !pnv_ioda_resource_fit(hose, r))
-                        pr_err("%s: Bus %d resource %d disabled, no room\n",
-                               pci_name(bus->self), bus->number, i);
-        }
-
-        /* Update self if it's not a PHB */
-        if (bus->self)
-                pci_setup_bridge(bus);
-
-        /* Update child devices */
-        list_for_each_entry(cdev, &bus->devices, bus_list) {
-                /* Check if resource fits, if not, disabled it */
-                for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
-                        struct resource *r = &cdev->resource[i];
-                        if (!pnv_ioda_resource_fit(hose, r))
-                                pr_err("%s: Resource %d disabled, no room\n",
-                                       pci_name(cdev), i);
-                }
-
-                /* Assign segments */
-                pnv_ioda_setup_pe_segments(cdev);
-
-                /* Update HW BARs */
-                for (i = 0; i <= PCI_ROM_RESOURCE; i++)
-                        pci_update_resource(cdev, i);
-        }
-
-        /* Update child busses */
-        list_for_each_entry(cbus, &bus->children, node)
-                pnv_ioda_update_resources(cbus);
-}
-
 static int __devinit pnv_ioda_alloc_pe(struct pnv_phb *phb)
 {
         unsigned long pe;
@@ -548,7 +106,7 @@ static void __devinit pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
  * but in the meantime, we need to protect them to avoid warnings
  */
 #ifdef CONFIG_PCI_MSI
-static struct pnv_ioda_pe * __devinit __pnv_ioda_get_one_pe(struct pci_dev *dev)
+static struct pnv_ioda_pe * __devinit pnv_ioda_get_pe(struct pci_dev *dev)
 {
         struct pci_controller *hose = pci_bus_to_host(dev->bus);
         struct pnv_phb *phb = hose->private_data;
@@ -560,19 +118,6 @@ static struct pnv_ioda_pe * __devinit __pnv_ioda_get_one_pe(struct pci_dev *dev)
                 return NULL;
         return &phb->ioda.pe_array[pdn->pe_number];
 }
-
-static struct pnv_ioda_pe * __devinit pnv_ioda_get_pe(struct pci_dev *dev)
-{
-        struct pnv_ioda_pe *pe = __pnv_ioda_get_one_pe(dev);
-
-        while (!pe && dev->bus->self) {
-                dev = dev->bus->self;
-                pe = __pnv_ioda_get_one_pe(dev);
-                if (pe)
-                        pe = pe->bus_pe;
-        }
-        return pe;
-}
 #endif /* CONFIG_PCI_MSI */
 
 static int __devinit pnv_ioda_configure_pe(struct pnv_phb *phb,
@@ -589,7 +134,11 @@ static int __devinit pnv_ioda_configure_pe(struct pnv_phb *phb,
                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
                 parent = pe->pbus->self;
-                count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
+                if (pe->flags & PNV_IODA_PE_BUS_ALL)
+                        count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
+                else
+                        count = 1;
+
                 switch(count) {
                 case  1: bcomp = OpalPciBusAll;         break;
                 case  2: bcomp = OpalPciBus7Bits;       break;
@@ -666,13 +215,13 @@ static void __devinit pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
 {
         struct pnv_ioda_pe *lpe;
 
-        list_for_each_entry(lpe, &phb->ioda.pe_list, link) {
+        list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
                 if (lpe->dma_weight < pe->dma_weight) {
-                        list_add_tail(&pe->link, &lpe->link);
+                        list_add_tail(&pe->dma_link, &lpe->dma_link);
                         return;
                 }
         }
-        list_add_tail(&pe->link, &phb->ioda.pe_list);
+        list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
 }
 
 static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
@@ -699,6 +248,7 @@ static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
         return 10;
 }
 
+#if 0
 static struct pnv_ioda_pe * __devinit pnv_ioda_setup_dev_PE(struct pci_dev *dev)
 {
         struct pci_controller *hose = pci_bus_to_host(dev->bus);
@@ -767,6 +317,7 @@ static struct pnv_ioda_pe * __devinit pnv_ioda_setup_dev_PE(struct pci_dev *dev)
 
         return pe;
 }
+#endif /* Useful for SRIOV case */
 
 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
 {
@@ -784,34 +335,33 @@ static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
                 pdn->pcidev = dev;
                 pdn->pe_number = pe->pe_number;
                 pe->dma_weight += pnv_ioda_dma_weight(dev);
-                if (dev->subordinate)
+                if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
         }
 }
 
-static void __devinit pnv_ioda_setup_bus_PE(struct pci_dev *dev,
-                                            struct pnv_ioda_pe *ppe)
+/*
+ * There're 2 types of PCI bus sensitive PEs: One that is compromised of
+ * single PCI bus. Another one that contains the primary PCI bus and its
+ * subordinate PCI devices and buses. The second type of PE is normally
+ * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
+ */
+static void __devinit pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all)
 {
-        struct pci_controller *hose = pci_bus_to_host(dev->bus);
+        struct pci_controller *hose = pci_bus_to_host(bus);
         struct pnv_phb *phb = hose->private_data;
-        struct pci_bus *bus = dev->subordinate;
         struct pnv_ioda_pe *pe;
         int pe_num;
 
-        if (!bus) {
-                pr_warning("%s: Bridge without a subordinate bus !\n",
-                           pci_name(dev));
-                return;
-        }
         pe_num = pnv_ioda_alloc_pe(phb);
         if (pe_num == IODA_INVALID_PE) {
-                pr_warning("%s: Not enough PE# available, disabling bus\n",
-                           pci_name(dev));
+                pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
+                        __func__, pci_domain_nr(bus), bus->number);
                 return;
         }
 
         pe = &phb->ioda.pe_array[pe_num];
-        ppe->bus_pe = pe;
+        pe->flags = (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
         pe->pbus = bus;
         pe->pdev = NULL;
         pe->tce32_seg = -1;
@@ -819,8 +369,12 @@ static void __devinit pnv_ioda_setup_bus_PE(struct pci_dev *dev,
         pe->rid = bus->busn_res.start << 8;
         pe->dma_weight = 0;
 
-        pe_info(pe, "Secondary busses %pR associated with PE\n",
-                &bus->busn_res);
+        if (all)
+                pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
+                        bus->busn_res.start, bus->busn_res.end, pe_num);
+        else
+                pe_info(pe, "Secondary bus %d associated with PE#%d\n",
+                        bus->busn_res.start, pe_num);
 
         if (pnv_ioda_configure_pe(phb, pe)) {
                 /* XXX What do we do here ? */
@@ -833,6 +387,9 @@ static void __devinit pnv_ioda_setup_bus_PE(struct pci_dev *dev,
         /* Associate it with all child devices */
         pnv_ioda_setup_same_PE(bus, pe);
 
+        /* Put PE to the list */
+        list_add_tail(&pe->list, &phb->ioda.pe_list);
+
         /* Account for one DMA PE if at least one DMA capable device exist
          * below the bridge
          */
@@ -848,17 +405,33 @@ static void __devinit pnv_ioda_setup_bus_PE(struct pci_dev *dev,
 static void __devinit pnv_ioda_setup_PEs(struct pci_bus *bus)
 {
         struct pci_dev *dev;
-        struct pnv_ioda_pe *pe;
+
+        pnv_ioda_setup_bus_PE(bus, 0);
 
         list_for_each_entry(dev, &bus->devices, bus_list) {
-                pe = pnv_ioda_setup_dev_PE(dev);
-                if (pe == NULL)
-                        continue;
-                /* Leaving the PCIe domain ... single PE# */
-                if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
-                        pnv_ioda_setup_bus_PE(dev, pe);
-                else if (dev->subordinate)
-                        pnv_ioda_setup_PEs(dev->subordinate);
+                if (dev->subordinate) {
+                        if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
+                                pnv_ioda_setup_bus_PE(dev->subordinate, 1);
+                        else
+                                pnv_ioda_setup_PEs(dev->subordinate);
+                }
+        }
+}
+
+/*
+ * Configure PEs so that the downstream PCI buses and devices
+ * could have their associated PE#. Unfortunately, we didn't
+ * figure out the way to identify the PLX bridge yet. So we
+ * simply put the PCI bus and the subordinate behind the root
+ * port to PE# here. The game rule here is expected to be changed
+ * as soon as we can detected PLX bridge correctly.
+ */
+static void __devinit pnv_pci_ioda_setup_PEs(void)
+{
+        struct pci_controller *hose, *tmp;
+
+        list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
+                pnv_ioda_setup_PEs(hose->bus);
         }
 }
 
@@ -1000,7 +573,7 @@ static void __devinit pnv_ioda_setup_dma(struct pnv_phb *phb)
         remaining = phb->ioda.tce32_count;
         tw = phb->ioda.dma_weight;
         base = 0;
-        list_for_each_entry(pe, &phb->ioda.pe_list, link) {
+        list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
                 if (!pe->dma_weight)
                         continue;
                 if (!remaining) {
@@ -1109,36 +682,115 @@ static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
 #endif /* CONFIG_PCI_MSI */
 
-/* This is the starting point of our IODA specific resource
- * allocation process
+/*
+ * This function is supposed to be called on basis of PE from top
+ * to bottom style. So the the I/O or MMIO segment assigned to
+ * parent PE could be overrided by its child PEs if necessary.
  */
-static void __devinit pnv_pci_ioda_fixup_phb(struct pci_controller *hose)
+static void __devinit pnv_ioda_setup_pe_seg(struct pci_controller *hose,
+                                struct pnv_ioda_pe *pe)
 {
-        resource_size_t size, align;
-        struct pci_bus *child;
+        struct pnv_phb *phb = hose->private_data;
+        struct pci_bus_region region;
+        struct resource *res;
+        int i, index;
+        int rc;
 
-        /* Associate PEs per functions */
-        pnv_ioda_setup_PEs(hose->bus);
+        /*
+         * NOTE: We only care PCI bus based PE for now. For PCI
+         * device based PE, for example SRIOV sensitive VF should
+         * be figured out later.
+         */
+        BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
 
-        /* Calculate all resources */
-        pnv_ioda_calc_bus(hose->bus, IORESOURCE_IO, &size, &align);
-        pnv_ioda_calc_bus(hose->bus, IORESOURCE_MEM, &size, &align);
+        pci_bus_for_each_resource(pe->pbus, res, i) {
+                if (!res || !res->flags ||
+                    res->start > res->end)
+                        continue;
 
-        /* Apply then to HW */
-        pnv_ioda_update_resources(hose->bus);
+                if (res->flags & IORESOURCE_IO) {
+                        region.start = res->start - phb->ioda.io_pci_base;
+                        region.end   = res->end - phb->ioda.io_pci_base;
+                        index = region.start / phb->ioda.io_segsize;
+
+                        while (index < phb->ioda.total_pe &&
+                               region.start <= region.end) {
+                                phb->ioda.io_segmap[index] = pe->pe_number;
+                                rc = opal_pci_map_pe_mmio_window(phb->opal_id,
+                                        pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
+                                if (rc != OPAL_SUCCESS) {
+                                        pr_err("%s: OPAL error %d when mapping IO "
+                                               "segment #%d to PE#%d\n",
+                                               __func__, rc, index, pe->pe_number);
+                                        break;
+                                }
+
+                                region.start += phb->ioda.io_segsize;
+                                index++;
+                        }
+                } else if (res->flags & IORESOURCE_MEM) {
+                        region.start = res->start -
+                                       hose->pci_mem_offset -
+                                       phb->ioda.m32_pci_base;
+                        region.end   = res->end -
+                                       hose->pci_mem_offset -
+                                       phb->ioda.m32_pci_base;
+                        index = region.start / phb->ioda.m32_segsize;
+
+                        while (index < phb->ioda.total_pe &&
+                               region.start <= region.end) {
+                                phb->ioda.m32_segmap[index] = pe->pe_number;
+                                rc = opal_pci_map_pe_mmio_window(phb->opal_id,
+                                        pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
+                                if (rc != OPAL_SUCCESS) {
+                                        pr_err("%s: OPAL error %d when mapping M32 "
+                                               "segment#%d to PE#%d",
+                                               __func__, rc, index, pe->pe_number);
+                                        break;
+                                }
+
+                                region.start += phb->ioda.m32_segsize;
+                                index++;
+                        }
+                }
+        }
+}
 
-        /* Setup DMA */
-        pnv_ioda_setup_dma(hose->private_data);
+static void __devinit pnv_pci_ioda_setup_seg(void)
+{
+        struct pci_controller *tmp, *hose;
+        struct pnv_phb *phb;
+        struct pnv_ioda_pe *pe;
 
-        /* Configure PCI Express settings */
-        list_for_each_entry(child, &hose->bus->children, node) {
-                struct pci_dev *self = child->self;
-                if (!self)
-                        continue;
-                pcie_bus_configure_settings(child, self->pcie_mpss);
+        list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
+                phb = hose->private_data;
+                list_for_each_entry(pe, &phb->ioda.pe_list, list) {
+                        pnv_ioda_setup_pe_seg(hose, pe);
+                }
+        }
+}
+
+static void __devinit pnv_pci_ioda_setup_DMA(void)
+{
+        struct pci_controller *hose, *tmp;
+        struct pnv_phb *phb;
+
+        list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
+                pnv_ioda_setup_dma(hose->private_data);
+
+                /* Mark the PHB initialization done */
+                phb = hose->private_data;
+                phb->initialized = 1;
         }
 }
 
+static void __devinit pnv_pci_ioda_fixup(void)
+{
+        pnv_pci_ioda_setup_PEs();
+        pnv_pci_ioda_setup_seg();
+        pnv_pci_ioda_setup_DMA();
+}
+
 /*
  * Returns the alignment for I/O or memory windows for P2P
  * bridges. That actually depends on how PEs are segmented.
@@ -1182,10 +834,22 @@ static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
  */
 static int __devinit pnv_pci_enable_device_hook(struct pci_dev *dev)
 {
-        struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
+        struct pci_controller *hose = pci_bus_to_host(dev->bus);
+        struct pnv_phb *phb = hose->private_data;
+        struct pci_dn *pdn;
 
+        /* The function is probably called while the PEs have
+         * not be created yet. For example, resource reassignment
+         * during PCI probe period. We just skip the check if
+         * PEs isn't ready.
+         */
+        if (!phb->initialized)
+                return 0;
+
+        pdn = pnv_ioda_get_pdn(dev);
         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
                 return -EINVAL;
+
         return 0;
 }
 
@@ -1276,9 +940,9 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
         /* Allocate aux data & arrays */
         size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
         m32map_off = size;
-        size += phb->ioda.total_pe;
+        size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
         iomap_off = size;
-        size += phb->ioda.total_pe;
+        size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
         pemap_off = size;
         size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
         aux = alloc_bootmem(size);
@@ -1289,6 +953,7 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
         phb->ioda.pe_array = aux + pemap_off;
         set_bit(0, phb->ioda.pe_alloc);
 
+        INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
         INIT_LIST_HEAD(&phb->ioda.pe_list);
 
         /* Calculate how many 32-bit TCE segments we have */
@@ -1337,15 +1002,17 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
         /* Setup MSI support */
         pnv_pci_init_ioda_msis(phb);
 
-        /* We set both PCI_PROBE_ONLY and PCI_REASSIGN_ALL_RSRC. This is an
-         * odd combination which essentially means that we skip all resource
-         * fixups and assignments in the generic code, and do it all
-         * ourselves here
+        /*
+         * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
+         * to let the PCI core do resource assignment. It's supposed
+         * that the PCI core will do correct I/O and MMIO alignment
+         * for the P2P bridge bars so that each PCI bus (excluding
+         * the child P2P bridges) can form individual PE.
          */
-        ppc_md.pcibios_fixup_phb = pnv_pci_ioda_fixup_phb;
+        ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
         ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook;
         ppc_md.pcibios_window_alignment = pnv_pci_window_alignment;
-        pci_add_flags(PCI_PROBE_ONLY | PCI_REASSIGN_ALL_RSRC);
+        pci_add_flags(PCI_REASSIGN_ALL_RSRC);
 
         /* Reset IODA tables to a clean state */
         rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET);
diff --git a/arch/powerpc/platforms/powernv/pci-p5ioc2.c b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
index 264967770c3a..6b4bef4e9d82 100644
--- a/arch/powerpc/platforms/powernv/pci-p5ioc2.c
+++ b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
@@ -30,7 +30,6 @@
 #include <asm/opal.h>
 #include <asm/iommu.h>
 #include <asm/tce.h>
-#include <asm/abs_addr.h>
 
 #include "powernv.h"
 #include "pci.h"
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index be3cfc5ceabb..c01688a1a741 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -30,7 +30,6 @@
 #include <asm/opal.h>
 #include <asm/iommu.h>
 #include <asm/tce.h>
-#include <asm/abs_addr.h>
 #include <asm/firmware.h>
 
 #include "powernv.h"
@@ -447,6 +446,11 @@ static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
                 pnv_tce_invalidate(tbl, tces, tcep - 1);
 }
 
+static unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
+{
+        return ((u64 *)tbl->it_base)[index - tbl->it_offset];
+}
+
 void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
                                void *tce_mem, u64 tce_size,
                                u64 dma_offset)
@@ -597,6 +601,7 @@ void __init pnv_pci_init(void)
         ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
         ppc_md.tce_build = pnv_tce_build;
         ppc_md.tce_free = pnv_tce_free;
+        ppc_md.tce_get = pnv_tce_get;
         ppc_md.pci_probe_mode = pnv_pci_probe_mode;
         set_pci_dma_ops(&dma_iommu_ops);
 
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 8bc479634643..7cfb7c883deb 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -17,9 +17,14 @@ enum pnv_phb_model {
 };
 
 #define PNV_PCI_DIAG_BUF_SIZE   4096
+#define PNV_IODA_PE_DEV         (1 << 0)        /* PE has single PCI device     */
+#define PNV_IODA_PE_BUS         (1 << 1)        /* PE has primary PCI bus       */
+#define PNV_IODA_PE_BUS_ALL     (1 << 2)        /* PE has subordinate buses     */
 
 /* Data associated with a PE, including IOMMU tracking etc.. */
 struct pnv_ioda_pe {
+        unsigned long           flags;
+
         /* A PE can be associated with a single device or an
          * entire bus (& children). In the former case, pdev
          * is populated, in the later case, pbus is.
@@ -40,11 +45,6 @@ struct pnv_ioda_pe {
          */
         unsigned int            dma_weight;
 
-        /* This is a PCI-E -> PCI-X bridge, this points to the
-         * corresponding bus PE
-         */
-        struct pnv_ioda_pe      *bus_pe;
-
         /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
         int                     tce32_seg;
         int                     tce32_segcount;
@@ -59,7 +59,8 @@ struct pnv_ioda_pe {
         int                     mve_number;
 
         /* Link in list of PE#s */
-        struct list_head        link;
+        struct list_head        dma_link;
+        struct list_head        list;
 };
 
 struct pnv_phb {
@@ -68,6 +69,7 @@ struct pnv_phb {
         enum pnv_phb_model      model;
         u64                     opal_id;
         void __iomem            *regs;
+        int                     initialized;
         spinlock_t              lock;
 
 #ifdef CONFIG_PCI_MSI
@@ -107,6 +109,11 @@ struct pnv_phb {
                         unsigned int            *io_segmap;
                         struct pnv_ioda_pe      *pe_array;
 
+                        /* Sorted list of used PE's based
+                         * on the sequence of creation
+                         */
+                        struct list_head        pe_list;
+
                         /* Reverse map of PEs, will have to extend if
                          * we are to support more than 256 PEs, indexed
                          * bus { bus, devfn }
@@ -125,7 +132,7 @@ struct pnv_phb {
                         /* Sorted list of used PE's, sorted at
                          * boot for resource allocation purposes
                          */
-                        struct list_head        pe_list;
+                        struct list_head        pe_dma_list;
                 } ioda;
         };
 
diff --git a/arch/powerpc/platforms/ps3/htab.c b/arch/powerpc/platforms/ps3/htab.c
index 3124cf791ebb..d00d7b0a3bda 100644
--- a/arch/powerpc/platforms/ps3/htab.c
+++ b/arch/powerpc/platforms/ps3/htab.c
@@ -43,7 +43,7 @@ enum ps3_lpar_vas_id {
 
 static DEFINE_SPINLOCK(ps3_htab_lock);
 
-static long ps3_hpte_insert(unsigned long hpte_group, unsigned long va,
+static long ps3_hpte_insert(unsigned long hpte_group, unsigned long vpn,
         unsigned long pa, unsigned long rflags, unsigned long vflags,
         int psize, int ssize)
 {
@@ -61,7 +61,7 @@ static long ps3_hpte_insert(unsigned long hpte_group, unsigned long va,
          */
         vflags &= ~HPTE_V_SECONDARY;
 
-        hpte_v = hpte_encode_v(va, psize, ssize) | vflags | HPTE_V_VALID;
+        hpte_v = hpte_encode_v(vpn, psize, ssize) | vflags | HPTE_V_VALID;
         hpte_r = hpte_encode_r(ps3_mm_phys_to_lpar(pa), psize) | rflags;
 
         spin_lock_irqsave(&ps3_htab_lock, flags);
@@ -75,8 +75,8 @@ static long ps3_hpte_insert(unsigned long hpte_group, unsigned long va,
 
         if (result) {
                 /* all entries bolted !*/
-                pr_info("%s:result=%d va=%lx pa=%lx ix=%lx v=%llx r=%llx\n",
-                        __func__, result, va, pa, hpte_group, hpte_v, hpte_r);
+                pr_info("%s:result=%d vpn=%lx pa=%lx ix=%lx v=%llx r=%llx\n",
+                        __func__, result, vpn, pa, hpte_group, hpte_v, hpte_r);
                 BUG();
         }
 
@@ -107,7 +107,7 @@ static long ps3_hpte_remove(unsigned long hpte_group)
 }
 
 static long ps3_hpte_updatepp(unsigned long slot, unsigned long newpp,
-        unsigned long va, int psize, int ssize, int local)
+        unsigned long vpn, int psize, int ssize, int local)
 {
         int result;
         u64 hpte_v, want_v, hpte_rs;
@@ -115,7 +115,7 @@ static long ps3_hpte_updatepp(unsigned long slot, unsigned long newpp,
         unsigned long flags;
         long ret;
 
-        want_v = hpte_encode_v(va, psize, ssize);
+        want_v = hpte_encode_v(vpn, psize, ssize);
 
         spin_lock_irqsave(&ps3_htab_lock, flags);
 
@@ -125,8 +125,8 @@ static long ps3_hpte_updatepp(unsigned long slot, unsigned long newpp,
                                        &hpte_rs);
 
         if (result) {
-                pr_info("%s: res=%d read va=%lx slot=%lx psize=%d\n",
-                        __func__, result, va, slot, psize);
+                pr_info("%s: res=%d read vpn=%lx slot=%lx psize=%d\n",
+                        __func__, result, vpn, slot, psize);
                 BUG();
         }
 
@@ -159,7 +159,7 @@ static void ps3_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
         panic("ps3_hpte_updateboltedpp() not implemented");
 }
 
-static void ps3_hpte_invalidate(unsigned long slot, unsigned long va,
+static void ps3_hpte_invalidate(unsigned long slot, unsigned long vpn,
         int psize, int ssize, int local)
 {
         unsigned long flags;
@@ -170,8 +170,8 @@ static void ps3_hpte_invalidate(unsigned long slot, unsigned long va,
         result = lv1_write_htab_entry(PS3_LPAR_VAS_ID_CURRENT, slot, 0, 0);
 
         if (result) {
-                pr_info("%s: res=%d va=%lx slot=%lx psize=%d\n",
-                        __func__, result, va, slot, psize);
+                pr_info("%s: res=%d vpn=%lx slot=%lx psize=%d\n",
+                        __func__, result, vpn, slot, psize);
                 BUG();
         }
 
diff --git a/arch/powerpc/platforms/ps3/setup.c b/arch/powerpc/platforms/ps3/setup.c
index 2d664c5a83b0..3f509f86432c 100644
--- a/arch/powerpc/platforms/ps3/setup.c
+++ b/arch/powerpc/platforms/ps3/setup.c
@@ -184,11 +184,15 @@ early_param("ps3flash", early_parse_ps3flash);
 #define prealloc_ps3flash_bounce_buffer()       do { } while (0)
 #endif
 
-static int ps3_set_dabr(unsigned long dabr)
+static int ps3_set_dabr(unsigned long dabr, unsigned long dabrx)
 {
-        enum {DABR_USER = 1, DABR_KERNEL = 2,};
+        /* Have to set at least one bit in the DABRX */
+        if (dabrx == 0 && dabr == 0)
+                dabrx = DABRX_USER;
+        /* hypervisor only allows us to set BTI, Kernel and user */
+        dabrx &= DABRX_BTI | DABRX_KERNEL | DABRX_USER;
 
-        return lv1_set_dabr(dabr, DABR_KERNEL | DABR_USER) ? -1 : 0;
+        return lv1_set_dabr(dabr, dabrx) ? -1 : 0;
 }
 
 static void __init ps3_setup_arch(void)
diff --git a/arch/powerpc/platforms/pseries/Makefile b/arch/powerpc/platforms/pseries/Makefile
index c222189f5bb2..890622b87c8f 100644
--- a/arch/powerpc/platforms/pseries/Makefile
+++ b/arch/powerpc/platforms/pseries/Makefile
@@ -6,8 +6,9 @@ obj-y			:= lpar.o hvCall.o nvram.o reconfig.o \
                            firmware.o power.o dlpar.o mobility.o
 obj-$(CONFIG_SMP)       += smp.o
 obj-$(CONFIG_SCANLOG)   += scanlog.o
-obj-$(CONFIG_EEH)       += eeh.o eeh_dev.o eeh_cache.o eeh_driver.o \
-                           eeh_event.o eeh_sysfs.o eeh_pseries.o
+obj-$(CONFIG_EEH)       += eeh.o eeh_pe.o eeh_dev.o eeh_cache.o \
+                           eeh_driver.o eeh_event.o eeh_sysfs.o \
+                           eeh_pseries.o
 obj-$(CONFIG_KEXEC)     += kexec.o
 obj-$(CONFIG_PCI)       += pci.o pci_dlpar.o
 obj-$(CONFIG_PSERIES_MSI)       += msi.o
diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c
index ecd394cf34e6..9a04322b1736 100644
--- a/arch/powerpc/platforms/pseries/eeh.c
+++ b/arch/powerpc/platforms/pseries/eeh.c
@@ -92,6 +92,20 @@ struct eeh_ops *eeh_ops = NULL;
 int eeh_subsystem_enabled;
 EXPORT_SYMBOL(eeh_subsystem_enabled);
 
+/*
+ * EEH probe mode support. The intention is to support multiple
+ * platforms for EEH. Some platforms like pSeries do PCI emunation
+ * based on device tree. However, other platforms like powernv probe
+ * PCI devices from hardware. The flag is used to distinguish that.
+ * In addition, struct eeh_ops::probe would be invoked for particular
+ * OF node or PCI device so that the corresponding PE would be created
+ * there.
+ */
+int eeh_probe_mode;
+
+/* Global EEH mutex */
+DEFINE_MUTEX(eeh_mutex);
+
 /* Lock to avoid races due to multiple reports of an error */
 static DEFINE_RAW_SPINLOCK(confirm_error_lock);
 
@@ -204,22 +218,12 @@ static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len)
                 }
         }
 
-        /* Gather status on devices under the bridge */
-        if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) {
-                struct device_node *child;
-
-                for_each_child_of_node(dn, child) {
-                        if (of_node_to_eeh_dev(child))
-                                n += eeh_gather_pci_data(of_node_to_eeh_dev(child), buf+n, len-n);
-                }
-        }
-
         return n;
 }
 
 /**
  * eeh_slot_error_detail - Generate combined log including driver log and error log
- * @edev: device to report error log for
+ * @pe: EEH PE
  * @severity: temporary or permanent error log
  *
  * This routine should be called to generate the combined log, which
@@ -227,17 +231,22 @@ static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len)
  * out from the config space of the corresponding PCI device, while
  * the error log is fetched through platform dependent function call.
  */
-void eeh_slot_error_detail(struct eeh_dev *edev, int severity)
+void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
 {
         size_t loglen = 0;
-        pci_regs_buf[0] = 0;
+        struct eeh_dev *edev;
 
-        eeh_pci_enable(edev, EEH_OPT_THAW_MMIO);
-        eeh_ops->configure_bridge(eeh_dev_to_of_node(edev));
-        eeh_restore_bars(edev);
-        loglen = eeh_gather_pci_data(edev, pci_regs_buf, EEH_PCI_REGS_LOG_LEN);
+        eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
+        eeh_ops->configure_bridge(pe);
+        eeh_pe_restore_bars(pe);
 
-        eeh_ops->get_log(eeh_dev_to_of_node(edev), severity, pci_regs_buf, loglen);
+        pci_regs_buf[0] = 0;
+        eeh_pe_for_each_dev(pe, edev) {
+                loglen += eeh_gather_pci_data(edev, pci_regs_buf,
+                                EEH_PCI_REGS_LOG_LEN);
+        }
+
+        eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
 }
 
 /**
@@ -261,126 +270,8 @@ static inline unsigned long eeh_token_to_phys(unsigned long token)
 }
 
 /**
- * eeh_find_device_pe - Retrieve the PE for the given device
- * @dn: device node
- *
- * Return the PE under which this device lies
- */
-struct device_node *eeh_find_device_pe(struct device_node *dn)
-{
-        while (dn->parent && of_node_to_eeh_dev(dn->parent) &&
-               (of_node_to_eeh_dev(dn->parent)->mode & EEH_MODE_SUPPORTED)) {
-                dn = dn->parent;
-        }
-        return dn;
-}
-
-/**
- * __eeh_mark_slot - Mark all child devices as failed
- * @parent: parent device
- * @mode_flag: failure flag
- *
- * Mark all devices that are children of this device as failed.
- * Mark the device driver too, so that it can see the failure
- * immediately; this is critical, since some drivers poll
- * status registers in interrupts ... If a driver is polling,
- * and the slot is frozen, then the driver can deadlock in
- * an interrupt context, which is bad.
- */
-static void __eeh_mark_slot(struct device_node *parent, int mode_flag)
-{
-        struct device_node *dn;
-
-        for_each_child_of_node(parent, dn) {
-                if (of_node_to_eeh_dev(dn)) {
-                        /* Mark the pci device driver too */
-                        struct pci_dev *dev = of_node_to_eeh_dev(dn)->pdev;
-
-                        of_node_to_eeh_dev(dn)->mode |= mode_flag;
-
-                        if (dev && dev->driver)
-                                dev->error_state = pci_channel_io_frozen;
-
-                        __eeh_mark_slot(dn, mode_flag);
-                }
-        }
-}
-
-/**
- * eeh_mark_slot - Mark the indicated device and its children as failed
- * @dn: parent device
- * @mode_flag: failure flag
- *
- * Mark the indicated device and its child devices as failed.
- * The device drivers are marked as failed as well.
- */
-void eeh_mark_slot(struct device_node *dn, int mode_flag)
-{
-        struct pci_dev *dev;
-        dn = eeh_find_device_pe(dn);
-
-        /* Back up one, since config addrs might be shared */
-        if (!pcibios_find_pci_bus(dn) && of_node_to_eeh_dev(dn->parent))
-                dn = dn->parent;
-
-        of_node_to_eeh_dev(dn)->mode |= mode_flag;
-
-        /* Mark the pci device too */
-        dev = of_node_to_eeh_dev(dn)->pdev;
-        if (dev)
-                dev->error_state = pci_channel_io_frozen;
-
-        __eeh_mark_slot(dn, mode_flag);
-}
-
-/**
- * __eeh_clear_slot - Clear failure flag for the child devices
- * @parent: parent device
- * @mode_flag: flag to be cleared
- *
- * Clear failure flag for the child devices.
- */
-static void __eeh_clear_slot(struct device_node *parent, int mode_flag)
-{
-        struct device_node *dn;
-
-        for_each_child_of_node(parent, dn) {
-                if (of_node_to_eeh_dev(dn)) {
-                        of_node_to_eeh_dev(dn)->mode &= ~mode_flag;
-                        of_node_to_eeh_dev(dn)->check_count = 0;
-                        __eeh_clear_slot(dn, mode_flag);
-                }
-        }
-}
-
-/**
- * eeh_clear_slot - Clear failure flag for the indicated device and its children
- * @dn: parent device
- * @mode_flag: flag to be cleared
- *
- * Clear failure flag for the indicated device and its children.
- */
-void eeh_clear_slot(struct device_node *dn, int mode_flag)
-{
-        unsigned long flags;
-        raw_spin_lock_irqsave(&confirm_error_lock, flags);
-        
-        dn = eeh_find_device_pe(dn);
-        
-        /* Back up one, since config addrs might be shared */
-        if (!pcibios_find_pci_bus(dn) && of_node_to_eeh_dev(dn->parent))
-                dn = dn->parent;
-
-        of_node_to_eeh_dev(dn)->mode &= ~mode_flag;
-        of_node_to_eeh_dev(dn)->check_count = 0;
-        __eeh_clear_slot(dn, mode_flag);
-        raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
-}
-
-/**
- * eeh_dn_check_failure - Check if all 1's data is due to EEH slot freeze
- * @dn: device node
- * @dev: pci device, if known
+ * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze
+ * @edev: eeh device
  *
  * Check for an EEH failure for the given device node.  Call this
  * routine if the result of a read was all 0xff's and you want to
@@ -392,11 +283,13 @@ void eeh_clear_slot(struct device_node *dn, int mode_flag)
  *
  * It is safe to call this routine in an interrupt context.
  */
-int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
+int eeh_dev_check_failure(struct eeh_dev *edev)
 {
         int ret;
         unsigned long flags;
-        struct eeh_dev *edev;
+        struct device_node *dn;
+        struct pci_dev *dev;
+        struct eeh_pe *pe;
         int rc = 0;
         const char *location;
 
@@ -405,23 +298,23 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
         if (!eeh_subsystem_enabled)
                 return 0;
 
-        if (!dn) {
+        if (!edev) {
                 eeh_stats.no_dn++;
                 return 0;
         }
-        dn = eeh_find_device_pe(dn);
-        edev = of_node_to_eeh_dev(dn);
+        dn = eeh_dev_to_of_node(edev);
+        dev = eeh_dev_to_pci_dev(edev);
+        pe = edev->pe;
 
         /* Access to IO BARs might get this far and still not want checking. */
-        if (!(edev->mode & EEH_MODE_SUPPORTED) ||
-            edev->mode & EEH_MODE_NOCHECK) {
+        if (!pe) {
                 eeh_stats.ignored_check++;
-                pr_debug("EEH: Ignored check (%x) for %s %s\n",
-                        edev->mode, eeh_pci_name(dev), dn->full_name);
+                pr_debug("EEH: Ignored check for %s %s\n",
+                        eeh_pci_name(dev), dn->full_name);
                 return 0;
         }
 
-        if (!edev->config_addr && !edev->pe_config_addr) {
+        if (!pe->addr && !pe->config_addr) {
                 eeh_stats.no_cfg_addr++;
                 return 0;
         }
@@ -434,13 +327,13 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
          */
         raw_spin_lock_irqsave(&confirm_error_lock, flags);
         rc = 1;
-        if (edev->mode & EEH_MODE_ISOLATED) {
-                edev->check_count++;
-                if (edev->check_count % EEH_MAX_FAILS == 0) {
+        if (pe->state & EEH_PE_ISOLATED) {
+                pe->check_count++;
+                if (pe->check_count % EEH_MAX_FAILS == 0) {
                         location = of_get_property(dn, "ibm,loc-code", NULL);
                         printk(KERN_ERR "EEH: %d reads ignored for recovering device at "
                                 "location=%s driver=%s pci addr=%s\n",
-                                edev->check_count, location,
+                                pe->check_count, location,
                                 eeh_driver_name(dev), eeh_pci_name(dev));
                         printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n",
                                 eeh_driver_name(dev));
@@ -456,7 +349,7 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
          * function zero of a multi-function device.
          * In any case they must share a common PHB.
          */
-        ret = eeh_ops->get_state(dn, NULL);
+        ret = eeh_ops->get_state(pe, NULL);
 
         /* Note that config-io to empty slots may fail;
          * they are empty when they don't have children.
@@ -469,7 +362,7 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
             (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) ==
             (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) {
                 eeh_stats.false_positives++;
-                edev->false_positives ++;
+                pe->false_positives++;
                 rc = 0;
                 goto dn_unlock;
         }
@@ -480,10 +373,10 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
          * with other functions on this device, and functions under
          * bridges.
          */
-        eeh_mark_slot(dn, EEH_MODE_ISOLATED);
+        eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
         raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
 
-        eeh_send_failure_event(edev);
+        eeh_send_failure_event(pe);
 
         /* Most EEH events are due to device driver bugs.  Having
          * a stack trace will help the device-driver authors figure
@@ -497,7 +390,7 @@ dn_unlock:
         return rc;
 }
 
-EXPORT_SYMBOL_GPL(eeh_dn_check_failure);
+EXPORT_SYMBOL_GPL(eeh_dev_check_failure);
 
 /**
  * eeh_check_failure - Check if all 1's data is due to EEH slot freeze
@@ -514,21 +407,19 @@ EXPORT_SYMBOL_GPL(eeh_dn_check_failure);
 unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
 {
         unsigned long addr;
-        struct pci_dev *dev;
-        struct device_node *dn;
+        struct eeh_dev *edev;
 
         /* Finding the phys addr + pci device; this is pretty quick. */
         addr = eeh_token_to_phys((unsigned long __force) token);
-        dev = pci_addr_cache_get_device(addr);
-        if (!dev) {
+        edev = eeh_addr_cache_get_dev(addr);
+        if (!edev) {
                 eeh_stats.no_device++;
                 return val;
         }
 
-        dn = pci_device_to_OF_node(dev);
-        eeh_dn_check_failure(dn, dev);
+        eeh_dev_check_failure(edev);
 
-        pci_dev_put(dev);
+        pci_dev_put(eeh_dev_to_pci_dev(edev));
         return val;
 }
 
@@ -537,23 +428,22 @@ EXPORT_SYMBOL(eeh_check_failure);
 
 /**
  * eeh_pci_enable - Enable MMIO or DMA transfers for this slot
- * @edev: pci device node
+ * @pe: EEH PE
  *
  * This routine should be called to reenable frozen MMIO or DMA
  * so that it would work correctly again. It's useful while doing
  * recovery or log collection on the indicated device.
  */
-int eeh_pci_enable(struct eeh_dev *edev, int function)
+int eeh_pci_enable(struct eeh_pe *pe, int function)
 {
         int rc;
-        struct device_node *dn = eeh_dev_to_of_node(edev);
 
-        rc = eeh_ops->set_option(dn, function);
+        rc = eeh_ops->set_option(pe, function);
         if (rc)
-                printk(KERN_WARNING "EEH: Unexpected state change %d, err=%d dn=%s\n",
-                        function, rc, dn->full_name);
+                pr_warning("%s: Unexpected state change %d on PHB#%d-PE#%x, err=%d\n",
+                        __func__, function, pe->phb->global_number, pe->addr, rc);
 
-        rc = eeh_ops->wait_state(dn, PCI_BUS_RESET_WAIT_MSEC);
+        rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
         if (rc > 0 && (rc & EEH_STATE_MMIO_ENABLED) &&
            (function == EEH_OPT_THAW_MMIO))
                 return 0;
@@ -571,17 +461,24 @@ int eeh_pci_enable(struct eeh_dev *edev, int function)
  */
 int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
 {
-        struct device_node *dn = pci_device_to_OF_node(dev);
+        struct eeh_dev *edev = pci_dev_to_eeh_dev(dev);
+        struct eeh_pe *pe = edev->pe;
+
+        if (!pe) {
+                pr_err("%s: No PE found on PCI device %s\n",
+                        __func__, pci_name(dev));
+                return -EINVAL;
+        }
 
         switch (state) {
         case pcie_deassert_reset:
-                eeh_ops->reset(dn, EEH_RESET_DEACTIVATE);
+                eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
                 break;
         case pcie_hot_reset:
-                eeh_ops->reset(dn, EEH_RESET_HOT);
+                eeh_ops->reset(pe, EEH_RESET_HOT);
                 break;
         case pcie_warm_reset:
-                eeh_ops->reset(dn, EEH_RESET_FUNDAMENTAL);
+                eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
                 break;
         default:
                 return -EINVAL;
@@ -591,66 +488,37 @@ int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state stat
 }
 
 /**
- * __eeh_set_pe_freset - Check the required reset for child devices
- * @parent: parent device
- * @freset: return value
- *
- * Each device might have its preferred reset type: fundamental or
- * hot reset. The routine is used to collect the information from
- * the child devices so that they could be reset accordingly.
- */
-void __eeh_set_pe_freset(struct device_node *parent, unsigned int *freset)
-{
-        struct device_node *dn;
-
-        for_each_child_of_node(parent, dn) {
-                if (of_node_to_eeh_dev(dn)) {
-                        struct pci_dev *dev = of_node_to_eeh_dev(dn)->pdev;
-
-                        if (dev && dev->driver)
-                                *freset |= dev->needs_freset;
-
-                        __eeh_set_pe_freset(dn, freset);
-                }
-        }
-}
-
-/**
- * eeh_set_pe_freset - Check the required reset for the indicated device and its children
- * @dn: parent device
- * @freset: return value
+ * eeh_set_pe_freset - Check the required reset for the indicated device
+ * @data: EEH device
+ * @flag: return value
  *
  * Each device might have its preferred reset type: fundamental or
  * hot reset. The routine is used to collected the information for
  * the indicated device and its children so that the bunch of the
  * devices could be reset properly.
  */
-void eeh_set_pe_freset(struct device_node *dn, unsigned int *freset)
+static void *eeh_set_dev_freset(void *data, void *flag)
 {
         struct pci_dev *dev;
-        dn = eeh_find_device_pe(dn);
-
-        /* Back up one, since config addrs might be shared */
-        if (!pcibios_find_pci_bus(dn) && of_node_to_eeh_dev(dn->parent))
-                dn = dn->parent;
+        unsigned int *freset = (unsigned int *)flag;
+        struct eeh_dev *edev = (struct eeh_dev *)data;
 
-        dev = of_node_to_eeh_dev(dn)->pdev;
+        dev = eeh_dev_to_pci_dev(edev);
         if (dev)
                 *freset |= dev->needs_freset;
 
-        __eeh_set_pe_freset(dn, freset);
+        return NULL;
 }
 
 /**
  * eeh_reset_pe_once - Assert the pci #RST line for 1/4 second
- * @edev: pci device node to be reset.
+ * @pe: EEH PE
  *
  * Assert the PCI #RST line for 1/4 second.
  */
-static void eeh_reset_pe_once(struct eeh_dev *edev)
+static void eeh_reset_pe_once(struct eeh_pe *pe)
 {
         unsigned int freset = 0;
-        struct device_node *dn = eeh_dev_to_of_node(edev);
 
         /* Determine type of EEH reset required for
          * Partitionable Endpoint, a hot-reset (1)
@@ -658,12 +526,12 @@ static void eeh_reset_pe_once(struct eeh_dev *edev)
          * A fundamental reset required by any device under
          * Partitionable Endpoint trumps hot-reset.
          */
-        eeh_set_pe_freset(dn, &freset);
+        eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);
 
         if (freset)
-                eeh_ops->reset(dn, EEH_RESET_FUNDAMENTAL);
+                eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
         else
-                eeh_ops->reset(dn, EEH_RESET_HOT);
+                eeh_ops->reset(pe, EEH_RESET_HOT);
 
         /* The PCI bus requires that the reset be held high for at least
          * a 100 milliseconds. We wait a bit longer 'just in case'.
@@ -675,9 +543,9 @@ static void eeh_reset_pe_once(struct eeh_dev *edev)
          * pci slot reset line is dropped. Make sure we don't miss
          * these, and clear the flag now.
          */
-        eeh_clear_slot(dn, EEH_MODE_ISOLATED);
+        eeh_pe_state_clear(pe, EEH_PE_ISOLATED);
 
-        eeh_ops->reset(dn, EEH_RESET_DEACTIVATE);
+        eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
 
         /* After a PCI slot has been reset, the PCI Express spec requires
          * a 1.5 second idle time for the bus to stabilize, before starting
@@ -689,116 +557,36 @@ static void eeh_reset_pe_once(struct eeh_dev *edev)
 
 /**
  * eeh_reset_pe - Reset the indicated PE
- * @edev: PCI device associated EEH device
+ * @pe: EEH PE
  *
  * This routine should be called to reset indicated device, including
  * PE. A PE might include multiple PCI devices and sometimes PCI bridges
  * might be involved as well.
  */
-int eeh_reset_pe(struct eeh_dev *edev)
+int eeh_reset_pe(struct eeh_pe *pe)
 {
         int i, rc;
-        struct device_node *dn = eeh_dev_to_of_node(edev);
 
         /* Take three shots at resetting the bus */
         for (i=0; i<3; i++) {
-                eeh_reset_pe_once(edev);
+                eeh_reset_pe_once(pe);
 
-                rc = eeh_ops->wait_state(dn, PCI_BUS_RESET_WAIT_MSEC);
+                rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
                 if (rc == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE))
                         return 0;
 
                 if (rc < 0) {
-                        printk(KERN_ERR "EEH: unrecoverable slot failure %s\n",
-                               dn->full_name);
+                        pr_err("%s: Unrecoverable slot failure on PHB#%d-PE#%x",
+                                __func__, pe->phb->global_number, pe->addr);
                         return -1;
                 }
-                printk(KERN_ERR "EEH: bus reset %d failed on slot %s, rc=%d\n",
-                       i+1, dn->full_name, rc);
+                pr_err("EEH: bus reset %d failed on PHB#%d-PE#%x, rc=%d\n",
+                        i+1, pe->phb->global_number, pe->addr, rc);
         }
 
         return -1;
 }
 
-/** Save and restore of PCI BARs
- *
- * Although firmware will set up BARs during boot, it doesn't
- * set up device BAR's after a device reset, although it will,
- * if requested, set up bridge configuration. Thus, we need to
- * configure the PCI devices ourselves.  
- */
-
-/**
- * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
- * @edev: PCI device associated EEH device
- *
- * Loads the PCI configuration space base address registers,
- * the expansion ROM base address, the latency timer, and etc.
- * from the saved values in the device node.
- */
-static inline void eeh_restore_one_device_bars(struct eeh_dev *edev)
-{
-        int i;
-        u32 cmd;
-        struct device_node *dn = eeh_dev_to_of_node(edev);
-
-        if (!edev->phb)
-                return;
-
-        for (i=4; i<10; i++) {
-                eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
-        }
-
-        /* 12 == Expansion ROM Address */
-        eeh_ops->write_config(dn, 12*4, 4, edev->config_space[12]);
-
-#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
-#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
-
-        eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
-                    SAVED_BYTE(PCI_CACHE_LINE_SIZE));
-
-        eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
-                    SAVED_BYTE(PCI_LATENCY_TIMER));
-
-        /* max latency, min grant, interrupt pin and line */
-        eeh_ops->write_config(dn, 15*4, 4, edev->config_space[15]);
-
-        /* Restore PERR & SERR bits, some devices require it,
-         * don't touch the other command bits
-         */
-        eeh_ops->read_config(dn, PCI_COMMAND, 4, &cmd);
-        if (edev->config_space[1] & PCI_COMMAND_PARITY)
-                cmd |= PCI_COMMAND_PARITY;
-        else
-                cmd &= ~PCI_COMMAND_PARITY;
-        if (edev->config_space[1] & PCI_COMMAND_SERR)
-                cmd |= PCI_COMMAND_SERR;
-        else
-                cmd &= ~PCI_COMMAND_SERR;
-        eeh_ops->write_config(dn, PCI_COMMAND, 4, cmd);
-}
-
-/**
- * eeh_restore_bars - Restore the PCI config space info
- * @edev: EEH device
- *
- * This routine performs a recursive walk to the children
- * of this device as well.
- */
-void eeh_restore_bars(struct eeh_dev *edev)
-{
-        struct device_node *dn;
-        if (!edev)
-                return;
-        
-        if ((edev->mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(edev->class_code))
-                eeh_restore_one_device_bars(edev);
-
-        for_each_child_of_node(eeh_dev_to_of_node(edev), dn)
-                eeh_restore_bars(of_node_to_eeh_dev(dn));
-}
-
 /**
  * eeh_save_bars - Save device bars
  * @edev: PCI device associated EEH device
@@ -808,7 +596,7 @@ void eeh_restore_bars(struct eeh_dev *edev)
  * PCI devices are added individually; but, for the restore,
  * an entire slot is reset at a time.
  */
-static void eeh_save_bars(struct eeh_dev *edev)
+void eeh_save_bars(struct eeh_dev *edev)
 {
         int i;
         struct device_node *dn;
@@ -822,102 +610,6 @@ static void eeh_save_bars(struct eeh_dev *edev)
 }
 
 /**
- * eeh_early_enable - Early enable EEH on the indicated device
- * @dn: device node
- * @data: BUID
- *
- * Enable EEH functionality on the specified PCI device. The function
- * is expected to be called before real PCI probing is done. However,
- * the PHBs have been initialized at this point.
- */
-static void *eeh_early_enable(struct device_node *dn, void *data)
-{
-        int ret;
-        const u32 *class_code = of_get_property(dn, "class-code", NULL);
-        const u32 *vendor_id = of_get_property(dn, "vendor-id", NULL);
-        const u32 *device_id = of_get_property(dn, "device-id", NULL);
-        const u32 *regs;
-        int enable;
-        struct eeh_dev *edev = of_node_to_eeh_dev(dn);
-
-        edev->class_code = 0;
-        edev->mode = 0;
-        edev->check_count = 0;
-        edev->freeze_count = 0;
-        edev->false_positives = 0;
-
-        if (!of_device_is_available(dn))
-                return NULL;
-
-        /* Ignore bad nodes. */
-        if (!class_code || !vendor_id || !device_id)
-                return NULL;
-
-        /* There is nothing to check on PCI to ISA bridges */
-        if (dn->type && !strcmp(dn->type, "isa")) {
-                edev->mode |= EEH_MODE_NOCHECK;
-                return NULL;
-        }
-        edev->class_code = *class_code;
-
-        /* Ok... see if this device supports EEH.  Some do, some don't,
-         * and the only way to find out is to check each and every one.
-         */
-        regs = of_get_property(dn, "reg", NULL);
-        if (regs) {
-                /* First register entry is addr (00BBSS00)  */
-                /* Try to enable eeh */
-                ret = eeh_ops->set_option(dn, EEH_OPT_ENABLE);
-
-                enable = 0;
-                if (ret == 0) {
-                        edev->config_addr = regs[0];
-
-                        /* If the newer, better, ibm,get-config-addr-info is supported, 
-                         * then use that instead.
-                         */
-                        edev->pe_config_addr = eeh_ops->get_pe_addr(dn);
-
-                        /* Some older systems (Power4) allow the
-                         * ibm,set-eeh-option call to succeed even on nodes
-                         * where EEH is not supported. Verify support
-                         * explicitly.
-                         */
-                        ret = eeh_ops->get_state(dn, NULL);
-                        if (ret > 0 && ret != EEH_STATE_NOT_SUPPORT)
-                                enable = 1;
-                }
-
-                if (enable) {
-                        eeh_subsystem_enabled = 1;
-                        edev->mode |= EEH_MODE_SUPPORTED;
-
-                        pr_debug("EEH: %s: eeh enabled, config=%x pe_config=%x\n",
-                                 dn->full_name, edev->config_addr,
-                                 edev->pe_config_addr);
-                } else {
-
-                        /* This device doesn't support EEH, but it may have an
-                         * EEH parent, in which case we mark it as supported.
-                         */
-                        if (dn->parent && of_node_to_eeh_dev(dn->parent) &&
-                            (of_node_to_eeh_dev(dn->parent)->mode & EEH_MODE_SUPPORTED)) {
-                                /* Parent supports EEH. */
-                                edev->mode |= EEH_MODE_SUPPORTED;
-                                edev->config_addr = of_node_to_eeh_dev(dn->parent)->config_addr;
-                                return NULL;
-                        }
-                }
-        } else {
-                printk(KERN_WARNING "EEH: %s: unable to get reg property.\n",
-                       dn->full_name);
-        }
-
-        eeh_save_bars(edev);
-        return NULL;
-}
-
-/**
  * eeh_ops_register - Register platform dependent EEH operations
  * @ops: platform dependent EEH operations
  *
@@ -982,7 +674,7 @@ int __exit eeh_ops_unregister(const char *name)
  * Even if force-off is set, the EEH hardware is still enabled, so that
  * newer systems can boot.
  */
-void __init eeh_init(void)
+static int __init eeh_init(void)
 {
         struct pci_controller *hose, *tmp;
         struct device_node *phb;
@@ -992,27 +684,34 @@ void __init eeh_init(void)
         if (!eeh_ops) {
                 pr_warning("%s: Platform EEH operation not found\n",
                         __func__);
-                return;
+                return -EEXIST;
         } else if ((ret = eeh_ops->init())) {
                 pr_warning("%s: Failed to call platform init function (%d)\n",
                         __func__, ret);
-                return;
+                return ret;
         }
 
         raw_spin_lock_init(&confirm_error_lock);
 
         /* Enable EEH for all adapters */
-        list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
-                phb = hose->dn;
-                traverse_pci_devices(phb, eeh_early_enable, NULL);
+        if (eeh_probe_mode_devtree()) {
+                list_for_each_entry_safe(hose, tmp,
+                        &hose_list, list_node) {
+                        phb = hose->dn;
+                        traverse_pci_devices(phb, eeh_ops->of_probe, NULL);
+                }
         }
 
         if (eeh_subsystem_enabled)
-                printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n");
+                pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n");
         else
-                printk(KERN_WARNING "EEH: No capable adapters found\n");
+                pr_warning("EEH: No capable adapters found\n");
+
+        return ret;
 }
 
+core_initcall_sync(eeh_init);
+
 /**
  * eeh_add_device_early - Enable EEH for the indicated device_node
  * @dn: device node for which to set up EEH
@@ -1029,7 +728,7 @@ static void eeh_add_device_early(struct device_node *dn)
 {
         struct pci_controller *phb;
 
-        if (!dn || !of_node_to_eeh_dev(dn))
+        if (!of_node_to_eeh_dev(dn))
                 return;
         phb = of_node_to_eeh_dev(dn)->phb;
 
@@ -1037,7 +736,8 @@ static void eeh_add_device_early(struct device_node *dn)
         if (NULL == phb || 0 == phb->buid)
                 return;
 
-        eeh_early_enable(dn, NULL);
+        /* FIXME: hotplug support on POWERNV */
+        eeh_ops->of_probe(dn, NULL);
 }
 
 /**
@@ -1087,7 +787,7 @@ static void eeh_add_device_late(struct pci_dev *dev)
         edev->pdev = dev;
         dev->dev.archdata.edev = edev;
 
-        pci_addr_cache_insert_device(dev);
+        eeh_addr_cache_insert_dev(dev);
         eeh_sysfs_add_device(dev);
 }
 
@@ -1117,6 +817,7 @@ EXPORT_SYMBOL_GPL(eeh_add_device_tree_late);
 /**
  * eeh_remove_device - Undo EEH setup for the indicated pci device
  * @dev: pci device to be removed
+ * @purge_pe: remove the PE or not
  *
  * This routine should be called when a device is removed from
  * a running system (e.g. by hotplug or dlpar).  It unregisters
@@ -1124,7 +825,7 @@ EXPORT_SYMBOL_GPL(eeh_add_device_tree_late);
  * this device will no longer be detected after this call; thus,
  * i/o errors affecting this slot may leave this device unusable.
  */
-static void eeh_remove_device(struct pci_dev *dev)
+static void eeh_remove_device(struct pci_dev *dev, int purge_pe)
 {
         struct eeh_dev *edev;
 
@@ -1143,28 +844,30 @@ static void eeh_remove_device(struct pci_dev *dev)
         dev->dev.archdata.edev = NULL;
         pci_dev_put(dev);
 
-        pci_addr_cache_remove_device(dev);
+        eeh_rmv_from_parent_pe(edev, purge_pe);
+        eeh_addr_cache_rmv_dev(dev);
         eeh_sysfs_remove_device(dev);
 }
 
 /**
  * eeh_remove_bus_device - Undo EEH setup for the indicated PCI device
  * @dev: PCI device
+ * @purge_pe: remove the corresponding PE or not
  *
  * This routine must be called when a device is removed from the
  * running system through hotplug or dlpar. The corresponding
  * PCI address cache will be removed.
  */
-void eeh_remove_bus_device(struct pci_dev *dev)
+void eeh_remove_bus_device(struct pci_dev *dev, int purge_pe)
 {
         struct pci_bus *bus = dev->subordinate;
         struct pci_dev *child, *tmp;
 
-        eeh_remove_device(dev);
+        eeh_remove_device(dev, purge_pe);
 
         if (bus && dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
                 list_for_each_entry_safe(child, tmp, &bus->devices, bus_list)
-                         eeh_remove_bus_device(child);
+                         eeh_remove_bus_device(child, purge_pe);
         }
 }
 EXPORT_SYMBOL_GPL(eeh_remove_bus_device);
diff --git a/arch/powerpc/platforms/pseries/eeh_cache.c b/arch/powerpc/platforms/pseries/eeh_cache.c
index e5ae1c687c66..5a4c87903057 100644
--- a/arch/powerpc/platforms/pseries/eeh_cache.c
+++ b/arch/powerpc/platforms/pseries/eeh_cache.c
@@ -50,6 +50,7 @@ struct pci_io_addr_range {
         struct rb_node rb_node;
         unsigned long addr_lo;
         unsigned long addr_hi;
+        struct eeh_dev *edev;
         struct pci_dev *pcidev;
         unsigned int flags;
 };
@@ -59,7 +60,7 @@ static struct pci_io_addr_cache {
         spinlock_t piar_lock;
 } pci_io_addr_cache_root;
 
-static inline struct pci_dev *__pci_addr_cache_get_device(unsigned long addr)
+static inline struct eeh_dev *__eeh_addr_cache_get_device(unsigned long addr)
 {
         struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node;
 
@@ -74,7 +75,7 @@ static inline struct pci_dev *__pci_addr_cache_get_device(unsigned long addr)
                                 n = n->rb_right;
                         } else {
                                 pci_dev_get(piar->pcidev);
-                                return piar->pcidev;
+                                return piar->edev;
                         }
                 }
         }
@@ -83,7 +84,7 @@ static inline struct pci_dev *__pci_addr_cache_get_device(unsigned long addr)
 }
 
 /**
- * pci_addr_cache_get_device - Get device, given only address
+ * eeh_addr_cache_get_dev - Get device, given only address
  * @addr: mmio (PIO) phys address or i/o port number
  *
  * Given an mmio phys address, or a port number, find a pci device
@@ -92,15 +93,15 @@ static inline struct pci_dev *__pci_addr_cache_get_device(unsigned long addr)
  * from zero (that is, they do *not* have pci_io_addr added in).
  * It is safe to call this function within an interrupt.
  */
-struct pci_dev *pci_addr_cache_get_device(unsigned long addr)
+struct eeh_dev *eeh_addr_cache_get_dev(unsigned long addr)
 {
-        struct pci_dev *dev;
+        struct eeh_dev *edev;
         unsigned long flags;
 
         spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
-        dev = __pci_addr_cache_get_device(addr);
+        edev = __eeh_addr_cache_get_device(addr);
         spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
-        return dev;
+        return edev;
 }
 
 #ifdef DEBUG
@@ -108,7 +109,7 @@ struct pci_dev *pci_addr_cache_get_device(unsigned long addr)
  * Handy-dandy debug print routine, does nothing more
  * than print out the contents of our addr cache.
  */
-static void pci_addr_cache_print(struct pci_io_addr_cache *cache)
+static void eeh_addr_cache_print(struct pci_io_addr_cache *cache)
 {
         struct rb_node *n;
         int cnt = 0;
@@ -117,7 +118,7 @@ static void pci_addr_cache_print(struct pci_io_addr_cache *cache)
         while (n) {
                 struct pci_io_addr_range *piar;
                 piar = rb_entry(n, struct pci_io_addr_range, rb_node);
-                printk(KERN_DEBUG "PCI: %s addr range %d [%lx-%lx]: %s\n",
+                pr_debug("PCI: %s addr range %d [%lx-%lx]: %s\n",
                        (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt,
                        piar->addr_lo, piar->addr_hi, pci_name(piar->pcidev));
                 cnt++;
@@ -128,7 +129,7 @@ static void pci_addr_cache_print(struct pci_io_addr_cache *cache)
 
 /* Insert address range into the rb tree. */
 static struct pci_io_addr_range *
-pci_addr_cache_insert(struct pci_dev *dev, unsigned long alo,
+eeh_addr_cache_insert(struct pci_dev *dev, unsigned long alo,
                       unsigned long ahi, unsigned int flags)
 {
         struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node;
@@ -146,23 +147,24 @@ pci_addr_cache_insert(struct pci_dev *dev, unsigned long alo,
                 } else {
                         if (dev != piar->pcidev ||
                             alo != piar->addr_lo || ahi != piar->addr_hi) {
-                                printk(KERN_WARNING "PIAR: overlapping address range\n");
+                                pr_warning("PIAR: overlapping address range\n");
                         }
                         return piar;
                 }
         }
-        piar = kmalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC);
+        piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC);
         if (!piar)
                 return NULL;
 
         pci_dev_get(dev);
         piar->addr_lo = alo;
         piar->addr_hi = ahi;
+        piar->edev = pci_dev_to_eeh_dev(dev);
         piar->pcidev = dev;
         piar->flags = flags;
 
 #ifdef DEBUG
-        printk(KERN_DEBUG "PIAR: insert range=[%lx:%lx] dev=%s\n",
+        pr_debug("PIAR: insert range=[%lx:%lx] dev=%s\n",
                           alo, ahi, pci_name(dev));
 #endif
 
@@ -172,7 +174,7 @@ pci_addr_cache_insert(struct pci_dev *dev, unsigned long alo,
         return piar;
 }
 
-static void __pci_addr_cache_insert_device(struct pci_dev *dev)
+static void __eeh_addr_cache_insert_dev(struct pci_dev *dev)
 {
         struct device_node *dn;
         struct eeh_dev *edev;
@@ -180,7 +182,7 @@ static void __pci_addr_cache_insert_device(struct pci_dev *dev)
 
         dn = pci_device_to_OF_node(dev);
         if (!dn) {
-                printk(KERN_WARNING "PCI: no pci dn found for dev=%s\n", pci_name(dev));
+                pr_warning("PCI: no pci dn found for dev=%s\n", pci_name(dev));
                 return;
         }
 
@@ -192,8 +194,7 @@ static void __pci_addr_cache_insert_device(struct pci_dev *dev)
         }
 
         /* Skip any devices for which EEH is not enabled. */
-        if (!(edev->mode & EEH_MODE_SUPPORTED) ||
-            edev->mode & EEH_MODE_NOCHECK) {
+        if (!edev->pe) {
 #ifdef DEBUG
                 pr_info("PCI: skip building address cache for=%s - %s\n",
                         pci_name(dev), dn->full_name);
@@ -212,19 +213,19 @@ static void __pci_addr_cache_insert_device(struct pci_dev *dev)
                         continue;
                 if (start == 0 || ~start == 0 || end == 0 || ~end == 0)
                          continue;
-                pci_addr_cache_insert(dev, start, end, flags);
+                eeh_addr_cache_insert(dev, start, end, flags);
         }
 }
 
 /**
- * pci_addr_cache_insert_device - Add a device to the address cache
+ * eeh_addr_cache_insert_dev - Add a device to the address cache
  * @dev: PCI device whose I/O addresses we are interested in.
  *
  * In order to support the fast lookup of devices based on addresses,
  * we maintain a cache of devices that can be quickly searched.
  * This routine adds a device to that cache.
  */
-void pci_addr_cache_insert_device(struct pci_dev *dev)
+void eeh_addr_cache_insert_dev(struct pci_dev *dev)
 {
         unsigned long flags;
 
@@ -233,11 +234,11 @@ void pci_addr_cache_insert_device(struct pci_dev *dev)
                 return;
 
         spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
-        __pci_addr_cache_insert_device(dev);
+        __eeh_addr_cache_insert_dev(dev);
         spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
 }
 
-static inline void __pci_addr_cache_remove_device(struct pci_dev *dev)
+static inline void __eeh_addr_cache_rmv_dev(struct pci_dev *dev)
 {
         struct rb_node *n;
 
@@ -258,7 +259,7 @@ restart:
 }
 
 /**
- * pci_addr_cache_remove_device - remove pci device from addr cache
+ * eeh_addr_cache_rmv_dev - remove pci device from addr cache
  * @dev: device to remove
  *
  * Remove a device from the addr-cache tree.
@@ -266,17 +267,17 @@ restart:
  * the tree multiple times (once per resource).
  * But so what; device removal doesn't need to be that fast.
  */
-void pci_addr_cache_remove_device(struct pci_dev *dev)
+void eeh_addr_cache_rmv_dev(struct pci_dev *dev)
 {
         unsigned long flags;
 
         spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
-        __pci_addr_cache_remove_device(dev);
+        __eeh_addr_cache_rmv_dev(dev);
         spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
 }
 
 /**
- * pci_addr_cache_build - Build a cache of I/O addresses
+ * eeh_addr_cache_build - Build a cache of I/O addresses
  *
  * Build a cache of pci i/o addresses.  This cache will be used to
  * find the pci device that corresponds to a given address.
@@ -284,7 +285,7 @@ void pci_addr_cache_remove_device(struct pci_dev *dev)
  * Must be run late in boot process, after the pci controllers
  * have been scanned for devices (after all device resources are known).
  */
-void __init pci_addr_cache_build(void)
+void __init eeh_addr_cache_build(void)
 {
         struct device_node *dn;
         struct eeh_dev *edev;
@@ -293,7 +294,7 @@ void __init pci_addr_cache_build(void)
         spin_lock_init(&pci_io_addr_cache_root.piar_lock);
 
         for_each_pci_dev(dev) {
-                pci_addr_cache_insert_device(dev);
+                eeh_addr_cache_insert_dev(dev);
 
                 dn = pci_device_to_OF_node(dev);
                 if (!dn)
@@ -312,7 +313,7 @@ void __init pci_addr_cache_build(void)
 
 #ifdef DEBUG
         /* Verify tree built up above, echo back the list of addrs. */
-        pci_addr_cache_print(&pci_io_addr_cache_root);
+        eeh_addr_cache_print(&pci_io_addr_cache_root);
 #endif
 }
 
diff --git a/arch/powerpc/platforms/pseries/eeh_dev.c b/arch/powerpc/platforms/pseries/eeh_dev.c
index c4507d095900..66442341d3a6 100644
--- a/arch/powerpc/platforms/pseries/eeh_dev.c
+++ b/arch/powerpc/platforms/pseries/eeh_dev.c
@@ -55,7 +55,7 @@ void * __devinit eeh_dev_init(struct device_node *dn, void *data)
         struct eeh_dev *edev;
 
         /* Allocate EEH device */
-        edev = zalloc_maybe_bootmem(sizeof(*edev), GFP_KERNEL);
+        edev = kzalloc(sizeof(*edev), GFP_KERNEL);
         if (!edev) {
                 pr_warning("%s: out of memory\n", __func__);
                 return NULL;
@@ -65,6 +65,7 @@ void * __devinit eeh_dev_init(struct device_node *dn, void *data)
         PCI_DN(dn)->edev = edev;
         edev->dn  = dn;
         edev->phb = phb;
+        INIT_LIST_HEAD(&edev->list);
 
         return NULL;
 }
@@ -80,6 +81,9 @@ void __devinit eeh_dev_phb_init_dynamic(struct pci_controller *phb)
 {
         struct device_node *dn = phb->dn;
 
+        /* EEH PE for PHB */
+        eeh_phb_pe_create(phb);
+
         /* EEH device for PHB */
         eeh_dev_init(dn, phb);
 
@@ -93,10 +97,16 @@ void __devinit eeh_dev_phb_init_dynamic(struct pci_controller *phb)
  * Scan all the existing PHBs and create EEH devices for their OF
  * nodes and their children OF nodes
  */
-void __init eeh_dev_phb_init(void)
+static int __init eeh_dev_phb_init(void)
 {
         struct pci_controller *phb, *tmp;
 
         list_for_each_entry_safe(phb, tmp, &hose_list, list_node)
                 eeh_dev_phb_init_dynamic(phb);
+
+        pr_info("EEH: devices created\n");
+
+        return 0;
 }
+
+core_initcall(eeh_dev_phb_init);
diff --git a/arch/powerpc/platforms/pseries/eeh_driver.c b/arch/powerpc/platforms/pseries/eeh_driver.c
index baf92cd9dfab..a3fefb61097c 100644
--- a/arch/powerpc/platforms/pseries/eeh_driver.c
+++ b/arch/powerpc/platforms/pseries/eeh_driver.c
@@ -25,6 +25,7 @@
 #include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/module.h>
 #include <linux/pci.h>
 #include <asm/eeh.h>
 #include <asm/eeh_event.h>
@@ -47,6 +48,41 @@ static inline const char *eeh_pcid_name(struct pci_dev *pdev)
         return "";
 }
 
+/**
+ * eeh_pcid_get - Get the PCI device driver
+ * @pdev: PCI device
+ *
+ * The function is used to retrieve the PCI device driver for
+ * the indicated PCI device. Besides, we will increase the reference
+ * of the PCI device driver to prevent that being unloaded on
+ * the fly. Otherwise, kernel crash would be seen.
+ */
+static inline struct pci_driver *eeh_pcid_get(struct pci_dev *pdev)
+{
+        if (!pdev || !pdev->driver)
+                return NULL;
+
+        if (!try_module_get(pdev->driver->driver.owner))
+                return NULL;
+
+        return pdev->driver;
+}
+
+/**
+ * eeh_pcid_put - Dereference on the PCI device driver
+ * @pdev: PCI device
+ *
+ * The function is called to do dereference on the PCI device
+ * driver of the indicated PCI device.
+ */
+static inline void eeh_pcid_put(struct pci_dev *pdev)
+{
+        if (!pdev || !pdev->driver)
+                return;
+
+        module_put(pdev->driver->driver.owner);
+}
+
 #if 0
 static void print_device_node_tree(struct pci_dn *pdn, int dent)
 {
@@ -93,7 +129,7 @@ static void eeh_disable_irq(struct pci_dev *dev)
         if (!irq_has_action(dev->irq))
                 return;
 
-        edev->mode |= EEH_MODE_IRQ_DISABLED;
+        edev->mode |= EEH_DEV_IRQ_DISABLED;
         disable_irq_nosync(dev->irq);
 }
 
@@ -108,36 +144,44 @@ static void eeh_enable_irq(struct pci_dev *dev)
 {
         struct eeh_dev *edev = pci_dev_to_eeh_dev(dev);
 
-        if ((edev->mode) & EEH_MODE_IRQ_DISABLED) {
-                edev->mode &= ~EEH_MODE_IRQ_DISABLED;
+        if ((edev->mode) & EEH_DEV_IRQ_DISABLED) {
+                edev->mode &= ~EEH_DEV_IRQ_DISABLED;
                 enable_irq(dev->irq);
         }
 }
 
 /**
  * eeh_report_error - Report pci error to each device driver
- * @dev: PCI device
+ * @data: eeh device
  * @userdata: return value
  * 
  * Report an EEH error to each device driver, collect up and 
  * merge the device driver responses. Cumulative response 
  * passed back in "userdata".
  */
-static int eeh_report_error(struct pci_dev *dev, void *userdata)
+static void *eeh_report_error(void *data, void *userdata)
 {
+        struct eeh_dev *edev = (struct eeh_dev *)data;
+        struct pci_dev *dev = eeh_dev_to_pci_dev(edev);
         enum pci_ers_result rc, *res = userdata;
-        struct pci_driver *driver = dev->driver;
+        struct pci_driver *driver;
 
+        /* We might not have the associated PCI device,
+         * then we should continue for next one.
+         */
+        if (!dev) return NULL;
         dev->error_state = pci_channel_io_frozen;
 
-        if (!driver)
-                return 0;
+        driver = eeh_pcid_get(dev);
+        if (!driver) return NULL;
 
         eeh_disable_irq(dev);
 
         if (!driver->err_handler ||
-            !driver->err_handler->error_detected)
-                return 0;
+            !driver->err_handler->error_detected) {
+                eeh_pcid_put(dev);
+                return NULL;
+        }
 
         rc = driver->err_handler->error_detected(dev, pci_channel_io_frozen);
 
@@ -145,27 +189,34 @@ static int eeh_report_error(struct pci_dev *dev, void *userdata)
         if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc;
         if (*res == PCI_ERS_RESULT_NONE) *res = rc;
 
-        return 0;
+        eeh_pcid_put(dev);
+        return NULL;
 }
 
 /**
  * eeh_report_mmio_enabled - Tell drivers that MMIO has been enabled
- * @dev: PCI device
+ * @data: eeh device
  * @userdata: return value
  *
  * Tells each device driver that IO ports, MMIO and config space I/O
  * are now enabled. Collects up and merges the device driver responses.
  * Cumulative response passed back in "userdata".
  */
-static int eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata)
+static void *eeh_report_mmio_enabled(void *data, void *userdata)
 {
+        struct eeh_dev *edev = (struct eeh_dev *)data;
+        struct pci_dev *dev = eeh_dev_to_pci_dev(edev);
         enum pci_ers_result rc, *res = userdata;
-        struct pci_driver *driver = dev->driver;
+        struct pci_driver *driver;
 
-        if (!driver ||
-            !driver->err_handler ||
-            !driver->err_handler->mmio_enabled)
-                return 0;
+        driver = eeh_pcid_get(dev);
+        if (!driver) return NULL;
+
+        if (!driver->err_handler ||
+            !driver->err_handler->mmio_enabled) {
+                eeh_pcid_put(dev);
+                return NULL;
+        }
 
         rc = driver->err_handler->mmio_enabled(dev);
 
@@ -173,12 +224,13 @@ static int eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata)
         if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc;
         if (*res == PCI_ERS_RESULT_NONE) *res = rc;
 
-        return 0;
+        eeh_pcid_put(dev);
+        return NULL;
 }
 
 /**
  * eeh_report_reset - Tell device that slot has been reset
- * @dev: PCI device
+ * @data: eeh device
  * @userdata: return value
  *
  * This routine must be called while EEH tries to reset particular
@@ -186,21 +238,26 @@ static int eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata)
  * some actions, usually to save data the driver needs so that the
  * driver can work again while the device is recovered.
  */
-static int eeh_report_reset(struct pci_dev *dev, void *userdata)
+static void *eeh_report_reset(void *data, void *userdata)
 {
+        struct eeh_dev *edev = (struct eeh_dev *)data;
+        struct pci_dev *dev = eeh_dev_to_pci_dev(edev);
         enum pci_ers_result rc, *res = userdata;
-        struct pci_driver *driver = dev->driver;
-
-        if (!driver)
-                return 0;
+        struct pci_driver *driver;
 
+        if (!dev) return NULL;
         dev->error_state = pci_channel_io_normal;
 
+        driver = eeh_pcid_get(dev);
+        if (!driver) return NULL;
+
         eeh_enable_irq(dev);
 
         if (!driver->err_handler ||
-            !driver->err_handler->slot_reset)
-                return 0;
+            !driver->err_handler->slot_reset) {
+                eeh_pcid_put(dev);
+                return NULL;
+        }
 
         rc = driver->err_handler->slot_reset(dev);
         if ((*res == PCI_ERS_RESULT_NONE) ||
@@ -208,109 +265,115 @@ static int eeh_report_reset(struct pci_dev *dev, void *userdata)
         if (*res == PCI_ERS_RESULT_DISCONNECT &&
              rc == PCI_ERS_RESULT_NEED_RESET) *res = rc;
 
-        return 0;
+        eeh_pcid_put(dev);
+        return NULL;
 }
 
 /**
  * eeh_report_resume - Tell device to resume normal operations
- * @dev: PCI device
+ * @data: eeh device
  * @userdata: return value
  *
  * This routine must be called to notify the device driver that it
  * could resume so that the device driver can do some initialization
  * to make the recovered device work again.
  */
-static int eeh_report_resume(struct pci_dev *dev, void *userdata)
+static void *eeh_report_resume(void *data, void *userdata)
 {
-        struct pci_driver *driver = dev->driver;
+        struct eeh_dev *edev = (struct eeh_dev *)data;
+        struct pci_dev *dev = eeh_dev_to_pci_dev(edev);
+        struct pci_driver *driver;
 
+        if (!dev) return NULL;
         dev->error_state = pci_channel_io_normal;
 
-        if (!driver)
-                return 0;
+        driver = eeh_pcid_get(dev);
+        if (!driver) return NULL;
 
         eeh_enable_irq(dev);
 
         if (!driver->err_handler ||
-            !driver->err_handler->resume)
-                return 0;
+            !driver->err_handler->resume) {
+                eeh_pcid_put(dev);
+                return NULL;
+        }
 
         driver->err_handler->resume(dev);
 
-        return 0;
+        eeh_pcid_put(dev);
+        return NULL;
 }
 
 /**
  * eeh_report_failure - Tell device driver that device is dead.
- * @dev: PCI device
+ * @data: eeh device
  * @userdata: return value
  *
  * This informs the device driver that the device is permanently
  * dead, and that no further recovery attempts will be made on it.
  */
-static int eeh_report_failure(struct pci_dev *dev, void *userdata)
+static void *eeh_report_failure(void *data, void *userdata)
 {
-        struct pci_driver *driver = dev->driver;
+        struct eeh_dev *edev = (struct eeh_dev *)data;
+        struct pci_dev *dev = eeh_dev_to_pci_dev(edev);
+        struct pci_driver *driver;
 
+        if (!dev) return NULL;
         dev->error_state = pci_channel_io_perm_failure;
 
-        if (!driver)
-                return 0;
+        driver = eeh_pcid_get(dev);
+        if (!driver) return NULL;
 
         eeh_disable_irq(dev);
 
         if (!driver->err_handler ||
-            !driver->err_handler->error_detected)
-                return 0;
+            !driver->err_handler->error_detected) {
+                eeh_pcid_put(dev);
+                return NULL;
+        }
 
         driver->err_handler->error_detected(dev, pci_channel_io_perm_failure);
 
-        return 0;
+        eeh_pcid_put(dev);
+        return NULL;
 }
 
 /**
  * eeh_reset_device - Perform actual reset of a pci slot
- * @edev: PE associated EEH device
+ * @pe: EEH PE
  * @bus: PCI bus corresponding to the isolcated slot
  *
  * This routine must be called to do reset on the indicated PE.
  * During the reset, udev might be invoked because those affected
  * PCI devices will be removed and then added.
  */
-static int eeh_reset_device(struct eeh_dev *edev, struct pci_bus *bus)
+static int eeh_reset_device(struct eeh_pe *pe, struct pci_bus *bus)
 {
-        struct device_node *dn;
         int cnt, rc;
 
         /* pcibios will clear the counter; save the value */
-        cnt = edev->freeze_count;
+        cnt = pe->freeze_count;
 
+        /*
+         * We don't remove the corresponding PE instances because
+         * we need the information afterwords. The attached EEH
+         * devices are expected to be attached soon when calling
+         * into pcibios_add_pci_devices().
+         */
         if (bus)
-                pcibios_remove_pci_devices(bus);
+                __pcibios_remove_pci_devices(bus, 0);
 
         /* Reset the pci controller. (Asserts RST#; resets config space).
          * Reconfigure bridges and devices. Don't try to bring the system
          * up if the reset failed for some reason.
          */
-        rc = eeh_reset_pe(edev);
+        rc = eeh_reset_pe(pe);
         if (rc)
                 return rc;
 
-        /* Walk over all functions on this device. */
-        dn = eeh_dev_to_of_node(edev);
-        if (!pcibios_find_pci_bus(dn) && of_node_to_eeh_dev(dn->parent))
-                dn = dn->parent->child;
-
-        while (dn) {
-                struct eeh_dev *pedev = of_node_to_eeh_dev(dn);
-
-                /* On Power4, always true because eeh_pe_config_addr=0 */
-                if (edev->pe_config_addr == pedev->pe_config_addr) {
-                        eeh_ops->configure_bridge(dn);
-                        eeh_restore_bars(pedev);
-                }
-                dn = dn->sibling;
-        }
+        /* Restore PE */
+        eeh_ops->configure_bridge(pe);
+        eeh_pe_restore_bars(pe);
 
         /* Give the system 5 seconds to finish running the user-space
          * hotplug shutdown scripts, e.g. ifdown for ethernet.  Yes, 
@@ -322,7 +385,7 @@ static int eeh_reset_device(struct eeh_dev *edev, struct pci_bus *bus)
                 ssleep(5);
                 pcibios_add_pci_devices(bus);
         }
-        edev->freeze_count = cnt;
+        pe->freeze_count = cnt;
 
         return 0;
 }
@@ -334,7 +397,7 @@ static int eeh_reset_device(struct eeh_dev *edev, struct pci_bus *bus)
 
 /**
  * eeh_handle_event - Reset a PCI device after hard lockup.
- * @event: EEH event
+ * @pe: EEH PE
  *
  * While PHB detects address or data parity errors on particular PCI
  * slot, the associated PE will be frozen. Besides, DMA's occurring
@@ -349,69 +412,24 @@ static int eeh_reset_device(struct eeh_dev *edev, struct pci_bus *bus)
  * drivers (which cause a second set of hotplug events to go out to
  * userspace).
  */
-struct eeh_dev *handle_eeh_events(struct eeh_event *event)
+void eeh_handle_event(struct eeh_pe *pe)
 {
-        struct device_node *frozen_dn;
-        struct eeh_dev *frozen_edev;
         struct pci_bus *frozen_bus;
         int rc = 0;
         enum pci_ers_result result = PCI_ERS_RESULT_NONE;
-        const char *location, *pci_str, *drv_str, *bus_pci_str, *bus_drv_str;
-
-        frozen_dn = eeh_find_device_pe(eeh_dev_to_of_node(event->edev));
-        if (!frozen_dn) {
-                location = of_get_property(eeh_dev_to_of_node(event->edev), "ibm,loc-code", NULL);
-                location = location ? location : "unknown";
-                printk(KERN_ERR "EEH: Error: Cannot find partition endpoint "
-                                "for location=%s pci addr=%s\n",
-                        location, eeh_pci_name(eeh_dev_to_pci_dev(event->edev)));
-                return NULL;
-        }
-
-        frozen_bus = pcibios_find_pci_bus(frozen_dn);
-        location = of_get_property(frozen_dn, "ibm,loc-code", NULL);
-        location = location ? location : "unknown";
-
-        /* There are two different styles for coming up with the PE.
-         * In the old style, it was the highest EEH-capable device
-         * which was always an EADS pci bridge.  In the new style,
-         * there might not be any EADS bridges, and even when there are,
-         * the firmware marks them as "EEH incapable". So another
-         * two-step is needed to find the pci bus..
-         */
-        if (!frozen_bus)
-                frozen_bus = pcibios_find_pci_bus(frozen_dn->parent);
 
+        frozen_bus = eeh_pe_bus_get(pe);
         if (!frozen_bus) {
-                printk(KERN_ERR "EEH: Cannot find PCI bus "
-                        "for location=%s dn=%s\n",
-                        location, frozen_dn->full_name);
-                return NULL;
+                pr_err("%s: Cannot find PCI bus for PHB#%d-PE#%x\n",
+                        __func__, pe->phb->global_number, pe->addr);
+                return;
         }
 
-        frozen_edev = of_node_to_eeh_dev(frozen_dn);
-        frozen_edev->freeze_count++;
-        pci_str = eeh_pci_name(eeh_dev_to_pci_dev(event->edev));
-        drv_str = eeh_pcid_name(eeh_dev_to_pci_dev(event->edev));
-
-        if (frozen_edev->freeze_count > EEH_MAX_ALLOWED_FREEZES)
+        pe->freeze_count++;
+        if (pe->freeze_count > EEH_MAX_ALLOWED_FREEZES)
                 goto excess_failures;
-
-        printk(KERN_WARNING
-           "EEH: This PCI device has failed %d times in the last hour:\n",
-                frozen_edev->freeze_count);
-
-        if (frozen_edev->pdev) {
-                bus_pci_str = pci_name(frozen_edev->pdev);
-                bus_drv_str = eeh_pcid_name(frozen_edev->pdev);
-                printk(KERN_WARNING
-                        "EEH: Bus location=%s driver=%s pci addr=%s\n",
-                        location, bus_drv_str, bus_pci_str);
-        }
-
-        printk(KERN_WARNING
-                "EEH: Device location=%s driver=%s pci addr=%s\n",
-                location, drv_str, pci_str);
+        pr_warning("EEH: This PCI device has failed %d times in the last hour\n",
+                pe->freeze_count);
 
         /* Walk the various device drivers attached to this slot through
          * a reset sequence, giving each an opportunity to do what it needs
@@ -419,12 +437,12 @@ struct eeh_dev *handle_eeh_events(struct eeh_event *event)
          * status ... if any child can't handle the reset, then the entire
          * slot is dlpar removed and added.
          */
-        pci_walk_bus(frozen_bus, eeh_report_error, &result);
+        eeh_pe_dev_traverse(pe, eeh_report_error, &result);
 
         /* Get the current PCI slot state. This can take a long time,
          * sometimes over 3 seconds for certain systems.
          */
-        rc = eeh_ops->wait_state(eeh_dev_to_of_node(frozen_edev), MAX_WAIT_FOR_RECOVERY*1000);
+        rc = eeh_ops->wait_state(pe, MAX_WAIT_FOR_RECOVERY*1000);
         if (rc < 0 || rc == EEH_STATE_NOT_SUPPORT) {
                 printk(KERN_WARNING "EEH: Permanent failure\n");
                 goto hard_fail;
@@ -434,14 +452,14 @@ struct eeh_dev *handle_eeh_events(struct eeh_event *event)
          * don't post the error log until after all dev drivers
          * have been informed.
          */
-        eeh_slot_error_detail(frozen_edev, EEH_LOG_TEMP);
+        eeh_slot_error_detail(pe, EEH_LOG_TEMP);
 
         /* If all device drivers were EEH-unaware, then shut
          * down all of the device drivers, and hope they
          * go down willingly, without panicing the system.
          */
         if (result == PCI_ERS_RESULT_NONE) {
-                rc = eeh_reset_device(frozen_edev, frozen_bus);
+                rc = eeh_reset_device(pe, frozen_bus);
                 if (rc) {
                         printk(KERN_WARNING "EEH: Unable to reset, rc=%d\n", rc);
                         goto hard_fail;
@@ -450,7 +468,7 @@ struct eeh_dev *handle_eeh_events(struct eeh_event *event)
 
         /* If all devices reported they can proceed, then re-enable MMIO */
         if (result == PCI_ERS_RESULT_CAN_RECOVER) {
-                rc = eeh_pci_enable(frozen_edev, EEH_OPT_THAW_MMIO);
+                rc = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
 
                 if (rc < 0)
                         goto hard_fail;
@@ -458,13 +476,13 @@ struct eeh_dev *handle_eeh_events(struct eeh_event *event)
                         result = PCI_ERS_RESULT_NEED_RESET;
                 } else {
                         result = PCI_ERS_RESULT_NONE;
-                        pci_walk_bus(frozen_bus, eeh_report_mmio_enabled, &result);
+                        eeh_pe_dev_traverse(pe, eeh_report_mmio_enabled, &result);
                 }
         }
 
         /* If all devices reported they can proceed, then re-enable DMA */
         if (result == PCI_ERS_RESULT_CAN_RECOVER) {
-                rc = eeh_pci_enable(frozen_edev, EEH_OPT_THAW_DMA);
+                rc = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);
 
                 if (rc < 0)
                         goto hard_fail;
@@ -482,13 +500,13 @@ struct eeh_dev *handle_eeh_events(struct eeh_event *event)
 
         /* If any device called out for a reset, then reset the slot */
         if (result == PCI_ERS_RESULT_NEED_RESET) {
-                rc = eeh_reset_device(frozen_edev, NULL);
+                rc = eeh_reset_device(pe, NULL);
                 if (rc) {
                         printk(KERN_WARNING "EEH: Cannot reset, rc=%d\n", rc);
                         goto hard_fail;
                 }
                 result = PCI_ERS_RESULT_NONE;
-                pci_walk_bus(frozen_bus, eeh_report_reset, &result);
+                eeh_pe_dev_traverse(pe, eeh_report_reset, &result);
         }
 
         /* All devices should claim they have recovered by now. */
@@ -499,9 +517,9 @@ struct eeh_dev *handle_eeh_events(struct eeh_event *event)
         }
 
         /* Tell all device drivers that they can resume operations */
-        pci_walk_bus(frozen_bus, eeh_report_resume, NULL);
+        eeh_pe_dev_traverse(pe, eeh_report_resume, NULL);
 
-        return frozen_edev;
+        return;
         
 excess_failures:
         /*
@@ -509,30 +527,26 @@ excess_failures:
          * are due to poorly seated PCI cards. Only 10% or so are
          * due to actual, failed cards.
          */
-        printk(KERN_ERR
-           "EEH: PCI device at location=%s driver=%s pci addr=%s\n"
-                "has failed %d times in the last hour "
-                "and has been permanently disabled.\n"
-                "Please try reseating this device or replacing it.\n",
-                location, drv_str, pci_str, frozen_edev->freeze_count);
+        pr_err("EEH: PHB#%d-PE#%x has failed %d times in the\n"
+               "last hour and has been permanently disabled.\n"
+               "Please try reseating or replacing it.\n",
+                pe->phb->global_number, pe->addr,
+                pe->freeze_count);
         goto perm_error;
 
 hard_fail:
-        printk(KERN_ERR
-           "EEH: Unable to recover from failure of PCI device "
-           "at location=%s driver=%s pci addr=%s\n"
-           "Please try reseating this device or replacing it.\n",
-                location, drv_str, pci_str);
+        pr_err("EEH: Unable to recover from failure from PHB#%d-PE#%x.\n"
+               "Please try reseating or replacing it\n",
+                pe->phb->global_number, pe->addr);
 
 perm_error:
-        eeh_slot_error_detail(frozen_edev, EEH_LOG_PERM);
+        eeh_slot_error_detail(pe, EEH_LOG_PERM);
 
         /* Notify all devices that they're about to go down. */
-        pci_walk_bus(frozen_bus, eeh_report_failure, NULL);
+        eeh_pe_dev_traverse(pe, eeh_report_failure, NULL);
 
         /* Shut down the device drivers for good. */
-        pcibios_remove_pci_devices(frozen_bus);
-
-        return NULL;
+        if (frozen_bus)
+                pcibios_remove_pci_devices(frozen_bus);
 }
 
diff --git a/arch/powerpc/platforms/pseries/eeh_event.c b/arch/powerpc/platforms/pseries/eeh_event.c
index fb506317ebb0..51faaac8abe6 100644
--- a/arch/powerpc/platforms/pseries/eeh_event.c
+++ b/arch/powerpc/platforms/pseries/eeh_event.c
@@ -57,7 +57,7 @@ static int eeh_event_handler(void * dummy)
 {
         unsigned long flags;
         struct eeh_event *event;
-        struct eeh_dev *edev;
+        struct eeh_pe *pe;
 
         set_task_comm(current, "eehd");
 
@@ -76,28 +76,23 @@ static int eeh_event_handler(void * dummy)
 
         /* Serialize processing of EEH events */
         mutex_lock(&eeh_event_mutex);
-        edev = event->edev;
-        eeh_mark_slot(eeh_dev_to_of_node(edev), EEH_MODE_RECOVERING);
-
-        printk(KERN_INFO "EEH: Detected PCI bus error on device %s\n",
-               eeh_pci_name(edev->pdev));
+        pe = event->pe;
+        eeh_pe_state_mark(pe, EEH_PE_RECOVERING);
+        pr_info("EEH: Detected PCI bus error on PHB#%d-PE#%x\n",
+                pe->phb->global_number, pe->addr);
 
         set_current_state(TASK_INTERRUPTIBLE);  /* Don't add to load average */
-        edev = handle_eeh_events(event);
-
-        if (edev) {
-                eeh_clear_slot(eeh_dev_to_of_node(edev), EEH_MODE_RECOVERING);
-                pci_dev_put(edev->pdev);
-        }
+        eeh_handle_event(pe);
+        eeh_pe_state_clear(pe, EEH_PE_RECOVERING);
 
         kfree(event);
         mutex_unlock(&eeh_event_mutex);
 
         /* If there are no new errors after an hour, clear the counter. */
-        if (edev && edev->freeze_count>0) {
+        if (pe && pe->freeze_count > 0) {
                 msleep_interruptible(3600*1000);
-                if (edev->freeze_count>0)
-                        edev->freeze_count--;
+                if (pe->freeze_count > 0)
+                        pe->freeze_count--;
 
         }
 
@@ -119,36 +114,23 @@ static void eeh_thread_launcher(struct work_struct *dummy)
 
 /**
  * eeh_send_failure_event - Generate a PCI error event
- * @edev: EEH device
+ * @pe: EEH PE
  *
  * This routine can be called within an interrupt context;
  * the actual event will be delivered in a normal context
  * (from a workqueue).
  */
-int eeh_send_failure_event(struct eeh_dev *edev)
+int eeh_send_failure_event(struct eeh_pe *pe)
 {
         unsigned long flags;
         struct eeh_event *event;
-        struct device_node *dn = eeh_dev_to_of_node(edev);
-        const char *location;
-
-        if (!mem_init_done) {
-                printk(KERN_ERR "EEH: event during early boot not handled\n");
-                location = of_get_property(dn, "ibm,loc-code", NULL);
-                printk(KERN_ERR "EEH: device node = %s\n", dn->full_name);
-                printk(KERN_ERR "EEH: PCI location = %s\n", location);
-                return 1;
-        }
-        event = kmalloc(sizeof(*event), GFP_ATOMIC);
-        if (event == NULL) {
-                printk(KERN_ERR "EEH: out of memory, event not handled\n");
-                return 1;
-        }
-
-        if (edev->pdev)
-                pci_dev_get(edev->pdev);
 
-        event->edev = edev;
+        event = kzalloc(sizeof(*event), GFP_ATOMIC);
+        if (!event) {
+                pr_err("EEH: out of memory, event not handled\n");
+                return -ENOMEM;
+        }
+        event->pe = pe;
 
         /* We may or may not be called in an interrupt context */
         spin_lock_irqsave(&eeh_eventlist_lock, flags);
diff --git a/arch/powerpc/platforms/pseries/eeh_pe.c b/arch/powerpc/platforms/pseries/eeh_pe.c
new file mode 100644
index 000000000000..797cd181dc3f
--- /dev/null
+++ b/arch/powerpc/platforms/pseries/eeh_pe.c
@@ -0,0 +1,652 @@
+/*
+ * The file intends to implement PE based on the information from
+ * platforms. Basically, there have 3 types of PEs: PHB/Bus/Device.
+ * All the PEs should be organized as hierarchy tree. The first level
+ * of the tree will be associated to existing PHBs since the particular
+ * PE is only meaningful in one PHB domain.
+ *
+ * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2012.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#include <linux/export.h>
+#include <linux/gfp.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/string.h>
+
+#include <asm/pci-bridge.h>
+#include <asm/ppc-pci.h>
+
+static LIST_HEAD(eeh_phb_pe);
+
+/**
+ * eeh_pe_alloc - Allocate PE
+ * @phb: PCI controller
+ * @type: PE type
+ *
+ * Allocate PE instance dynamically.
+ */
+static struct eeh_pe *eeh_pe_alloc(struct pci_controller *phb, int type)
+{
+        struct eeh_pe *pe;
+
+        /* Allocate PHB PE */
+        pe = kzalloc(sizeof(struct eeh_pe), GFP_KERNEL);
+        if (!pe) return NULL;
+
+        /* Initialize PHB PE */
+        pe->type = type;
+        pe->phb = phb;
+        INIT_LIST_HEAD(&pe->child_list);
+        INIT_LIST_HEAD(&pe->child);
+        INIT_LIST_HEAD(&pe->edevs);
+
+        return pe;
+}
+
+/**
+ * eeh_phb_pe_create - Create PHB PE
+ * @phb: PCI controller
+ *
+ * The function should be called while the PHB is detected during
+ * system boot or PCI hotplug in order to create PHB PE.
+ */
+int __devinit eeh_phb_pe_create(struct pci_controller *phb)
+{
+        struct eeh_pe *pe;
+
+        /* Allocate PHB PE */
+        pe = eeh_pe_alloc(phb, EEH_PE_PHB);
+        if (!pe) {
+                pr_err("%s: out of memory!\n", __func__);
+                return -ENOMEM;
+        }
+
+        /* Put it into the list */
+        eeh_lock();
+        list_add_tail(&pe->child, &eeh_phb_pe);
+        eeh_unlock();
+
+        pr_debug("EEH: Add PE for PHB#%d\n", phb->global_number);
+
+        return 0;
+}
+
+/**
+ * eeh_phb_pe_get - Retrieve PHB PE based on the given PHB
+ * @phb: PCI controller
+ *
+ * The overall PEs form hierarchy tree. The first layer of the
+ * hierarchy tree is composed of PHB PEs. The function is used
+ * to retrieve the corresponding PHB PE according to the given PHB.
+ */
+static struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb)
+{
+        struct eeh_pe *pe;
+
+        list_for_each_entry(pe, &eeh_phb_pe, child) {
+                /*
+                 * Actually, we needn't check the type since
+                 * the PE for PHB has been determined when that
+                 * was created.
+                 */
+                if ((pe->type & EEH_PE_PHB) && pe->phb == phb)
+                        return pe;
+        }
+
+        return NULL;
+}
+
+/**
+ * eeh_pe_next - Retrieve the next PE in the tree
+ * @pe: current PE
+ * @root: root PE
+ *
+ * The function is used to retrieve the next PE in the
+ * hierarchy PE tree.
+ */
+static struct eeh_pe *eeh_pe_next(struct eeh_pe *pe,
+                                  struct eeh_pe *root)
+{
+        struct list_head *next = pe->child_list.next;
+
+        if (next == &pe->child_list) {
+                while (1) {
+                        if (pe == root)
+                                return NULL;
+                        next = pe->child.next;
+                        if (next != &pe->parent->child_list)
+                                break;
+                        pe = pe->parent;
+                }
+        }
+
+        return list_entry(next, struct eeh_pe, child);
+}
+
+/**
+ * eeh_pe_traverse - Traverse PEs in the specified PHB
+ * @root: root PE
+ * @fn: callback
+ * @flag: extra parameter to callback
+ *
+ * The function is used to traverse the specified PE and its
+ * child PEs. The traversing is to be terminated once the
+ * callback returns something other than NULL, or no more PEs
+ * to be traversed.
+ */
+static void *eeh_pe_traverse(struct eeh_pe *root,
+                        eeh_traverse_func fn, void *flag)
+{
+        struct eeh_pe *pe;
+        void *ret;
+
+        for (pe = root; pe; pe = eeh_pe_next(pe, root)) {
+                ret = fn(pe, flag);
+                if (ret) return ret;
+        }
+
+        return NULL;
+}
+
+/**
+ * eeh_pe_dev_traverse - Traverse the devices from the PE
+ * @root: EEH PE
+ * @fn: function callback
+ * @flag: extra parameter to callback
+ *
+ * The function is used to traverse the devices of the specified
+ * PE and its child PEs.
+ */
+void *eeh_pe_dev_traverse(struct eeh_pe *root,
+                eeh_traverse_func fn, void *flag)
+{
+        struct eeh_pe *pe;
+        struct eeh_dev *edev;
+        void *ret;
+
+        if (!root) {
+                pr_warning("%s: Invalid PE %p\n", __func__, root);
+                return NULL;
+        }
+
+        eeh_lock();
+
+        /* Traverse root PE */
+        for (pe = root; pe; pe = eeh_pe_next(pe, root)) {
+                eeh_pe_for_each_dev(pe, edev) {
+                        ret = fn(edev, flag);
+                        if (ret) {
+                                eeh_unlock();
+                                return ret;
+                        }
+                }
+        }
+
+        eeh_unlock();
+
+        return NULL;
+}
+
+/**
+ * __eeh_pe_get - Check the PE address
+ * @data: EEH PE
+ * @flag: EEH device
+ *
+ * For one particular PE, it can be identified by PE address
+ * or tranditional BDF address. BDF address is composed of
+ * Bus/Device/Function number. The extra data referred by flag
+ * indicates which type of address should be used.
+ */
+static void *__eeh_pe_get(void *data, void *flag)
+{
+        struct eeh_pe *pe = (struct eeh_pe *)data;
+        struct eeh_dev *edev = (struct eeh_dev *)flag;
+
+        /* Unexpected PHB PE */
+        if (pe->type & EEH_PE_PHB)
+                return NULL;
+
+        /* We prefer PE address */
+        if (edev->pe_config_addr &&
+           (edev->pe_config_addr == pe->addr))
+                return pe;
+
+        /* Try BDF address */
+        if (edev->pe_config_addr &&
+           (edev->config_addr == pe->config_addr))
+                return pe;
+
+        return NULL;
+}
+
+/**
+ * eeh_pe_get - Search PE based on the given address
+ * @edev: EEH device
+ *
+ * Search the corresponding PE based on the specified address which
+ * is included in the eeh device. The function is used to check if
+ * the associated PE has been created against the PE address. It's
+ * notable that the PE address has 2 format: traditional PE address
+ * which is composed of PCI bus/device/function number, or unified
+ * PE address.
+ */
+static struct eeh_pe *eeh_pe_get(struct eeh_dev *edev)
+{
+        struct eeh_pe *root = eeh_phb_pe_get(edev->phb);
+        struct eeh_pe *pe;
+
+        pe = eeh_pe_traverse(root, __eeh_pe_get, edev);
+
+        return pe;
+}
+
+/**
+ * eeh_pe_get_parent - Retrieve the parent PE
+ * @edev: EEH device
+ *
+ * The whole PEs existing in the system are organized as hierarchy
+ * tree. The function is used to retrieve the parent PE according
+ * to the parent EEH device.
+ */
+static struct eeh_pe *eeh_pe_get_parent(struct eeh_dev *edev)
+{
+        struct device_node *dn;
+        struct eeh_dev *parent;
+
+        /*
+         * It might have the case for the indirect parent
+         * EEH device already having associated PE, but
+         * the direct parent EEH device doesn't have yet.
+         */
+        dn = edev->dn->parent;
+        while (dn) {
+                /* We're poking out of PCI territory */
+                if (!PCI_DN(dn)) return NULL;
+
+                parent = of_node_to_eeh_dev(dn);
+                /* We're poking out of PCI territory */
+                if (!parent) return NULL;
+
+                if (parent->pe)
+                        return parent->pe;
+
+                dn = dn->parent;
+        }
+
+        return NULL;
+}
+
+/**
+ * eeh_add_to_parent_pe - Add EEH device to parent PE
+ * @edev: EEH device
+ *
+ * Add EEH device to the parent PE. If the parent PE already
+ * exists, the PE type will be changed to EEH_PE_BUS. Otherwise,
+ * we have to create new PE to hold the EEH device and the new
+ * PE will be linked to its parent PE as well.
+ */
+int eeh_add_to_parent_pe(struct eeh_dev *edev)
+{
+        struct eeh_pe *pe, *parent;
+
+        eeh_lock();
+
+        /*
+         * Search the PE has been existing or not according
+         * to the PE address. If that has been existing, the
+         * PE should be composed of PCI bus and its subordinate
+         * components.
+         */
+        pe = eeh_pe_get(edev);
+        if (pe && !(pe->type & EEH_PE_INVALID)) {
+                if (!edev->pe_config_addr) {
+                        eeh_unlock();
+                        pr_err("%s: PE with addr 0x%x already exists\n",
+                                __func__, edev->config_addr);
+                        return -EEXIST;
+                }
+
+                /* Mark the PE as type of PCI bus */
+                pe->type = EEH_PE_BUS;
+                edev->pe = pe;
+
+                /* Put the edev to PE */
+                list_add_tail(&edev->list, &pe->edevs);
+                eeh_unlock();
+                pr_debug("EEH: Add %s to Bus PE#%x\n",
+                        edev->dn->full_name, pe->addr);
+
+                return 0;
+        } else if (pe && (pe->type & EEH_PE_INVALID)) {
+                list_add_tail(&edev->list, &pe->edevs);
+                edev->pe = pe;
+                /*
+                 * We're running to here because of PCI hotplug caused by
+                 * EEH recovery. We need clear EEH_PE_INVALID until the top.
+                 */
+                parent = pe;
+                while (parent) {
+                        if (!(parent->type & EEH_PE_INVALID))
+                                break;
+                        parent->type &= ~EEH_PE_INVALID;
+                        parent = parent->parent;
+                }
+                eeh_unlock();
+                pr_debug("EEH: Add %s to Device PE#%x, Parent PE#%x\n",
+                        edev->dn->full_name, pe->addr, pe->parent->addr);
+
+                return 0;
+        }
+
+        /* Create a new EEH PE */
+        pe = eeh_pe_alloc(edev->phb, EEH_PE_DEVICE);
+        if (!pe) {
+                eeh_unlock();
+                pr_err("%s: out of memory!\n", __func__);
+                return -ENOMEM;
+        }
+        pe->addr        = edev->pe_config_addr;
+        pe->config_addr = edev->config_addr;
+
+        /*
+         * Put the new EEH PE into hierarchy tree. If the parent
+         * can't be found, the newly created PE will be attached
+         * to PHB directly. Otherwise, we have to associate the
+         * PE with its parent.
+         */
+        parent = eeh_pe_get_parent(edev);
+        if (!parent) {
+                parent = eeh_phb_pe_get(edev->phb);
+                if (!parent) {
+                        eeh_unlock();
+                        pr_err("%s: No PHB PE is found (PHB Domain=%d)\n",
+                                __func__, edev->phb->global_number);
+                        edev->pe = NULL;
+                        kfree(pe);
+                        return -EEXIST;
+                }
+        }
+        pe->parent = parent;
+
+        /*
+         * Put the newly created PE into the child list and
+         * link the EEH device accordingly.
+         */
+        list_add_tail(&pe->child, &parent->child_list);
+        list_add_tail(&edev->list, &pe->edevs);
+        edev->pe = pe;
+        eeh_unlock();
+        pr_debug("EEH: Add %s to Device PE#%x, Parent PE#%x\n",
+                edev->dn->full_name, pe->addr, pe->parent->addr);
+
+        return 0;
+}
+
+/**
+ * eeh_rmv_from_parent_pe - Remove one EEH device from the associated PE
+ * @edev: EEH device
+ * @purge_pe: remove PE or not
+ *
+ * The PE hierarchy tree might be changed when doing PCI hotplug.
+ * Also, the PCI devices or buses could be removed from the system
+ * during EEH recovery. So we have to call the function remove the
+ * corresponding PE accordingly if necessary.
+ */
+int eeh_rmv_from_parent_pe(struct eeh_dev *edev, int purge_pe)
+{
+        struct eeh_pe *pe, *parent, *child;
+        int cnt;
+
+        if (!edev->pe) {
+                pr_warning("%s: No PE found for EEH device %s\n",
+                        __func__, edev->dn->full_name);
+                return -EEXIST;
+        }
+
+        eeh_lock();
+
+        /* Remove the EEH device */
+        pe = edev->pe;
+        edev->pe = NULL;
+        list_del(&edev->list);
+
+        /*
+         * Check if the parent PE includes any EEH devices.
+         * If not, we should delete that. Also, we should
+         * delete the parent PE if it doesn't have associated
+         * child PEs and EEH devices.
+         */
+        while (1) {
+                parent = pe->parent;
+                if (pe->type & EEH_PE_PHB)
+                        break;
+
+                if (purge_pe) {
+                        if (list_empty(&pe->edevs) &&
+                            list_empty(&pe->child_list)) {
+                                list_del(&pe->child);
+                                kfree(pe);
+                        } else {
+                                break;
+                        }
+                } else {
+                        if (list_empty(&pe->edevs)) {
+                                cnt = 0;
+                                list_for_each_entry(child, &pe->child_list, child) {
+                                        if (!(pe->type & EEH_PE_INVALID)) {
+                                                cnt++;
+                                                break;
+                                        }
+                                }
+
+                                if (!cnt)
+                                        pe->type |= EEH_PE_INVALID;
+                                else
+                                        break;
+                        }
+                }
+
+                pe = parent;
+        }
+
+        eeh_unlock();
+
+        return 0;
+}
+
+/**
+ * __eeh_pe_state_mark - Mark the state for the PE
+ * @data: EEH PE
+ * @flag: state
+ *
+ * The function is used to mark the indicated state for the given
+ * PE. Also, the associated PCI devices will be put into IO frozen
+ * state as well.
+ */
+static void *__eeh_pe_state_mark(void *data, void *flag)
+{
+        struct eeh_pe *pe = (struct eeh_pe *)data;
+        int state = *((int *)flag);
+        struct eeh_dev *tmp;
+        struct pci_dev *pdev;
+
+        /*
+         * Mark the PE with the indicated state. Also,
+         * the associated PCI device will be put into
+         * I/O frozen state to avoid I/O accesses from
+         * the PCI device driver.
+         */
+        pe->state |= state;
+        eeh_pe_for_each_dev(pe, tmp) {
+                pdev = eeh_dev_to_pci_dev(tmp);
+                if (pdev)
+                        pdev->error_state = pci_channel_io_frozen;
+        }
+
+        return NULL;
+}
+
+/**
+ * eeh_pe_state_mark - Mark specified state for PE and its associated device
+ * @pe: EEH PE
+ *
+ * EEH error affects the current PE and its child PEs. The function
+ * is used to mark appropriate state for the affected PEs and the
+ * associated devices.
+ */
+void eeh_pe_state_mark(struct eeh_pe *pe, int state)
+{
+        eeh_lock();
+        eeh_pe_traverse(pe, __eeh_pe_state_mark, &state);
+        eeh_unlock();
+}
+
+/**
+ * __eeh_pe_state_clear - Clear state for the PE
+ * @data: EEH PE
+ * @flag: state
+ *
+ * The function is used to clear the indicated state from the
+ * given PE. Besides, we also clear the check count of the PE
+ * as well.
+ */
+static void *__eeh_pe_state_clear(void *data, void *flag)
+{
+        struct eeh_pe *pe = (struct eeh_pe *)data;
+        int state = *((int *)flag);
+
+        pe->state &= ~state;
+        pe->check_count = 0;
+
+        return NULL;
+}
+
+/**
+ * eeh_pe_state_clear - Clear state for the PE and its children
+ * @pe: PE
+ * @state: state to be cleared
+ *
+ * When the PE and its children has been recovered from error,
+ * we need clear the error state for that. The function is used
+ * for the purpose.
+ */
+void eeh_pe_state_clear(struct eeh_pe *pe, int state)
+{
+        eeh_lock();
+        eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
+        eeh_unlock();
+}
+
+/**
+ * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
+ * @data: EEH device
+ * @flag: Unused
+ *
+ * Loads the PCI configuration space base address registers,
+ * the expansion ROM base address, the latency timer, and etc.
+ * from the saved values in the device node.
+ */
+static void *eeh_restore_one_device_bars(void *data, void *flag)
+{
+        int i;
+        u32 cmd;
+        struct eeh_dev *edev = (struct eeh_dev *)data;
+        struct device_node *dn = eeh_dev_to_of_node(edev);
+
+        for (i = 4; i < 10; i++)
+                eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
+        /* 12 == Expansion ROM Address */
+        eeh_ops->write_config(dn, 12*4, 4, edev->config_space[12]);
+
+#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
+#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
+
+        eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
+                SAVED_BYTE(PCI_CACHE_LINE_SIZE));
+        eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
+                SAVED_BYTE(PCI_LATENCY_TIMER));
+
+        /* max latency, min grant, interrupt pin and line */
+        eeh_ops->write_config(dn, 15*4, 4, edev->config_space[15]);
+
+        /*
+         * Restore PERR & SERR bits, some devices require it,
+         * don't touch the other command bits
+         */
+        eeh_ops->read_config(dn, PCI_COMMAND, 4, &cmd);
+        if (edev->config_space[1] & PCI_COMMAND_PARITY)
+                cmd |= PCI_COMMAND_PARITY;
+        else
+                cmd &= ~PCI_COMMAND_PARITY;
+        if (edev->config_space[1] & PCI_COMMAND_SERR)
+                cmd |= PCI_COMMAND_SERR;
+        else
+                cmd &= ~PCI_COMMAND_SERR;
+        eeh_ops->write_config(dn, PCI_COMMAND, 4, cmd);
+
+        return NULL;
+}
+
+/**
+ * eeh_pe_restore_bars - Restore the PCI config space info
+ * @pe: EEH PE
+ *
+ * This routine performs a recursive walk to the children
+ * of this device as well.
+ */
+void eeh_pe_restore_bars(struct eeh_pe *pe)
+{
+        /*
+         * We needn't take the EEH lock since eeh_pe_dev_traverse()
+         * will take that.
+         */
+        eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL);
+}
+
+/**
+ * eeh_pe_bus_get - Retrieve PCI bus according to the given PE
+ * @pe: EEH PE
+ *
+ * Retrieve the PCI bus according to the given PE. Basically,
+ * there're 3 types of PEs: PHB/Bus/Device. For PHB PE, the
+ * primary PCI bus will be retrieved. The parent bus will be
+ * returned for BUS PE. However, we don't have associated PCI
+ * bus for DEVICE PE.
+ */
+struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe)
+{
+        struct pci_bus *bus = NULL;
+        struct eeh_dev *edev;
+        struct pci_dev *pdev;
+
+        eeh_lock();
+
+        if (pe->type & EEH_PE_PHB) {
+                bus = pe->phb->bus;
+        } else if (pe->type & EEH_PE_BUS) {
+                edev = list_first_entry(&pe->edevs, struct eeh_dev, list);
+                pdev = eeh_dev_to_pci_dev(edev);
+                if (pdev)
+                        bus = pdev->bus;
+        }
+
+        eeh_unlock();
+
+        return bus;
+}
diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c
index c33360ec4f4f..19506f935737 100644
--- a/arch/powerpc/platforms/pseries/eeh_pseries.c
+++ b/arch/powerpc/platforms/pseries/eeh_pseries.c
@@ -129,27 +129,117 @@ static int pseries_eeh_init(void)
                 eeh_error_buf_size = RTAS_ERROR_LOG_MAX;
         }
 
+        /* Set EEH probe mode */
+        eeh_probe_mode_set(EEH_PROBE_MODE_DEVTREE);
+
         return 0;
 }
 
 /**
+ * pseries_eeh_of_probe - EEH probe on the given device
+ * @dn: OF node
+ * @flag: Unused
+ *
+ * When EEH module is installed during system boot, all PCI devices
+ * are checked one by one to see if it supports EEH. The function
+ * is introduced for the purpose.
+ */
+static void *pseries_eeh_of_probe(struct device_node *dn, void *flag)
+{
+        struct eeh_dev *edev;
+        struct eeh_pe pe;
+        const u32 *class_code, *vendor_id, *device_id;
+        const u32 *regs;
+        int enable = 0;
+        int ret;
+
+        /* Retrieve OF node and eeh device */
+        edev = of_node_to_eeh_dev(dn);
+        if (!of_device_is_available(dn))
+                return NULL;
+
+        /* Retrieve class/vendor/device IDs */
+        class_code = of_get_property(dn, "class-code", NULL);
+        vendor_id  = of_get_property(dn, "vendor-id", NULL);
+        device_id  = of_get_property(dn, "device-id", NULL);
+
+        /* Skip for bad OF node or PCI-ISA bridge */
+        if (!class_code || !vendor_id || !device_id)
+                return NULL;
+        if (dn->type && !strcmp(dn->type, "isa"))
+                return NULL;
+
+        /* Update class code and mode of eeh device */
+        edev->class_code = *class_code;
+        edev->mode = 0;
+
+        /* Retrieve the device address */
+        regs = of_get_property(dn, "reg", NULL);
+        if (!regs) {
+                pr_warning("%s: OF node property %s::reg not found\n",
+                        __func__, dn->full_name);
+                return NULL;
+        }
+
+        /* Initialize the fake PE */
+        memset(&pe, 0, sizeof(struct eeh_pe));
+        pe.phb = edev->phb;
+        pe.config_addr = regs[0];
+
+        /* Enable EEH on the device */
+        ret = eeh_ops->set_option(&pe, EEH_OPT_ENABLE);
+        if (!ret) {
+                edev->config_addr = regs[0];
+                /* Retrieve PE address */
+                edev->pe_config_addr = eeh_ops->get_pe_addr(&pe);
+                pe.addr = edev->pe_config_addr;
+
+                /* Some older systems (Power4) allow the ibm,set-eeh-option
+                 * call to succeed even on nodes where EEH is not supported.
+                 * Verify support explicitly.
+                 */
+                ret = eeh_ops->get_state(&pe, NULL);
+                if (ret > 0 && ret != EEH_STATE_NOT_SUPPORT)
+                        enable = 1;
+
+                if (enable) {
+                        eeh_subsystem_enabled = 1;
+                        eeh_add_to_parent_pe(edev);
+
+                        pr_debug("%s: EEH enabled on %s PHB#%d-PE#%x, config addr#%x\n",
+                                __func__, dn->full_name, pe.phb->global_number,
+                                pe.addr, pe.config_addr);
+                } else if (dn->parent && of_node_to_eeh_dev(dn->parent) &&
+                           (of_node_to_eeh_dev(dn->parent))->pe) {
+                        /* This device doesn't support EEH, but it may have an
+                         * EEH parent, in which case we mark it as supported.
+                         */
+                        edev->config_addr = of_node_to_eeh_dev(dn->parent)->config_addr;
+                        edev->pe_config_addr = of_node_to_eeh_dev(dn->parent)->pe_config_addr;
+                        eeh_add_to_parent_pe(edev);
+                }
+        }
+
+        /* Save memory bars */
+        eeh_save_bars(edev);
+
+        return NULL;
+}
+
+/**
  * pseries_eeh_set_option - Initialize EEH or MMIO/DMA reenable
- * @dn: device node
+ * @pe: EEH PE
  * @option: operation to be issued
  *
  * The function is used to control the EEH functionality globally.
  * Currently, following options are support according to PAPR:
  * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
  */
-static int pseries_eeh_set_option(struct device_node *dn, int option)
+static int pseries_eeh_set_option(struct eeh_pe *pe, int option)
 {
         int ret = 0;
-        struct eeh_dev *edev;
-        const u32 *reg;
         int config_addr;
 
-        edev = of_node_to_eeh_dev(dn);
-
         /*
          * When we're enabling or disabling EEH functioality on
          * the particular PE, the PE config address is possibly
@@ -159,15 +249,11 @@ static int pseries_eeh_set_option(struct device_node *dn, int option)
         switch (option) {
         case EEH_OPT_DISABLE:
         case EEH_OPT_ENABLE:
-                reg = of_get_property(dn, "reg", NULL);
-                config_addr = reg[0];
-                break;
-
         case EEH_OPT_THAW_MMIO:
         case EEH_OPT_THAW_DMA:
-                config_addr = edev->config_addr;
-                if (edev->pe_config_addr)
-                        config_addr = edev->pe_config_addr;
+                config_addr = pe->config_addr;
+                if (pe->addr)
+                        config_addr = pe->addr;
                 break;
 
         default:
@@ -177,15 +263,15 @@ static int pseries_eeh_set_option(struct device_node *dn, int option)
         }
 
         ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
-                        config_addr, BUID_HI(edev->phb->buid),
-                        BUID_LO(edev->phb->buid), option);
+                        config_addr, BUID_HI(pe->phb->buid),
+                        BUID_LO(pe->phb->buid), option);
 
         return ret;
 }
 
 /**
  * pseries_eeh_get_pe_addr - Retrieve PE address
- * @dn: device node
+ * @pe: EEH PE
  *
  * Retrieve the assocated PE address. Actually, there're 2 RTAS
  * function calls dedicated for the purpose. We need implement
@@ -196,14 +282,11 @@ static int pseries_eeh_set_option(struct device_node *dn, int option)
  * It's notable that zero'ed return value means invalid PE config
  * address.
  */
-static int pseries_eeh_get_pe_addr(struct device_node *dn)
+static int pseries_eeh_get_pe_addr(struct eeh_pe *pe)
 {
-        struct eeh_dev *edev;
         int ret = 0;
         int rets[3];
 
-        edev = of_node_to_eeh_dev(dn);
-
         if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) {
                 /*
                  * First of all, we need to make sure there has one PE
@@ -211,18 +294,18 @@ static int pseries_eeh_get_pe_addr(struct device_node *dn)
                  * meaningless.
                  */
                 ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
-                                edev->config_addr, BUID_HI(edev->phb->buid),
-                                BUID_LO(edev->phb->buid), 1);
+                                pe->config_addr, BUID_HI(pe->phb->buid),
+                                BUID_LO(pe->phb->buid), 1);
                 if (ret || (rets[0] == 0))
                         return 0;
 
                 /* Retrieve the associated PE config address */
                 ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
-                                edev->config_addr, BUID_HI(edev->phb->buid),
-                                BUID_LO(edev->phb->buid), 0);
+                                pe->config_addr, BUID_HI(pe->phb->buid),
+                                BUID_LO(pe->phb->buid), 0);
                 if (ret) {
-                        pr_warning("%s: Failed to get PE address for %s\n",
-                                __func__, dn->full_name);
+                        pr_warning("%s: Failed to get address for PHB#%d-PE#%x\n",
+                                __func__, pe->phb->global_number, pe->config_addr);
                         return 0;
                 }
 
@@ -231,11 +314,11 @@ static int pseries_eeh_get_pe_addr(struct device_node *dn)
 
         if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
                 ret = rtas_call(ibm_get_config_addr_info, 4, 2, rets,
-                                edev->config_addr, BUID_HI(edev->phb->buid),
-                                BUID_LO(edev->phb->buid), 0);
+                                pe->config_addr, BUID_HI(pe->phb->buid),
+                                BUID_LO(pe->phb->buid), 0);
                 if (ret) {
-                        pr_warning("%s: Failed to get PE address for %s\n",
-                                __func__, dn->full_name);
+                        pr_warning("%s: Failed to get address for PHB#%d-PE#%x\n",
+                                __func__, pe->phb->global_number, pe->config_addr);
                         return 0;
                 }
 
@@ -247,7 +330,7 @@ static int pseries_eeh_get_pe_addr(struct device_node *dn)
 
 /**
  * pseries_eeh_get_state - Retrieve PE state
- * @dn: PE associated device node
+ * @pe: EEH PE
  * @state: return value
  *
  * Retrieve the state of the specified PE. On RTAS compliant
@@ -258,30 +341,28 @@ static int pseries_eeh_get_pe_addr(struct device_node *dn)
  * RTAS calls for the purpose, we need to try the new one and back
  * to the old one if the new one couldn't work properly.
  */
-static int pseries_eeh_get_state(struct device_node *dn, int *state)
+static int pseries_eeh_get_state(struct eeh_pe *pe, int *state)
 {
-        struct eeh_dev *edev;
         int config_addr;
         int ret;
         int rets[4];
         int result;
 
         /* Figure out PE config address if possible */
-        edev = of_node_to_eeh_dev(dn);
-        config_addr = edev->config_addr;
-        if (edev->pe_config_addr)
-                config_addr = edev->pe_config_addr;
+        config_addr = pe->config_addr;
+        if (pe->addr)
+                config_addr = pe->addr;
 
         if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) {
                 ret = rtas_call(ibm_read_slot_reset_state2, 3, 4, rets,
-                                config_addr, BUID_HI(edev->phb->buid),
-                                BUID_LO(edev->phb->buid));
+                                config_addr, BUID_HI(pe->phb->buid),
+                                BUID_LO(pe->phb->buid));
         } else if (ibm_read_slot_reset_state != RTAS_UNKNOWN_SERVICE) {
                 /* Fake PE unavailable info */
                 rets[2] = 0;
                 ret = rtas_call(ibm_read_slot_reset_state, 3, 3, rets,
-                                config_addr, BUID_HI(edev->phb->buid),
-                                BUID_LO(edev->phb->buid));
+                                config_addr, BUID_HI(pe->phb->buid),
+                                BUID_LO(pe->phb->buid));
         } else {
                 return EEH_STATE_NOT_SUPPORT;
         }
@@ -333,34 +414,32 @@ static int pseries_eeh_get_state(struct device_node *dn, int *state)
 
 /**
  * pseries_eeh_reset - Reset the specified PE
- * @dn: PE associated device node
+ * @pe: EEH PE
  * @option: reset option
  *
  * Reset the specified PE
  */
-static int pseries_eeh_reset(struct device_node *dn, int option)
+static int pseries_eeh_reset(struct eeh_pe *pe, int option)
 {
-        struct eeh_dev *edev;
         int config_addr;
         int ret;
 
         /* Figure out PE address */
-        edev = of_node_to_eeh_dev(dn);
-        config_addr = edev->config_addr;
-        if (edev->pe_config_addr)
-                config_addr = edev->pe_config_addr;
+        config_addr = pe->config_addr;
+        if (pe->addr)
+                config_addr = pe->addr;
 
         /* Reset PE through RTAS call */
         ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
-                        config_addr, BUID_HI(edev->phb->buid),
-                        BUID_LO(edev->phb->buid), option);
+                        config_addr, BUID_HI(pe->phb->buid),
+                        BUID_LO(pe->phb->buid), option);
 
         /* If fundamental-reset not supported, try hot-reset */
         if (option == EEH_RESET_FUNDAMENTAL &&
             ret == -8) {
                 ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
-                                config_addr, BUID_HI(edev->phb->buid),
-                                BUID_LO(edev->phb->buid), EEH_RESET_HOT);
+                                config_addr, BUID_HI(pe->phb->buid),
+                                BUID_LO(pe->phb->buid), EEH_RESET_HOT);
         }
 
         return ret;
@@ -368,13 +447,13 @@ static int pseries_eeh_reset(struct device_node *dn, int option)
 
 /**
  * pseries_eeh_wait_state - Wait for PE state
- * @dn: PE associated device node
+ * @pe: EEH PE
  * @max_wait: maximal period in microsecond
  *
  * Wait for the state of associated PE. It might take some time
  * to retrieve the PE's state.
  */
-static int pseries_eeh_wait_state(struct device_node *dn, int max_wait)
+static int pseries_eeh_wait_state(struct eeh_pe *pe, int max_wait)
 {
         int ret;
         int mwait;
@@ -391,7 +470,7 @@ static int pseries_eeh_wait_state(struct device_node *dn, int max_wait)
 #define EEH_STATE_MAX_WAIT_TIME (300 * 1000)
 
         while (1) {
-                ret = pseries_eeh_get_state(dn, &mwait);
+                ret = pseries_eeh_get_state(pe, &mwait);
 
                 /*
                  * If the PE's state is temporarily unavailable,
@@ -426,7 +505,7 @@ static int pseries_eeh_wait_state(struct device_node *dn, int max_wait)
 
 /**
  * pseries_eeh_get_log - Retrieve error log
- * @dn: device node
+ * @pe: EEH PE
  * @severity: temporary or permanent error log
  * @drv_log: driver log to be combined with retrieved error log
  * @len: length of driver log
@@ -435,24 +514,22 @@ static int pseries_eeh_wait_state(struct device_node *dn, int max_wait)
  * Actually, the error will be retrieved through the dedicated
  * RTAS call.
  */
-static int pseries_eeh_get_log(struct device_node *dn, int severity, char *drv_log, unsigned long len)
+static int pseries_eeh_get_log(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len)
 {
-        struct eeh_dev *edev;
         int config_addr;
         unsigned long flags;
         int ret;
 
-        edev = of_node_to_eeh_dev(dn);
         spin_lock_irqsave(&slot_errbuf_lock, flags);
         memset(slot_errbuf, 0, eeh_error_buf_size);
 
         /* Figure out the PE address */
-        config_addr = edev->config_addr;
-        if (edev->pe_config_addr)
-                config_addr = edev->pe_config_addr;
+        config_addr = pe->config_addr;
+        if (pe->addr)
+                config_addr = pe->addr;
 
         ret = rtas_call(ibm_slot_error_detail, 8, 1, NULL, config_addr,
-                        BUID_HI(edev->phb->buid), BUID_LO(edev->phb->buid),
+                        BUID_HI(pe->phb->buid), BUID_LO(pe->phb->buid),
                         virt_to_phys(drv_log), len,
                         virt_to_phys(slot_errbuf), eeh_error_buf_size,
                         severity);
@@ -465,40 +542,38 @@ static int pseries_eeh_get_log(struct device_node *dn, int severity, char *drv_l
 
 /**
  * pseries_eeh_configure_bridge - Configure PCI bridges in the indicated PE
- * @dn: PE associated device node
+ * @pe: EEH PE
  *
  * The function will be called to reconfigure the bridges included
  * in the specified PE so that the mulfunctional PE would be recovered
  * again.
  */
-static int pseries_eeh_configure_bridge(struct device_node *dn)
+static int pseries_eeh_configure_bridge(struct eeh_pe *pe)
 {
-        struct eeh_dev *edev;
         int config_addr;
         int ret;
 
         /* Figure out the PE address */
-        edev = of_node_to_eeh_dev(dn);
-        config_addr = edev->config_addr;
-        if (edev->pe_config_addr)
-                config_addr = edev->pe_config_addr;
+        config_addr = pe->config_addr;
+        if (pe->addr)
+                config_addr = pe->addr;
 
         /* Use new configure-pe function, if supported */
         if (ibm_configure_pe != RTAS_UNKNOWN_SERVICE) {
                 ret = rtas_call(ibm_configure_pe, 3, 1, NULL,
-                                config_addr, BUID_HI(edev->phb->buid),
-                                BUID_LO(edev->phb->buid));
+                                config_addr, BUID_HI(pe->phb->buid),
+                                BUID_LO(pe->phb->buid));
         } else if (ibm_configure_bridge != RTAS_UNKNOWN_SERVICE) {
                 ret = rtas_call(ibm_configure_bridge, 3, 1, NULL,
-                                config_addr, BUID_HI(edev->phb->buid),
-                                BUID_LO(edev->phb->buid));
+                                config_addr, BUID_HI(pe->phb->buid),
+                                BUID_LO(pe->phb->buid));
         } else {
                 return -EFAULT;
         }
 
         if (ret)
-                pr_warning("%s: Unable to configure bridge %d for %s\n",
-                        __func__, ret, dn->full_name);
+                pr_warning("%s: Unable to configure bridge PHB#%d-PE#%x (%d)\n",
+                        __func__, pe->phb->global_number, pe->addr, ret);
 
         return ret;
 }
@@ -542,6 +617,8 @@ static int pseries_eeh_write_config(struct device_node *dn, int where, int size,
 static struct eeh_ops pseries_eeh_ops = {
         .name                   = "pseries",
         .init                   = pseries_eeh_init,
+        .of_probe               = pseries_eeh_of_probe,
+        .dev_probe              = NULL,
         .set_option             = pseries_eeh_set_option,
         .get_pe_addr            = pseries_eeh_get_pe_addr,
         .get_state              = pseries_eeh_get_state,
@@ -559,7 +636,21 @@ static struct eeh_ops pseries_eeh_ops = {
  * EEH initialization on pseries platform. This function should be
  * called before any EEH related functions.
  */
-int __init eeh_pseries_init(void)
+static int __init eeh_pseries_init(void)
 {
-        return eeh_ops_register(&pseries_eeh_ops);
+        int ret = -EINVAL;
+
+        if (!machine_is(pseries))
+                return ret;
+
+        ret = eeh_ops_register(&pseries_eeh_ops);
+        if (!ret)
+                pr_info("EEH: pSeries platform initialized\n");
+        else
+                pr_info("EEH: pSeries platform initialization failure (%d)\n",
+                        ret);
+
+        return ret;
 }
+
+early_initcall(eeh_pseries_init);
diff --git a/arch/powerpc/platforms/pseries/eeh_sysfs.c b/arch/powerpc/platforms/pseries/eeh_sysfs.c
index 243b3510d70f..d37708360f2e 100644
--- a/arch/powerpc/platforms/pseries/eeh_sysfs.c
+++ b/arch/powerpc/platforms/pseries/eeh_sysfs.c
@@ -53,9 +53,6 @@ static DEVICE_ATTR(_name, S_IRUGO, eeh_show_##_name, NULL);
 EEH_SHOW_ATTR(eeh_mode,            mode,            "0x%x");
 EEH_SHOW_ATTR(eeh_config_addr,     config_addr,     "0x%x");
 EEH_SHOW_ATTR(eeh_pe_config_addr,  pe_config_addr,  "0x%x");
-EEH_SHOW_ATTR(eeh_check_count,     check_count,     "%d"  );
-EEH_SHOW_ATTR(eeh_freeze_count,    freeze_count,    "%d"  );
-EEH_SHOW_ATTR(eeh_false_positives, false_positives, "%d"  );
 
 void eeh_sysfs_add_device(struct pci_dev *pdev)
 {
@@ -64,9 +61,6 @@ void eeh_sysfs_add_device(struct pci_dev *pdev)
         rc += device_create_file(&pdev->dev, &dev_attr_eeh_mode);
         rc += device_create_file(&pdev->dev, &dev_attr_eeh_config_addr);
         rc += device_create_file(&pdev->dev, &dev_attr_eeh_pe_config_addr);
-        rc += device_create_file(&pdev->dev, &dev_attr_eeh_check_count);
-        rc += device_create_file(&pdev->dev, &dev_attr_eeh_false_positives);
-        rc += device_create_file(&pdev->dev, &dev_attr_eeh_freeze_count);
 
         if (rc)
                 printk(KERN_WARNING "EEH: Unable to create sysfs entries\n");
@@ -77,8 +71,5 @@ void eeh_sysfs_remove_device(struct pci_dev *pdev)
         device_remove_file(&pdev->dev, &dev_attr_eeh_mode);
         device_remove_file(&pdev->dev, &dev_attr_eeh_config_addr);
         device_remove_file(&pdev->dev, &dev_attr_eeh_pe_config_addr);
-        device_remove_file(&pdev->dev, &dev_attr_eeh_check_count);
-        device_remove_file(&pdev->dev, &dev_attr_eeh_false_positives);
-        device_remove_file(&pdev->dev, &dev_attr_eeh_freeze_count);
 }
 
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index bca220f2873c..6153eea27ce7 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -28,6 +28,7 @@
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <linux/mm.h>
+#include <linux/memblock.h>
 #include <linux/spinlock.h>
 #include <linux/sched.h>        /* for show_stack */
 #include <linux/string.h>
@@ -41,7 +42,6 @@
 #include <asm/iommu.h>
 #include <asm/pci-bridge.h>
 #include <asm/machdep.h>
-#include <asm/abs_addr.h>
 #include <asm/pSeries_reconfig.h>
 #include <asm/firmware.h>
 #include <asm/tce.h>
@@ -99,7 +99,7 @@ static int tce_build_pSeries(struct iommu_table *tbl, long index,
 
         while (npages--) {
                 /* can't move this out since we might cross MEMBLOCK boundary */
-                rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
+                rpn = __pa(uaddr) >> TCE_SHIFT;
                 *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
 
                 uaddr += TCE_PAGE_SIZE;
@@ -148,7 +148,7 @@ static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
         int ret = 0;
         long tcenum_start = tcenum, npages_start = npages;
 
-        rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
+        rpn = __pa(uaddr) >> TCE_SHIFT;
         proto_tce = TCE_PCI_READ;
         if (direction != DMA_TO_DEVICE)
                 proto_tce |= TCE_PCI_WRITE;
@@ -217,7 +217,7 @@ static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
                 __get_cpu_var(tce_page) = tcep;
         }
 
-        rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
+        rpn = __pa(uaddr) >> TCE_SHIFT;
         proto_tce = TCE_PCI_READ;
         if (direction != DMA_TO_DEVICE)
                 proto_tce |= TCE_PCI_WRITE;
@@ -237,7 +237,7 @@ static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
 
                 rc = plpar_tce_put_indirect((u64)tbl->it_index,
                                             (u64)tcenum << 12,
-                                            (u64)virt_to_abs(tcep),
+                                            (u64)__pa(tcep),
                                             limit);
 
                 npages -= limit;
@@ -441,7 +441,7 @@ static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
 
                 rc = plpar_tce_put_indirect(liobn,
                                             dma_offset,
-                                            (u64)virt_to_abs(tcep),
+                                            (u64)__pa(tcep),
                                             limit);
 
                 num_tce -= limit;
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index 5f3ef876ded2..0da39fed355a 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -31,7 +31,6 @@
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/machdep.h>
-#include <asm/abs_addr.h>
 #include <asm/mmu_context.h>
 #include <asm/iommu.h>
 #include <asm/tlbflush.h>
@@ -108,9 +107,9 @@ void vpa_init(int cpu)
 }
 
 static long pSeries_lpar_hpte_insert(unsigned long hpte_group,
-                              unsigned long va, unsigned long pa,
-                              unsigned long rflags, unsigned long vflags,
-                              int psize, int ssize)
+                                     unsigned long vpn, unsigned long pa,
+                                     unsigned long rflags, unsigned long vflags,
+                                     int psize, int ssize)
 {
         unsigned long lpar_rc;
         unsigned long flags;
@@ -118,11 +117,11 @@ static long pSeries_lpar_hpte_insert(unsigned long hpte_group,
         unsigned long hpte_v, hpte_r;
 
         if (!(vflags & HPTE_V_BOLTED))
-                pr_devel("hpte_insert(group=%lx, va=%016lx, pa=%016lx, "
-                         "rflags=%lx, vflags=%lx, psize=%d)\n",
-                         hpte_group, va, pa, rflags, vflags, psize);
+                pr_devel("hpte_insert(group=%lx, vpn=%016lx, "
+                         "pa=%016lx, rflags=%lx, vflags=%lx, psize=%d)\n",
+                         hpte_group, vpn,  pa, rflags, vflags, psize);
 
-        hpte_v = hpte_encode_v(va, psize, ssize) | vflags | HPTE_V_VALID;
+        hpte_v = hpte_encode_v(vpn, psize, ssize) | vflags | HPTE_V_VALID;
         hpte_r = hpte_encode_r(pa, psize) | rflags;
 
         if (!(vflags & HPTE_V_BOLTED))
@@ -227,22 +226,6 @@ static void pSeries_lpar_hptab_clear(void)
 }
 
 /*
- * This computes the AVPN and B fields of the first dword of a HPTE,
- * for use when we want to match an existing PTE.  The bottom 7 bits
- * of the returned value are zero.
- */
-static inline unsigned long hpte_encode_avpn(unsigned long va, int psize,
-                                             int ssize)
-{
-        unsigned long v;
-
-        v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
-        v <<= HPTE_V_AVPN_SHIFT;
-        v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
-        return v;
-}
-
-/*
  * NOTE: for updatepp ops we are fortunate that the linux "newpp" bits and
  * the low 3 bits of flags happen to line up.  So no transform is needed.
  * We can probably optimize here and assume the high bits of newpp are
@@ -250,14 +233,14 @@ static inline unsigned long hpte_encode_avpn(unsigned long va, int psize,
  */
 static long pSeries_lpar_hpte_updatepp(unsigned long slot,
                                        unsigned long newpp,
-                                       unsigned long va,
+                                       unsigned long vpn,
                                        int psize, int ssize, int local)
 {
         unsigned long lpar_rc;
         unsigned long flags = (newpp & 7) | H_AVPN;
         unsigned long want_v;
 
-        want_v = hpte_encode_avpn(va, psize, ssize);
+        want_v = hpte_encode_avpn(vpn, psize, ssize);
 
         pr_devel("    update: avpnv=%016lx, hash=%016lx, f=%lx, psize: %d ...",
                  want_v, slot, flags, psize);
@@ -295,15 +278,15 @@ static unsigned long pSeries_lpar_hpte_getword0(unsigned long slot)
         return dword0;
 }
 
-static long pSeries_lpar_hpte_find(unsigned long va, int psize, int ssize)
+static long pSeries_lpar_hpte_find(unsigned long vpn, int psize, int ssize)
 {
         unsigned long hash;
         unsigned long i;
         long slot;
         unsigned long want_v, hpte_v;
 
-        hash = hpt_hash(va, mmu_psize_defs[psize].shift, ssize);
-        want_v = hpte_encode_avpn(va, psize, ssize);
+        hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize);
+        want_v = hpte_encode_avpn(vpn, psize, ssize);
 
         /* Bolted entries are always in the primary group */
         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
@@ -323,12 +306,13 @@ static void pSeries_lpar_hpte_updateboltedpp(unsigned long newpp,
                                              unsigned long ea,
                                              int psize, int ssize)
 {
-        unsigned long lpar_rc, slot, vsid, va, flags;
+        unsigned long vpn;
+        unsigned long lpar_rc, slot, vsid, flags;
 
         vsid = get_kernel_vsid(ea, ssize);
-        va = hpt_va(ea, vsid, ssize);
+        vpn = hpt_vpn(ea, vsid, ssize);
 
-        slot = pSeries_lpar_hpte_find(va, psize, ssize);
+        slot = pSeries_lpar_hpte_find(vpn, psize, ssize);
         BUG_ON(slot == -1);
 
         flags = newpp & 7;
@@ -337,17 +321,17 @@ static void pSeries_lpar_hpte_updateboltedpp(unsigned long newpp,
         BUG_ON(lpar_rc != H_SUCCESS);
 }
 
-static void pSeries_lpar_hpte_invalidate(unsigned long slot, unsigned long va,
+static void pSeries_lpar_hpte_invalidate(unsigned long slot, unsigned long vpn,
                                          int psize, int ssize, int local)
 {
         unsigned long want_v;
         unsigned long lpar_rc;
         unsigned long dummy1, dummy2;
 
-        pr_devel("    inval : slot=%lx, va=%016lx, psize: %d, local: %d\n",
-                 slot, va, psize, local);
+        pr_devel("    inval : slot=%lx, vpn=%016lx, psize: %d, local: %d\n",
+                 slot, vpn, psize, local);
 
-        want_v = hpte_encode_avpn(va, psize, ssize);
+        want_v = hpte_encode_avpn(vpn, psize, ssize);
         lpar_rc = plpar_pte_remove(H_AVPN, slot, want_v, &dummy1, &dummy2);
         if (lpar_rc == H_NOT_FOUND)
                 return;
@@ -358,15 +342,16 @@ static void pSeries_lpar_hpte_invalidate(unsigned long slot, unsigned long va,
 static void pSeries_lpar_hpte_removebolted(unsigned long ea,
                                            int psize, int ssize)
 {
-        unsigned long slot, vsid, va;
+        unsigned long vpn;
+        unsigned long slot, vsid;
 
         vsid = get_kernel_vsid(ea, ssize);
-        va = hpt_va(ea, vsid, ssize);
+        vpn = hpt_vpn(ea, vsid, ssize);
 
-        slot = pSeries_lpar_hpte_find(va, psize, ssize);
+        slot = pSeries_lpar_hpte_find(vpn, psize, ssize);
         BUG_ON(slot == -1);
 
-        pSeries_lpar_hpte_invalidate(slot, va, psize, ssize, 0);
+        pSeries_lpar_hpte_invalidate(slot, vpn, psize, ssize, 0);
 }
 
 /* Flag bits for H_BULK_REMOVE */
@@ -382,12 +367,12 @@ static void pSeries_lpar_hpte_removebolted(unsigned long ea,
  */
 static void pSeries_lpar_flush_hash_range(unsigned long number, int local)
 {
+        unsigned long vpn;
         unsigned long i, pix, rc;
         unsigned long flags = 0;
         struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
         int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
         unsigned long param[9];
-        unsigned long va;
         unsigned long hash, index, shift, hidx, slot;
         real_pte_t pte;
         int psize, ssize;
@@ -399,21 +384,21 @@ static void pSeries_lpar_flush_hash_range(unsigned long number, int local)
         ssize = batch->ssize;
         pix = 0;
         for (i = 0; i < number; i++) {
-                va = batch->vaddr[i];
+                vpn = batch->vpn[i];
                 pte = batch->pte[i];
-                pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
-                        hash = hpt_hash(va, shift, ssize);
+                pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
+                        hash = hpt_hash(vpn, shift, ssize);
                         hidx = __rpte_to_hidx(pte, index);
                         if (hidx & _PTEIDX_SECONDARY)
                                 hash = ~hash;
                         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
                         slot += hidx & _PTEIDX_GROUP_IX;
                         if (!firmware_has_feature(FW_FEATURE_BULK_REMOVE)) {
-                                pSeries_lpar_hpte_invalidate(slot, va, psize,
+                                pSeries_lpar_hpte_invalidate(slot, vpn, psize,
                                                              ssize, local);
                         } else {
                                 param[pix] = HBR_REQUEST | HBR_AVPN | slot;
-                                param[pix+1] = hpte_encode_avpn(va, psize,
+                                param[pix+1] = hpte_encode_avpn(vpn, psize,
                                                                 ssize);
                                 pix += 2;
                                 if (pix == 8) {
diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c
index 109fdb75578d..d19f4977c834 100644
--- a/arch/powerpc/platforms/pseries/msi.c
+++ b/arch/powerpc/platforms/pseries/msi.c
@@ -210,6 +210,7 @@ static struct device_node *find_pe_total_msi(struct pci_dev *dev, int *total)
 static struct device_node *find_pe_dn(struct pci_dev *dev, int *total)
 {
         struct device_node *dn;
+        struct eeh_dev *edev;
 
         /* Found our PE and assume 8 at that point. */
 
@@ -217,7 +218,10 @@ static struct device_node *find_pe_dn(struct pci_dev *dev, int *total)
         if (!dn)
                 return NULL;
 
-        dn = eeh_find_device_pe(dn);
+        /* Get the top level device in the PE */
+        edev = of_node_to_eeh_dev(dn);
+        edev = list_first_entry(&edev->pe->edevs, struct eeh_dev, list);
+        dn = eeh_dev_to_of_node(edev);
         if (!dn)
                 return NULL;
 
@@ -387,12 +391,13 @@ static int check_msix_entries(struct pci_dev *pdev)
         return 0;
 }
 
-static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
+static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec_in, int type)
 {
         struct pci_dn *pdn;
         int hwirq, virq, i, rc;
         struct msi_desc *entry;
         struct msi_msg msg;
+        int nvec = nvec_in;
 
         pdn = get_pdn(pdev);
         if (!pdn)
@@ -402,10 +407,23 @@ static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
                 return -EINVAL;
 
         /*
+         * Firmware currently refuse any non power of two allocation
+         * so we round up if the quota will allow it.
+         */
+        if (type == PCI_CAP_ID_MSIX) {
+                int m = roundup_pow_of_two(nvec);
+                int quota = msi_quota_for_device(pdev, m);
+
+                if (quota >= m)
+                        nvec = m;
+        }
+
+        /*
          * Try the new more explicit firmware interface, if that fails fall
          * back to the old interface. The old interface is known to never
          * return MSI-Xs.
          */
+again:
         if (type == PCI_CAP_ID_MSI) {
                 rc = rtas_change_msi(pdn, RTAS_CHANGE_MSI_FN, nvec);
 
@@ -417,6 +435,10 @@ static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
                 rc = rtas_change_msi(pdn, RTAS_CHANGE_MSIX_FN, nvec);
 
         if (rc != nvec) {
+                if (nvec != nvec_in) {
+                        nvec = nvec_in;
+                        goto again;
+                }
                 pr_debug("rtas_msi: rtas_change_msi() failed\n");
                 return rc;
         }
diff --git a/arch/powerpc/platforms/pseries/pci.c b/arch/powerpc/platforms/pseries/pci.c
index 2c6ded29f73d..56b864d777ee 100644
--- a/arch/powerpc/platforms/pseries/pci.c
+++ b/arch/powerpc/platforms/pseries/pci.c
@@ -73,7 +73,7 @@ void __init pSeries_final_fixup(void)
 {
         pSeries_request_regions();
 
-        pci_addr_cache_build();
+        eeh_addr_cache_build();
 }
 
 /*
diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c b/arch/powerpc/platforms/pseries/pci_dlpar.c
index 3ccebc83dc02..261a577a3dd2 100644
--- a/arch/powerpc/platforms/pseries/pci_dlpar.c
+++ b/arch/powerpc/platforms/pseries/pci_dlpar.c
@@ -65,27 +65,43 @@ pcibios_find_pci_bus(struct device_node *dn)
 EXPORT_SYMBOL_GPL(pcibios_find_pci_bus);
 
 /**
- * pcibios_remove_pci_devices - remove all devices under this bus
+ * __pcibios_remove_pci_devices - remove all devices under this bus
+ * @bus: the indicated PCI bus
+ * @purge_pe: destroy the PE on removal of PCI devices
  *
  * Remove all of the PCI devices under this bus both from the
  * linux pci device tree, and from the powerpc EEH address cache.
+ * By default, the corresponding PE will be destroied during the
+ * normal PCI hotplug path. For PCI hotplug during EEH recovery,
+ * the corresponding PE won't be destroied and deallocated.
  */
-void pcibios_remove_pci_devices(struct pci_bus *bus)
+void __pcibios_remove_pci_devices(struct pci_bus *bus, int purge_pe)
 {
-        struct pci_dev *dev, *tmp;
+        struct pci_dev *dev, *tmp;
         struct pci_bus *child_bus;
 
         /* First go down child busses */
         list_for_each_entry(child_bus, &bus->children, node)
-                pcibios_remove_pci_devices(child_bus);
+                __pcibios_remove_pci_devices(child_bus, purge_pe);
 
         pr_debug("PCI: Removing devices on bus %04x:%02x\n",
-                 pci_domain_nr(bus),  bus->number);
+                pci_domain_nr(bus),  bus->number);
         list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) {
                 pr_debug("     * Removing %s...\n", pci_name(dev));
-                eeh_remove_bus_device(dev);
-                pci_stop_and_remove_bus_device(dev);
-        }
+                eeh_remove_bus_device(dev, purge_pe);
+                pci_stop_and_remove_bus_device(dev);
+        }
+}
+
+/**
+ * pcibios_remove_pci_devices - remove all devices under this bus
+ *
+ * Remove all of the PCI devices under this bus both from the
+ * linux pci device tree, and from the powerpc EEH address cache.
+ */
+void pcibios_remove_pci_devices(struct pci_bus *bus)
+{
+        __pcibios_remove_pci_devices(bus, 1);
 }
 EXPORT_SYMBOL_GPL(pcibios_remove_pci_devices);
 
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 51ecac920dd8..e3cb7ae61658 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -388,10 +388,8 @@ static void __init pSeries_setup_arch(void)
 
         /* Find and initialize PCI host bridges */
         init_pci_config_tokens();
-        eeh_pseries_init();
         find_and_init_phbs();
         pSeries_reconfig_notifier_register(&pci_dn_reconfig_nb);
-        eeh_init();
 
         pSeries_nvram_init();
 
@@ -416,16 +414,20 @@ static int __init pSeries_init_panel(void)
 }
 machine_arch_initcall(pseries, pSeries_init_panel);
 
-static int pseries_set_dabr(unsigned long dabr)
+static int pseries_set_dabr(unsigned long dabr, unsigned long dabrx)
 {
         return plpar_hcall_norets(H_SET_DABR, dabr);
 }
 
-static int pseries_set_xdabr(unsigned long dabr)
+static int pseries_set_xdabr(unsigned long dabr, unsigned long dabrx)
 {
-        /* We want to catch accesses from kernel and userspace */
-        return plpar_hcall_norets(H_SET_XDABR, dabr,
-                        H_DABRX_KERNEL | H_DABRX_USER);
+        /* Have to set at least one bit in the DABRX according to PAPR */
+        if (dabrx == 0 && dabr == 0)
+                dabrx = DABRX_USER;
+        /* PAPR says we can only set kernel and user bits */
+        dabrx &= DABRX_KERNEL | DABRX_USER;
+
+        return plpar_hcall_norets(H_SET_XDABR, dabr, dabrx);
 }
 
 #define CMO_CHARACTERISTICS_TOKEN 44
@@ -529,10 +531,10 @@ static void __init pSeries_init_early(void)
         if (firmware_has_feature(FW_FEATURE_LPAR))
                 hvc_vio_init_early();
 #endif
-        if (firmware_has_feature(FW_FEATURE_DABR))
-                ppc_md.set_dabr = pseries_set_dabr;
-        else if (firmware_has_feature(FW_FEATURE_XDABR))
+        if (firmware_has_feature(FW_FEATURE_XDABR))
                 ppc_md.set_dabr = pseries_set_xdabr;
+        else if (firmware_has_feature(FW_FEATURE_DABR))
+                ppc_md.set_dabr = pseries_set_dabr;
 
         pSeries_cmo_feature_init();
         iommu_init_early_pSeries();
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 1bd7ecb24620..a57600b3a4e3 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_PPC_DCR_NATIVE)	+= dcr-low.o
 obj-$(CONFIG_PPC_PMI)           += pmi.o
 obj-$(CONFIG_U3_DART)           += dart_iommu.o
 obj-$(CONFIG_MMIO_NVRAM)        += mmio_nvram.o
-obj-$(CONFIG_FSL_SOC)           += fsl_soc.o
+obj-$(CONFIG_FSL_SOC)           += fsl_soc.o fsl_mpic_err.o
 obj-$(CONFIG_FSL_PCI)           += fsl_pci.o $(fsl-msi-obj-y)
 obj-$(CONFIG_FSL_PMC)           += fsl_pmc.o
 obj-$(CONFIG_FSL_LBC)           += fsl_lbc.o
diff --git a/arch/powerpc/sysdev/dart_iommu.c b/arch/powerpc/sysdev/dart_iommu.c
index 4f2680f431b5..bd968a43a48b 100644
--- a/arch/powerpc/sysdev/dart_iommu.c
+++ b/arch/powerpc/sysdev/dart_iommu.c
@@ -43,7 +43,6 @@
 #include <asm/iommu.h>
 #include <asm/pci-bridge.h>
 #include <asm/machdep.h>
-#include <asm/abs_addr.h>
 #include <asm/cacheflush.h>
 #include <asm/ppc-pci.h>
 
@@ -74,11 +73,16 @@ static int dart_is_u4;
 
 #define DBG(...)
 
+static DEFINE_SPINLOCK(invalidate_lock);
+
 static inline void dart_tlb_invalidate_all(void)
 {
         unsigned long l = 0;
         unsigned int reg, inv_bit;
         unsigned long limit;
+        unsigned long flags;
+
+        spin_lock_irqsave(&invalidate_lock, flags);
 
         DBG("dart: flush\n");
 
@@ -111,12 +115,17 @@ retry:
                         panic("DART: TLB did not flush after waiting a long "
                               "time. Buggy U3 ?");
         }
+
+        spin_unlock_irqrestore(&invalidate_lock, flags);
 }
 
 static inline void dart_tlb_invalidate_one(unsigned long bus_rpn)
 {
         unsigned int reg;
         unsigned int l, limit;
+        unsigned long flags;
+
+        spin_lock_irqsave(&invalidate_lock, flags);
 
         reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE |
                 (bus_rpn & DART_CNTL_U4_IONE_MASK);
@@ -138,6 +147,8 @@ wait_more:
                         panic("DART: TLB did not flush after waiting a long "
                               "time. Buggy U4 ?");
         }
+
+        spin_unlock_irqrestore(&invalidate_lock, flags);
 }
 
 static void dart_flush(struct iommu_table *tbl)
@@ -167,7 +178,7 @@ static int dart_build(struct iommu_table *tbl, long index,
          */
         l = npages;
         while (l--) {
-                rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT;
+                rpn = __pa(uaddr) >> DART_PAGE_SHIFT;
 
                 *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);
 
@@ -244,7 +255,7 @@ static int __init dart_init(struct device_node *dart_node)
                 panic("DART: Cannot map registers!");
 
         /* Map in DART table */
-        dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize);
+        dart_vbase = ioremap(__pa(dart_tablebase), dart_tablesize);
 
         /* Fill initial table */
         for (i = 0; i < dart_tablesize/4; i++)
@@ -463,7 +474,7 @@ void __init alloc_dart_table(void)
          * will blow up an entire large page anyway in the kernel mapping
          */
         dart_tablebase = (unsigned long)
-                abs_to_virt(memblock_alloc_base(1UL<<24, 1UL<<24, 0x80000000L));
+                __va(memblock_alloc_base(1UL<<24, 1UL<<24, 0x80000000L));
 
         printk(KERN_INFO "DART table allocated at: %lx\n", dart_tablebase);
 }
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
index 68ac3aacb191..d131c8a1cb15 100644
--- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -193,6 +193,16 @@ static struct of_device_id mpc85xx_l2ctlr_of_match[] = {
         {
                 .compatible = "fsl,mpc8548-l2-cache-controller",
         },
+        {       .compatible = "fsl,mpc8544-l2-cache-controller",},
+        {       .compatible = "fsl,mpc8572-l2-cache-controller",},
+        {       .compatible = "fsl,mpc8536-l2-cache-controller",},
+        {       .compatible = "fsl,p1021-l2-cache-controller",},
+        {       .compatible = "fsl,p1012-l2-cache-controller",},
+        {       .compatible = "fsl,p1025-l2-cache-controller",},
+        {       .compatible = "fsl,p1016-l2-cache-controller",},
+        {       .compatible = "fsl,p1024-l2-cache-controller",},
+        {       .compatible = "fsl,p1015-l2-cache-controller",},
+        {       .compatible = "fsl,p1010-l2-cache-controller",},
         {},
 };
 
diff --git a/arch/powerpc/sysdev/fsl_ifc.c b/arch/powerpc/sysdev/fsl_ifc.c
index b31f19f61031..097cc9d2585b 100644
--- a/arch/powerpc/sysdev/fsl_ifc.c
+++ b/arch/powerpc/sysdev/fsl_ifc.c
@@ -244,12 +244,6 @@ static int __devinit fsl_ifc_ctrl_probe(struct platform_device *dev)
         /* get the nand machine irq */
         fsl_ifc_ctrl_dev->nand_irq =
                         irq_of_parse_and_map(dev->dev.of_node, 1);
-        if (fsl_ifc_ctrl_dev->nand_irq == NO_IRQ) {
-                dev_err(&dev->dev, "failed to get irq resource "
-                                                "for NAND Machine\n");
-                ret = -ENODEV;
-                goto err;
-        }
 
         fsl_ifc_ctrl_dev->dev = &dev->dev;
 
@@ -267,12 +261,14 @@ static int __devinit fsl_ifc_ctrl_probe(struct platform_device *dev)
                 goto err_irq;
         }
 
-        ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq, 0,
-                          "fsl-ifc-nand", fsl_ifc_ctrl_dev);
-        if (ret != 0) {
-                dev_err(&dev->dev, "failed to install irq (%d)\n",
-                        fsl_ifc_ctrl_dev->nand_irq);
-                goto err_nandirq;
+        if (fsl_ifc_ctrl_dev->nand_irq) {
+                ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq,
+                                0, "fsl-ifc-nand", fsl_ifc_ctrl_dev);
+                if (ret != 0) {
+                        dev_err(&dev->dev, "failed to install irq (%d)\n",
+                                fsl_ifc_ctrl_dev->nand_irq);
+                        goto err_nandirq;
+                }
         }
 
         return 0;
diff --git a/arch/powerpc/sysdev/fsl_mpic_err.c b/arch/powerpc/sysdev/fsl_mpic_err.c
new file mode 100644
index 000000000000..b83f32562a37
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_mpic_err.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Varun Sethi <varun.sethi@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ */
+
+#include <linux/irq.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mpic.h>
+
+#include "mpic.h"
+
+#define MPIC_ERR_INT_BASE       0x3900
+#define MPIC_ERR_INT_EISR       0x0000
+#define MPIC_ERR_INT_EIMR       0x0010
+
+static inline u32 mpic_fsl_err_read(u32 __iomem *base, unsigned int err_reg)
+{
+        return in_be32(base + (err_reg >> 2));
+}
+
+static inline void mpic_fsl_err_write(u32 __iomem *base, u32 value)
+{
+        out_be32(base + (MPIC_ERR_INT_EIMR >> 2), value);
+}
+
+static void fsl_mpic_mask_err(struct irq_data *d)
+{
+        u32 eimr;
+        struct mpic *mpic = irq_data_get_irq_chip_data(d);
+        unsigned int src = virq_to_hw(d->irq) - mpic->err_int_vecs[0];
+
+        eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR);
+        eimr |= (1 << (31 - src));
+        mpic_fsl_err_write(mpic->err_regs, eimr);
+}
+
+static void fsl_mpic_unmask_err(struct irq_data *d)
+{
+        u32 eimr;
+        struct mpic *mpic = irq_data_get_irq_chip_data(d);
+        unsigned int src = virq_to_hw(d->irq) - mpic->err_int_vecs[0];
+
+        eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR);
+        eimr &= ~(1 << (31 - src));
+        mpic_fsl_err_write(mpic->err_regs, eimr);
+}
+
+static struct irq_chip fsl_mpic_err_chip = {
+        .irq_disable    = fsl_mpic_mask_err,
+        .irq_mask       = fsl_mpic_mask_err,
+        .irq_unmask     = fsl_mpic_unmask_err,
+};
+
+int mpic_setup_error_int(struct mpic *mpic, int intvec)
+{
+        int i;
+
+        mpic->err_regs = ioremap(mpic->paddr + MPIC_ERR_INT_BASE, 0x1000);
+        if (!mpic->err_regs) {
+                pr_err("could not map mpic error registers\n");
+                return -ENOMEM;
+        }
+        mpic->hc_err = fsl_mpic_err_chip;
+        mpic->hc_err.name = mpic->name;
+        mpic->flags |= MPIC_FSL_HAS_EIMR;
+        /* allocate interrupt vectors for error interrupts */
+        for (i = MPIC_MAX_ERR - 1; i >= 0; i--)
+                mpic->err_int_vecs[i] = --intvec;
+
+        return 0;
+}
+
+int mpic_map_error_int(struct mpic *mpic, unsigned int virq, irq_hw_number_t  hw)
+{
+        if ((mpic->flags & MPIC_FSL_HAS_EIMR) &&
+            (hw >= mpic->err_int_vecs[0] &&
+             hw <= mpic->err_int_vecs[MPIC_MAX_ERR - 1])) {
+                WARN_ON(mpic->flags & MPIC_SECONDARY);
+
+                pr_debug("mpic: mapping as Error Interrupt\n");
+                irq_set_chip_data(virq, mpic);
+                irq_set_chip_and_handler(virq, &mpic->hc_err,
+                                         handle_level_irq);
+                return 1;
+        }
+
+        return 0;
+}
+
+static irqreturn_t fsl_error_int_handler(int irq, void *data)
+{
+        struct mpic *mpic = (struct mpic *) data;
+        u32 eisr, eimr;
+        int errint;
+        unsigned int cascade_irq;
+
+        eisr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EISR);
+        eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR);
+
+        if (!(eisr & ~eimr))
+                return IRQ_NONE;
+
+        while (eisr) {
+                errint = __builtin_clz(eisr);
+                cascade_irq = irq_linear_revmap(mpic->irqhost,
+                                 mpic->err_int_vecs[errint]);
+                WARN_ON(cascade_irq == NO_IRQ);
+                if (cascade_irq != NO_IRQ) {
+                        generic_handle_irq(cascade_irq);
+                } else {
+                        eimr |=  1 << (31 - errint);
+                        mpic_fsl_err_write(mpic->err_regs, eimr);
+                }
+                eisr &= ~(1 << (31 - errint));
+        }
+
+        return IRQ_HANDLED;
+}
+
+void mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum)
+{
+        unsigned int virq;
+        int ret;
+
+        virq = irq_create_mapping(mpic->irqhost, irqnum);
+        if (virq == NO_IRQ) {
+                pr_err("Error interrupt setup failed\n");
+                return;
+        }
+
+        /* Mask all error interrupts */
+        mpic_fsl_err_write(mpic->err_regs, ~0);
+
+        ret = request_irq(virq, fsl_error_int_handler, IRQF_NO_THREAD,
+                    "mpic-error-int", mpic);
+        if (ret)
+                pr_err("Failed to register error interrupt handler\n");
+}
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index c37f46136321..ffb93ae9379b 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -38,15 +38,15 @@ static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
 
 static void __devinit quirk_fsl_pcie_header(struct pci_dev *dev)
 {
-        u8 progif;
+        u8 hdr_type;
 
         /* if we aren't a PCIe don't bother */
         if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
                 return;
 
         /* if we aren't in host mode don't bother */
-        pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
-        if (progif & 0x1)
+        pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
+        if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
                 return;
 
         dev->class = PCI_CLASS_BRIDGE_PCI << 8;
@@ -143,18 +143,20 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
         pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
                  (u64)rsrc->start, (u64)resource_size(rsrc));
 
-        if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) {
-                win_idx = 2;
-                start_idx = 0;
-                end_idx = 3;
-        }
-
         pci = ioremap(rsrc->start, resource_size(rsrc));
         if (!pci) {
             dev_err(hose->parent, "Unable to map ATMU registers\n");
             return;
         }
 
+        if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
+                if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
+                        win_idx = 2;
+                        start_idx = 0;
+                        end_idx = 3;
+                }
+        }
+
         /* Disable all windows (except powar0 since it's ignored) */
         for(i = 1; i < 5; i++)
                 out_be32(&pci->pow[i].powar, 0);
@@ -425,7 +427,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
         struct pci_controller *hose;
         struct resource rsrc;
         const int *bus_range;
-        u8 progif;
+        u8 hdr_type, progif;
 
         if (!of_device_is_available(dev)) {
                 pr_warning("%s: disabled\n", dev->full_name);
@@ -457,15 +459,17 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
         setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
                 PPC_INDIRECT_TYPE_BIG_ENDIAN);
 
-        early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
-        if ((progif & 1) == 1) {
-                /* unmap cfg_data & cfg_addr separately if not on same page */
-                if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
-                    ((unsigned long)hose->cfg_addr & PAGE_MASK))
-                        iounmap(hose->cfg_data);
-                iounmap(hose->cfg_addr);
-                pcibios_free_controller(hose);
-                return -ENODEV;
+        if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
+                /* For PCIE read HEADER_TYPE to identify controler mode */
+                early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
+                if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
+                        goto no_bridge;
+
+        } else {
+                /* For PCI read PROG to identify controller mode */
+                early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
+                if ((progif & 1) == 1)
+                        goto no_bridge;
         }
 
         setup_pci_cmd(hose);
@@ -494,6 +498,15 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
         setup_pci_atmu(hose, &rsrc);
 
         return 0;
+
+no_bridge:
+        /* unmap cfg_data & cfg_addr separately if not on same page */
+        if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
+            ((unsigned long)hose->cfg_addr & PAGE_MASK))
+                iounmap(hose->cfg_data);
+        iounmap(hose->cfg_addr);
+        pcibios_free_controller(hose);
+        return -ENODEV;
 }
 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
 
@@ -818,6 +831,7 @@ static const struct of_device_id pci_ids[] = {
         { .compatible = "fsl,p1010-pcie", },
         { .compatible = "fsl,p1023-pcie", },
         { .compatible = "fsl,p4080-pcie", },
+        { .compatible = "fsl,qoriq-pcie-v2.4", },
         { .compatible = "fsl,qoriq-pcie-v2.3", },
         { .compatible = "fsl,qoriq-pcie-v2.2", },
         {},
@@ -825,57 +839,80 @@ static const struct of_device_id pci_ids[] = {
 
 struct device_node *fsl_pci_primary;
 
-void __devinit fsl_pci_init(void)
+void fsl_pci_assign_primary(void)
 {
-        int ret;
-        struct device_node *node;
-        struct pci_controller *hose;
-        dma_addr_t max = 0xffffffff;
+        struct device_node *np;
 
         /* Callers can specify the primary bus using other means. */
-        if (!fsl_pci_primary) {
-                /* If a PCI host bridge contains an ISA node, it's primary. */
-                node = of_find_node_by_type(NULL, "isa");
-                while ((fsl_pci_primary = of_get_parent(node))) {
-                        of_node_put(node);
-                        node = fsl_pci_primary;
-
-                        if (of_match_node(pci_ids, node))
-                                break;
-                }
+        if (fsl_pci_primary)
+                return;
+
+        /* If a PCI host bridge contains an ISA node, it's primary. */
+        np = of_find_node_by_type(NULL, "isa");
+        while ((fsl_pci_primary = of_get_parent(np))) {
+                of_node_put(np);
+                np = fsl_pci_primary;
+
+                if (of_match_node(pci_ids, np) && of_device_is_available(np))
+                        return;
         }
 
-        node = NULL;
-        for_each_node_by_type(node, "pci") {
-                if (of_match_node(pci_ids, node)) {
-                        /*
-                         * If there's no PCI host bridge with ISA, arbitrarily
-                         * designate one as primary.  This can go away once
-                         * various bugs with primary-less systems are fixed.
-                         */
-                        if (!fsl_pci_primary)
-                                fsl_pci_primary = node;
-
-                        ret = fsl_add_bridge(node, fsl_pci_primary == node);
-                        if (ret == 0) {
-                                hose = pci_find_hose_for_OF_device(node);
-                                max = min(max, hose->dma_window_base_cur +
-                                                hose->dma_window_size);
-                        }
+        /*
+         * If there's no PCI host bridge with ISA, arbitrarily
+         * designate one as primary.  This can go away once
+         * various bugs with primary-less systems are fixed.
+         */
+        for_each_matching_node(np, pci_ids) {
+                if (of_device_is_available(np)) {
+                        fsl_pci_primary = np;
+                        of_node_put(np);
+                        return;
                 }
         }
+}
 
+static int __devinit fsl_pci_probe(struct platform_device *pdev)
+{
+        int ret;
+        struct device_node *node;
 #ifdef CONFIG_SWIOTLB
-        /*
-         * if we couldn't map all of DRAM via the dma windows
-         * we need SWIOTLB to handle buffers located outside of
-         * dma capable memory region
-         */
-        if (memblock_end_of_DRAM() - 1 > max) {
-                ppc_swiotlb_enable = 1;
-                set_pci_dma_ops(&swiotlb_dma_ops);
-                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
+        struct pci_controller *hose;
+#endif
+
+        node = pdev->dev.of_node;
+        ret = fsl_add_bridge(node, fsl_pci_primary == node);
+
+#ifdef CONFIG_SWIOTLB
+        if (ret == 0) {
+                hose = pci_find_hose_for_OF_device(pdev->dev.of_node);
+
+                /*
+                 * if we couldn't map all of DRAM via the dma windows
+                 * we need SWIOTLB to handle buffers located outside of
+                 * dma capable memory region
+                 */
+                if (memblock_end_of_DRAM() - 1 > hose->dma_window_base_cur +
+                                hose->dma_window_size)
+                        ppc_swiotlb_enable = 1;
         }
 #endif
+
+        mpc85xx_pci_err_probe(pdev);
+
+        return 0;
+}
+
+static struct platform_driver fsl_pci_driver = {
+        .driver = {
+                .name = "fsl-pci",
+                .of_match_table = pci_ids,
+        },
+        .probe = fsl_pci_probe,
+};
+
+static int __init fsl_pci_init(void)
+{
+        return platform_driver_register(&fsl_pci_driver);
 }
+arch_initcall(fsl_pci_init);
 #endif
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index baa0fd18289f..d078537adece 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -16,6 +16,7 @@
 
 #define PCIE_LTSSM      0x0404          /* PCIE Link Training and Status */
 #define PCIE_LTSSM_L0   0x16            /* L0 state */
+#define PCIE_IP_REV_2_2         0x02080202 /* PCIE IP block version Rev2.2 */
 #define PIWAR_EN                0x80000000      /* Enable */
 #define PIWAR_PF                0x20000000      /* prefetch */
 #define PIWAR_TGI_LOCAL         0x00f00000      /* target - local memory */
@@ -57,7 +58,9 @@ struct ccsr_pci {
         __be32  pex_pme_mes_disr;       /* 0x.024 - PCIE PME and message disable register */
         __be32  pex_pme_mes_ier;        /* 0x.028 - PCIE PME and message interrupt enable register */
         __be32  pex_pmcr;               /* 0x.02c - PCIE power management command register */
-        u8      res3[3024];
+        u8      res3[3016];
+        __be32  block_rev1;     /* 0x.bf8 - PCIE Block Revision register 1 */
+        __be32  block_rev2;     /* 0x.bfc - PCIE Block Revision register 2 */
 
 /* PCI/PCI Express outbound window 0-4
  * Window 0 is the default window and is the only window enabled upon reset.
@@ -95,10 +98,19 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose);
 
 extern struct device_node *fsl_pci_primary;
 
-#ifdef CONFIG_FSL_PCI
-void fsl_pci_init(void);
+#ifdef CONFIG_PCI
+void fsl_pci_assign_primary(void);
 #else
-static inline void fsl_pci_init(void) {}
+static inline void fsl_pci_assign_primary(void) {}
+#endif
+
+#ifdef CONFIG_EDAC_MPC85XX
+int mpc85xx_pci_err_probe(struct platform_device *op);
+#else
+static inline int mpc85xx_pci_err_probe(struct platform_device *op)
+{
+        return -ENOTSUPP;
+}
 #endif
 
 #endif /* __POWERPC_FSL_PCI_H */
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index bfc6211e5422..9c6e535daad2 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -6,7 +6,7 @@
  *  with various broken implementations of this HW.
  *
  *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
- *  Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *  Copyright 2010-2012 Freescale Semiconductor, Inc.
  *
  *  This file is subject to the terms and conditions of the GNU General Public
  *  License.  See the file COPYING in the main directory of this archive
@@ -221,24 +221,24 @@ static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 valu
         _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
 }
 
-static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
+static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm)
 {
-        unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
-                              ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
+        return (tm >> 2) * MPIC_TIMER_GROUP_STRIDE +
+               (tm & 3) * MPIC_INFO(TIMER_STRIDE);
+}
 
-        if (tm >= 4)
-                offset += 0x1000 / 4;
+static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
+{
+        unsigned int offset = mpic_tm_offset(mpic, tm) +
+                              MPIC_INFO(TIMER_VECTOR_PRI);
 
         return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
 }
 
 static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
 {
-        unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
-                              ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
-
-        if (tm >= 4)
-                offset += 0x1000 / 4;
+        unsigned int offset = mpic_tm_offset(mpic, tm) +
+                              MPIC_INFO(TIMER_VECTOR_PRI);
 
         _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
 }
@@ -1026,6 +1026,9 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq,
                 return 0;
         }
 
+        if (mpic_map_error_int(mpic, virq, hw))
+                return 0;
+
         if (hw >= mpic->num_sources)
                 return -EINVAL;
 
@@ -1085,7 +1088,16 @@ static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
                  */
                 switch (intspec[2]) {
                 case 0:
-                case 1: /* no EISR/EIMR support for now, treat as shared IRQ */
+                        break;
+                case 1:
+                        if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
+                                break;
+
+                        if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs))
+                                return -EINVAL;
+
+                        *out_hwirq = mpic->err_int_vecs[intspec[3]];
+
                         break;
                 case 2:
                         if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
@@ -1301,6 +1313,42 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
         mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
 
+        if (mpic->flags & MPIC_FSL) {
+                u32 brr1, version;
+                int ret;
+
+                /*
+                 * Yes, Freescale really did put global registers in the
+                 * magic per-cpu area -- and they don't even show up in the
+                 * non-magic per-cpu copies that this driver normally uses.
+                 */
+                mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
+                         MPIC_CPU_THISBASE, 0x1000);
+
+                brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
+                                MPIC_FSL_BRR1);
+                version = brr1 & MPIC_FSL_BRR1_VER;
+
+                /* Error interrupt mask register (EIMR) is required for
+                 * handling individual device error interrupts. EIMR
+                 * was added in MPIC version 4.1.
+                 *
+                 * Over here we reserve vector number space for error
+                 * interrupt vectors. This space is stolen from the
+                 * global vector number space, as in case of ipis
+                 * and timer interrupts.
+                 *
+                 * Available vector space = intvec_top - 12, where 12
+                 * is the number of vectors which have been consumed by
+                 * ipis and timer interrupts.
+                 */
+                if (version >= 0x401) {
+                        ret = mpic_setup_error_int(mpic, intvec_top - 12);
+                        if (ret)
+                                return NULL;
+                }
+        }
+
         /* Reset */
 
         /* When using a device-node, reset requests are only honored if the MPIC
@@ -1440,6 +1488,7 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
 void __init mpic_init(struct mpic *mpic)
 {
         int i, cpu;
+        int num_timers = 4;
 
         BUG_ON(mpic->num_sources == 0);
 
@@ -1448,15 +1497,34 @@ void __init mpic_init(struct mpic *mpic)
         /* Set current processor priority to max */
         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
 
+        if (mpic->flags & MPIC_FSL) {
+                u32 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
+                                      MPIC_FSL_BRR1);
+                u32 version = brr1 & MPIC_FSL_BRR1_VER;
+
+                /*
+                 * Timer group B is present at the latest in MPIC 3.1 (e.g.
+                 * mpc8536).  It is not present in MPIC 2.0 (e.g. mpc8544).
+                 * I don't know about the status of intermediate versions (or
+                 * whether they even exist).
+                 */
+                if (version >= 0x0301)
+                        num_timers = 8;
+        }
+
+        /* FSL mpic error interrupt intialization */
+        if (mpic->flags & MPIC_FSL_HAS_EIMR)
+                mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
+
         /* Initialize timers to our reserved vectors and mask them for now */
-        for (i = 0; i < 4; i++) {
+        for (i = 0; i < num_timers; i++) {
+                unsigned int offset = mpic_tm_offset(mpic, i);
+
                 mpic_write(mpic->tmregs,
-                           i * MPIC_INFO(TIMER_STRIDE) +
-                           MPIC_INFO(TIMER_DESTINATION),
+                           offset + MPIC_INFO(TIMER_DESTINATION),
                            1 << hard_smp_processor_id());
                 mpic_write(mpic->tmregs,
-                           i * MPIC_INFO(TIMER_STRIDE) +
-                           MPIC_INFO(TIMER_VECTOR_PRI),
+                           offset + MPIC_INFO(TIMER_VECTOR_PRI),
                            MPIC_VECPRI_MASK |
                            (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
                            (mpic->timer_vecs[0] + i));
diff --git a/arch/powerpc/sysdev/mpic.h b/arch/powerpc/sysdev/mpic.h
index 13f3e8913a93..24bf07a63924 100644
--- a/arch/powerpc/sysdev/mpic.h
+++ b/arch/powerpc/sysdev/mpic.h
@@ -40,4 +40,26 @@ extern int mpic_set_affinity(struct irq_data *d,
                              const struct cpumask *cpumask, bool force);
 extern void mpic_reset_core(int cpu);
 
+#ifdef CONFIG_FSL_SOC
+extern int mpic_map_error_int(struct mpic *mpic, unsigned int virq, irq_hw_number_t  hw);
+extern void mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum);
+extern int mpic_setup_error_int(struct mpic *mpic, int intvec);
+#else
+static inline int mpic_map_error_int(struct mpic *mpic, unsigned int virq, irq_hw_number_t  hw)
+{
+        return 0;
+}
+
+
+static inline void mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum)
+{
+        return;
+}
+
+static inline int mpic_setup_error_int(struct mpic *mpic, int intvec)
+{
+        return -1;
+}
+#endif
+
 #endif /* _POWERPC_SYSDEV_MPIC_H */
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 9b49c65ee7a4..3a56a639a92e 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -60,6 +60,8 @@ static cpumask_t cpus_in_xmon = CPU_MASK_NONE;
 static unsigned long xmon_taken = 1;
 static int xmon_owner;
 static int xmon_gate;
+#else
+#define xmon_owner 0
 #endif /* CONFIG_SMP */
 
 static unsigned long in_xmon __read_mostly = 0;
@@ -202,7 +204,13 @@ Commands:\n\
   di    dump instructions\n\
   df    dump float values\n\
   dd    dump double values\n\
-  dl    dump the kernel log buffer\n\
+  dl    dump the kernel log buffer\n"
+#ifdef CONFIG_PPC64
+  "\
+  dp[#] dump paca for current cpu, or cpu #\n\
+  dpa   dump paca for all possible cpus\n"
+#endif
+  "\
   dr    dump stream of raw bytes\n\
   e     print exception information\n\
   f     flush cache\n\
@@ -740,7 +748,7 @@ static void insert_bpts(void)
 static void insert_cpu_bpts(void)
 {
         if (dabr.enabled)
-                set_dabr(dabr.address | (dabr.enabled & 7));
+                set_dabr(dabr.address | (dabr.enabled & 7), DABRX_ALL);
         if (iabr && cpu_has_feature(CPU_FTR_IABR))
                 mtspr(SPRN_IABR, iabr->address
                          | (iabr->enabled & (BP_IABR|BP_IABR_TE)));
@@ -768,7 +776,7 @@ static void remove_bpts(void)
 
 static void remove_cpu_bpts(void)
 {
-        set_dabr(0);
+        set_dabr(0, 0);
         if (cpu_has_feature(CPU_FTR_IABR))
                 mtspr(SPRN_IABR, 0);
 }
@@ -2009,6 +2017,95 @@ static void xmon_rawdump (unsigned long adrs, long ndump)
         printf("\n");
 }
 
+#ifdef CONFIG_PPC64
+static void dump_one_paca(int cpu)
+{
+        struct paca_struct *p;
+
+        if (setjmp(bus_error_jmp) != 0) {
+                printf("*** Error dumping paca for cpu 0x%x!\n", cpu);
+                return;
+        }
+
+        catch_memory_errors = 1;
+        sync();
+
+        p = &paca[cpu];
+
+        printf("paca for cpu 0x%x @ %p:\n", cpu, p);
+
+        printf(" %-*s = %s\n", 16, "possible", cpu_possible(cpu) ? "yes" : "no");
+        printf(" %-*s = %s\n", 16, "present", cpu_present(cpu) ? "yes" : "no");
+        printf(" %-*s = %s\n", 16, "online", cpu_online(cpu) ? "yes" : "no");
+
+#define DUMP(paca, name, format) \
+        printf(" %-*s = %#-*"format"\t(0x%lx)\n", 16, #name, 18, paca->name, \
+                offsetof(struct paca_struct, name));
+
+        DUMP(p, lock_token, "x");
+        DUMP(p, paca_index, "x");
+        DUMP(p, kernel_toc, "lx");
+        DUMP(p, kernelbase, "lx");
+        DUMP(p, kernel_msr, "lx");
+#ifdef CONFIG_PPC_STD_MMU_64
+        DUMP(p, stab_real, "lx");
+        DUMP(p, stab_addr, "lx");
+#endif
+        DUMP(p, emergency_sp, "p");
+        DUMP(p, data_offset, "lx");
+        DUMP(p, hw_cpu_id, "x");
+        DUMP(p, cpu_start, "x");
+        DUMP(p, kexec_state, "x");
+        DUMP(p, __current, "p");
+        DUMP(p, kstack, "lx");
+        DUMP(p, stab_rr, "lx");
+        DUMP(p, saved_r1, "lx");
+        DUMP(p, trap_save, "x");
+        DUMP(p, soft_enabled, "x");
+        DUMP(p, irq_happened, "x");
+        DUMP(p, io_sync, "x");
+        DUMP(p, irq_work_pending, "x");
+        DUMP(p, nap_state_lost, "x");
+
+#undef DUMP
+
+        catch_memory_errors = 0;
+        sync();
+}
+
+static void dump_all_pacas(void)
+{
+        int cpu;
+
+        if (num_possible_cpus() == 0) {
+                printf("No possible cpus, use 'dp #' to dump individual cpus\n");
+                return;
+        }
+
+        for_each_possible_cpu(cpu)
+                dump_one_paca(cpu);
+}
+
+static void dump_pacas(void)
+{
+        unsigned long num;
+        int c;
+
+        c = inchar();
+        if (c == 'a') {
+                dump_all_pacas();
+                return;
+        }
+
+        termch = c;     /* Put c back, it wasn't 'a' */
+
+        if (scanhex(&num))
+                dump_one_paca(num);
+        else
+                dump_one_paca(xmon_owner);
+}
+#endif
+
 #define isxdigit(c)     (('0' <= (c) && (c) <= '9') \
                          || ('a' <= (c) && (c) <= 'f') \
                          || ('A' <= (c) && (c) <= 'F'))
@@ -2018,6 +2115,14 @@ dump(void)
         int c;
 
         c = inchar();
+
+#ifdef CONFIG_PPC64
+        if (c == 'p') {
+                dump_pacas();
+                return;
+        }
+#endif
+
         if ((isxdigit(c) && c != 'f' && c != 'd') || c == '\n')
                 termch = c;
         scanhex((void *)&adrs);
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index f9acddd9ace3..c8af429991d9 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -656,7 +656,6 @@ config S390_GUEST
         depends on 64BIT && EXPERIMENTAL
         select VIRTUALIZATION
         select VIRTIO
-        select VIRTIO_RING
         select VIRTIO_CONSOLE
         help
           Enabling this option adds support for virtio based paravirtual device
diff --git a/arch/s390/include/asm/compat.h b/arch/s390/include/asm/compat.h
index 234f1d859cea..a34a9d612fc0 100644
--- a/arch/s390/include/asm/compat.h
+++ b/arch/s390/include/asm/compat.h
@@ -65,6 +65,7 @@ typedef s64		compat_s64;
 typedef u32             compat_uint_t;
 typedef u32             compat_ulong_t;
 typedef u64             compat_u64;
+typedef u32             compat_uptr_t;
 
 struct compat_timespec {
         compat_time_t   tv_sec;
@@ -144,6 +145,79 @@ typedef u32		compat_old_sigset_t;	/* at least 32 bits */
 
 typedef u32             compat_sigset_word;
 
+typedef union compat_sigval {
+        compat_int_t    sival_int;
+        compat_uptr_t   sival_ptr;
+} compat_sigval_t;
+
+typedef struct compat_siginfo {
+        int     si_signo;
+        int     si_errno;
+        int     si_code;
+
+        union {
+                int _pad[128/sizeof(int) - 3];
+
+                /* kill() */
+                struct {
+                        pid_t   _pid;   /* sender's pid */
+                        uid_t   _uid;   /* sender's uid */
+                } _kill;
+
+                /* POSIX.1b timers */
+                struct {
+                        compat_timer_t _tid;            /* timer id */
+                        int _overrun;                   /* overrun count */
+                        compat_sigval_t _sigval;        /* same as below */
+                        int _sys_private;       /* not to be passed to user */
+                } _timer;
+
+                /* POSIX.1b signals */
+                struct {
+                        pid_t                   _pid;   /* sender's pid */
+                        uid_t                   _uid;   /* sender's uid */
+                        compat_sigval_t         _sigval;
+                } _rt;
+
+                /* SIGCHLD */
+                struct {
+                        pid_t                   _pid;   /* which child */
+                        uid_t                   _uid;   /* sender's uid */
+                        int                     _status;/* exit code */
+                        compat_clock_t          _utime;
+                        compat_clock_t          _stime;
+                } _sigchld;
+
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+                struct {
+                        __u32   _addr;  /* faulting insn/memory ref. - pointer */
+                } _sigfault;
+
+                /* SIGPOLL */
+                struct {
+                        int     _band;  /* POLL_IN, POLL_OUT, POLL_MSG */
+                        int     _fd;
+                } _sigpoll;
+        } _sifields;
+} compat_siginfo_t;
+
+/*
+ * How these fields are to be accessed.
+ */
+#define si_pid          _sifields._kill._pid
+#define si_uid          _sifields._kill._uid
+#define si_status       _sifields._sigchld._status
+#define si_utime        _sifields._sigchld._utime
+#define si_stime        _sifields._sigchld._stime
+#define si_value        _sifields._rt._sigval
+#define si_int          _sifields._rt._sigval.sival_int
+#define si_ptr          _sifields._rt._sigval.sival_ptr
+#define si_addr         _sifields._sigfault._addr
+#define si_band         _sifields._sigpoll._band
+#define si_fd           _sifields._sigpoll._fd
+#define si_tid          _sifields._timer._tid
+#define si_overrun      _sifields._timer._overrun
+
 #define COMPAT_OFF_T_MAX        0x7fffffff
 #define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
 
@@ -153,7 +227,6 @@ typedef u32		compat_sigset_word;
  * as pointers because the syscall entry code will have
  * appropriately converted them already.
  */
-typedef u32             compat_uptr_t;
 
 static inline void __user *compat_ptr(compat_uptr_t uptr)
 {
diff --git a/arch/s390/kernel/compat_linux.h b/arch/s390/kernel/compat_linux.h
index 9635d759c2b9..90887bd98cf0 100644
--- a/arch/s390/kernel/compat_linux.h
+++ b/arch/s390/kernel/compat_linux.h
@@ -23,74 +23,6 @@ struct old_sigaction32 {
        __u32                    sa_flags;
        __u32                    sa_restorer;    /* Another 32 bit pointer */
 };
- 
-typedef struct compat_siginfo {
-        int     si_signo;
-        int     si_errno;
-        int     si_code;
-
-        union {
-                int _pad[((128/sizeof(int)) - 3)];
-
-                /* kill() */
-                struct {
-                        pid_t   _pid;   /* sender's pid */
-                        uid_t   _uid;   /* sender's uid */
-                } _kill;
-
-                /* POSIX.1b timers */
-                struct {
-                        compat_timer_t _tid;            /* timer id */
-                        int _overrun;           /* overrun count */
-                        compat_sigval_t _sigval;        /* same as below */
-                        int _sys_private;       /* not to be passed to user */
-                } _timer;
-
-                /* POSIX.1b signals */
-                struct {
-                        pid_t                   _pid;   /* sender's pid */
-                        uid_t                   _uid;   /* sender's uid */
-                        compat_sigval_t         _sigval;
-                } _rt;
-
-                /* SIGCHLD */
-                struct {
-                        pid_t                   _pid;   /* which child */
-                        uid_t                   _uid;   /* sender's uid */
-                        int                     _status;/* exit code */
-                        compat_clock_t          _utime;
-                        compat_clock_t          _stime;
-                } _sigchld;
-
-                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
-                struct {
-                        __u32   _addr;  /* faulting insn/memory ref. - pointer */
-                } _sigfault;
-                          
-                /* SIGPOLL */
-                struct {
-                        int     _band;  /* POLL_IN, POLL_OUT, POLL_MSG */
-                        int     _fd;
-                } _sigpoll;
-        } _sifields;
-} compat_siginfo_t;
-
-/*
- * How these fields are to be accessed.
- */
-#define si_pid          _sifields._kill._pid
-#define si_uid          _sifields._kill._uid
-#define si_status       _sifields._sigchld._status
-#define si_utime        _sifields._sigchld._utime
-#define si_stime        _sifields._sigchld._stime
-#define si_value        _sifields._rt._sigval
-#define si_int          _sifields._rt._sigval.sival_int
-#define si_ptr          _sifields._rt._sigval.sival_ptr
-#define si_addr         _sifields._sigfault._addr
-#define si_band         _sifields._sigpoll._band
-#define si_fd           _sifields._sigpoll._fd    
-#define si_tid          _sifields._timer._tid
-#define si_overrun      _sifields._timer._overrun
 
 /* asm/sigcontext.h */
 typedef union
diff --git a/arch/score/Kconfig b/arch/score/Kconfig
index ba0f412920be..461c23747491 100644
--- a/arch/score/Kconfig
+++ b/arch/score/Kconfig
@@ -5,6 +5,7 @@ config SCORE
        select HAVE_GENERIC_HARDIRQS
        select GENERIC_IRQ_SHOW
        select GENERIC_IOMAP
+       select GENERIC_ATOMIC64
        select HAVE_MEMBLOCK
        select HAVE_MEMBLOCK_NODE_MAP
        select ARCH_DISCARD_MEMBLOCK
diff --git a/arch/score/include/asm/elf.h b/arch/score/include/asm/elf.h
index f478ce94181f..5d566c7a0af2 100644
--- a/arch/score/include/asm/elf.h
+++ b/arch/score/include/asm/elf.h
@@ -54,7 +54,7 @@ typedef elf_fpreg_t	elf_fpregset_t;
 
 #define SET_PERSONALITY(ex)                                     \
 do {                                                            \
-        set_personality(PER_LINUX);                             \
+        set_personality(PER_LINUX | (current->personality & (~PER_MASK))); \
 } while (0)
 
 struct task_struct;
diff --git a/arch/score/include/asm/unistd.h b/arch/score/include/asm/unistd.h
index 4aa957364d4d..a862384e9c16 100644
--- a/arch/score/include/asm/unistd.h
+++ b/arch/score/include/asm/unistd.h
@@ -1,6 +1,3 @@
-#if !defined(_ASM_SCORE_UNISTD_H) || defined(__SYSCALL)
-#define _ASM_SCORE_UNISTD_H
-
 #define __ARCH_HAVE_MMU
 
 #define __ARCH_WANT_SYSCALL_NO_AT
@@ -9,5 +6,3 @@
 #define __ARCH_WANT_SYSCALL_DEPRECATED
 
 #include <asm-generic/unistd.h>
-
-#endif /* _ASM_SCORE_UNISTD_H */
diff --git a/arch/score/kernel/sys_score.c b/arch/score/kernel/sys_score.c
index e478bf9a7e91..21e867974066 100644
--- a/arch/score/kernel/sys_score.c
+++ b/arch/score/kernel/sys_score.c
@@ -112,6 +112,7 @@ score_execve(struct pt_regs *regs)
  * Do a system call from kernel instead of calling sys_execve so we
  * end up with proper pt_regs.
  */
+asmlinkage
 int kernel_execve(const char *filename,
                   const char *const argv[],
                   const char *const envp[])
diff --git a/arch/sh/include/asm/elf.h b/arch/sh/include/asm/elf.h
index f38112be67d2..37924afa8d8a 100644
--- a/arch/sh/include/asm/elf.h
+++ b/arch/sh/include/asm/elf.h
@@ -183,7 +183,8 @@ do {									\
 } while (0)
 #endif
 
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX_32BIT)
+#define SET_PERSONALITY(ex) \
+        set_personality(PER_LINUX_32BIT | (current->personality & (~PER_MASK)))
 
 #ifdef CONFIG_VSYSCALL
 /* vDSO has arch_setup_additional_pages */
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 0cf60a628814..73a23f4617a3 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -134,7 +134,7 @@ __BUILD_MEMORY_STRING(__raw_, q, u64)
  * load/store instructions. sh_io_port_base is the virtual address to
  * which all ports are being mapped.
  */
-extern const unsigned long sh_io_port_base;
+extern unsigned long sh_io_port_base;
 
 static inline void __set_io_port_base(unsigned long pbase)
 {
diff --git a/arch/sh/kernel/ioport.c b/arch/sh/kernel/ioport.c
index e3ad6103e7c1..cca14ba84a37 100644
--- a/arch/sh/kernel/ioport.c
+++ b/arch/sh/kernel/ioport.c
@@ -11,7 +11,7 @@
 #include <linux/module.h>
 #include <linux/io.h>
 
-const unsigned long sh_io_port_base __read_mostly = -1;
+unsigned long sh_io_port_base __read_mostly = -1;
 EXPORT_SYMBOL(sh_io_port_base);
 
 void __iomem *__ioport_map(unsigned long addr, unsigned int size)
diff --git a/arch/sparc/include/asm/compat.h b/arch/sparc/include/asm/compat.h
index b8be20d42a0a..cef99fbc0a21 100644
--- a/arch/sparc/include/asm/compat.h
+++ b/arch/sparc/include/asm/compat.h
@@ -36,6 +36,7 @@ typedef s64		compat_s64;
 typedef u32             compat_uint_t;
 typedef u32             compat_ulong_t;
 typedef u64             compat_u64;
+typedef u32             compat_uptr_t;
 
 struct compat_timespec {
         compat_time_t   tv_sec;
@@ -147,6 +148,65 @@ typedef u32		compat_old_sigset_t;
 
 typedef u32             compat_sigset_word;
 
+typedef union compat_sigval {
+        compat_int_t    sival_int;
+        compat_uptr_t   sival_ptr;
+} compat_sigval_t;
+
+#define SI_PAD_SIZE32   (128/sizeof(int) - 3)
+
+typedef struct compat_siginfo {
+        int si_signo;
+        int si_errno;
+        int si_code;
+
+        union {
+                int _pad[SI_PAD_SIZE32];
+
+                /* kill() */
+                struct {
+                        compat_pid_t _pid;              /* sender's pid */
+                        unsigned int _uid;              /* sender's uid */
+                } _kill;
+
+                /* POSIX.1b timers */
+                struct {
+                        compat_timer_t _tid;            /* timer id */
+                        int _overrun;                   /* overrun count */
+                        compat_sigval_t _sigval;        /* same as below */
+                        int _sys_private;       /* not to be passed to user */
+                } _timer;
+
+                /* POSIX.1b signals */
+                struct {
+                        compat_pid_t _pid;              /* sender's pid */
+                        unsigned int _uid;              /* sender's uid */
+                        compat_sigval_t _sigval;
+                } _rt;
+
+                /* SIGCHLD */
+                struct {
+                        compat_pid_t _pid;              /* which child */
+                        unsigned int _uid;              /* sender's uid */
+                        int _status;                    /* exit code */
+                        compat_clock_t _utime;
+                        compat_clock_t _stime;
+                } _sigchld;
+
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS, SIGEMT */
+                struct {
+                        u32 _addr; /* faulting insn/memory ref. */
+                        int _trapno;
+                } _sigfault;
+
+                /* SIGPOLL */
+                struct {
+                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
+                        int _fd;
+                } _sigpoll;
+        } _sifields;
+} compat_siginfo_t;
+
 #define COMPAT_OFF_T_MAX        0x7fffffff
 #define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
 
@@ -156,7 +216,6 @@ typedef u32		compat_sigset_word;
  * as pointers because the syscall entry code will have
  * appropriately converted them already.
  */
-typedef u32             compat_uptr_t;
 
 static inline void __user *compat_ptr(compat_uptr_t uptr)
 {
diff --git a/arch/sparc/include/asm/elf_32.h b/arch/sparc/include/asm/elf_32.h
index 2d4d755cba9e..ac74a2c98e6d 100644
--- a/arch/sparc/include/asm/elf_32.h
+++ b/arch/sparc/include/asm/elf_32.h
@@ -128,6 +128,7 @@ typedef struct {
 
 #define ELF_PLATFORM    (NULL)
 
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) \
+        set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
 
 #endif /* !(__ASMSPARC_ELF_H) */
diff --git a/arch/sparc/include/asm/siginfo.h b/arch/sparc/include/asm/siginfo.h
index 215900fce21b..dbc182c438b4 100644
--- a/arch/sparc/include/asm/siginfo.h
+++ b/arch/sparc/include/asm/siginfo.h
@@ -3,7 +3,6 @@
 
 #if defined(__sparc__) && defined(__arch64__)
 
-#define SI_PAD_SIZE32   ((SI_MAX_SIZE/sizeof(int)) - 3)
 #define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
 #define __ARCH_SI_BAND_T int
 
diff --git a/arch/sparc/kernel/signal32.c b/arch/sparc/kernel/signal32.c
index a53e0a5fd3a3..53e48f721ce3 100644
--- a/arch/sparc/kernel/signal32.c
+++ b/arch/sparc/kernel/signal32.c
@@ -54,58 +54,6 @@ struct signal_frame32 {
         /* __siginfo_rwin_t * */u32 rwin_save;
 } __attribute__((aligned(8)));
 
-typedef struct compat_siginfo{
-        int si_signo;
-        int si_errno;
-        int si_code;
-
-        union {
-                int _pad[SI_PAD_SIZE32];
-
-                /* kill() */
-                struct {
-                        compat_pid_t _pid;              /* sender's pid */
-                        unsigned int _uid;              /* sender's uid */
-                } _kill;
-
-                /* POSIX.1b timers */
-                struct {
-                        compat_timer_t _tid;                    /* timer id */
-                        int _overrun;                   /* overrun count */
-                        compat_sigval_t _sigval;                /* same as below */
-                        int _sys_private;               /* not to be passed to user */
-                } _timer;
-
-                /* POSIX.1b signals */
-                struct {
-                        compat_pid_t _pid;              /* sender's pid */
-                        unsigned int _uid;              /* sender's uid */
-                        compat_sigval_t _sigval;
-                } _rt;
-
-                /* SIGCHLD */
-                struct {
-                        compat_pid_t _pid;              /* which child */
-                        unsigned int _uid;              /* sender's uid */
-                        int _status;                    /* exit code */
-                        compat_clock_t _utime;
-                        compat_clock_t _stime;
-                } _sigchld;
-
-                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS, SIGEMT */
-                struct {
-                        u32 _addr; /* faulting insn/memory ref. */
-                        int _trapno;
-                } _sigfault;
-
-                /* SIGPOLL */
-                struct {
-                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
-                        int _fd;
-                } _sigpoll;
-        } _sifields;
-}compat_siginfo_t;
-
 struct rt_signal_frame32 {
         struct sparc_stackf32   ss;
         compat_siginfo_t        info;
diff --git a/arch/tile/include/asm/compat.h b/arch/tile/include/asm/compat.h
index 6e74450ff0a1..3063e6fc8daa 100644
--- a/arch/tile/include/asm/compat.h
+++ b/arch/tile/include/asm/compat.h
@@ -110,6 +110,68 @@ struct compat_flock64 {
 
 typedef u32               compat_sigset_word;
 
+typedef union compat_sigval {
+        compat_int_t    sival_int;
+        compat_uptr_t   sival_ptr;
+} compat_sigval_t;
+
+#define COMPAT_SI_PAD_SIZE      (128/sizeof(int) - 3)
+
+typedef struct compat_siginfo {
+        int si_signo;
+        int si_errno;
+        int si_code;
+
+        union {
+                int _pad[COMPAT_SI_PAD_SIZE];
+
+                /* kill() */
+                struct {
+                        unsigned int _pid;      /* sender's pid */
+                        unsigned int _uid;      /* sender's uid */
+                } _kill;
+
+                /* POSIX.1b timers */
+                struct {
+                        compat_timer_t _tid;    /* timer id */
+                        int _overrun;           /* overrun count */
+                        compat_sigval_t _sigval;        /* same as below */
+                        int _sys_private;       /* not to be passed to user */
+                        int _overrun_incr;      /* amount to add to overrun */
+                } _timer;
+
+                /* POSIX.1b signals */
+                struct {
+                        unsigned int _pid;      /* sender's pid */
+                        unsigned int _uid;      /* sender's uid */
+                        compat_sigval_t _sigval;
+                } _rt;
+
+                /* SIGCHLD */
+                struct {
+                        unsigned int _pid;      /* which child */
+                        unsigned int _uid;      /* sender's uid */
+                        int _status;            /* exit code */
+                        compat_clock_t _utime;
+                        compat_clock_t _stime;
+                } _sigchld;
+
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+                struct {
+                        unsigned int _addr;     /* faulting insn/memory ref. */
+#ifdef __ARCH_SI_TRAPNO
+                        int _trapno;    /* TRAP # which caused the signal */
+#endif
+                } _sigfault;
+
+                /* SIGPOLL */
+                struct {
+                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
+                        int _fd;
+                } _sigpoll;
+        } _sifields;
+} compat_siginfo_t;
+
 #define COMPAT_OFF_T_MAX        0x7fffffff
 #define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
 
diff --git a/arch/tile/include/asm/elf.h b/arch/tile/include/asm/elf.h
index d16d006d660e..f8ccf08f6934 100644
--- a/arch/tile/include/asm/elf.h
+++ b/arch/tile/include/asm/elf.h
@@ -156,12 +156,12 @@ extern int arch_setup_additional_pages(struct linux_binprm *bprm,
 #undef SET_PERSONALITY
 #define SET_PERSONALITY(ex) \
 do { \
-        current->personality = PER_LINUX; \
+        set_personality(PER_LINUX | (current->personality & (~PER_MASK))); \
         current_thread_info()->status &= ~TS_COMPAT; \
 } while (0)
 #define COMPAT_SET_PERSONALITY(ex) \
 do { \
-        current->personality = PER_LINUX_32BIT; \
+        set_personality(PER_LINUX | (current->personality & (~PER_MASK))); \
         current_thread_info()->status |= TS_COMPAT; \
 } while (0)
 
diff --git a/arch/tile/include/asm/unistd.h b/arch/tile/include/asm/unistd.h
index a017246ca0ce..0e1f3e66e492 100644
--- a/arch/tile/include/asm/unistd.h
+++ b/arch/tile/include/asm/unistd.h
@@ -12,9 +12,6 @@
  *   more details.
  */
 
-#if !defined(_ASM_TILE_UNISTD_H) || defined(__SYSCALL)
-#define _ASM_TILE_UNISTD_H
-
 #if !defined(__LP64__) || defined(__SYSCALL_COMPAT)
 /* Use the flavor of this syscall that matches the 32-bit API better. */
 #define __ARCH_WANT_SYNC_FILE_RANGE2
@@ -43,5 +40,3 @@ __SYSCALL(__NR_cmpxchg_badaddr, sys_cmpxchg_badaddr)
 #endif
 #define __ARCH_WANT_SYS_NEWFSTATAT
 #endif
-
-#endif /* _ASM_TILE_UNISTD_H */
diff --git a/arch/tile/kernel/compat_signal.c b/arch/tile/kernel/compat_signal.c
index 474571b84085..7bc0859a9f5e 100644
--- a/arch/tile/kernel/compat_signal.c
+++ b/arch/tile/kernel/compat_signal.c
@@ -55,63 +55,6 @@ struct compat_ucontext {
         sigset_t          uc_sigmask;   /* mask last for extensibility */
 };
 
-#define COMPAT_SI_PAD_SIZE      ((SI_MAX_SIZE - 3 * sizeof(int)) / sizeof(int))
-
-struct compat_siginfo {
-        int si_signo;
-        int si_errno;
-        int si_code;
-
-        union {
-                int _pad[COMPAT_SI_PAD_SIZE];
-
-                /* kill() */
-                struct {
-                        unsigned int _pid;      /* sender's pid */
-                        unsigned int _uid;      /* sender's uid */
-                } _kill;
-
-                /* POSIX.1b timers */
-                struct {
-                        compat_timer_t _tid;    /* timer id */
-                        int _overrun;           /* overrun count */
-                        compat_sigval_t _sigval;        /* same as below */
-                        int _sys_private;       /* not to be passed to user */
-                        int _overrun_incr;      /* amount to add to overrun */
-                } _timer;
-
-                /* POSIX.1b signals */
-                struct {
-                        unsigned int _pid;      /* sender's pid */
-                        unsigned int _uid;      /* sender's uid */
-                        compat_sigval_t _sigval;
-                } _rt;
-
-                /* SIGCHLD */
-                struct {
-                        unsigned int _pid;      /* which child */
-                        unsigned int _uid;      /* sender's uid */
-                        int _status;            /* exit code */
-                        compat_clock_t _utime;
-                        compat_clock_t _stime;
-                } _sigchld;
-
-                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
-                struct {
-                        unsigned int _addr;     /* faulting insn/memory ref. */
-#ifdef __ARCH_SI_TRAPNO
-                        int _trapno;    /* TRAP # which caused the signal */
-#endif
-                } _sigfault;
-
-                /* SIGPOLL */
-                struct {
-                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
-                        int _fd;
-                } _sigpoll;
-        } _sifields;
-};
-
 struct compat_rt_sigframe {
         unsigned char save_area[C_ABI_SAVE_AREA_SIZE]; /* caller save area */
         struct compat_siginfo info;
diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig
index b0a47433341e..1e638e75a6b7 100644
--- a/arch/unicore32/Kconfig
+++ b/arch/unicore32/Kconfig
@@ -6,6 +6,7 @@ config UNICORE32
         select HAVE_DMA_ATTRS
         select HAVE_KERNEL_GZIP
         select HAVE_KERNEL_BZIP2
+        select GENERIC_ATOMIC64
         select HAVE_KERNEL_LZO
         select HAVE_KERNEL_LZMA
         select ARCH_HAVE_CUSTOM_GPIO_H
diff --git a/arch/unicore32/include/asm/unistd.h b/arch/unicore32/include/asm/unistd.h
index 9b2428019961..2abcf61c615d 100644
--- a/arch/unicore32/include/asm/unistd.h
+++ b/arch/unicore32/include/asm/unistd.h
@@ -9,10 +9,6 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#if !defined(__UNICORE_UNISTD_H__) || defined(__SYSCALL)
-#define __UNICORE_UNISTD_H__
 
 /* Use the standard ABI for syscalls. */
 #include <asm-generic/unistd.h>
-
-#endif /* __UNICORE_UNISTD_H__ */
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 474ca35b1bce..58790bd85c1d 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -92,7 +92,7 @@ endif
 ifdef CONFIG_X86_X32
         x32_ld_ok := $(call try-run,\
                         /bin/echo -e '1: .quad 1b' | \
-                        $(CC) $(KBUILD_AFLAGS) -c -xassembler -o "$$TMP" - && \
+                        $(CC) $(KBUILD_AFLAGS) -c -x assembler -o "$$TMP" - && \
                         $(OBJCOPY) -O elf32-x86-64 "$$TMP" "$$TMPO" && \
                         $(LD) -m elf32_x86_64 "$$TMPO" -o "$$TMP",y,n)
         ifeq ($(x32_ld_ok),y)
@@ -142,7 +142,7 @@ KBUILD_CFLAGS += $(call cc-option,-mno-avx,)
 KBUILD_CFLAGS += $(mflags-y)
 KBUILD_AFLAGS += $(mflags-y)
 
-archscripts: scripts_basic
+archscripts:
         $(Q)$(MAKE) $(build)=arch/x86/tools relocs
 
 ###
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index f34261296ffb..338803422239 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -409,7 +409,7 @@ extern struct apic *apic;
  * to enforce the order with in them.
  */
 #define apic_driver(sym)                                        \
-        static struct apic *__apicdrivers_##sym __used          \
+        static const struct apic *__apicdrivers_##sym __used            \
         __aligned(sizeof(struct apic *))                        \
         __section(.apicdrivers) = { &sym }
 
diff --git a/arch/x86/include/asm/compat.h b/arch/x86/include/asm/compat.h
index fedf32b73e65..59c6c401f79f 100644
--- a/arch/x86/include/asm/compat.h
+++ b/arch/x86/include/asm/compat.h
@@ -41,6 +41,7 @@ typedef s64 __attribute__((aligned(4))) compat_s64;
 typedef u32             compat_uint_t;
 typedef u32             compat_ulong_t;
 typedef u64 __attribute__((aligned(4))) compat_u64;
+typedef u32             compat_uptr_t;
 
 struct compat_timespec {
         compat_time_t   tv_sec;
@@ -124,6 +125,78 @@ typedef u32		compat_old_sigset_t;	/* at least 32 bits */
 
 typedef u32               compat_sigset_word;
 
+typedef union compat_sigval {
+        compat_int_t    sival_int;
+        compat_uptr_t   sival_ptr;
+} compat_sigval_t;
+
+typedef struct compat_siginfo {
+        int si_signo;
+        int si_errno;
+        int si_code;
+
+        union {
+                int _pad[128/sizeof(int) - 3];
+
+                /* kill() */
+                struct {
+                        unsigned int _pid;      /* sender's pid */
+                        unsigned int _uid;      /* sender's uid */
+                } _kill;
+
+                /* POSIX.1b timers */
+                struct {
+                        compat_timer_t _tid;    /* timer id */
+                        int _overrun;           /* overrun count */
+                        compat_sigval_t _sigval;        /* same as below */
+                        int _sys_private;       /* not to be passed to user */
+                        int _overrun_incr;      /* amount to add to overrun */
+                } _timer;
+
+                /* POSIX.1b signals */
+                struct {
+                        unsigned int _pid;      /* sender's pid */
+                        unsigned int _uid;      /* sender's uid */
+                        compat_sigval_t _sigval;
+                } _rt;
+
+                /* SIGCHLD */
+                struct {
+                        unsigned int _pid;      /* which child */
+                        unsigned int _uid;      /* sender's uid */
+                        int _status;            /* exit code */
+                        compat_clock_t _utime;
+                        compat_clock_t _stime;
+                } _sigchld;
+
+                /* SIGCHLD (x32 version) */
+                struct {
+                        unsigned int _pid;      /* which child */
+                        unsigned int _uid;      /* sender's uid */
+                        int _status;            /* exit code */
+                        compat_s64 _utime;
+                        compat_s64 _stime;
+                } _sigchld_x32;
+
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+                struct {
+                        unsigned int _addr;     /* faulting insn/memory ref. */
+                } _sigfault;
+
+                /* SIGPOLL */
+                struct {
+                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
+                        int _fd;
+                } _sigpoll;
+
+                struct {
+                        unsigned int _call_addr; /* calling insn */
+                        int _syscall;   /* triggering system call number */
+                        unsigned int _arch;     /* AUDIT_ARCH_* of syscall */
+                } _sigsys;
+        } _sifields;
+} compat_siginfo_t;
+
 #define COMPAT_OFF_T_MAX        0x7fffffff
 #define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
 
@@ -209,7 +282,6 @@ typedef struct user_regs_struct32 compat_elf_gregset_t;
  * as pointers because the syscall entry code will have
  * appropriately converted them already.
  */
-typedef u32             compat_uptr_t;
 
 static inline void __user *compat_ptr(compat_uptr_t uptr)
 {
diff --git a/arch/x86/include/asm/ia32.h b/arch/x86/include/asm/ia32.h
index b04cbdb138cd..e6232773ce49 100644
--- a/arch/x86/include/asm/ia32.h
+++ b/arch/x86/include/asm/ia32.h
@@ -86,73 +86,6 @@ struct stat64 {
         unsigned long long      st_ino;
 } __attribute__((packed));
 
-typedef struct compat_siginfo {
-        int si_signo;
-        int si_errno;
-        int si_code;
-
-        union {
-                int _pad[((128 / sizeof(int)) - 3)];
-
-                /* kill() */
-                struct {
-                        unsigned int _pid;      /* sender's pid */
-                        unsigned int _uid;      /* sender's uid */
-                } _kill;
-
-                /* POSIX.1b timers */
-                struct {
-                        compat_timer_t _tid;    /* timer id */
-                        int _overrun;           /* overrun count */
-                        compat_sigval_t _sigval;        /* same as below */
-                        int _sys_private;       /* not to be passed to user */
-                        int _overrun_incr;      /* amount to add to overrun */
-                } _timer;
-
-                /* POSIX.1b signals */
-                struct {
-                        unsigned int _pid;      /* sender's pid */
-                        unsigned int _uid;      /* sender's uid */
-                        compat_sigval_t _sigval;
-                } _rt;
-
-                /* SIGCHLD */
-                struct {
-                        unsigned int _pid;      /* which child */
-                        unsigned int _uid;      /* sender's uid */
-                        int _status;            /* exit code */
-                        compat_clock_t _utime;
-                        compat_clock_t _stime;
-                } _sigchld;
-
-                /* SIGCHLD (x32 version) */
-                struct {
-                        unsigned int _pid;      /* which child */
-                        unsigned int _uid;      /* sender's uid */
-                        int _status;            /* exit code */
-                        compat_s64 _utime;
-                        compat_s64 _stime;
-                } _sigchld_x32;
-
-                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
-                struct {
-                        unsigned int _addr;     /* faulting insn/memory ref. */
-                } _sigfault;
-
-                /* SIGPOLL */
-                struct {
-                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
-                        int _fd;
-                } _sigpoll;
-
-                struct {
-                        unsigned int _call_addr; /* calling insn */
-                        int _syscall;   /* triggering system call number */
-                        unsigned int _arch;     /* AUDIT_ARCH_* of syscall */
-                } _sigsys;
-        } _sifields;
-} compat_siginfo_t;
-
 #define IA32_STACK_TOP IA32_PAGE_OFFSET
 
 #ifdef __KERNEL__
diff --git a/arch/x86/include/asm/xen/interface.h b/arch/x86/include/asm/xen/interface.h
index 1707cfa928fb..6d2f75a82a14 100644
--- a/arch/x86/include/asm/xen/interface.h
+++ b/arch/x86/include/asm/xen/interface.h
@@ -51,6 +51,7 @@
  * with Xen so that on ARM we can have one ABI that works for 32 and 64
  * bit guests. */
 typedef unsigned long xen_pfn_t;
+typedef unsigned long xen_ulong_t;
 /* Guest handles for primitive C types. */
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint,  unsigned int);
diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c
index bc552cff2578..a65829ac2b9a 100644
--- a/arch/x86/kernel/apic/apic_numachip.c
+++ b/arch/x86/kernel/apic/apic_numachip.c
@@ -30,7 +30,7 @@
 
 static int numachip_system __read_mostly;
 
-static struct apic apic_numachip __read_mostly;
+static const struct apic apic_numachip __read_mostly;
 
 static unsigned int get_apic_id(unsigned long x)
 {
@@ -199,7 +199,7 @@ static int numachip_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
         return 0;
 }
 
-static struct apic apic_numachip __refconst = {
+static const struct apic apic_numachip __refconst = {
 
         .name                           = "NumaConnect system",
         .probe                          = numachip_probe,
diff --git a/arch/x86/kernel/rtc.c b/arch/x86/kernel/rtc.c
index af6db6ec5b2a..4929c1be0ac0 100644
--- a/arch/x86/kernel/rtc.c
+++ b/arch/x86/kernel/rtc.c
@@ -225,7 +225,7 @@ static struct platform_device rtc_device = {
 static __init int add_rtc_cmos(void)
 {
 #ifdef CONFIG_PNP
-        static const char *ids[] __initconst =
+        static const char * const  const ids[] __initconst =
             { "PNP0b00", "PNP0b01", "PNP0b02", };
         struct pnp_dev *dev;
         struct pnp_id *id;
diff --git a/arch/x86/lguest/Kconfig b/arch/x86/lguest/Kconfig
index 6e121a2a49e1..7872a3330fb5 100644
--- a/arch/x86/lguest/Kconfig
+++ b/arch/x86/lguest/Kconfig
@@ -4,7 +4,6 @@ config LGUEST_GUEST
         depends on X86_32
         select VIRTUALIZATION
         select VIRTIO
-        select VIRTIO_RING
         select VIRTIO_CONSOLE
         help
           Lguest is a tiny in-kernel hypervisor.  Selecting this will
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 2d932c351f91..bf788d34530d 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -33,6 +33,7 @@
 #include <linux/memblock.h>
 
 #include <xen/xen.h>
+#include <xen/events.h>
 #include <xen/interface/xen.h>
 #include <xen/interface/version.h>
 #include <xen/interface/physdev.h>
diff --git a/arch/x86/xen/irq.c b/arch/x86/xen/irq.c
index 157337657971..01a4dc015ae1 100644
--- a/arch/x86/xen/irq.c
+++ b/arch/x86/xen/irq.c
@@ -5,6 +5,7 @@
 #include <xen/interface/xen.h>
 #include <xen/interface/sched.h>
 #include <xen/interface/vcpu.h>
+#include <xen/events.h>
 
 #include <asm/xen/hypercall.h>
 #include <asm/xen/hypervisor.h>
diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
index bb5a8105ea86..a95b41744ad0 100644
--- a/arch/x86/xen/xen-ops.h
+++ b/arch/x86/xen/xen-ops.h
@@ -35,7 +35,6 @@ void xen_set_pat(u64);
 
 char * __init xen_memory_setup(void);
 void __init xen_arch_setup(void);
-void __init xen_init_IRQ(void);
 void xen_enable_sysenter(void);
 void xen_enable_syscall(void);
 void xen_vcpu_restore(void);
diff --git a/arch/xtensa/include/asm/elf.h b/arch/xtensa/include/asm/elf.h
index 6e65eadaae14..5293312bc6a4 100644
--- a/arch/xtensa/include/asm/elf.h
+++ b/arch/xtensa/include/asm/elf.h
@@ -189,7 +189,8 @@ typedef struct {
 #endif
 } elf_xtregs_t;
 
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX_32BIT)
+#define SET_PERSONALITY(ex) \
+        set_personality(PER_LINUX_32BIT | (current->personality & (~PER_MASK)))
 
 struct task_struct;