354 files changed, 8445 insertions, 2475 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index 4877a8c8ee16..fe48fc7a3eba 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -32,8 +32,9 @@ config HAVE_OPROFILE
 
 config KPROBES
         bool "Kprobes"
-        depends on KALLSYMS && MODULES
+        depends on MODULES
         depends on HAVE_KPROBES
+        select KALLSYMS
         help
           Kprobes allows you to trap at almost any kernel address and
           execute a callback function.  register_kprobe() establishes
@@ -45,7 +46,6 @@ config OPTPROBES
         def_bool y
         depends on KPROBES && HAVE_OPTPROBES
         depends on !PREEMPT
-        select KALLSYMS_ALL
 
 config HAVE_EFFICIENT_UNALIGNED_ACCESS
         bool
diff --git a/arch/alpha/kernel/entry.S b/arch/alpha/kernel/entry.S
index ab1ee0ab082b..6d159cee5f2f 100644
--- a/arch/alpha/kernel/entry.S
+++ b/arch/alpha/kernel/entry.S
@@ -73,8 +73,6 @@
         ldq     $20, HAE_REG($19);      \
         stq     $21, HAE_CACHE($19);    \
         stq     $21, 0($20);            \
-        ldq     $0, 0($sp);             \
-        ldq     $1, 8($sp);             \
 99:;                                    \
         ldq     $19, 72($sp);           \
         ldq     $20, 80($sp);           \
@@ -316,7 +314,7 @@ ret_from_sys_call:
         cmovne  $26, 0, $19             /* $19 = 0 => non-restartable */
         ldq     $0, SP_OFF($sp)
         and     $0, 8, $0
-        beq     $0, restore_all
+        beq     $0, ret_to_kernel
 ret_to_user:
         /* Make sure need_resched and sigpending don't change between
                 sampling and the rti.  */
@@ -329,6 +327,11 @@ restore_all:
         RESTORE_ALL
         call_pal PAL_rti
 
+ret_to_kernel:
+        lda     $16, 7
+        call_pal PAL_swpipl
+        br restore_all
+
         .align 3
 $syscall_error:
         /*
@@ -657,7 +660,7 @@ kernel_thread:
         /* We don't actually care for a3 success widgetry in the kernel.
            Not for positive errno values.  */
         stq     $0, 0($sp)              /* $0 */
-        br      restore_all
+        br      ret_to_kernel
 .end kernel_thread
 
 /*
@@ -912,15 +915,6 @@ sys_execve:
 .end sys_execve
 
         .align  4
-        .globl  osf_sigprocmask
-        .ent    osf_sigprocmask
-osf_sigprocmask:
-        .prologue 0
-        mov     $sp, $18
-        jmp     $31, sys_osf_sigprocmask
-.end osf_sigprocmask
-
-        .align  4
         .globl  alpha_ni_syscall
         .ent    alpha_ni_syscall
 alpha_ni_syscall:
diff --git a/arch/alpha/kernel/process.c b/arch/alpha/kernel/process.c
index 842dba308eab..3ec35066f1dc 100644
--- a/arch/alpha/kernel/process.c
+++ b/arch/alpha/kernel/process.c
@@ -356,7 +356,7 @@ dump_elf_thread(elf_greg_t *dest, struct pt_regs *pt, struct thread_info *ti)
         dest[27] = pt->r27;
         dest[28] = pt->r28;
         dest[29] = pt->gp;
-        dest[30] = rdusp();
+        dest[30] = ti == current_thread_info() ? rdusp() : ti->pcb.usp;
         dest[31] = pt->pc;
 
         /* Once upon a time this was the PS value.  Which is stupid
diff --git a/arch/alpha/kernel/signal.c b/arch/alpha/kernel/signal.c
index 0f6b51ae865a..6f7feb5db271 100644
--- a/arch/alpha/kernel/signal.c
+++ b/arch/alpha/kernel/signal.c
@@ -41,46 +41,20 @@ static void do_signal(struct pt_regs *, struct switch_stack *,
 /*
  * The OSF/1 sigprocmask calling sequence is different from the
  * C sigprocmask() sequence..
- *
- * how:
- * 1 - SIG_BLOCK
- * 2 - SIG_UNBLOCK
- * 3 - SIG_SETMASK
- *
- * We change the range to -1 .. 1 in order to let gcc easily
- * use the conditional move instructions.
- *
- * Note that we don't need to acquire the kernel lock for SMP
- * operation, as all of this is local to this thread.
  */
-SYSCALL_DEFINE3(osf_sigprocmask, int, how, unsigned long, newmask,
-                struct pt_regs *, regs)
+SYSCALL_DEFINE2(osf_sigprocmask, int, how, unsigned long, newmask)
 {
-        unsigned long oldmask = -EINVAL;
-
-        if ((unsigned long)how-1 <= 2) {
-                long sign = how-2;              /* -1 .. 1 */
-                unsigned long block, unblock;
-
-                newmask &= _BLOCKABLE;
-                spin_lock_irq(&current->sighand->siglock);
-                oldmask = current->blocked.sig[0];
-
-                unblock = oldmask & ~newmask;
-                block = oldmask | newmask;
-                if (!sign)
-                        block = unblock;
-                if (sign <= 0)
-                        newmask = block;
-                if (_NSIG_WORDS > 1 && sign > 0)
-                        sigemptyset(&current->blocked);
-                current->blocked.sig[0] = newmask;
-                recalc_sigpending();
-                spin_unlock_irq(&current->sighand->siglock);
-
-                regs->r0 = 0;           /* special no error return */
+        sigset_t oldmask;
+        sigset_t mask;
+        unsigned long res;
+
+        siginitset(&mask, newmask & _BLOCKABLE);
+        res = sigprocmask(how, &mask, &oldmask);
+        if (!res) {
+                force_successful_syscall_return();
+                res = oldmask.sig[0];
         }
-        return oldmask;
+        return res;
 }
 
 SYSCALL_DEFINE3(osf_sigaction, int, sig,
@@ -94,9 +68,9 @@ SYSCALL_DEFINE3(osf_sigaction, int, sig,
                 old_sigset_t mask;
                 if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
                     __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
-                    __get_user(new_ka.sa.sa_flags, &act->sa_flags))
+                    __get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
+                    __get_user(mask, &act->sa_mask))
                         return -EFAULT;
-                __get_user(mask, &act->sa_mask);
                 siginitset(&new_ka.sa.sa_mask, mask);
                 new_ka.ka_restorer = NULL;
         }
@@ -106,9 +80,9 @@ SYSCALL_DEFINE3(osf_sigaction, int, sig,
         if (!ret && oact) {
                 if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
                     __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
-                    __put_user(old_ka.sa.sa_flags, &oact->sa_flags))
+                    __put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
+                    __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
                         return -EFAULT;
-                __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
         }
 
         return ret;
diff --git a/arch/alpha/kernel/systbls.S b/arch/alpha/kernel/systbls.S
index ce594ef533cc..a6a1de9db16f 100644
--- a/arch/alpha/kernel/systbls.S
+++ b/arch/alpha/kernel/systbls.S
@@ -58,7 +58,7 @@ sys_call_table:
         .quad sys_open                          /* 45 */
         .quad alpha_ni_syscall
         .quad sys_getxgid
-        .quad osf_sigprocmask
+        .quad sys_osf_sigprocmask
         .quad alpha_ni_syscall
         .quad alpha_ni_syscall                  /* 50 */
         .quad sys_acct
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 553b7cf17bfb..7949fe65ecd4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -271,7 +271,6 @@ config ARCH_AT91
         bool "Atmel AT91"
         select ARCH_REQUIRE_GPIOLIB
         select HAVE_CLK
-        select ARCH_USES_GETTIMEOFFSET
         help
           This enables support for systems based on the Atmel AT91RM9200,
           AT91SAM9 and AT91CAP9 processors.
@@ -511,6 +510,7 @@ config ARCH_MMP
         select GENERIC_CLOCKEVENTS
         select TICK_ONESHOT
         select PLAT_PXA
+        select SPARSE_IRQ
         help
           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 
@@ -588,6 +588,7 @@ config ARCH_PXA
         select GENERIC_CLOCKEVENTS
         select TICK_ONESHOT
         select PLAT_PXA
+        select SPARSE_IRQ
         help
           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 
@@ -748,6 +749,15 @@ config ARCH_SHARK
           Support for the StrongARM based Digital DNARD machine, also known
           as "Shark" (<http://www.shark-linux.de/shark.html>).
 
+config ARCH_TCC_926
+        bool "Telechips TCC ARM926-based systems"
+        select CPU_ARM926T
+        select HAVE_CLK
+        select COMMON_CLKDEV
+        select GENERIC_CLOCKEVENTS
+        help
+          Support for Telechips TCC ARM926-based systems.
+
 config ARCH_LH7A40X
         bool "Sharp LH7A40X"
         select CPU_ARM922T
@@ -916,6 +926,8 @@ source "arch/arm/plat-s5p/Kconfig"
 
 source "arch/arm/plat-spear/Kconfig"
 
+source "arch/arm/plat-tcc/Kconfig"
+
 if ARCH_S3C2410
 source "arch/arm/mach-s3c2400/Kconfig"
 source "arch/arm/mach-s3c2410/Kconfig"
@@ -1051,6 +1063,32 @@ config ARM_ERRATA_460075
           ACTLR register. Note that setting specific bits in the ACTLR register
           may not be available in non-secure mode.
 
+config ARM_ERRATA_742230
+        bool "ARM errata: DMB operation may be faulty"
+        depends on CPU_V7 && SMP
+        help
+          This option enables the workaround for the 742230 Cortex-A9
+          (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
+          between two write operations may not ensure the correct visibility
+          ordering of the two writes. This workaround sets a specific bit in
+          the diagnostic register of the Cortex-A9 which causes the DMB
+          instruction to behave as a DSB, ensuring the correct behaviour of
+          the two writes.
+
+config ARM_ERRATA_742231
+        bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
+        depends on CPU_V7 && SMP
+        help
+          This option enables the workaround for the 742231 Cortex-A9
+          (r2p0..r2p2) erratum. Under certain conditions, specific to the
+          Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
+          accessing some data located in the same cache line, may get corrupted
+          data due to bad handling of the address hazard when the line gets
+          replaced from one of the CPUs at the same time as another CPU is
+          accessing it. This workaround sets specific bits in the diagnostic
+          register of the Cortex-A9 which reduces the linefill issuing
+          capabilities of the processor.
+
 config PL310_ERRATA_588369
         bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
         depends on CACHE_L2X0 && ARCH_OMAP4
@@ -1438,6 +1476,20 @@ config UACCESS_WITH_MEMCPY
           However, if the CPU data cache is using a write-allocate mode,
           this option is unlikely to provide any performance gain.
 
+config SECCOMP
+        bool
+        prompt "Enable seccomp to safely compute untrusted bytecode"
+        ---help---
+          This kernel feature is useful for number crunching applications
+          that may need to compute untrusted bytecode during their
+          execution. By using pipes or other transports made available to
+          the process as file descriptors supporting the read/write
+          syscalls, it's possible to isolate those applications in
+          their own address space using seccomp. Once seccomp is
+          enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
+          and the task is only allowed to execute a few safe syscalls
+          defined by each seccomp mode.
+
 config CC_STACKPROTECTOR
         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
         help
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 91344af75f39..c29fb382aeee 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -2,6 +2,20 @@ menu "Kernel hacking"
 
 source "lib/Kconfig.debug"
 
+config STRICT_DEVMEM
+        bool "Filter access to /dev/mem"
+        depends on MMU
+        ---help---
+          If this option is disabled, you allow userspace (root) access to all
+          of memory, including kernel and userspace memory. Accidental
+          access to this is obviously disastrous, but specific access can
+          be used by people debugging the kernel.
+
+          If this option is switched on, the /dev/mem file only allows
+          userspace access to memory mapped peripherals.
+
+          If in doubt, say Y.
+
 # RMK wants arm kernels compiled with frame pointers or stack unwinding.
 # If you know what you are doing and are willing to live without stack
 # traces, you can get a slightly smaller kernel by setting this option to
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 59c1ce858fc8..502255905c4e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -183,6 +183,7 @@ machine-$(CONFIG_ARCH_SHARK)		:= shark
 machine-$(CONFIG_ARCH_SHMOBILE)         := shmobile
 machine-$(CONFIG_ARCH_STMP378X)         := stmp378x
 machine-$(CONFIG_ARCH_STMP37XX)         := stmp37xx
+machine-$(CONFIG_ARCH_TCC8K)            := tcc8k
 machine-$(CONFIG_ARCH_TEGRA)            := tegra
 machine-$(CONFIG_ARCH_U300)             := u300
 machine-$(CONFIG_ARCH_U8500)            := ux500
@@ -202,6 +203,7 @@ plat-$(CONFIG_ARCH_MXC)		:= mxc
 plat-$(CONFIG_ARCH_OMAP)        := omap
 plat-$(CONFIG_ARCH_S3C64XX)     := samsung
 plat-$(CONFIG_ARCH_STMP3XXX)    := stmp3xxx
+plat-$(CONFIG_ARCH_TCC_926)     := tcc
 plat-$(CONFIG_PLAT_IOP)         := iop
 plat-$(CONFIG_PLAT_NOMADIK)     := nomadik
 plat-$(CONFIG_PLAT_ORION)       := orion
@@ -245,13 +247,14 @@ ifeq ($(FASTFPE),$(wildcard $(FASTFPE)))
 FASTFPE_OBJ     :=$(FASTFPE)/
 endif
 
-# If we have a machine-specific directory, then include it in the build.
-core-y                          += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
-core-y                          += $(machdirs) $(platdirs)
 core-$(CONFIG_FPE_NWFPE)        += arch/arm/nwfpe/
 core-$(CONFIG_FPE_FASTFPE)      += $(FASTFPE_OBJ)
 core-$(CONFIG_VFP)              += arch/arm/vfp/
 
+# If we have a machine-specific directory, then include it in the build.
+core-y                          += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
+core-y                          += $(machdirs) $(platdirs)
+
 drivers-$(CONFIG_OPROFILE)      += arch/arm/oprofile/
 
 libs-y                          := arch/arm/lib/ $(libs-y)
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index b23f6bc46cfa..65a7c1c588a9 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -116,5 +116,5 @@ CFLAGS_font.o := -Dstatic=
 $(obj)/font.c: $(FONTC)
         $(call cmd,shipped)
 
-$(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile .config
+$(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile $(KCONFIG_CONFIG)
         @sed "$(SEDFLAGS)" < $< > $@
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index 7974baacafce..1bec96e85196 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -271,6 +271,14 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
                 ((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
 }
 
+int dma_set_coherent_mask(struct device *dev, u64 mask)
+{
+        if (mask >= PHYS_OFFSET + SZ_64M - 1)
+                return 0;
+
+        return -EIO;
+}
+
 int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
 {
         it8152_io.start = IT8152_IO_BASE + 0x12000;
diff --git a/arch/arm/configs/at91sam9g20ek_defconfig b/arch/arm/configs/at91sam9g20ek_defconfig
index f1bac70d6ce9..9e90e6d79297 100644
--- a/arch/arm/configs/at91sam9g20ek_defconfig
+++ b/arch/arm/configs/at91sam9g20ek_defconfig
@@ -13,6 +13,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G20=y
 CONFIG_MACH_AT91SAM9G20EK=y
+CONFIG_MACH_AT91SAM9G20EK_2MMC=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index ccc9c9959b82..2f7042813765 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -15,6 +15,7 @@ CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
 CONFIG_MACH_ESATA_SHEEVAPLUG=y
 CONFIG_MACH_GURUPLUG=y
+CONFIG_MACH_DOCKSTAR=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
 CONFIG_MACH_OPENRD_BASE=y
diff --git a/arch/arm/configs/mx27_defconfig b/arch/arm/configs/mx27_defconfig
index b2038b0e266f..813cfb366c18 100644
--- a/arch/arm/configs/mx27_defconfig
+++ b/arch/arm/configs/mx27_defconfig
@@ -21,8 +21,14 @@ CONFIG_ARCH_MX2=y
 CONFIG_MACH_MX27=y
 CONFIG_MACH_MX27ADS=y
 CONFIG_MACH_PCM038=y
+CONFIG_MACH_CPUIMX27=y
+CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y
+CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y
 CONFIG_MACH_MX27_3DS=y
+CONFIG_MACH_IMX27_VISSTRIM_M10=y
 CONFIG_MACH_IMX27LITE=y
+CONFIG_MACH_PCA100=y
+CONFIG_MACH_MXT_TD60=y
 CONFIG_MXC_IRQ_PRIOR=y
 CONFIG_MXC_PWM=y
 CONFIG_NO_HZ=y
@@ -76,7 +82,9 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=m
 # CONFIG_SERIO is not set
+CONFIG_SERIAL_8250=m
 CONFIG_SERIAL_IMX=y
 CONFIG_SERIAL_IMX_CONSOLE=y
 # CONFIG_LEGACY_PTYS is not set
@@ -85,19 +93,20 @@ CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_IMX=y
 CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
+CONFIG_SPI_IMX=y
 CONFIG_W1=y
 CONFIG_W1_MASTER_MXC=y
 CONFIG_W1_SLAVE_THERM=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_IMX=y
-# CONFIG_VGA_CONSOLE is not set
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FONTS=y
 CONFIG_FONT_8x8=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=m
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_ULPI=y
 CONFIG_MMC=y
 CONFIG_MMC_MXC=y
 CONFIG_RTC_CLASS=y
diff --git a/arch/arm/configs/mx31pdk_defconfig b/arch/arm/configs/mx31pdk_defconfig
deleted file mode 100644
index 2d29329749e4..000000000000
--- a/arch/arm/configs/mx31pdk_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-# CONFIG_COMPAT_BRK is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_MXC=y
-# CONFIG_MACH_MX31ADS is not set
-CONFIG_MACH_MX31_3DS=y
-CONFIG_AEABI=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_LRO is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-# CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig
index 161f907b611f..f0c339fd5d21 100644
--- a/arch/arm/configs/mx3_defconfig
+++ b/arch/arm/configs/mx3_defconfig
@@ -24,6 +24,7 @@ CONFIG_MACH_PCM043=y
 CONFIG_MACH_ARMADILLO5X0=y
 CONFIG_MACH_MX35_3DS=y
 CONFIG_MACH_KZM_ARM11_01=y
+CONFIG_MACH_EUKREA_CPUIMX35=y
 CONFIG_MXC_IRQ_PRIOR=y
 CONFIG_MXC_PWM=y
 CONFIG_NO_HZ=y
@@ -108,7 +109,6 @@ CONFIG_MMC=y
 CONFIG_MMC_MXC=y
 CONFIG_DMADEVICES=y
 # CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY=y
 CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_UBIFS_FS=y
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig
index a665ecbbe2bc..163cfee7644c 100644
--- a/arch/arm/configs/mx51_defconfig
+++ b/arch/arm/configs/mx51_defconfig
@@ -15,6 +15,8 @@ CONFIG_MODULE_SRCVERSION_ALL=y
 CONFIG_ARCH_MXC=y
 CONFIG_ARCH_MX5=y
 CONFIG_MACH_MX51_BABBAGE=y
+CONFIG_MACH_MX51_3DS=y
+CONFIG_MACH_EUKREA_CPUIMX51=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT_VOLUNTARY=y
@@ -69,7 +71,6 @@ CONFIG_REALTEK_PHY=y
 CONFIG_NATIONAL_PHY=y
 CONFIG_STE10XP=y
 CONFIG_LSI_ET1011C_PHY=y
-CONFIG_FIXED_PHY=y
 CONFIG_MDIO_BITBANG=y
 CONFIG_MDIO_GPIO=y
 CONFIG_NET_ETHERNET=y
@@ -100,7 +101,6 @@ CONFIG_I2C_ALGOPCF=m
 CONFIG_I2C_ALGOPCA=m
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
@@ -117,13 +117,11 @@ CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 CONFIG_EXT2_FS_SECURITY=y
 CONFIG_EXT3_FS=y
-CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
 CONFIG_EXT3_FS_POSIX_ACL=y
 CONFIG_EXT3_FS_SECURITY=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
-CONFIG_INOTIFY=y
 CONFIG_QUOTA=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
@@ -136,6 +134,7 @@ CONFIG_ZISOFS=y
 CONFIG_UDF_FS=m
 CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
 CONFIG_CONFIGFS_FS=m
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -151,7 +150,6 @@ CONFIG_NLS_UTF8=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
@@ -159,7 +157,6 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_ARM_UNWIND is not set
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
-CONFIG_KEYS=y
 CONFIG_SECURITYFS=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_LZO=y
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 5747a8baa413..8bb66bca2e3e 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -127,4 +127,8 @@ struct mm_struct;
 extern unsigned long arch_randomize_brk(struct mm_struct *mm);
 #define arch_randomize_brk arch_randomize_brk
 
+extern int vectors_user_mapping(void);
+#define arch_setup_additional_pages(bprm, uses_interp) vectors_user_mapping()
+#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
+
 #endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 1261b1f928d9..815efa2d4e07 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -294,6 +294,7 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 extern int valid_phys_addr_range(unsigned long addr, size_t size);
 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
+extern int devmem_is_allowed(unsigned long pfn);
 #endif
 
 /*
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index a0b3cac0547c..71605d9f8e42 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -18,7 +18,6 @@
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
 #include <asm/proc-fns.h>
-#include <asm-generic/mm_hooks.h>
 
 void __check_kvm_seq(struct mm_struct *mm);
 
@@ -134,4 +133,32 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 #define deactivate_mm(tsk,mm)   do { } while (0)
 #define activate_mm(prev,next)  switch_mm(prev, next, NULL)
 
+/*
+ * We are inserting a "fake" vma for the user-accessible vector page so
+ * gdb and friends can get to it through ptrace and /proc/<pid>/mem.
+ * But we also want to remove it before the generic code gets to see it
+ * during process exit or the unmapping of it would  cause total havoc.
+ * (the macro is used as remove_vma() is static to mm/mmap.c)
+ */
+#define arch_exit_mmap(mm) \
+do { \
+        struct vm_area_struct *high_vma = find_vma(mm, 0xffff0000); \
+        if (high_vma) { \
+                BUG_ON(high_vma->vm_next);  /* it should be last */ \
+                if (high_vma->vm_prev) \
+                        high_vma->vm_prev->vm_next = NULL; \
+                else \
+                        mm->mmap = NULL; \
+                rb_erase(&high_vma->vm_rb, &mm->mm_rb); \
+                mm->mmap_cache = NULL; \
+                mm->map_count--; \
+                remove_vma(high_vma); \
+        } \
+} while (0)
+
+static inline void arch_dup_mmap(struct mm_struct *oldmm,
+                                 struct mm_struct *mm)
+{
+}
+
 #endif
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index ab68cf1ef80f..e90b167ea848 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -317,6 +317,10 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 #define pgprot_dmacoherent(prot) \
         __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_BUFFERABLE)
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+struct file;
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                                     unsigned long size, pgprot_t vma_prot);
 #else
 #define pgprot_dmacoherent(prot) \
         __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_UNCACHED)
diff --git a/arch/arm/include/asm/seccomp.h b/arch/arm/include/asm/seccomp.h
new file mode 100644
index 000000000000..52b156b341f5
--- /dev/null
+++ b/arch/arm/include/asm/seccomp.h
@@ -0,0 +1,11 @@
+#ifndef _ASM_ARM_SECCOMP_H
+#define _ASM_ARM_SECCOMP_H
+
+#include <linux/unistd.h>
+
+#define __NR_seccomp_read __NR_read
+#define __NR_seccomp_write __NR_write
+#define __NR_seccomp_exit __NR_exit
+#define __NR_seccomp_sigreturn __NR_rt_sigreturn
+
+#endif /* _ASM_ARM_SECCOMP_H */
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 763e29fa8530..7b5cc8dae06e 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -144,6 +144,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
 #define TIF_MEMDIE              18      /* is terminating due to OOM killer */
 #define TIF_FREEZE              19
 #define TIF_RESTORE_SIGMASK     20
+#define TIF_SECCOMP             21
 
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
@@ -153,6 +154,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
 #define _TIF_USING_IWMMXT       (1 << TIF_USING_IWMMXT)
 #define _TIF_FREEZE             (1 << TIF_FREEZE)
 #define _TIF_RESTORE_SIGMASK    (1 << TIF_RESTORE_SIGMASK)
+#define _TIF_SECCOMP            (1 << TIF_SECCOMP)
 
 /*
  * Change these and you break ASM code in entry-common.S
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 1b560825e1cf..0385a8207b67 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -48,6 +48,8 @@ work_pending:
         beq     no_work_pending
         mov     r0, sp                          @ 'regs'
         mov     r2, why                         @ 'syscall'
+        tst     r1, #_TIF_SIGPENDING            @ delivering a signal?
+        movne   why, #0                         @ prevent further restarts
         bl      do_notify_resume
         b       ret_slow_syscall                @ Check work again
 
@@ -293,7 +295,6 @@ ENTRY(vector_swi)
 
         get_thread_info tsk
         adr     tbl, sys_call_table             @ load syscall table pointer
-        ldr     ip, [tsk, #TI_FLAGS]            @ check for syscall tracing
 
 #if defined(CONFIG_OABI_COMPAT)
         /*
@@ -310,8 +311,20 @@ ENTRY(vector_swi)
         eor     scno, scno, #__NR_SYSCALL_BASE  @ check OS number
 #endif
 
+        ldr     r10, [tsk, #TI_FLAGS]           @ check for syscall tracing
         stmdb   sp!, {r4, r5}                   @ push fifth and sixth args
-        tst     ip, #_TIF_SYSCALL_TRACE         @ are we tracing syscalls?
+
+#ifdef CONFIG_SECCOMP
+        tst     r10, #_TIF_SECCOMP
+        beq     1f
+        mov     r0, scno
+        bl      __secure_computing      
+        add     r0, sp, #S_R0 + S_OFF           @ pointer to regs
+        ldmia   r0, {r0 - r3}                   @ have to reload r0 - r3
+1:
+#endif
+
+        tst     r10, #_TIF_SYSCALL_TRACE                @ are we tracing syscalls?
         bne     __sys_trace
 
         cmp     scno, #NR_syscalls              @ check upper syscall limit
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 401e38be1f78..66ac9c926200 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -458,3 +458,24 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
         unsigned long range_end = mm->brk + 0x02000000;
         return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
 }
+
+/*
+ * The vectors page is always readable from user space for the
+ * atomic helpers and the signal restart code.  Let's declare a mapping
+ * for it so it is visible through ptrace and /proc/<pid>/mem.
+ */
+
+int vectors_user_mapping(void)
+{
+        struct mm_struct *mm = current->mm;
+        return install_special_mapping(mm, 0xffff0000, PAGE_SIZE,
+                                       VM_READ | VM_EXEC |
+                                       VM_MAYREAD | VM_MAYEXEC |
+                                       VM_ALWAYSDUMP | VM_RESERVED,
+                                       NULL);
+}
+
+const char *arch_vma_name(struct vm_area_struct *vma)
+{
+        return (vma->vm_start == 0xffff0000) ? "[vectors]" : NULL;
+}
diff --git a/arch/arm/mach-aaec2000/include/mach/vmalloc.h b/arch/arm/mach-aaec2000/include/mach/vmalloc.h
index 551f68f666bf..cff4e0a996ce 100644
--- a/arch/arm/mach-aaec2000/include/mach/vmalloc.h
+++ b/arch/arm/mach-aaec2000/include/mach/vmalloc.h
@@ -11,6 +11,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END             (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END             0xd0000000
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 939bccd70569..bbd5efa65099 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -33,6 +33,7 @@ config ARCH_AT91SAM9260
         select HAVE_AT91_USART3
         select HAVE_AT91_USART4
         select HAVE_AT91_USART5
+        select HAVE_NET_MACB
 
 config ARCH_AT91SAM9261
         bool "AT91SAM9261"
@@ -51,6 +52,7 @@ config ARCH_AT91SAM9263
         select CPU_ARM926T
         select GENERIC_CLOCKEVENTS
         select HAVE_FB_ATMEL
+        select HAVE_NET_MACB
 
 config ARCH_AT91SAM9RL
         bool "AT91SAM9RL"
@@ -66,6 +68,7 @@ config ARCH_AT91SAM9G20
         select HAVE_AT91_USART3
         select HAVE_AT91_USART4
         select HAVE_AT91_USART5
+        select HAVE_NET_MACB
 
 config ARCH_AT91SAM9G45
         bool "AT91SAM9G45"
@@ -73,6 +76,7 @@ config ARCH_AT91SAM9G45
         select GENERIC_CLOCKEVENTS
         select HAVE_AT91_USART3
         select HAVE_FB_ATMEL
+        select HAVE_NET_MACB
 
 config ARCH_AT91CAP9
         bool "AT91CAP9"
@@ -338,6 +342,7 @@ config MACH_AT91SAM9G20EK
           that embeds only one SD/MMC slot.
 
 config MACH_AT91SAM9G20EK_2MMC
+        depends on MACH_AT91SAM9G20EK
         bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots"
         select HAVE_NAND_ATMEL_BUSWIDTH_16
         help
@@ -383,8 +388,8 @@ if ARCH_AT91SAM9G45
 
 comment "AT91SAM9G45 Board Type"
 
-config MACH_AT91SAM9G45EKES
-        bool "Atmel AT91SAM9G45-EKES Evaluation Kit"
+config MACH_AT91SAM9M10G45EK
+        bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
         select HAVE_NAND_ATMEL_BUSWIDTH_16
         help
           Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit.
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index ca2ac003f41f..3a07a3696441 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -61,7 +61,6 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK)	+= board-sam9rlek.o
 
 # AT91SAM9G20 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
-obj-$(CONFIG_MACH_AT91SAM9G20EK_2MMC) += board-sam9g20ek-2slot-mmc.o
 obj-$(CONFIG_MACH_CPU9G20)      += board-cpu9krea.o
 obj-$(CONFIG_MACH_STAMP9G20)    += board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)    += board-stamp9g20.o
@@ -70,7 +69,7 @@ obj-$(CONFIG_MACH_PORTUXG20)	+= board-stamp9g20.o
 obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
 
 # AT91SAM9G45 board-specific support
-obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
+obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
 
 # AT91CAP9 board-specific support
 obj-$(CONFIG_MACH_AT91CAP9ADK)  += board-cap9adk.o
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 5e71ccd5e7d3..1276babf84d5 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -426,7 +426,7 @@ static struct i2c_gpio_platform_data pdata_i2c0 = {
         .sda_is_open_drain      = 1,
         .scl_pin                = AT91_PIN_PA21,
         .scl_is_open_drain      = 1,
-        .udelay                 = 2,            /* ~100 kHz */
+        .udelay                 = 5,            /* ~100 kHz */
 };
 
 static struct platform_device at91sam9g45_twi0_device = {
@@ -440,7 +440,7 @@ static struct i2c_gpio_platform_data pdata_i2c1 = {
         .sda_is_open_drain      = 1,
         .scl_pin                = AT91_PIN_PB11,
         .scl_is_open_drain      = 1,
-        .udelay                 = 2,            /* ~100 kHz */
+        .udelay                 = 5,            /* ~100 kHz */
 };
 
 static struct platform_device at91sam9g45_twi1_device = {
diff --git a/arch/arm/mach-at91/board-at572d940hf_ek.c b/arch/arm/mach-at91/board-at572d940hf_ek.c
index 5daff277f53e..46651623f208 100644
--- a/arch/arm/mach-at91/board-at572d940hf_ek.c
+++ b/arch/arm/mach-at91/board-at572d940hf_ek.c
@@ -216,7 +216,7 @@ static struct atmel_nand_data __initdata eb_nand_data = {
 /*      .rdy_pin        = AT91_PIN_PC16, */
         .enable_pin     = AT91_PIN_PA15,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
         .bus_width_16   = 1,
 #else
         .bus_width_16   = 0,
diff --git a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
deleted file mode 100644
index c49f5c003ee1..000000000000
--- a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2008 Atmel
- *  Copyright (C) 2009 Rob Emanuele
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/at73c213.h>
-#include <linux/clk.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/consumer.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <mach/board.h>
-#include <mach/gpio.h>
-#include <mach/at91sam9_smc.h>
-
-#include "sam9_smc.h"
-#include "generic.h"
-
-
-static void __init ek_map_io(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91sam9260_initialize(18432000);
-
-        /* DGBU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-
-        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
-
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
-}
-
-static void __init ek_init_irq(void)
-{
-        at91sam9260_init_interrupts(NULL);
-}
-
-
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata ek_usbh_data = {
-        .ports          = 2,
-};
-
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata ek_udc_data = {
-        .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
-};
-
-
-/*
- * SPI devices.
- */
-static struct spi_board_info ek_spi_devices[] = {
-#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91))
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 1,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
-        {       /* DataFlash card */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#endif
-#endif
-};
-
-
-/*
- * MACB Ethernet device
- */
-static struct at91_eth_data __initdata ek_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PB0,
-        .is_rmii        = 1,
-};
-
-
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata ek_nand_partition[] = {
-        {
-                .name   = "Bootstrap",
-                .offset = 0,
-                .size   = 4 * SZ_1M,
-        },
-        {
-                .name   = "Partition 1",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 60 * SZ_1M,
-        },
-        {
-                .name   = "Partition 2",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-
-static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
-{
-        *num_partitions = ARRAY_SIZE(ek_nand_partition);
-        return ek_nand_partition;
-}
-
-/* det_pin is not connected */
-static struct atmel_nand_data __initdata ek_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .rdy_pin        = AT91_PIN_PC13,
-        .enable_pin     = AT91_PIN_PC14,
-        .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
-        .bus_width_16   = 1,
-#else
-        .bus_width_16   = 0,
-#endif
-};
-
-static struct sam9_smc_config __initdata ek_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 2,
-
-        .ncs_read_pulse         = 4,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 4,
-        .nwe_pulse              = 4,
-
-        .read_cycle             = 7,
-        .write_cycle            = 7,
-
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-        .tdf_cycles             = 3,
-};
-
-static void __init ek_add_device_nand(void)
-{
-        /* setup bus-width (8 or 16) */
-        if (ek_nand_data.bus_width_16)
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
-        else
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
-
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
-
-        at91_add_device_nand(&ek_nand_data);
-}
-
-
-/*
- * MCI (SD/MMC)
- * wp_pin is not connected
- */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
-static struct mci_platform_data __initdata ek_mmc_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PC2,
-                .wp_pin         = -ENODEV,
-        },
-        .slot[1] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PC9,
-                .wp_pin         = -ENODEV,
-        },
-
-};
-#else
-static struct at91_mmc_data __initdata ek_mmc_data = {
-        .slot_b         = 1,    /* Only one slot so use slot B */
-        .wire4          = 1,
-        .det_pin        = AT91_PIN_PC9,
-};
-#endif
-
-/*
- * LEDs
- */
-static struct gpio_led ek_leds[] = {
-        {       /* "bottom" led, green, userled1 to be defined */
-                .name                   = "ds5",
-                .gpio                   = AT91_PIN_PB8,
-                .active_low             = 1,
-                .default_trigger        = "none",
-        },
-        {       /* "power" led, yellow */
-                .name                   = "ds1",
-                .gpio                   = AT91_PIN_PB9,
-                .default_trigger        = "heartbeat",
-        }
-};
-
-#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
-static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
-        REGULATOR_SUPPLY("AVDD", "0-001b"),
-        REGULATOR_SUPPLY("HPVDD", "0-001b"),
-        REGULATOR_SUPPLY("DBVDD", "0-001b"),
-        REGULATOR_SUPPLY("DCVDD", "0-001b"),
-};
-
-static struct regulator_init_data ek_avdd_reg_init_data = {
-        .constraints    = {
-                .name   = "3V3",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .consumer_supplies = ek_audio_consumer_supplies,
-        .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
-};
-
-static struct fixed_voltage_config ek_vdd_pdata = {
-        .supply_name    = "board-3V3",
-        .microvolts     = 3300000,
-        .gpio           = -EINVAL,
-        .enabled_at_boot = 0,
-        .init_data      = &ek_avdd_reg_init_data,
-};
-static struct platform_device ek_voltage_regulator = {
-        .name           = "reg-fixed-voltage",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &ek_vdd_pdata,
-        },
-};
-static void __init ek_add_regulators(void)
-{
-        platform_device_register(&ek_voltage_regulator);
-}
-#else
-static void __init ek_add_regulators(void) {}
-#endif
-
-static struct i2c_board_info __initdata ek_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("24c512", 0x50),
-        },
-};
-
-
-static void __init ek_board_init(void)
-{
-        /* Serial */
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&ek_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&ek_udc_data);
-        /* SPI */
-        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
-        /* NAND */
-        ek_add_device_nand();
-        /* Ethernet */
-        at91_add_device_eth(&ek_macb_data);
-        /* Regulators */
-        ek_add_regulators();
-        /* MMC */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
-        at91_add_device_mci(0, &ek_mmc_data);
-#else
-        at91_add_device_mmc(0, &ek_mmc_data);
-#endif
-        /* I2C */
-        at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
-        /* LEDs */
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-        /* PCK0 provides MCLK to the WM8731 */
-        at91_set_B_periph(AT91_PIN_PC1, 0);
-        /* SSC (for WM8731) */
-        at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
-}
-
-MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
-        /* Maintainer: Rob Emanuele */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
-        .timer          = &at91sam926x_timer,
-        .map_io         = ek_map_io,
-        .init_irq       = ek_init_irq,
-        .init_machine   = ek_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 6ea9808b8868..b463e340c4a0 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -47,6 +47,18 @@
 #include "sam9_smc.h"
 #include "generic.h"
 
+/*
+ * board revision encoding
+ * bit 0:
+ *      0 => 1 sd/mmc slot
+ *      1 => 2 sd/mmc slots connectors (board from revision C)
+ */
+#define HAVE_2MMC       (1 << 0)
+static int inline ek_have_2mmc(void)
+{
+        return machine_is_at91sam9g20ek_2mmc() || (system_rev & HAVE_2MMC);
+}
+
 
 static void __init ek_map_io(void)
 {
@@ -94,7 +106,7 @@ static struct at91_udc_data __initdata ek_udc_data = {
  * SPI devices.
  */
 static struct spi_board_info ek_spi_devices[] = {
-#if !defined(CONFIG_MMC_AT91)
+#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91))
         {       /* DataFlash chip */
                 .modalias       = "mtd_dataflash",
                 .chip_select    = 1,
@@ -121,6 +133,13 @@ static struct at91_eth_data __initdata ek_macb_data = {
         .is_rmii        = 1,
 };
 
+static void __init ek_add_device_macb(void)
+{
+        if (ek_have_2mmc())
+                ek_macb_data.phy_irq_pin = AT91_PIN_PB0;
+
+        at91_add_device_eth(&ek_macb_data);
+}
 
 /*
  * NAND flash
@@ -198,13 +217,36 @@ static void __init ek_add_device_nand(void)
 
 /*
  * MCI (SD/MMC)
- * det_pin, wp_pin and vcc_pin are not connected
+ * wp_pin and vcc_pin are not connected
  */
+#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
+static struct mci_platform_data __initdata ek_mmc_data = {
+        .slot[1] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PC9,
+        },
+
+};
+#else
 static struct at91_mmc_data __initdata ek_mmc_data = {
-        .slot_b         = 1,
+        .slot_b         = 1,    /* Only one slot so use slot B */
         .wire4          = 1,
+        .det_pin        = AT91_PIN_PC9,
 };
+#endif
 
+static void __init ek_add_device_mmc(void)
+{
+#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
+        if (ek_have_2mmc()) {
+                ek_mmc_data.slot[0].bus_width = 4;
+                ek_mmc_data.slot[0].detect_pin = AT91_PIN_PC2;
+        }
+        at91_add_device_mci(0, &ek_mmc_data);
+#else
+        at91_add_device_mmc(0, &ek_mmc_data);
+#endif
+}
 
 /*
  * LEDs
@@ -223,6 +265,15 @@ static struct gpio_led ek_leds[] = {
         }
 };
 
+static void __init ek_add_device_gpio_leds(void)
+{
+        if (ek_have_2mmc()) {
+                ek_leds[0].gpio = AT91_PIN_PB8;
+                ek_leds[1].gpio = AT91_PIN_PB9;
+        }
+
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+}
 
 /*
  * GPIO Buttons
@@ -336,15 +387,15 @@ static void __init ek_board_init(void)
         /* NAND */
         ek_add_device_nand();
         /* Ethernet */
-        at91_add_device_eth(&ek_macb_data);
+        ek_add_device_macb();
         /* Regulators */
         ek_add_regulators();
         /* MMC */
-        at91_add_device_mmc(0, &ek_mmc_data);
+        ek_add_device_mmc();
         /* I2C */
         at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
         /* LEDs */
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        ek_add_device_gpio_leds();
         /* Push Buttons */
         ek_add_device_buttons();
         /* PCK0 provides MCLK to the WM8731 */
@@ -363,3 +414,14 @@ MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
         .init_irq       = ek_init_irq,
         .init_machine   = ek_board_init,
 MACHINE_END
+
+MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
+        /* Maintainer: Atmel */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index ee800595594d..ae0e0843e5f5 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -135,7 +135,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PC8,
         .enable_pin     = AT91_PIN_PC14,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
         .bus_width_16   = 1,
 #else
         .bus_width_16   = 0,
@@ -399,7 +399,7 @@ static void __init ek_board_init(void)
         at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
 }
 
-MACHINE_START(AT91SAM9G45EKES, "Atmel AT91SAM9G45-EKES")
+MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
         /* Maintainer: Atmel */
         .phys_io        = AT91_BASE_SYS,
         .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
index d34cdb8abdca..063ac44a0204 100644
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -52,4 +52,10 @@
 #define AT91_DBGU_CIDR  (AT91_SF + 0)   /* CIDR in PS segment */
 #define AT91_DBGU_EXID  (AT91_SF + 4)   /* EXID in PS segment */
 
+/*
+ * Support defines for the simple Power Controller module.
+ */
+#define AT91_PS_CR      (AT91_PS + 0)   /* PS Control register */
+#define AT91_PS_CR_CPU  (1 << 0)        /* CPU clock disable bit */
+
 #endif /* AT91X40_H */
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h
index c80e090b3670..bfbb612265d6 100644
--- a/arch/arm/mach-at91/include/mach/system.h
+++ b/arch/arm/mach-at91/include/mach/system.h
@@ -33,7 +33,11 @@ static inline void arch_idle(void)
          * Disable the processor clock.  The processor will be automatically
          * re-enabled by an interrupt or by a reset.
          */
+#ifdef AT91_PS
+        at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
+#else
         at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+#endif
 #else
         /*
          * Set the processor (CP15) into 'Wait for Interrupt' mode.
diff --git a/arch/arm/mach-bcmring/include/mach/vmalloc.h b/arch/arm/mach-bcmring/include/mach/vmalloc.h
index 35e2ead8395c..3db3a09fd398 100644
--- a/arch/arm/mach-bcmring/include/mach/vmalloc.h
+++ b/arch/arm/mach-bcmring/include/mach/vmalloc.h
@@ -22,4 +22,4 @@
  * 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles
  * larger physical memory designs better.
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x30000000)
+#define VMALLOC_END       0xf0000000
diff --git a/arch/arm/mach-clps711x/include/mach/vmalloc.h b/arch/arm/mach-clps711x/include/mach/vmalloc.h
index ea6cc7beff28..30b3a287ed88 100644
--- a/arch/arm/mach-clps711x/include/mach/vmalloc.h
+++ b/arch/arm/mach-clps711x/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 3d996b659ff4..9be261beae7d 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -769,8 +769,7 @@ static struct map_desc dm355_io_desc[] = {
                 .virtual        = SRAM_VIRT,
                 .pfn            = __phys_to_pfn(0x00010000),
                 .length         = SZ_32K,
-                /* MT_MEMORY_NONCACHED requires supersection alignment */
-                .type           = MT_DEVICE,
+                .type           = MT_MEMORY_NONCACHED,
         },
 };
 
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 6b6f4c643709..7781e35daec3 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -969,8 +969,7 @@ static struct map_desc dm365_io_desc[] = {
                 .virtual        = SRAM_VIRT,
                 .pfn            = __phys_to_pfn(0x00010000),
                 .length         = SZ_32K,
-                /* MT_MEMORY_NONCACHED requires supersection alignment */
-                .type           = MT_DEVICE,
+                .type           = MT_MEMORY_NONCACHED,
         },
 };
 
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 40fec315c99a..5e5b0a7831fb 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -653,8 +653,7 @@ static struct map_desc dm644x_io_desc[] = {
                 .virtual        = SRAM_VIRT,
                 .pfn            = __phys_to_pfn(0x00008000),
                 .length         = SZ_16K,
-                /* MT_MEMORY_NONCACHED requires supersection alignment */
-                .type           = MT_DEVICE,
+                .type           = MT_MEMORY_NONCACHED,
         },
 };
 
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index e4a3df1872ac..26e8a9c7f50b 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -737,8 +737,7 @@ static struct map_desc dm646x_io_desc[] = {
                 .virtual        = SRAM_VIRT,
                 .pfn            = __phys_to_pfn(0x00010000),
                 .length         = SZ_32K,
-                /* MT_MEMORY_NONCACHED requires supersection alignment */
-                .type           = MT_DEVICE,
+                .type           = MT_MEMORY_NONCACHED,
         },
 };
 
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
index 3b3e4721ce2e..eb4936ff90ad 100644
--- a/arch/arm/mach-dove/include/mach/io.h
+++ b/arch/arm/mach-dove/include/mach/io.h
@@ -13,8 +13,8 @@
 
 #define IO_SPACE_LIMIT          0xffffffff
 
-#define __io(a)  ((void __iomem *)(((a) - DOVE_PCIE0_IO_PHYS_BASE) +\
-                                   DOVE_PCIE0_IO_VIRT_BASE))
-#define __mem_pci(a)            (a)
+#define __io(a)         ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \
+                                                 DOVE_PCIE0_IO_VIRT_BASE))
+#define __mem_pci(a)    (a)
 
 #endif
diff --git a/arch/arm/mach-ebsa110/include/mach/vmalloc.h b/arch/arm/mach-ebsa110/include/mach/vmalloc.h
index 9b44c19e95ec..60bde56fba4c 100644
--- a/arch/arm/mach-ebsa110/include/mach/vmalloc.h
+++ b/arch/arm/mach-ebsa110/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x1f000000)
+#define VMALLOC_END       0xdf000000
diff --git a/arch/arm/mach-footbridge/include/mach/vmalloc.h b/arch/arm/mach-footbridge/include/mach/vmalloc.h
index d0958d860a3c..0ffbb7c85e59 100644
--- a/arch/arm/mach-footbridge/include/mach/vmalloc.h
+++ b/arch/arm/mach-footbridge/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
  */
 
 
-#define VMALLOC_END       (PAGE_OFFSET + 0x30000000)
+#define VMALLOC_END       0xf0000000
diff --git a/arch/arm/mach-h720x/include/mach/vmalloc.h b/arch/arm/mach-h720x/include/mach/vmalloc.h
index ff1460d6841b..a45915b88756 100644
--- a/arch/arm/mach-h720x/include/mach/vmalloc.h
+++ b/arch/arm/mach-h720x/include/mach/vmalloc.h
@@ -5,6 +5,6 @@
 #ifndef __ARCH_ARM_VMALLOC_H
 #define __ARCH_ARM_VMALLOC_H
 
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
 
 #endif
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index c5c0369bb481..9b45f1f523fa 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -146,8 +146,8 @@ choice
         default MACH_EUKREA_MBIMX27_BASEBOARD
 
 config MACH_EUKREA_MBIMX27_BASEBOARD
-        prompt "Eukrea MBIMX27 development board"
-        bool
+        bool "Eukrea MBIMX27 development board"
+        select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_SPI_IMX
         help
@@ -163,6 +163,15 @@ config MACH_MX27_3DS
           Include support for MX27PDK platform. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_IMX27_VISSTRIM_M10
+        bool "Vista Silicon i.MX27 Visstrim_m10"
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Include support for Visstrim_m10 platform and its different variants.
+          This includes specific configurations for the board and its
+          peripherals.
+
 config MACH_IMX27LITE
         bool "LogicPD MX27 LITEKIT platform"
         select IMX_HAVE_PLATFORM_IMX_UART
@@ -173,6 +182,7 @@ config MACH_IMX27LITE
 config MACH_PCA100
         bool "Phytec phyCARD-s (pca100)"
         select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SPI_IMX
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 46a9fdfbbd15..5582692bb176 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
 obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
 obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
 obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
+obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
 obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
 obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c
index c05096c38301..daca30b2d5b1 100644
--- a/arch/arm/mach-imx/clock-imx1.c
+++ b/arch/arm/mach-imx/clock-imx1.c
@@ -592,7 +592,7 @@ static struct clk_lookup lookups[] __initdata = {
         _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
         _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
-        _REGISTER_CLOCK("spi_imx.0", NULL, spi_clk)
+        _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk)
         _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
         _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
diff --git a/arch/arm/mach-imx/clock-imx21.c b/arch/arm/mach-imx/clock-imx21.c
index bb419ef4d133..cf15ea516a72 100644
--- a/arch/arm/mach-imx/clock-imx21.c
+++ b/arch/arm/mach-imx/clock-imx21.c
@@ -1172,9 +1172,9 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0])
         _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0])
         _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1])
-        _REGISTER_CLOCK(NULL, "cspi1", cspi_clk[0])
-        _REGISTER_CLOCK(NULL, "cspi2", cspi_clk[1])
-        _REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2])
+        _REGISTER_CLOCK("imx21-cspi.0", NULL, cspi_clk[0])
+        _REGISTER_CLOCK("imx21-cspi.1", NULL, cspi_clk[1])
+        _REGISTER_CLOCK("imx21-cspi.2", NULL, cspi_clk[2])
         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0])
         _REGISTER_CLOCK(NULL, "csi", csi_clk[0])
         _REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0])
diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
index 5a1aa15c8a16..98a25bada783 100644
--- a/arch/arm/mach-imx/clock-imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -594,27 +594,27 @@ DEFINE_CLOCK(uart2_clk1,   0, PCCR1, 30, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(uart1_clk1,   0, PCCR1, 31, NULL, NULL, &ipg_clk);
 
 /* Clocks we cannot directly gate, but drivers need their rates */
-DEFINE_CLOCK(cspi1_clk,    0, 0,      0, NULL, &cspi1_clk1, &per2_clk);
-DEFINE_CLOCK(cspi2_clk,    1, 0,      0, NULL, &cspi2_clk1, &per2_clk);
-DEFINE_CLOCK(cspi3_clk,    2, 0,      0, NULL, &cspi13_clk1, &per2_clk);
-DEFINE_CLOCK(sdhc1_clk,    0, 0,      0, NULL, &sdhc1_clk1, &per2_clk);
-DEFINE_CLOCK(sdhc2_clk,    1, 0,      0, NULL, &sdhc2_clk1, &per2_clk);
-DEFINE_CLOCK(sdhc3_clk,    2, 0,      0, NULL, &sdhc3_clk1, &per2_clk);
-DEFINE_CLOCK(pwm_clk,      0, 0,      0, NULL, &pwm_clk1, &per1_clk);
-DEFINE_CLOCK(gpt1_clk,     0, 0,      0, NULL, &gpt1_clk1, &per1_clk);
-DEFINE_CLOCK(gpt2_clk,     1, 0,      0, NULL, &gpt2_clk1, &per1_clk);
-DEFINE_CLOCK(gpt3_clk,     2, 0,      0, NULL, &gpt3_clk1, &per1_clk);
-DEFINE_CLOCK(gpt4_clk,     3, 0,      0, NULL, &gpt4_clk1, &per1_clk);
-DEFINE_CLOCK(gpt5_clk,     4, 0,      0, NULL, &gpt5_clk1, &per1_clk);
-DEFINE_CLOCK(gpt6_clk,     5, 0,      0, NULL, &gpt6_clk1, &per1_clk);
-DEFINE_CLOCK(uart1_clk,    0, 0,      0, NULL, &uart1_clk1, &per1_clk);
-DEFINE_CLOCK(uart2_clk,    1, 0,      0, NULL, &uart2_clk1, &per1_clk);
-DEFINE_CLOCK(uart3_clk,    2, 0,      0, NULL, &uart3_clk1, &per1_clk);
-DEFINE_CLOCK(uart4_clk,    3, 0,      0, NULL, &uart4_clk1, &per1_clk);
-DEFINE_CLOCK(uart5_clk,    4, 0,      0, NULL, &uart5_clk1, &per1_clk);
-DEFINE_CLOCK(uart6_clk,    5, 0,      0, NULL, &uart6_clk1, &per1_clk);
-DEFINE_CLOCK1(lcdc_clk,    0, 0,      0, parent, &lcdc_clk1, &per3_clk);
-DEFINE_CLOCK1(csi_clk,     0, 0,      0, parent, &csi_clk1, &per4_clk);
+DEFINE_CLOCK(cspi1_clk,    0, NULL,   0, NULL, &cspi1_clk1, &per2_clk);
+DEFINE_CLOCK(cspi2_clk,    1, NULL,   0, NULL, &cspi2_clk1, &per2_clk);
+DEFINE_CLOCK(cspi3_clk,    2, NULL,   0, NULL, &cspi13_clk1, &per2_clk);
+DEFINE_CLOCK(sdhc1_clk,    0, NULL,   0, NULL, &sdhc1_clk1, &per2_clk);
+DEFINE_CLOCK(sdhc2_clk,    1, NULL,   0, NULL, &sdhc2_clk1, &per2_clk);
+DEFINE_CLOCK(sdhc3_clk,    2, NULL,   0, NULL, &sdhc3_clk1, &per2_clk);
+DEFINE_CLOCK(pwm_clk,      0, NULL,   0, NULL, &pwm_clk1, &per1_clk);
+DEFINE_CLOCK(gpt1_clk,     0, NULL,   0, NULL, &gpt1_clk1, &per1_clk);
+DEFINE_CLOCK(gpt2_clk,     1, NULL,   0, NULL, &gpt2_clk1, &per1_clk);
+DEFINE_CLOCK(gpt3_clk,     2, NULL,   0, NULL, &gpt3_clk1, &per1_clk);
+DEFINE_CLOCK(gpt4_clk,     3, NULL,   0, NULL, &gpt4_clk1, &per1_clk);
+DEFINE_CLOCK(gpt5_clk,     4, NULL,   0, NULL, &gpt5_clk1, &per1_clk);
+DEFINE_CLOCK(gpt6_clk,     5, NULL,   0, NULL, &gpt6_clk1, &per1_clk);
+DEFINE_CLOCK(uart1_clk,    0, NULL,   0, NULL, &uart1_clk1, &per1_clk);
+DEFINE_CLOCK(uart2_clk,    1, NULL,   0, NULL, &uart2_clk1, &per1_clk);
+DEFINE_CLOCK(uart3_clk,    2, NULL,   0, NULL, &uart3_clk1, &per1_clk);
+DEFINE_CLOCK(uart4_clk,    3, NULL,   0, NULL, &uart4_clk1, &per1_clk);
+DEFINE_CLOCK(uart5_clk,    4, NULL,   0, NULL, &uart5_clk1, &per1_clk);
+DEFINE_CLOCK(uart6_clk,    5, NULL,   0, NULL, &uart6_clk1, &per1_clk);
+DEFINE_CLOCK1(lcdc_clk,    0, NULL,   0, parent, &lcdc_clk1, &per3_clk);
+DEFINE_CLOCK1(csi_clk,     0, NULL,   0, parent, &csi_clk1, &per4_clk);
 
 #define _REGISTER_CLOCK(d, n, c) \
         { \
@@ -640,9 +640,9 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
         _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
         _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
-        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
-        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
-        _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
+        _REGISTER_CLOCK("imx27-cspi.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("imx27-cspi.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("imx27-cspi.2", NULL, cspi3_clk)
         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
         _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
index a8d94f078196..81979486218e 100644
--- a/arch/arm/mach-imx/devices-imx1.h
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -9,10 +9,12 @@
 #include <mach/mx1.h>
 #include <mach/devices-common.h>
 
-#define imx1_add_i2c_imx(pdata)         \
-        imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata)
+extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst;
+#define imx1_add_imx_i2c(pdata)         \
+        imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
 
-#define imx1_add_imx_uart0(pdata)       \
-        imx_add_imx_uart_3irq(0, MX1_UART1_BASE_ADDR, 0xd0, MX1_INT_UART1RX, MX1_INT_UART1TX, MX1_INT_UART1RTS, pdata)
-#define imx1_add_imx_uart1(pdata)       \
-        imx_add_imx_uart_3irq(0, MX1_UART2_BASE_ADDR, 0xd0, MX1_INT_UART2RX, MX1_INT_UART2TX, MX1_INT_UART2RTS, pdata)
+extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst;
+#define imx1_add_imx_uart(id, pdata)    \
+        imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
+#define imx1_add_imx_uart0(pdata)       imx1_add_imx_uart(0, pdata)
+#define imx1_add_imx_uart1(pdata)       imx1_add_imx_uart(1, pdata)
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index 42788e99d127..d189039749b0 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -9,22 +9,28 @@
 #include <mach/mx21.h>
 #include <mach/devices-common.h>
 
-#define imx21_add_i2c_imx(pdata)        \
-        imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata)
+extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst;
+#define imx21_add_imx_i2c(pdata)        \
+        imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
 
-#define imx21_add_imx_uart0(pdata)      \
-        imx_add_imx_uart_1irq(0, MX21_UART1_BASE_ADDR, SZ_4K, MX21_INT_UART1, pdata)
-#define imx21_add_imx_uart1(pdata)      \
-        imx_add_imx_uart_1irq(1, MX21_UART2_BASE_ADDR, SZ_4K, MX21_INT_UART2, pdata)
-#define imx21_add_imx_uart2(pdata)      \
-        imx_add_imx_uart_1irq(2, MX21_UART3_BASE_ADDR, SZ_4K, MX21_INT_UART3, pdata)
-#define imx21_add_imx_uart3(pdata)      \
-        imx_add_imx_uart_1irq(3, MX21_UART4_BASE_ADDR, SZ_4K, MX21_INT_UART4, pdata)
+extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst;
+#define imx21_add_imx_ssi(id, pdata)    \
+        imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
 
+extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
+#define imx21_add_imx_uart(id, pdata)   \
+        imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata)
+#define imx21_add_imx_uart0(pdata)      imx21_add_imx_uart(0, pdata)
+#define imx21_add_imx_uart1(pdata)      imx21_add_imx_uart(1, pdata)
+#define imx21_add_imx_uart2(pdata)      imx21_add_imx_uart(2, pdata)
+#define imx21_add_imx_uart3(pdata)      imx21_add_imx_uart(3, pdata)
+
+extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst;
 #define imx21_add_mxc_nand(pdata)       \
-        imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata)
+        imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
 
-#define imx21_add_spi_imx0(pdata)       \
-        imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata)
-#define imx21_add_spi_imx1(pdata)       \
-        imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata)
+extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst;
+#define imx21_add_cspi(id, pdata)       \
+        imx_add_spi_imx(&imx21_cspi_data[id], pdata)
+#define imx21_add_spi_imx0(pdata)       imx21_add_cspi(0, pdata)
+#define imx21_add_spi_imx1(pdata)       imx21_add_cspi(1, pdata)
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 65e7bb7ec2e8..7011690364f2 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -9,30 +9,35 @@
 #include <mach/mx27.h>
 #include <mach/devices-common.h>
 
-#define imx27_add_i2c_imx0(pdata)       \
-        imx_add_imx_i2c(0, MX27_I2C1_BASE_ADDR, SZ_4K, MX27_INT_I2C1, pdata)
-#define imx27_add_i2c_imx1(pdata)       \
-        imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata)
+extern const struct imx_fec_data imx27_fec_data __initconst;
+#define imx27_add_fec(pdata)    \
+        imx_add_fec(&imx27_fec_data, pdata)
 
-#define imx27_add_imx_uart0(pdata)      \
-        imx_add_imx_uart_1irq(0, MX27_UART1_BASE_ADDR, SZ_4K, MX27_INT_UART1, pdata)
-#define imx27_add_imx_uart1(pdata)      \
-        imx_add_imx_uart_1irq(1, MX27_UART2_BASE_ADDR, SZ_4K, MX27_INT_UART2, pdata)
-#define imx27_add_imx_uart2(pdata)      \
-        imx_add_imx_uart_1irq(2, MX27_UART3_BASE_ADDR, SZ_4K, MX27_INT_UART3, pdata)
-#define imx27_add_imx_uart3(pdata)      \
-        imx_add_imx_uart_1irq(3, MX27_UART4_BASE_ADDR, SZ_4K, MX27_INT_UART4, pdata)
-#define imx27_add_imx_uart4(pdata)      \
-        imx_add_imx_uart_1irq(4, MX27_UART5_BASE_ADDR, SZ_4K, MX27_INT_UART5, pdata)
-#define imx27_add_imx_uart5(pdata)      \
-        imx_add_imx_uart_1irq(5, MX27_UART6_BASE_ADDR, SZ_4K, MX27_INT_UART6, pdata)
+extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst;
+#define imx27_add_imx_i2c(id, pdata)    \
+        imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
 
+extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst;
+#define imx27_add_imx_ssi(id, pdata)    \
+        imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
+
+extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
+#define imx27_add_imx_uart(id, pdata)   \
+        imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata)
+#define imx27_add_imx_uart0(pdata)      imx27_add_imx_uart(0, pdata)
+#define imx27_add_imx_uart1(pdata)      imx27_add_imx_uart(1, pdata)
+#define imx27_add_imx_uart2(pdata)      imx27_add_imx_uart(2, pdata)
+#define imx27_add_imx_uart3(pdata)      imx27_add_imx_uart(3, pdata)
+#define imx27_add_imx_uart4(pdata)      imx27_add_imx_uart(4, pdata)
+#define imx27_add_imx_uart5(pdata)      imx27_add_imx_uart(5, pdata)
+
+extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst;
 #define imx27_add_mxc_nand(pdata)       \
-        imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata)
+        imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
 
-#define imx27_add_spi_imx0(pdata)       \
-        imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata)
-#define imx27_add_spi_imx1(pdata)       \
-        imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata)
-#define imx27_add_spi_imx2(pdata)       \
-        imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata)
+extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst;
+#define imx27_add_cspi(id, pdata)       \
+        imx_add_spi_imx(&imx27_cspi_data[id], pdata)
+#define imx27_add_spi_imx0(pdata)       imx27_add_cspi(0, pdata)
+#define imx27_add_spi_imx1(pdata)       imx27_add_cspi(1, pdata)
+#define imx27_add_spi_imx2(pdata)       imx27_add_cspi(2, pdata)
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index 9c271a752b84..fba5047de8b1 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -314,27 +314,6 @@ struct platform_device mxc_fb_device = {
         },
 };
 
-#ifdef CONFIG_MACH_MX27
-static struct resource mxc_fec_resources[] = {
-        {
-                .start = MX27_FEC_BASE_ADDR,
-                .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX27_INT_FEC,
-                .end = MX27_INT_FEC,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_fec_device = {
-        .name = "fec",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_fec_resources),
-        .resource = mxc_fec_resources,
-};
-#endif
-
 static struct resource mxc_pwm_resources[] = {
         {
                 .start = MX2x_PWM_BASE_ADDR,
@@ -480,41 +459,6 @@ struct platform_device mxc_usbh2 = {
 };
 #endif
 
-#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix)                      \
-        {                                                               \
-                .name = _name,                                          \
-                .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix,       \
-                .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix,         \
-                .flags = IORESOURCE_DMA,                                \
-        }
-
-#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq)                   \
-        static struct resource imx_ssi_resources ## n[] = {             \
-                {                                                       \
-                        .start = MX2x_SSI ## ssin ## _BASE_ADDR,        \
-                        .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f,   \
-                        .flags = IORESOURCE_MEM,                        \
-                }, {                                                    \
-                        .start = MX2x_INT_SSI1,                         \
-                        .end = MX2x_INT_SSI1,                           \
-                        .flags = IORESOURCE_IRQ,                        \
-                },                                                      \
-                DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0),                \
-                DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0),                \
-                DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1),                \
-                DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1),                \
-        };                                                              \
-                                                                        \
-        struct platform_device imx_ssi_device ## n = {                  \
-                .name = "imx-ssi",                                      \
-                .id = n,                                                \
-                .num_resources = ARRAY_SIZE(imx_ssi_resources ## n),    \
-                .resource = imx_ssi_resources ## n,                     \
-        }
-
-DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
-DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
-
 /* GPIO port description */
 #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq)                          \
         {                                                               \
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
index efd4527506a5..807f02a031c9 100644
--- a/arch/arm/mach-imx/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -16,7 +16,6 @@ extern struct platform_device mxc_gpt5;
 extern struct platform_device mxc_wdt;
 extern struct platform_device mxc_w1_master_device;
 extern struct platform_device mxc_fb_device;
-extern struct platform_device mxc_fec_device;
 extern struct platform_device mxc_pwm_device;
 extern struct platform_device mxc_sdhc_device0;
 extern struct platform_device mxc_sdhc_device1;
@@ -26,7 +25,5 @@ extern struct platform_device mxc_otg_host;
 extern struct platform_device mxc_usbh1;
 extern struct platform_device mxc_usbh2;
 extern struct platform_device mx21_usbhc_device;
-extern struct platform_device imx_ssi_device0;
-extern struct platform_device imx_ssi_device1;
 extern struct platform_device imx_kpp_device;
 #endif
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 4edc5f439201..026263c665ca 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -36,13 +36,12 @@
 #include <mach/hardware.h>
 #include <mach/mmc.h>
 #include <mach/spi.h>
-#include <mach/ssi.h>
 #include <mach/audmux.h>
 
 #include "devices-imx27.h"
 #include "devices.h"
 
-static int eukrea_mbimx27_pins[] = {
+static const int eukrea_mbimx27_pins[] __initconst = {
         /* UART2 */
         PE3_PF_UART2_CTS,
         PE4_PF_UART2_RTS,
@@ -311,7 +310,8 @@ static struct imxmmc_platform_data sdhc_pdata = {
         .dat3_card_detect = 1,
 };
 
-struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata = {
+static const
+struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata __initconst = {
         .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
 };
 
@@ -357,7 +357,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
         i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
                                 ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
 
-        mxc_register_device(&imx_ssi_device0, &eukrea_mbimx27_ssi_pdata);
+        imx27_add_imx_ssi(0, &eukrea_mbimx27_ssi_pdata);
 
 #if defined(CONFIG_TOUCHSCREEN_ADS7846) \
         || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 339150ab0ea5..28f73a1c79f7 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -46,7 +46,7 @@
 #include "devices-imx27.h"
 #include "devices.h"
 
-static int eukrea_cpuimx27_pins[] = {
+static const int eukrea_cpuimx27_pins[] __initconst = {
         /* UART1 */
         PE12_PF_UART1_TXD,
         PE13_PF_UART1_RXD,
@@ -157,7 +157,6 @@ cpuimx27_nand_board_info __initconst = {
 
 static struct platform_device *platform_devices[] __initdata = {
         &eukrea_cpuimx27_nor_mtd_device,
-        &mxc_fec_device,
         &mxc_wdt,
         &mxc_w1_master_device,
 };
@@ -259,8 +258,9 @@ static void __init eukrea_cpuimx27_init(void)
         i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
                                 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
 
-        imx27_add_i2c_imx1(&cpuimx27_i2c1_data);
+        imx27_add_imx_i2c(1, &cpuimx27_i2c1_data);
 
+        imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
 #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
new file mode 100644
index 000000000000..a0d78faa08e8
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -0,0 +1,263 @@
+/*
+ * mach-imx27_visstrim_m10.c
+ *
+ * Copyright 2010  Javier Martin <javier.martin@vista-silicon.com>
+ *
+ * Based on mach-pcm038.c, mach-pca100.c, mach-mx27ads.c and others.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/i2c.h>
+#include <linux/i2c/pca953x.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/mmc.h>
+#include <mach/iomux.h>
+#include <mach/mxc_ehci.h>
+
+#include "devices-imx27.h"
+#include "devices.h"
+
+#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
+#define SDHC1_IRQ IRQ_GPIOB(25)
+
+static const int visstrim_m10_pins[] __initconst = {
+        /* UART1 (console) */
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS,
+        /* FEC */
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_RX_CLK,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN,
+        /* SDHC1 */
+        PE18_PF_SD1_D0,
+        PE19_PF_SD1_D1,
+        PE20_PF_SD1_D2,
+        PE21_PF_SD1_D3,
+        PE22_PF_SD1_CMD,
+        PE23_PF_SD1_CLK,
+        /* Both I2Cs */
+        PD17_PF_I2C_DATA,
+        PD18_PF_I2C_CLK,
+        PC5_PF_I2C2_SDA,
+        PC6_PF_I2C2_SCL,
+        /* USB OTG */
+        OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
+        PC9_PF_USBOTG_DATA0,
+        PC11_PF_USBOTG_DATA1,
+        PC10_PF_USBOTG_DATA2,
+        PC13_PF_USBOTG_DATA3,
+        PC12_PF_USBOTG_DATA4,
+        PC7_PF_USBOTG_DATA5,
+        PC8_PF_USBOTG_DATA6,
+        PE25_PF_USBOTG_DATA7,
+        PE24_PF_USBOTG_CLK,
+        PE2_PF_USBOTG_DIR,
+        PE0_PF_USBOTG_NXT,
+        PE1_PF_USBOTG_STP,
+        PB23_PF_USB_PWR,
+        PB24_PF_USB_OC,
+};
+
+/* GPIOs used as events for applications */
+static struct gpio_keys_button visstrim_gpio_keys[] = {
+        {
+                .type   = EV_KEY,
+                .code   = KEY_RESTART,
+                .gpio   = (GPIO_PORTC + 15),
+                .desc   = "Default config",
+                .active_low = 0,
+                .wakeup = 1,
+        },
+        {
+                .type   = EV_KEY,
+                .code   = KEY_RECORD,
+                .gpio   = (GPIO_PORTF + 14),
+                .desc   = "Record",
+                .active_low = 0,
+                .wakeup = 1,
+        },
+        {
+                .type   = EV_KEY,
+                .code   = KEY_STOP,
+                .gpio   = (GPIO_PORTF + 13),
+                .desc   = "Stop",
+                .active_low = 0,
+                .wakeup = 1,
+        }
+};
+
+static struct gpio_keys_platform_data visstrim_gpio_keys_platform_data = {
+        .buttons        = visstrim_gpio_keys,
+        .nbuttons       = ARRAY_SIZE(visstrim_gpio_keys),
+};
+
+static struct platform_device visstrim_gpio_keys_device = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &visstrim_gpio_keys_platform_data,
+        },
+};
+
+/* Visstrim_SM10 has a microSD slot connected to sdhc1 */
+static int visstrim_m10_sdhc1_init(struct device *dev,
+                irq_handler_t detect_irq, void *data)
+{
+        int ret;
+
+        ret = request_irq(SDHC1_IRQ, detect_irq, IRQF_TRIGGER_FALLING,
+                                "mmc-detect", data);
+        return ret;
+}
+
+static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
+{
+        free_irq(SDHC1_IRQ, data);
+}
+
+static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = {
+        .init = visstrim_m10_sdhc1_init,
+        .exit = visstrim_m10_sdhc1_exit,
+};
+
+/* Visstrim_SM10 NOR flash */
+static struct physmap_flash_data visstrim_m10_flash_data = {
+        .width = 2,
+};
+
+static struct resource visstrim_m10_flash_resource = {
+        .start = 0xc0000000,
+        .end = 0xc0000000 + SZ_64M - 1,
+        .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device visstrim_m10_nor_mtd_device = {
+        .name = "physmap-flash",
+        .id = 0,
+        .dev = {
+                .platform_data = &visstrim_m10_flash_data,
+        },
+        .num_resources = 1,
+        .resource = &visstrim_m10_flash_resource,
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+        &visstrim_gpio_keys_device,
+        &visstrim_m10_nor_mtd_device,
+};
+
+/* Visstrim_M10 uses UART0 as console */
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+/* I2C */
+static const struct imxi2c_platform_data visstrim_m10_i2c_data __initconst = {
+        .bitrate = 100000,
+};
+
+static struct pca953x_platform_data visstrim_m10_pca9555_pdata = {
+        .gpio_base = 240, /* After MX27 internal GPIOs */
+        .invert = 0,
+};
+
+static struct i2c_board_info visstrim_m10_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("pca9555", 0x20),
+                .platform_data = &visstrim_m10_pca9555_pdata,
+        },
+};
+
+/* USB OTG */
+static int otg_phy_init(struct platform_device *pdev)
+{
+        gpio_set_value(OTG_PHY_CS_GPIO, 0);
+        return 0;
+}
+
+static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = {
+        .init = otg_phy_init,
+        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
+};
+
+static void __init visstrim_m10_board_init(void)
+{
+        int ret;
+
+        ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins,
+                        ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10");
+        if (ret)
+                pr_err("Failed to setup pins (%d)\n", ret);
+
+        imx27_add_imx_uart0(&uart_pdata);
+
+        i2c_register_board_info(0, visstrim_m10_i2c_devices,
+                                ARRAY_SIZE(visstrim_m10_i2c_devices));
+        imx27_add_imx_i2c(0, &visstrim_m10_i2c_data);
+        imx27_add_imx_i2c(1, &visstrim_m10_i2c_data);
+        mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata);
+        mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata);
+        imx27_add_fec(NULL);
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+
+static void __init visstrim_m10_timer_init(void)
+{
+        mx27_clocks_init((unsigned long)25000000);
+}
+
+static struct sys_timer visstrim_m10_timer = {
+        .init   = visstrim_m10_timer_init,
+};
+
+MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
+        .phys_io        = MX27_AIPI_BASE_ADDR,
+        .io_pg_offst    = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = MX27_PHYS_OFFSET + 0x100,
+        .map_io         = mx27_map_io,
+        .init_irq       = mx27_init_irq,
+        .init_machine   = visstrim_m10_board_init,
+        .timer          = &visstrim_m10_timer,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index 22a2b5d91213..60d4d0ac4939 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -27,7 +27,7 @@
 #include "devices-imx27.h"
 #include "devices.h"
 
-static unsigned int mx27lite_pins[] = {
+static const int mx27lite_pins[] __initconst = {
         /* UART1 */
         PE12_PF_UART1_TXD,
         PE13_PF_UART1_RXD,
@@ -58,16 +58,12 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct platform_device *platform_devices[] __initdata = {
-        &mxc_fec_device,
-};
-
 static void __init mx27lite_init(void)
 {
         mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
                 "imx27lite");
         imx27_add_imx_uart0(&uart_pdata);
-        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        imx27_add_fec(NULL);
 }
 
 static void __init mx27lite_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 77a760cfadc0..85e2877572b5 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -32,7 +32,7 @@
 #include "devices-imx1.h"
 #include "devices.h"
 
-static int mx1ads_pins[] = {
+static const int mx1ads_pins[] __initconst = {
         /* UART1 */
         PC9_PF_UART1_CTS,
         PC10_PF_UART1_RTS,
@@ -131,7 +131,7 @@ static void __init mx1ads_init(void)
         i2c_register_board_info(0, mx1ads_i2c_devices,
                                 ARRAY_SIZE(mx1ads_i2c_devices));
 
-        imx1_add_i2c_imx(&mx1ads_i2c_data);
+        imx1_add_imx_i2c(&mx1ads_i2c_data);
 }
 
 static void __init mx1ads_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 96d7f8189f32..7f021e6f6acd 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -67,7 +67,7 @@
 #define MX21ADS_IO_LED4_ON      0x4000
 #define MX21ADS_IO_LED3_ON      0x8000
 
-static unsigned int mx21ads_pins[] = {
+static const int mx21ads_pins[] __initconst = {
 
         /* CS8900A */
         (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index e66ffaa1c26c..a69dba252658 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -33,7 +33,7 @@
 #include "devices-imx27.h"
 #include "devices.h"
 
-static unsigned int mx27pdk_pins[] = {
+static const int mx27pdk_pins[] __initconst = {
         /* UART1 */
         PE12_PF_UART1_TXD,
         PE13_PF_UART1_RXD,
@@ -64,10 +64,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct platform_device *platform_devices[] __initdata = {
-        &mxc_fec_device,
-};
-
 /*
  * Matrix keyboard
  */
@@ -94,7 +90,7 @@ static void __init mx27pdk_init(void)
         mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
                 "mx27pdk");
         imx27_add_imx_uart0(&uart_pdata);
-        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        imx27_add_fec(NULL);
         mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
 }
 
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 9c77da98a10e..ffb39a42f240 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -66,7 +66,7 @@
 /* to determine the correct external crystal reference */
 #define CKIH_27MHZ_BIT_SET      (1 << 3)
 
-static unsigned int mx27ads_pins[] = {
+static const int mx27ads_pins[] __initconst = {
         /* UART0 */
         PE12_PF_UART1_TXD,
         PE13_PF_UART1_RXD,
@@ -284,7 +284,6 @@ static struct imxmmc_platform_data sdhc2_pdata = {
 
 static struct platform_device *platform_devices[] __initdata = {
         &mx27ads_nor_mtd_device,
-        &mxc_fec_device,
         &mxc_w1_master_device,
 };
 
@@ -308,11 +307,12 @@ static void __init mx27ads_board_init(void)
         /* only the i2c master 1 is used on this CPU card */
         i2c_register_board_info(1, mx27ads_i2c_devices,
                                 ARRAY_SIZE(mx27ads_i2c_devices));
-        imx27_add_i2c_imx1(&mx27ads_i2c1_data);
+        imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
         mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
         mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
         mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
 
+        imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index a3a1e452d4c5..f4c397dec794 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -37,7 +37,7 @@
 #include "devices-imx27.h"
 #include "devices.h"
 
-static unsigned int mxt_td60_pins[] __initdata = {
+static const int mxt_td60_pins[] __initconst = {
         /* UART0 */
         PE12_PF_UART1_TXD,
         PE13_PF_UART1_RXD,
@@ -231,10 +231,6 @@ static struct imxmmc_platform_data sdhc1_pdata = {
         .exit = mxt_td60_sdhc1_exit,
 };
 
-static struct platform_device *platform_devices[] __initdata = {
-        &mxc_fec_device,
-};
-
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -255,12 +251,11 @@ static void __init mxt_td60_board_init(void)
         i2c_register_board_info(1, mxt_td60_i2c2_devices,
                                 ARRAY_SIZE(mxt_td60_i2c2_devices));
 
-        imx27_add_i2c_imx0(&mxt_td60_i2c0_data);
-        imx27_add_i2c_imx1(&mxt_td60_i2c1_data);
+        imx27_add_imx_i2c(0, &mxt_td60_i2c0_data);
+        imx27_add_imx_i2c(1, &mxt_td60_i2c1_data);
         mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
         mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
-
-        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        imx27_add_fec(NULL);
 }
 
 static void __init mxt_td60_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 23c9e1f37b9c..223c31c48db6 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -38,7 +38,6 @@
 #include <mach/iomux-mx27.h>
 #include <asm/mach/time.h>
 #include <mach/audmux.h>
-#include <mach/ssi.h>
 #include <mach/mxc_nand.h>
 #include <mach/irqs.h>
 #include <mach/mmc.h>
@@ -55,7 +54,7 @@
 #define SPI1_SS1 (GPIO_PORTD + 27)
 #define SD2_CD (GPIO_PORTC + 29)
 
-static int pca100_pins[] = {
+static const int pca100_pins[] __initconst = {
         /* UART1 */
         PE12_PF_UART1_TXD,
         PE13_PF_UART1_RXD,
@@ -174,7 +173,6 @@ pca100_nand_board_info __initconst = {
 
 static struct platform_device *platform_devices[] __initdata = {
         &mxc_w1_master_device,
-        &mxc_fec_device,
         &mxc_wdt,
 };
 
@@ -193,11 +191,9 @@ static struct i2c_board_info pca100_i2c_devices[] = {
                 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
                 .platform_data = &board_eeprom,
         }, {
-                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
-                .type = "pcf8563"
+                I2C_BOARD_INFO("pcf8563", 0x51),
         }, {
                 I2C_BOARD_INFO("lm75", 0x4a),
-                .type = "lm75"
         }
 };
 
@@ -252,7 +248,7 @@ static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
         msleep(2);
 }
 
-static struct imx_ssi_platform_data pca100_ssi_pdata = {
+static const struct imx_ssi_platform_data pca100_ssi_pdata __initconst = {
         .ac97_reset             = pca100_ac97_cold_reset,
         .ac97_warm_reset        = pca100_ac97_warm_reset,
         .flags                  = IMX_SSI_USE_AC97,
@@ -389,7 +385,7 @@ static void __init pca100_init(void)
         if (ret)
                 printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
 
-        mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata);
+        imx27_add_imx_ssi(0, &pca100_ssi_pdata);
 
         imx27_add_imx_uart0(&uart_pdata);
 
@@ -401,7 +397,7 @@ static void __init pca100_init(void)
         i2c_register_board_info(1, pca100_i2c_devices,
                                 ARRAY_SIZE(pca100_i2c_devices));
 
-        imx27_add_i2c_imx1(&pca100_i2c1_data);
+        imx27_add_imx_i2c(1, &pca100_i2c1_data);
 
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
         mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
@@ -436,6 +432,7 @@ static void __init pca100_init(void)
 
         mxc_register_device(&mxc_fb_device, &pca100_fb_data);
 
+        imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 9212e8f37001..b9888a8defc1 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -43,7 +43,7 @@
 #include "devices-imx27.h"
 #include "devices.h"
 
-static int pcm038_pins[] = {
+static const int pcm038_pins[] __initconst = {
         /* UART1 */
         PE12_PF_UART1_TXD,
         PE13_PF_UART1_RXD,
@@ -173,7 +173,6 @@ pcm038_nand_board_info __initconst = {
 static struct platform_device *platform_devices[] __initdata = {
         &pcm038_nor_mtd_device,
         &mxc_w1_master_device,
-        &mxc_fec_device,
         &pcm038_sram_mtd_device,
         &mxc_wdt,
 };
@@ -257,7 +256,7 @@ static struct regulator_init_data cam_data = {
         .consumer_supplies = cam_consumers,
 };
 
-struct mc13783_regulator_init_data pcm038_regulators[] = {
+static struct mc13783_regulator_init_data pcm038_regulators[] = {
         {
                 .id = MC13783_REGU_VCAM,
                 .init_data = &cam_data,
@@ -309,7 +308,7 @@ static void __init pcm038_init(void)
         i2c_register_board_info(1, pcm038_i2c_devices,
                                 ARRAY_SIZE(pcm038_i2c_devices));
 
-        imx27_add_i2c_imx1(&pcm038_i2c1_data);
+        imx27_add_imx_i2c(1, &pcm038_i2c1_data);
 
         /* PE18 for user-LED D40 */
         mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
@@ -325,6 +324,7 @@ static void __init pcm038_init(void)
 
         mxc_register_device(&mxc_usbh2, &usbh2_pdata);
 
+        imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
 #ifdef CONFIG_MACH_PCM970_BASEBOARD
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index 88bf0d1e26e6..fb2e5f3d37f6 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -95,7 +95,7 @@ static struct platform_device dm9000x_device = {
         }
 };
 
-static int mxc_uart1_pins[] = {
+static const int mxc_uart1_pins[] = {
         PC9_PF_UART1_CTS,
         PC10_PF_UART1_RTS,
         PC11_PF_UART1_TXD,
diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
index f490a406d57e..9110d9cca7a2 100644
--- a/arch/arm/mach-imx/pcm970-baseboard.c
+++ b/arch/arm/mach-imx/pcm970-baseboard.c
@@ -31,7 +31,7 @@
 
 #include "devices.h"
 
-static int pcm970_pins[] = {
+static const int pcm970_pins[] __initconst = {
         /* SDHC */
         PB4_PF_SD2_D0,
         PB5_PF_SD2_D1,
@@ -200,7 +200,7 @@ static struct resource pcm970_sja1000_resources[] = {
         },
 };
 
-struct sja1000_platform_data pcm970_sja1000_platform_data = {
+static struct sja1000_platform_data pcm970_sja1000_platform_data = {
         .osc_freq       = 16000000,
         .ocr            = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
         .cdr            = CDR_CBP,
diff --git a/arch/arm/mach-integrator/include/mach/vmalloc.h b/arch/arm/mach-integrator/include/mach/vmalloc.h
index e87ab0b37bdd..e056e7cf5645 100644
--- a/arch/arm/mach-integrator/include/mach/vmalloc.h
+++ b/arch/arm/mach-integrator/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 61cd4d64b985..24498a932ba6 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -503,6 +503,14 @@ struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
         return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys);
 }
 
+int dma_set_coherent_mask(struct device *dev, u64 mask)
+{
+        if (mask >= SZ_64M - 1)
+                return 0;
+
+        return -EIO;
+}
+
 EXPORT_SYMBOL(ixp4xx_pci_read);
 EXPORT_SYMBOL(ixp4xx_pci_write);
 
diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h
index f91ca6d4fbe8..8138371c406e 100644
--- a/arch/arm/mach-ixp4xx/include/mach/hardware.h
+++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h
@@ -26,6 +26,8 @@
 #define PCIBIOS_MAX_MEM         0x4BFFFFFF
 #endif
 
+#define ARCH_HAS_DMA_SET_COHERENT_MASK
+
 #define pcibios_assign_all_busses()     1
 
 /* Register locations and bits */
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index cc25501b57fa..34106335c728 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -58,6 +58,12 @@ config MACH_TS41X
           QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS
           devices.
 
+config MACH_DOCKSTAR
+        bool "Seagate FreeAgent DockStar"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Seagate FreeAgent DockStar.
+
 config MACH_OPENRD
         bool
 
@@ -100,6 +106,12 @@ config MACH_NETSPACE_MAX_V2
           Say 'Y' here if you want your kernel to support the
           LaCie Network Space Max v2 NAS.
 
+config MACH_D2NET_V2
+        bool "LaCie d2 Network v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie d2 Network v2 NAS.
+
 config MACH_NET2BIG_V2
         bool "LaCie 2Big Network v2 NAS Board"
         help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 295d7baa6ae1..5dcaa81a2ec3 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -7,14 +7,16 @@ obj-$(CONFIG_MACH_MV88F6281GTW_GE)	+= mv88f6281gtw_ge-setup.o
 obj-$(CONFIG_MACH_SHEEVAPLUG)           += sheevaplug-setup.o
 obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG)     += sheevaplug-setup.o
 obj-$(CONFIG_MACH_GURUPLUG)             += guruplug-setup.o
+obj-$(CONFIG_MACH_DOCKSTAR)             += dockstar-setup.o
 obj-$(CONFIG_MACH_TS219)                += ts219-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_TS41X)                += ts41x-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_OPENRD)               += openrd-setup.o
-obj-$(CONFIG_MACH_NETSPACE_V2)          += netspace_v2-setup.o
-obj-$(CONFIG_MACH_INETSPACE_V2)         += netspace_v2-setup.o
-obj-$(CONFIG_MACH_NETSPACE_MAX_V2)      += netspace_v2-setup.o
-obj-$(CONFIG_MACH_NET2BIG_V2)           += netxbig_v2-setup.o
-obj-$(CONFIG_MACH_NET5BIG_V2)           += netxbig_v2-setup.o
+obj-$(CONFIG_MACH_NETSPACE_V2)          += netspace_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_INETSPACE_V2)         += netspace_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_NETSPACE_MAX_V2)      += netspace_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_D2NET_V2)             += d2net_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_NET2BIG_V2)           += netxbig_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_NET5BIG_V2)           += netxbig_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_T5325)                += t5325-setup.o
 
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
new file mode 100644
index 000000000000..cd62d0f82a73
--- /dev/null
+++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c
@@ -0,0 +1,231 @@
+/*
+ * arch/arm/mach-kirkwood/d2net_v2-setup.c
+ *
+ * LaCie d2 Network Space v2 Board Setup
+ *
+ * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/input.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/leds.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include <mach/leds-ns2.h>
+#include "common.h"
+#include "mpp.h"
+#include "lacie_v2-common.h"
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+static struct mv643xx_eth_platform_data d2net_v2_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+
+static struct mv_sata_platform_data d2net_v2_sata_data = {
+        .n_ports        = 2,
+};
+
+/*****************************************************************************
+ * GPIO keys
+ ****************************************************************************/
+
+#define D2NET_V2_GPIO_PUSH_BUTTON          34
+#define D2NET_V2_GPIO_POWER_SWITCH_ON      13
+#define D2NET_V2_GPIO_POWER_SWITCH_OFF     15
+
+#define D2NET_V2_SWITCH_POWER_ON           0x1
+#define D2NET_V2_SWITCH_POWER_OFF          0x2
+
+static struct gpio_keys_button d2net_v2_buttons[] = {
+        [0] = {
+                .type           = EV_SW,
+                .code           = D2NET_V2_SWITCH_POWER_ON,
+                .gpio           = D2NET_V2_GPIO_POWER_SWITCH_ON,
+                .desc           = "Back power switch (on|auto)",
+                .active_low     = 0,
+        },
+        [1] = {
+                .type           = EV_SW,
+                .code           = D2NET_V2_SWITCH_POWER_OFF,
+                .gpio           = D2NET_V2_GPIO_POWER_SWITCH_OFF,
+                .desc           = "Back power switch (auto|off)",
+                .active_low     = 0,
+        },
+        [2] = {
+                .code           = KEY_POWER,
+                .gpio           = D2NET_V2_GPIO_PUSH_BUTTON,
+                .desc           = "Front Push Button",
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data d2net_v2_button_data = {
+        .buttons        = d2net_v2_buttons,
+        .nbuttons       = ARRAY_SIZE(d2net_v2_buttons),
+};
+
+static struct platform_device d2net_v2_gpio_buttons = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &d2net_v2_button_data,
+        },
+};
+
+/*****************************************************************************
+ * GPIO LEDs
+ ****************************************************************************/
+
+#define D2NET_V2_GPIO_RED_LED           12
+
+static struct gpio_led d2net_v2_gpio_led_pins[] = {
+        {
+                .name   = "d2net_v2:red:fail",
+                .gpio   = D2NET_V2_GPIO_RED_LED,
+        },
+};
+
+static struct gpio_led_platform_data d2net_v2_gpio_leds_data = {
+        .num_leds       = ARRAY_SIZE(d2net_v2_gpio_led_pins),
+        .leds           = d2net_v2_gpio_led_pins,
+};
+
+static struct platform_device d2net_v2_gpio_leds = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &d2net_v2_gpio_leds_data,
+        },
+};
+
+/*****************************************************************************
+ * Dual-GPIO CPLD LEDs
+ ****************************************************************************/
+
+#define D2NET_V2_GPIO_BLUE_LED_SLOW     29
+#define D2NET_V2_GPIO_BLUE_LED_CMD      30
+
+static struct ns2_led d2net_v2_led_pins[] = {
+        {
+                .name   = "d2net_v2:blue:sata",
+                .cmd    = D2NET_V2_GPIO_BLUE_LED_CMD,
+                .slow   = D2NET_V2_GPIO_BLUE_LED_SLOW,
+        },
+};
+
+static struct ns2_led_platform_data d2net_v2_leds_data = {
+        .num_leds       = ARRAY_SIZE(d2net_v2_led_pins),
+        .leds           = d2net_v2_led_pins,
+};
+
+static struct platform_device d2net_v2_leds = {
+        .name           = "leds-ns2",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &d2net_v2_leds_data,
+        },
+};
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+
+static unsigned int d2net_v2_mpp_config[] __initdata = {
+        MPP0_SPI_SCn,
+        MPP1_SPI_MOSI,
+        MPP2_SPI_SCK,
+        MPP3_SPI_MISO,
+        MPP6_SYSRST_OUTn,
+        MPP7_GPO,               /* Request power-off */
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
+        MPP10_UART0_TXD,
+        MPP11_UART0_RXD,
+        MPP12_GPO,              /* Red led */
+        MPP13_GPIO,             /* Rear power switch (on|auto) */
+        MPP14_GPIO,             /* USB fuse */
+        MPP15_GPIO,             /* Rear power switch (auto|off) */
+        MPP16_GPIO,             /* SATA 0 power */
+        MPP21_SATA0_ACTn,
+        MPP24_GPIO,             /* USB mode select */
+        MPP26_GPIO,             /* USB device vbus */
+        MPP28_GPIO,             /* USB enable host vbus */
+        MPP29_GPIO,             /* Blue led (slow register) */
+        MPP30_GPIO,             /* Blue led (command register) */
+        MPP34_GPIO,             /* Power button (1 = Released, 0 = Pushed) */
+        MPP35_GPIO,             /* Inhibit power-off */
+        0
+};
+
+#define D2NET_V2_GPIO_POWER_OFF         7
+
+static void d2net_v2_power_off(void)
+{
+        gpio_set_value(D2NET_V2_GPIO_POWER_OFF, 1);
+}
+
+static void __init d2net_v2_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        kirkwood_mpp_conf(d2net_v2_mpp_config);
+
+        lacie_v2_hdd_power_init(1);
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&d2net_v2_ge00_data);
+        kirkwood_sata_init(&d2net_v2_sata_data);
+        kirkwood_uart0_init();
+        lacie_v2_register_flash();
+        lacie_v2_register_i2c_devices();
+
+        platform_device_register(&d2net_v2_leds);
+        platform_device_register(&d2net_v2_gpio_leds);
+        platform_device_register(&d2net_v2_gpio_buttons);
+
+        if (gpio_request(D2NET_V2_GPIO_POWER_OFF, "power-off") == 0 &&
+            gpio_direction_output(D2NET_V2_GPIO_POWER_OFF, 0) == 0)
+                pm_power_off = d2net_v2_power_off;
+        else
+                pr_err("d2net_v2: failed to configure power-off GPIO\n");
+}
+
+MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = d2net_v2_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &lacie_v2_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
new file mode 100644
index 000000000000..a90475d5059c
--- /dev/null
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -0,0 +1,112 @@
+/*
+ * arch/arm/mach-kirkwood/dockstar-setup.c
+ *
+ * Seagate FreeAgent DockStar Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mtd_partition dockstar_nand_parts[] = {
+        {
+                .name = "u-boot",
+                .offset = 0,
+                .size = SZ_1M
+        }, {
+                .name = "uImage",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = SZ_4M
+        }, {
+                .name = "root",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = MTDPART_SIZ_FULL
+        },
+};
+
+static struct mv643xx_eth_platform_data dockstar_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static struct gpio_led dockstar_led_pins[] = {
+        {
+                .name                   = "dockstar:green:health",
+                .default_trigger        = "default-on",
+                .gpio                   = 46,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "dockstar:orange:misc",
+                .default_trigger        = "none",
+                .gpio                   = 47,
+                .active_low             = 1,
+        },
+};
+
+static struct gpio_led_platform_data dockstar_led_data = {
+        .leds           = dockstar_led_pins,
+        .num_leds       = ARRAY_SIZE(dockstar_led_pins),
+};
+
+static struct platform_device dockstar_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &dockstar_led_data,
+        }
+};
+
+static unsigned int dockstar_mpp_config[] __initdata = {
+        MPP29_GPIO,     /* USB Power Enable */
+        MPP46_GPIO,     /* LED green */
+        MPP47_GPIO,     /* LED orange */
+        0
+};
+
+static void __init dockstar_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+
+        /* setup gpio pin select */
+        kirkwood_mpp_conf(dockstar_mpp_config);
+
+        kirkwood_uart0_init();
+        kirkwood_nand_init(ARRAY_AND_SIZE(dockstar_nand_parts), 25);
+
+        if (gpio_request(29, "USB Power Enable") != 0 ||
+            gpio_direction_output(29, 1) != 0)
+                printk(KERN_ERR "can't set up GPIO 29 (USB Power Enable)\n");
+        kirkwood_ehci_init();
+
+        kirkwood_ge00_init(&dockstar_ge00_data);
+
+        platform_device_register(&dockstar_leds);
+}
+
+MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar")
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = dockstar_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 93fc2ec95e76..6e924b398919 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -38,7 +38,7 @@
 
 #define KIRKWOOD_PCIE1_IO_PHYS_BASE     0xf3000000
 #define KIRKWOOD_PCIE1_IO_VIRT_BASE     0xfef00000
-#define KIRKWOOD_PCIE1_IO_BUS_BASE      0x00000000
+#define KIRKWOOD_PCIE1_IO_BUS_BASE      0x00100000
 #define KIRKWOOD_PCIE1_IO_SIZE          SZ_1M
 
 #define KIRKWOOD_PCIE_IO_PHYS_BASE      0xf2000000
diff --git a/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h b/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
new file mode 100644
index 000000000000..24b536ebdf13
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
@@ -0,0 +1,55 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
+ *
+ * Platform data structure for netxbig LED driver
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_LEDS_NETXBIG_H
+#define __MACH_LEDS_NETXBIG_H
+
+struct netxbig_gpio_ext {
+        unsigned        *addr;
+        int             num_addr;
+        unsigned        *data;
+        int             num_data;
+        unsigned        enable;
+};
+
+enum netxbig_led_mode {
+        NETXBIG_LED_OFF,
+        NETXBIG_LED_ON,
+        NETXBIG_LED_SATA,
+        NETXBIG_LED_TIMER1,
+        NETXBIG_LED_TIMER2,
+        NETXBIG_LED_MODE_NUM,
+};
+
+#define NETXBIG_LED_INVALID_MODE NETXBIG_LED_MODE_NUM
+
+struct netxbig_led_timer {
+        unsigned long           delay_on;
+        unsigned long           delay_off;
+        enum netxbig_led_mode   mode;
+};
+
+struct netxbig_led {
+        const char      *name;
+        const char      *default_trigger;
+        int             mode_addr;
+        int             *mode_val;
+        int             bright_addr;
+};
+
+struct netxbig_led_platform_data {
+        struct netxbig_gpio_ext *gpio_ext;
+        struct netxbig_led_timer *timer;
+        int                     num_timer;
+        struct netxbig_led      *leds;
+        int                     num_leds;
+};
+
+#endif /* __MACH_LEDS_NETXBIG_H */
diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.c b/arch/arm/mach-kirkwood/lacie_v2-common.c
new file mode 100644
index 000000000000..d3ea1b6c8a02
--- /dev/null
+++ b/arch/arm/mach-kirkwood/lacie_v2-common.c
@@ -0,0 +1,127 @@
+/*
+ * arch/arm/mach-kirkwood/lacie_v2-common.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/gpio.h>
+#include <asm/mach/time.h>
+#include <mach/kirkwood.h>
+#include <mach/irqs.h>
+#include <plat/time.h>
+#include "common.h"
+
+/*****************************************************************************
+ * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
+ ****************************************************************************/
+
+static struct mtd_partition lacie_v2_flash_parts[] = {
+        {
+                .name = "u-boot",
+                .size = MTDPART_SIZ_FULL,
+                .offset = 0,
+                .mask_flags = MTD_WRITEABLE, /* force read-only */
+        },
+};
+
+static const struct flash_platform_data lacie_v2_flash = {
+        .type           = "mx25l4005a",
+        .name           = "spi_flash",
+        .parts          = lacie_v2_flash_parts,
+        .nr_parts       = ARRAY_SIZE(lacie_v2_flash_parts),
+};
+
+static struct spi_board_info __initdata lacie_v2_spi_slave_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &lacie_v2_flash,
+                .irq            = -1,
+                .max_speed_hz   = 20000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+
+void __init lacie_v2_register_flash(void)
+{
+        spi_register_board_info(lacie_v2_spi_slave_info,
+                                ARRAY_SIZE(lacie_v2_spi_slave_info));
+        kirkwood_spi_init();
+}
+
+/*****************************************************************************
+ * I2C devices
+ ****************************************************************************/
+
+static struct at24_platform_data at24c04 = {
+        .byte_len       = SZ_4K / 8,
+        .page_size      = 16,
+};
+
+/*
+ * i2c addr | chip         | description
+ * 0x50     | HT24LC04     | eeprom (512B)
+ */
+
+static struct i2c_board_info __initdata lacie_v2_i2c_info[] = {
+        {
+                I2C_BOARD_INFO("24c04", 0x50),
+                .platform_data  = &at24c04,
+        }
+};
+
+void __init lacie_v2_register_i2c_devices(void)
+{
+        kirkwood_i2c_init();
+        i2c_register_board_info(0, lacie_v2_i2c_info,
+                                ARRAY_SIZE(lacie_v2_i2c_info));
+}
+
+/*****************************************************************************
+ * Hard Disk power
+ ****************************************************************************/
+
+static int __initdata lacie_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 };
+
+void __init lacie_v2_hdd_power_init(int hdd_num)
+{
+        int i;
+        int err;
+
+        /* Power up all hard disks. */
+        for (i = 0; i < hdd_num; i++) {
+                err = gpio_request(lacie_v2_gpio_hdd_power[i], NULL);
+                if (err == 0) {
+                        err = gpio_direction_output(
+                                        lacie_v2_gpio_hdd_power[i], 1);
+                        /* Free the HDD power GPIOs. This allow user-space to
+                         * configure them via the gpiolib sysfs interface. */
+                        gpio_free(lacie_v2_gpio_hdd_power[i]);
+                }
+                if (err)
+                        pr_err("Failed to power up HDD%d\n", i + 1);
+        }
+}
+
+/*****************************************************************************
+ * Timer
+ ****************************************************************************/
+
+static void lacie_v2_timer_init(void)
+{
+        kirkwood_tclk = 166666667;
+        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
+}
+
+struct sys_timer lacie_v2_timer = {
+        .init = lacie_v2_timer_init,
+};
diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.h b/arch/arm/mach-kirkwood/lacie_v2-common.h
new file mode 100644
index 000000000000..af521315b87b
--- /dev/null
+++ b/arch/arm/mach-kirkwood/lacie_v2-common.h
@@ -0,0 +1,18 @@
+/*
+ * arch/arm/mach-kirkwood/lacie_v2-common.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_KIRKWOOD_LACIE_V2_COMMON_H
+#define __ARCH_KIRKWOOD_LACIE_V2_COMMON_H
+
+void lacie_v2_register_flash(void);
+void lacie_v2_register_i2c_devices(void);
+void lacie_v2_hdd_power_init(int hdd_num);
+
+extern struct sys_timer lacie_v2_timer;
+
+#endif
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index d26bf324738b..fed264d28f4a 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -24,56 +24,19 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/i2c.h>
-#include <linux/i2c/at24.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/time.h>
 #include <mach/kirkwood.h>
 #include <mach/leds-ns2.h>
-#include <plat/time.h>
 #include "common.h"
 #include "mpp.h"
-
-/*****************************************************************************
- * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
- ****************************************************************************/
-
-static struct mtd_partition netspace_v2_flash_parts[] = {
-        {
-                .name = "u-boot",
-                .size = MTDPART_SIZ_FULL,
-                .offset = 0,
-                .mask_flags = MTD_WRITEABLE, /* force read-only */
-        },
-};
-
-static const struct flash_platform_data netspace_v2_flash = {
-        .type           = "mx25l4005a",
-        .name           = "spi_flash",
-        .parts          = netspace_v2_flash_parts,
-        .nr_parts       = ARRAY_SIZE(netspace_v2_flash_parts),
-};
-
-static struct spi_board_info __initdata netspace_v2_spi_slave_info[] = {
-        {
-                .modalias       = "m25p80",
-                .platform_data  = &netspace_v2_flash,
-                .irq            = -1,
-                .max_speed_hz   = 20000000,
-                .bus_num        = 0,
-                .chip_select    = 0,
-        },
-};
+#include "lacie_v2-common.h"
 
 /*****************************************************************************
  * Ethernet
@@ -84,27 +47,6 @@ static struct mv643xx_eth_platform_data netspace_v2_ge00_data = {
 };
 
 /*****************************************************************************
- * I2C devices
- ****************************************************************************/
-
-static struct at24_platform_data at24c04 = {
-        .byte_len       = SZ_4K / 8,
-        .page_size      = 16,
-};
-
-/*
- * i2c addr | chip         | description
- * 0x50     | HT24LC04     | eeprom (512B)
- */
-
-static struct i2c_board_info __initdata netspace_v2_i2c_info[] = {
-        {
-                I2C_BOARD_INFO("24c04", 0x50),
-                .platform_data  = &at24c04,
-        }
-};
-
-/*****************************************************************************
  * SATA
  ****************************************************************************/
 
@@ -112,35 +54,6 @@ static struct mv_sata_platform_data netspace_v2_sata_data = {
         .n_ports        = 2,
 };
 
-#define NETSPACE_V2_GPIO_SATA0_POWER    16
-#define NETSPACE_V2_GPIO_SATA1_POWER    17
-
-static void __init netspace_v2_sata_power_init(void)
-{
-        int err;
-
-        err = gpio_request(NETSPACE_V2_GPIO_SATA0_POWER, "SATA0 power");
-        if (err == 0) {
-                err = gpio_direction_output(NETSPACE_V2_GPIO_SATA0_POWER, 1);
-                if (err)
-                        gpio_free(NETSPACE_V2_GPIO_SATA0_POWER);
-        }
-        if (err)
-                pr_err("netspace_v2: failed to setup SATA0 power\n");
-
-        if (machine_is_netspace_max_v2()) {
-                err = gpio_request(NETSPACE_V2_GPIO_SATA1_POWER, "SATA1 power");
-                if (err == 0) {
-                        err = gpio_direction_output(
-                                        NETSPACE_V2_GPIO_SATA1_POWER, 1);
-                        if (err)
-                                gpio_free(NETSPACE_V2_GPIO_SATA1_POWER);
-                }
-                if (err)
-                        pr_err("netspace_v2: failed to setup SATA1 power\n");
-        }
-}
-
 /*****************************************************************************
  * GPIO keys
  ****************************************************************************/
@@ -224,20 +137,6 @@ static struct platform_device netspace_v2_leds = {
 };
 
 /*****************************************************************************
- * Timer
- ****************************************************************************/
-
-static void netspace_v2_timer_init(void)
-{
-        kirkwood_tclk = 166666667;
-        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
-}
-
-struct sys_timer netspace_v2_timer = {
-        .init = netspace_v2_timer_init,
-};
-
-/*****************************************************************************
  * General Setup
  ****************************************************************************/
 
@@ -291,18 +190,17 @@ static void __init netspace_v2_init(void)
         kirkwood_init();
         kirkwood_mpp_conf(netspace_v2_mpp_config);
 
-        netspace_v2_sata_power_init();
+        if (machine_is_netspace_max_v2())
+                lacie_v2_hdd_power_init(2);
+        else
+                lacie_v2_hdd_power_init(1);
 
         kirkwood_ehci_init();
         kirkwood_ge00_init(&netspace_v2_ge00_data);
         kirkwood_sata_init(&netspace_v2_sata_data);
         kirkwood_uart0_init();
-        spi_register_board_info(netspace_v2_spi_slave_info,
-                                ARRAY_SIZE(netspace_v2_spi_slave_info));
-        kirkwood_spi_init();
-        kirkwood_i2c_init();
-        i2c_register_board_info(0, netspace_v2_i2c_info,
-                                ARRAY_SIZE(netspace_v2_i2c_info));
+        lacie_v2_register_flash();
+        lacie_v2_register_i2c_devices();
 
         platform_device_register(&netspace_v2_leds);
         platform_device_register(&netspace_v2_gpio_leds);
@@ -323,7 +221,7 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &netspace_v2_timer,
+        .timer          = &lacie_v2_timer,
 MACHINE_END
 #endif
 
@@ -335,7 +233,7 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &netspace_v2_timer,
+        .timer          = &lacie_v2_timer,
 MACHINE_END
 #endif
 
@@ -347,6 +245,6 @@ MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &netspace_v2_timer,
+        .timer          = &lacie_v2_timer,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 2bd14c5079de..d970e1eee37d 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -23,55 +23,19 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/i2c.h>
-#include <linux/i2c/at24.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/time.h>
 #include <mach/kirkwood.h>
-#include <plat/time.h>
+#include <mach/leds-netxbig.h>
 #include "common.h"
 #include "mpp.h"
-
-/*****************************************************************************
- * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
- ****************************************************************************/
-
-static struct mtd_partition netxbig_v2_flash_parts[] = {
-        {
-                .name = "u-boot",
-                .size = MTDPART_SIZ_FULL,
-                .offset = 0,
-                .mask_flags = MTD_WRITEABLE, /* force read-only */
-        },
-};
-
-static const struct flash_platform_data netxbig_v2_flash = {
-        .type           = "mx25l4005a",
-        .name           = "spi_flash",
-        .parts          = netxbig_v2_flash_parts,
-        .nr_parts       = ARRAY_SIZE(netxbig_v2_flash_parts),
-};
-
-static struct spi_board_info __initdata netxbig_v2_spi_slave_info[] = {
-        {
-                .modalias       = "m25p80",
-                .platform_data  = &netxbig_v2_flash,
-                .irq            = -1,
-                .max_speed_hz   = 20000000,
-                .bus_num        = 0,
-                .chip_select    = 0,
-        },
-};
+#include "lacie_v2-common.h"
 
 /*****************************************************************************
  * Ethernet
@@ -86,27 +50,6 @@ static struct mv643xx_eth_platform_data netxbig_v2_ge01_data = {
 };
 
 /*****************************************************************************
- * I2C devices
- ****************************************************************************/
-
-static struct at24_platform_data at24c04 = {
-        .byte_len       = SZ_4K / 8,
-        .page_size      = 16,
-};
-
-/*
- * i2c addr | chip         | description
- * 0x50     | HT24LC04     | eeprom (512B)
- */
-
-static struct i2c_board_info __initdata netxbig_v2_i2c_info[] = {
-        {
-                I2C_BOARD_INFO("24c04", 0x50),
-                .platform_data  = &at24c04,
-        }
-};
-
-/*****************************************************************************
  * SATA
  ****************************************************************************/
 
@@ -114,34 +57,6 @@ static struct mv_sata_platform_data netxbig_v2_sata_data = {
         .n_ports        = 2,
 };
 
-static int __initdata netxbig_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 };
-
-static void __init netxbig_v2_sata_power_init(void)
-{
-        int i;
-        int err;
-        int hdd_nb;
-
-        if (machine_is_net2big_v2())
-                hdd_nb = 2;
-        else
-                hdd_nb = 5;
-
-        /* Power up all hard disks. */
-        for (i = 0; i < hdd_nb; i++) {
-                err = gpio_request(netxbig_v2_gpio_hdd_power[i], NULL);
-                if (err == 0) {
-                        err = gpio_direction_output(
-                                        netxbig_v2_gpio_hdd_power[i], 1);
-                        /* Free the HDD power GPIOs. This allow user-space to
-                         * configure them via the gpiolib sysfs interface. */
-                        gpio_free(netxbig_v2_gpio_hdd_power[i]);
-                }
-                if (err)
-                        pr_err("netxbig_v2: failed to power up HDD%d\n", i + 1);
-        }
-}
-
 /*****************************************************************************
  * GPIO keys
  ****************************************************************************/
@@ -190,7 +105,7 @@ static struct platform_device netxbig_v2_gpio_buttons = {
 };
 
 /*****************************************************************************
- * GPIO LEDs
+ * GPIO extension LEDs
  ****************************************************************************/
 
 /*
@@ -200,19 +115,32 @@ static struct platform_device netxbig_v2_gpio_buttons = {
  * - address register : bit [0-2] -> GPIO [47-49]
  * - data register    : bit [0-2] -> GPIO [44-46]
  * - enable register  : GPIO 29
- *
+ */
+
+static int netxbig_v2_gpio_ext_addr[] = { 47, 48, 49 };
+static int netxbig_v2_gpio_ext_data[] = { 44, 45, 46 };
+
+static struct netxbig_gpio_ext netxbig_v2_gpio_ext = {
+        .addr           = netxbig_v2_gpio_ext_addr,
+        .num_addr       = ARRAY_SIZE(netxbig_v2_gpio_ext_addr),
+        .data           = netxbig_v2_gpio_ext_data,
+        .num_data       = ARRAY_SIZE(netxbig_v2_gpio_ext_data),
+        .enable         = 29,
+};
+
+/*
  * Address register selection:
  *
  * addr | register
  * ----------------------------
  *   0  | front LED
  *   1  | front LED brightness
- *   2  | HDD LED brightness
- *   3  | HDD1 LED
- *   4  | HDD2 LED
- *   5  | HDD3 LED
- *   6  | HDD4 LED
- *   7  | HDD5 LED
+ *   2  | SATA LED brightness
+ *   3  | SATA0 LED
+ *   4  | SATA1 LED
+ *   5  | SATA2 LED
+ *   6  | SATA3 LED
+ *   7  | SATA4 LED
  *
  * Data register configuration:
  *
@@ -233,30 +161,107 @@ static struct platform_device netxbig_v2_gpio_buttons = {
  *   6  | blink blue on=1 sec and red on=1 sec
  *   7  | blink blue on=0.5 sec and blue off=2.5 sec
  *
- * data | HDD LED mode
+ * data | SATA LED mode
  * -------------------------------------------------
- *   0  | fix blue on
+ *   0  | fix off
  *   1  | SATA activity blink
  *   2  | fix red on
  *   3  | blink blue on=1 sec and blue off=1 sec
  *   4  | blink red on=1 sec and red off=1 sec
  *   5  | blink blue on=2.5 sec and red on=0.5 sec
  *   6  | blink blue on=1 sec and red on=1 sec
- *   7  | blink blue on=0.5 sec and blue off=2.5 sec
+ *   7  | fix blue on
  */
 
-/*****************************************************************************
- * Timer
- ****************************************************************************/
+static int netxbig_v2_red_mled[NETXBIG_LED_MODE_NUM] = {
+        [NETXBIG_LED_OFF]       = 0,
+        [NETXBIG_LED_ON]        = 2,
+        [NETXBIG_LED_SATA]      = NETXBIG_LED_INVALID_MODE,
+        [NETXBIG_LED_TIMER1]    = 4,
+        [NETXBIG_LED_TIMER2]    = NETXBIG_LED_INVALID_MODE,
+};
 
-static void netxbig_v2_timer_init(void)
-{
-        kirkwood_tclk = 166666667;
-        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
-}
+static int netxbig_v2_blue_pwr_mled[NETXBIG_LED_MODE_NUM] = {
+        [NETXBIG_LED_OFF]       = 0,
+        [NETXBIG_LED_ON]        = 1,
+        [NETXBIG_LED_SATA]      = NETXBIG_LED_INVALID_MODE,
+        [NETXBIG_LED_TIMER1]    = 3,
+        [NETXBIG_LED_TIMER2]    = 7,
+};
+
+static int netxbig_v2_blue_sata_mled[NETXBIG_LED_MODE_NUM] = {
+        [NETXBIG_LED_OFF]       = 0,
+        [NETXBIG_LED_ON]        = 7,
+        [NETXBIG_LED_SATA]      = 1,
+        [NETXBIG_LED_TIMER1]    = 3,
+        [NETXBIG_LED_TIMER2]    = NETXBIG_LED_INVALID_MODE,
+};
+
+static struct netxbig_led_timer netxbig_v2_led_timer[] = {
+        [0] = {
+                .delay_on       = 500,
+                .delay_off      = 500,
+                .mode           = NETXBIG_LED_TIMER1,
+        },
+        [1] = {
+                .delay_on       = 500,
+                .delay_off      = 1000,
+                .mode           = NETXBIG_LED_TIMER2,
+        },
+};
+
+#define NETXBIG_LED(_name, maddr, mval, baddr)                  \
+        { .name         = _name,                                \
+          .mode_addr    = maddr,                                \
+          .mode_val     = mval,                                 \
+          .bright_addr  = baddr }
+
+static struct netxbig_led net2big_v2_leds_ctrl[] = {
+        NETXBIG_LED("net2big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled,  1),
+        NETXBIG_LED("net2big-v2:red:power",  0, netxbig_v2_red_mled,       1),
+        NETXBIG_LED("net2big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net2big-v2:red:sata0",  3, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net2big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net2big-v2:red:sata1",  4, netxbig_v2_red_mled,       2),
+};
+
+static struct netxbig_led_platform_data net2big_v2_leds_data = {
+        .gpio_ext       = &netxbig_v2_gpio_ext,
+        .timer          = netxbig_v2_led_timer,
+        .num_timer      = ARRAY_SIZE(netxbig_v2_led_timer),
+        .leds           = net2big_v2_leds_ctrl,
+        .num_leds       = ARRAY_SIZE(net2big_v2_leds_ctrl),
+};
+
+static struct netxbig_led net5big_v2_leds_ctrl[] = {
+        NETXBIG_LED("net5big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled,  1),
+        NETXBIG_LED("net5big-v2:red:power",  0, netxbig_v2_red_mled,       1),
+        NETXBIG_LED("net5big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata0",  3, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata1",  4, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata2", 5, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata2",  5, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata3", 6, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata3",  6, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata4", 7, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata5",  7, netxbig_v2_red_mled,       2),
+};
 
-struct sys_timer netxbig_v2_timer = {
-        .init = netxbig_v2_timer_init,
+static struct netxbig_led_platform_data net5big_v2_leds_data = {
+        .gpio_ext       = &netxbig_v2_gpio_ext,
+        .timer          = netxbig_v2_led_timer,
+        .num_timer      = ARRAY_SIZE(netxbig_v2_led_timer),
+        .leds           = net5big_v2_leds_ctrl,
+        .num_leds       = ARRAY_SIZE(net5big_v2_leds_ctrl),
+};
+
+static struct platform_device netxbig_v2_leds = {
+        .name           = "leds-netxbig",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &net2big_v2_leds_data,
+        },
 };
 
 /*****************************************************************************
@@ -284,18 +289,18 @@ static unsigned int net2big_v2_mpp_config[] __initdata = {
         MPP24_GPIO,             /* USB mode select */
         MPP26_GPIO,             /* USB device vbus */
         MPP28_GPIO,             /* USB enable host vbus */
-        MPP29_GPIO,             /* CPLD extension ALE */
+        MPP29_GPIO,             /* GPIO extension ALE */
         MPP34_GPIO,             /* Rear Push button */
         MPP35_GPIO,             /* Inhibit switch power-off */
         MPP36_GPIO,             /* SATA HDD1 presence */
         MPP37_GPIO,             /* SATA HDD2 presence */
         MPP40_GPIO,             /* eSATA presence */
-        MPP44_GPIO,             /* CPLD extension (data 0) */
-        MPP45_GPIO,             /* CPLD extension (data 1) */
-        MPP46_GPIO,             /* CPLD extension (data 2) */
-        MPP47_GPIO,             /* CPLD extension (addr 0) */
-        MPP48_GPIO,             /* CPLD extension (addr 1) */
-        MPP49_GPIO,             /* CPLD extension (addr 2) */
+        MPP44_GPIO,             /* GPIO extension (data 0) */
+        MPP45_GPIO,             /* GPIO extension (data 1) */
+        MPP46_GPIO,             /* GPIO extension (data 2) */
+        MPP47_GPIO,             /* GPIO extension (addr 0) */
+        MPP48_GPIO,             /* GPIO extension (addr 1) */
+        MPP49_GPIO,             /* GPIO extension (addr 2) */
         0
 };
 
@@ -324,7 +329,7 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
         MPP26_GE1_RXD2,
         MPP27_GE1_RXD3,
         MPP28_GPIO,             /* USB enable host vbus */
-        MPP29_GPIO,             /* CPLD extension ALE */
+        MPP29_GPIO,             /* GPIO extension ALE */
         MPP30_GE1_RXCTL,
         MPP31_GE1_RXCLK,
         MPP32_GE1_TCLKOUT,
@@ -339,12 +344,12 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
         MPP41_GPIO,             /* SATA HDD3 power */
         MPP42_GPIO,             /* SATA HDD4 power */
         MPP43_GPIO,             /* SATA HDD5 power */
-        MPP44_GPIO,             /* CPLD extension (data 0) */
-        MPP45_GPIO,             /* CPLD extension (data 1) */
-        MPP46_GPIO,             /* CPLD extension (data 2) */
-        MPP47_GPIO,             /* CPLD extension (addr 0) */
-        MPP48_GPIO,             /* CPLD extension (addr 1) */
-        MPP49_GPIO,             /* CPLD extension (addr 2) */
+        MPP44_GPIO,             /* GPIO extension (data 0) */
+        MPP45_GPIO,             /* GPIO extension (data 1) */
+        MPP46_GPIO,             /* GPIO extension (data 2) */
+        MPP47_GPIO,             /* GPIO extension (addr 0) */
+        MPP48_GPIO,             /* GPIO extension (addr 1) */
+        MPP49_GPIO,             /* GPIO extension (addr 2) */
         0
 };
 
@@ -366,7 +371,10 @@ static void __init netxbig_v2_init(void)
         else
                 kirkwood_mpp_conf(net5big_v2_mpp_config);
 
-        netxbig_v2_sata_power_init();
+        if (machine_is_net2big_v2())
+                lacie_v2_hdd_power_init(2);
+        else
+                lacie_v2_hdd_power_init(5);
 
         kirkwood_ehci_init();
         kirkwood_ge00_init(&netxbig_v2_ge00_data);
@@ -374,13 +382,12 @@ static void __init netxbig_v2_init(void)
                 kirkwood_ge01_init(&netxbig_v2_ge01_data);
         kirkwood_sata_init(&netxbig_v2_sata_data);
         kirkwood_uart0_init();
-        spi_register_board_info(netxbig_v2_spi_slave_info,
-                                ARRAY_SIZE(netxbig_v2_spi_slave_info));
-        kirkwood_spi_init();
-        kirkwood_i2c_init();
-        i2c_register_board_info(0, netxbig_v2_i2c_info,
-                                ARRAY_SIZE(netxbig_v2_i2c_info));
+        lacie_v2_register_flash();
+        lacie_v2_register_i2c_devices();
 
+        if (machine_is_net5big_v2())
+                netxbig_v2_leds.dev.platform_data = &net5big_v2_leds_data;
+        platform_device_register(&netxbig_v2_leds);
         platform_device_register(&netxbig_v2_gpio_buttons);
 
         if (gpio_request(NETXBIG_V2_GPIO_POWER_OFF, "power-off") == 0 &&
@@ -398,7 +405,7 @@ MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
         .init_machine   = netxbig_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &netxbig_v2_timer,
+        .timer          = &lacie_v2_timer,
 MACHINE_END
 #endif
 
@@ -410,6 +417,6 @@ MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
         .init_machine   = netxbig_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &netxbig_v2_timer,
+        .timer          = &lacie_v2_timer,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index fd06be618815..38017c8ac43f 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -16,6 +16,7 @@
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/i2c.h>
+#include <linux/gpio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
@@ -57,7 +58,22 @@ static struct mvsdio_platform_data openrd_mvsdio_data = {
 };
 
 static unsigned int openrd_mpp_config[] __initdata = {
+        MPP12_SD_CLK,
+        MPP13_SD_CMD,
+        MPP14_SD_D0,
+        MPP15_SD_D1,
+        MPP16_SD_D2,
+        MPP17_SD_D3,
+        MPP28_GPIO,
         MPP29_GPIO,
+        MPP34_GPIO,
+        0
+};
+
+/* Configure MPP for UART1 */
+static unsigned int openrd_uart1_mpp_config[] __initdata = {
+        MPP13_UART1_TXD,
+        MPP14_UART1_RXD,
         0
 };
 
@@ -67,6 +83,68 @@ static struct i2c_board_info i2c_board_info[] __initdata = {
         },
 };
 
+static int __initdata uart1;
+
+static int __init sd_uart_selection(char *str)
+{
+        uart1 = -EINVAL;
+
+        /* Default is SD. Change if required, for UART */
+        if (!str)
+                return 0;
+
+        if (!strncmp(str, "232", 3)) {
+                uart1 = 232;
+        } else if (!strncmp(str, "485", 3)) {
+                /* OpenRD-Base doesn't have RS485. Treat is as an
+                 * unknown argument & just have default setting -
+                 * which is SD */
+                if (machine_is_openrd_base()) {
+                        uart1 = -ENODEV;
+                        return 1;
+                }
+
+                uart1 = 485;
+        }
+        return 1;
+}
+/* Parse boot_command_line string kw_openrd_init_uart1=232/485 */
+__setup("kw_openrd_init_uart1=", sd_uart_selection);
+
+static int __init uart1_mpp_config(void)
+{
+        kirkwood_mpp_conf(openrd_uart1_mpp_config);
+
+        if (gpio_request(34, "SD_UART1_SEL")) {
+                printk(KERN_ERR "GPIO request failed for SD/UART1 selection"
+                                ", gpio: 34\n");
+                return -EIO;
+        }
+
+        if (gpio_request(28, "RS232_RS485_SEL")) {
+                printk(KERN_ERR "GPIO request failed for RS232/RS485 selection"
+                                ", gpio# 28\n");
+                gpio_free(34);
+                return -EIO;
+        }
+
+        /* Select UART1
+         * Pin # 34: 0 => UART1, 1 => SD */
+        gpio_direction_output(34, 0);
+
+        /* Select RS232 OR RS485
+         * Pin # 28: 0 => RS232, 1 => RS485 */
+        if (uart1 == 232)
+                gpio_direction_output(28, 0);
+        else
+                gpio_direction_output(28, 1);
+
+        gpio_free(34);
+        gpio_free(28);
+
+        return 0;
+}
+
 static void __init openrd_init(void)
 {
         /*
@@ -90,7 +168,6 @@ static void __init openrd_init(void)
                 kirkwood_ge01_init(&openrd_ge01_data);
 
         kirkwood_sata_init(&openrd_sata_data);
-        kirkwood_sdio_init(&openrd_mvsdio_data);
 
         kirkwood_i2c_init();
 
@@ -99,6 +176,28 @@ static void __init openrd_init(void)
                         ARRAY_SIZE(i2c_board_info));
                 kirkwood_audio_init();
         }
+
+        if (uart1 <= 0) {
+                if (uart1 < 0)
+                        printk(KERN_ERR "Invalid kernel parameter to select "
+                                "UART1. Defaulting to SD. ERROR CODE: %d\n",
+                                uart1);
+
+                /* Select SD
+                 * Pin # 34: 0 => UART1, 1 => SD */
+                if (gpio_request(34, "SD_UART1_SEL")) {
+                        printk(KERN_ERR "GPIO request failed for SD/UART1 "
+                                        "selection, gpio: 34\n");
+                } else {
+
+                        gpio_direction_output(34, 1);
+                        gpio_free(34);
+                        kirkwood_sdio_init(&openrd_mvsdio_data);
+                }
+        } else {
+                if (!uart1_mpp_config())
+                        kirkwood_uart1_init();
+        }
 }
 
 static int __init openrd_pci_init(void)
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 55e7f00836b7..513ad3102d7c 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -117,7 +117,7 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp)
          * IORESOURCE_IO
          */
         pp->res[0].name = "PCIe 0 I/O Space";
-        pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
+        pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
         pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
         pp->res[0].flags = IORESOURCE_IO;
 
@@ -139,7 +139,7 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp)
          * IORESOURCE_IO
          */
         pp->res[0].name = "PCIe 1 I/O Space";
-        pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
+        pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
         pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
         pp->res[0].flags = IORESOURCE_IO;
 
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 6ab843eaa35b..0711d3b620ad 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -57,6 +57,13 @@ config MACH_MARVELL_JASPER
           PXA910-based development board. Since MMP2 is compatible to
           ARMv6 architecture.
 
+config MACH_TETON_BGA
+        bool "Marvell's PXA168 Teton BGA Development Board"
+        select CPU_PXA168
+        help
+          Say 'Y' here if you want to support the Marvell PXA168-based
+          Teton BGA Development Board.
+
 endmenu
 
 config CPU_PXA168
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 8b66d06739c4..751cdbf733c8 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_MACH_TAVOREVB)	+= tavorevb.o
 obj-$(CONFIG_MACH_TTC_DKB)      += ttc_dkb.o
 obj-$(CONFIG_MACH_FLINT)        += flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
+obj-$(CONFIG_MACH_TETON_BGA)    += teton_bga.o
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 0629394a5fb9..4681bedbe788 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -16,6 +16,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
+#include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -23,6 +24,9 @@
 #include <mach/mfp-pxa168.h>
 #include <mach/pxa168.h>
 #include <mach/gpio.h>
+#include <video/pxa168fb.h>
+#include <linux/input.h>
+#include <plat/pxa27x_keypad.h>
 
 #include "common.h"
 
@@ -66,6 +70,43 @@ static unsigned long common_pin_config[] __initdata = {
         GPIO115_I2S_BCLK,
         GPIO116_I2S_RXD,
         GPIO117_I2S_TXD,
+
+        /* LCD */
+        GPIO56_LCD_FCLK_RD,
+        GPIO57_LCD_LCLK_A0,
+        GPIO58_LCD_PCLK_WR,
+        GPIO59_LCD_DENA_BIAS,
+        GPIO60_LCD_DD0,
+        GPIO61_LCD_DD1,
+        GPIO62_LCD_DD2,
+        GPIO63_LCD_DD3,
+        GPIO64_LCD_DD4,
+        GPIO65_LCD_DD5,
+        GPIO66_LCD_DD6,
+        GPIO67_LCD_DD7,
+        GPIO68_LCD_DD8,
+        GPIO69_LCD_DD9,
+        GPIO70_LCD_DD10,
+        GPIO71_LCD_DD11,
+        GPIO72_LCD_DD12,
+        GPIO73_LCD_DD13,
+        GPIO74_LCD_DD14,
+        GPIO75_LCD_DD15,
+        GPIO76_LCD_DD16,
+        GPIO77_LCD_DD17,
+        GPIO78_LCD_DD18,
+        GPIO79_LCD_DD19,
+        GPIO80_LCD_DD20,
+        GPIO81_LCD_DD21,
+        GPIO82_LCD_DD22,
+        GPIO83_LCD_DD23,
+
+        /* Keypad */
+        GPIO109_KP_MKIN1,
+        GPIO110_KP_MKIN0,
+        GPIO111_KP_MKOUT7,
+        GPIO112_KP_MKOUT6,
+        GPIO121_KP_MKIN4,
 };
 
 static struct smc91x_platdata smc91x_info = {
@@ -134,6 +175,51 @@ static struct i2c_board_info aspenite_i2c_info[] __initdata = {
         { I2C_BOARD_INFO("wm8753", 0x1b), },
 };
 
+static struct fb_videomode video_modes[] = {
+        [0] = {
+                .pixclock       = 30120,
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 480,
+                .hsync_len      = 1,
+                .left_margin    = 215,
+                .right_margin   = 40,
+                .vsync_len      = 1,
+                .upper_margin   = 34,
+                .lower_margin   = 10,
+                .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
+        },
+};
+
+struct pxa168fb_mach_info aspenite_lcd_info = {
+        .id                     = "Graphic Frame",
+        .modes                  = video_modes,
+        .num_modes              = ARRAY_SIZE(video_modes),
+        .pix_fmt                = PIX_FMT_RGB565,
+        .io_pin_allocation_mode = PIN_MODE_DUMB_24,
+        .dumb_mode              = DUMB_MODE_RGB888,
+        .active                 = 1,
+        .panel_rbswap           = 0,
+        .invert_pixclock        = 0,
+};
+
+static unsigned int aspenite_matrix_key_map[] = {
+        KEY(0, 6, KEY_UP),      /* SW 4 */
+        KEY(0, 7, KEY_DOWN),    /* SW 5 */
+        KEY(1, 6, KEY_LEFT),    /* SW 6 */
+        KEY(1, 7, KEY_RIGHT),   /* SW 7 */
+        KEY(4, 6, KEY_ENTER),   /* SW 8 */
+        KEY(4, 7, KEY_ESC),     /* SW 9 */
+};
+
+static struct pxa27x_keypad_platform_data aspenite_keypad_info __initdata = {
+        .matrix_key_rows        = 5,
+        .matrix_key_cols        = 8,
+        .matrix_key_map         = aspenite_matrix_key_map,
+        .matrix_key_map_size    = ARRAY_SIZE(aspenite_matrix_key_map),
+        .debounce_interval      = 30,
+};
+
 static void __init common_init(void)
 {
         mfp_config(ARRAY_AND_SIZE(common_pin_config));
@@ -143,6 +229,8 @@ static void __init common_init(void)
         pxa168_add_twsi(1, NULL, ARRAY_AND_SIZE(aspenite_i2c_info));
         pxa168_add_ssp(1);
         pxa168_add_nand(&aspenite_nand_info);
+        pxa168_add_fb(&aspenite_lcd_info);
+        pxa168_add_keypad(&aspenite_keypad_info);
 
         /* off-chip devices */
         platform_device_register(&smc91x_device);
@@ -152,6 +240,7 @@ MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
         .phys_io        = APB_PHYS_BASE,
         .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
+        .nr_irqs        = IRQ_BOARD_START,
         .init_irq       = pxa168_init_irq,
         .timer          = &pxa168_timer,
         .init_machine   = common_init,
@@ -161,6 +250,7 @@ MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
         .phys_io        = APB_PHYS_BASE,
         .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
+        .nr_irqs        = IRQ_BOARD_START,
         .init_irq       = pxa168_init_irq,
         .timer          = &pxa168_timer,
         .init_machine   = common_init,
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 3b29fa7e9b08..0ec0ca80bb3e 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -10,13 +10,20 @@
 
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/module.h>
 
 #include <asm/page.h>
 #include <asm/mach/map.h>
 #include <mach/addr-map.h>
+#include <mach/cputype.h>
 
 #include "common.h"
 
+#define MMP_CHIPID      (AXI_VIRT_BASE + 0x82c00)
+
+unsigned int mmp_chip_id;
+EXPORT_SYMBOL(mmp_chip_id);
+
 static struct map_desc standard_io_desc[] __initdata = {
         {
                 .pfn            = __phys_to_pfn(APB_PHYS_BASE),
@@ -34,4 +41,7 @@ static struct map_desc standard_io_desc[] __initdata = {
 void __init mmp_map_io(void)
 {
         iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
+
+        /* this is early, initialize mmp_chip_id here */
+        mmp_chip_id = __raw_readl(MMP_CHIPID);
 }
diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c
index e4312d238eae..c558425c3613 100644
--- a/arch/arm/mach-mmp/flint.c
+++ b/arch/arm/mach-mmp/flint.c
@@ -16,6 +16,7 @@
 #include <linux/smc91x.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -25,6 +26,8 @@
 
 #include "common.h"
 
+#define FLINT_NR_IRQS   (IRQ_BOARD_START + 48)
+
 static unsigned long flint_pin_config[] __initdata = {
         /* UART1 */
         GPIO45_UART1_RXD,
@@ -116,6 +119,7 @@ MACHINE_START(FLINT, "Flint Development Platform")
         .phys_io        = APB_PHYS_BASE,
         .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
+        .nr_irqs        = FLINT_NR_IRQS,
         .init_irq       = mmp2_init_irq,
         .timer          = &mmp2_timer,
         .init_machine   = flint_init,
diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h
index 83b18721d933..f43a68b213f1 100644
--- a/arch/arm/mach-mmp/include/mach/cputype.h
+++ b/arch/arm/mach-mmp/include/mach/cputype.h
@@ -4,36 +4,51 @@
 #include <asm/cputype.h>
 
 /*
- *  CPU   Stepping   OLD_ID       CPU_ID      CHIP_ID
+ *  CPU   Stepping   CPU_ID      CHIP_ID
  *
- * PXA168    A0    0x41159263   0x56158400   0x00A0A333
- * PXA910    Y0    0x41159262   0x56158000   0x00F0C910
- * MMP2      Z0                 0x560f5811
+ * PXA168    S0    0x56158400   0x0000C910
+ * PXA168    A0    0x56158400   0x00A0A168
+ * PXA910    Y1    0x56158400   0x00F2C920
+ * PXA910    A0    0x56158400   0x00F2C910
+ * PXA910    A1    0x56158400   0x00A0C910
+ * PXA920    Y0    0x56158400   0x00F2C920
+ * PXA920    A0    0x56158400   0x00A0C920
+ * PXA920    A1    0x56158400   0x00A1C920
+ * MMP2      Z0    0x560f5811   0x00F00410
+ * MMP2      Z1    0x560f5811   0x00E00410
+ * MMP2      A0    0x560f5811   0x00A0A610
  */
 
+extern unsigned int mmp_chip_id;
+
 #ifdef CONFIG_CPU_PXA168
-#  define __cpu_is_pxa168(id)   \
-        ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x84; })
+static inline int cpu_is_pxa168(void)
+{
+        return (((read_cpuid_id() >> 8) & 0xff) == 0x84) &&
+                ((mmp_chip_id & 0xfff) == 0x168);
+}
 #else
-#  define __cpu_is_pxa168(id)   (0)
+#define cpu_is_pxa168() (0)
 #endif
 
+/* cpu_is_pxa910() is shared on both pxa910 and pxa920 */
 #ifdef CONFIG_CPU_PXA910
-#  define __cpu_is_pxa910(id)   \
-        ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x80; })
+static inline int cpu_is_pxa910(void)
+{
+        return (((read_cpuid_id() >> 8) & 0xff) == 0x84) &&
+                (((mmp_chip_id & 0xfff) == 0x910) ||
+                 ((mmp_chip_id & 0xfff) == 0x920));
+}
 #else
-#  define __cpu_is_pxa910(id)   (0)
+#define cpu_is_pxa910() (0)
 #endif
 
 #ifdef CONFIG_CPU_MMP2
-#  define __cpu_is_mmp2(id)     \
-        ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x58; })
+static inline int cpu_is_mmp2(void)
+{
+        return (((cpu_readid_id() >> 8) & 0xff) == 0x58);
 #else
-#  define __cpu_is_mmp2(id)     (0)
+#define cpu_is_mmp2()   (0)
 #endif
 
-#define cpu_is_pxa168()         ({ __cpu_is_pxa168(read_cpuid_id()); })
-#define cpu_is_pxa910()         ({ __cpu_is_pxa910(read_cpuid_id()); })
-#define cpu_is_mmp2()           ({ __cpu_is_mmp2(read_cpuid_id()); })
-
 #endif /* __ASM_MACH_CPUTYPE_H */
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
index b379cdec4d38..a09d328e2ddd 100644
--- a/arch/arm/mach-mmp/include/mach/irqs.h
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -222,10 +222,8 @@
 #define IRQ_GPIO_NUM                    192
 #define IRQ_GPIO(x)                     (IRQ_GPIO_START + (x))
 
-/* Board IRQ - 64 by default, increase if not enough */
 #define IRQ_BOARD_START                 (IRQ_GPIO_START + IRQ_GPIO_NUM)
-#define IRQ_BOARD_END                   (IRQ_BOARD_START + 64)
 
-#define NR_IRQS                         (IRQ_BOARD_END)
+#define NR_IRQS                         (IRQ_BOARD_START)
 
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
index ded43c455ec3..4621067c7720 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
@@ -289,4 +289,11 @@
 #define GPIO86_PWM1_OUT         MFP_CFG(GPIO86, AF2)
 #define GPIO86_PWM2_OUT         MFP_CFG(GPIO86, AF3)
 
+/* Keypad */
+#define GPIO109_KP_MKIN1        MFP_CFG(GPIO109, AF7)
+#define GPIO110_KP_MKIN0        MFP_CFG(GPIO110, AF7)
+#define GPIO111_KP_MKOUT7       MFP_CFG(GPIO111, AF7)
+#define GPIO112_KP_MKOUT6       MFP_CFG(GPIO112, AF7)
+#define GPIO121_KP_MKIN4        MFP_CFG(GPIO121, AF7)
+
 #endif /* __ASM_MACH_MFP_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 27e1bc758623..1801e4206232 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -5,11 +5,15 @@ struct sys_timer;
 
 extern struct sys_timer pxa168_timer;
 extern void __init pxa168_init_irq(void);
+extern void pxa168_clear_keypad_wakeup(void);
 
 #include <linux/i2c.h>
 #include <mach/devices.h>
 #include <plat/i2c.h>
 #include <plat/pxa3xx_nand.h>
+#include <video/pxa168fb.h>
+#include <plat/pxa27x_keypad.h>
+#include <mach/cputype.h>
 
 extern struct pxa_device_desc pxa168_device_uart1;
 extern struct pxa_device_desc pxa168_device_uart2;
@@ -25,6 +29,8 @@ extern struct pxa_device_desc pxa168_device_ssp3;
 extern struct pxa_device_desc pxa168_device_ssp4;
 extern struct pxa_device_desc pxa168_device_ssp5;
 extern struct pxa_device_desc pxa168_device_nand;
+extern struct pxa_device_desc pxa168_device_fb;
+extern struct pxa_device_desc pxa168_device_keypad;
 
 static inline int pxa168_add_uart(int id)
 {
@@ -97,4 +103,18 @@ static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info)
 {
         return pxa_register_device(&pxa168_device_nand, info, sizeof(*info));
 }
+
+static inline int pxa168_add_fb(struct pxa168fb_mach_info *mi)
+{
+        return pxa_register_device(&pxa168_device_fb, mi, sizeof(*mi));
+}
+
+static inline int pxa168_add_keypad(struct pxa27x_keypad_platform_data *data)
+{
+        if (cpu_is_pxa168())
+                data->clear_wakeup_event = pxa168_clear_keypad_wakeup;
+
+        return pxa_register_device(&pxa168_device_keypad, data, sizeof(*data));
+}
+
 #endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index 919030514120..ac4702357a6e 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -33,4 +33,16 @@
 #define APMU_FNRST_DIS  (1 << 1)
 #define APMU_AXIRST_DIS (1 << 0)
 
+/* Wake Clear Register */
+#define APMU_WAKE_CLR   APMU_REG(0x07c)
+
+#define APMU_PXA168_KP_WAKE_CLR         (1 << 7)
+#define APMU_PXA168_CFI_WAKE_CLR        (1 << 6)
+#define APMU_PXA168_XD_WAKE_CLR         (1 << 5)
+#define APMU_PXA168_MSP_WAKE_CLR        (1 << 4)
+#define APMU_PXA168_SD4_WAKE_CLR        (1 << 3)
+#define APMU_PXA168_SD3_WAKE_CLR        (1 << 2)
+#define APMU_PXA168_SD2_WAKE_CLR        (1 << 1)
+#define APMU_PXA168_SD1_WAKE_CLR        (1 << 0)
+
 #endif /* __ASM_MACH_REGS_APMU_H */
diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h
index 4f5b0e0ce6cf..1a8a25edb1b4 100644
--- a/arch/arm/mach-mmp/include/mach/system.h
+++ b/arch/arm/mach-mmp/include/mach/system.h
@@ -9,6 +9,8 @@
 #ifndef __ASM_MACH_SYSTEM_H
 #define __ASM_MACH_SYSTEM_H
 
+#include <mach/cputype.h>
+
 static inline void arch_idle(void)
 {
         cpu_do_idle();
@@ -16,6 +18,9 @@ static inline void arch_idle(void)
 
 static inline void arch_reset(char mode, const char *cmd)
 {
-        cpu_reset(0);
+        if (cpu_is_pxa168())
+                cpu_reset(0xffff0000);
+        else
+                cpu_reset(0);
 }
 #endif /* __ASM_MACH_SYSTEM_H */
diff --git a/arch/arm/mach-mmp/include/mach/teton_bga.h b/arch/arm/mach-mmp/include/mach/teton_bga.h
new file mode 100644
index 000000000000..61a539b2cc98
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/teton_bga.h
@@ -0,0 +1,27 @@
+/*
+ *  linux/arch/arm/mach-mmp/include/mach/teton_bga.h
+ *
+ *  Support for the Marvell PXA168 Teton BGA Development Platform.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+#ifndef __ASM_MACH_TETON_BGA_H
+#define __ASM_MACH_TETON_BGA_H
+
+/* GPIOs */
+#define MMC_PWENA_GPIO          27
+#define USBHPENB_GPIO           55
+#define RTC_INT_GPIO            78
+#define LCD_VBLK_EN_GPIO        79
+#define LCD_DVDD_EN_GPIO        80
+#define RST_WIFI_GPIO           81
+#define CF_PWEN_GPIO            82
+#define USB_OC_GPIO             83
+#define PWM_GPIO                84
+#define USBHPENA_GPIO           85
+#define TS_INT_GPIO             86
+#define CIR_GPIO                108
+
+#endif /* __ASM_MACH_TETON_BGA_H */
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index 80c3e7ab1e17..940ee03e3682 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -18,16 +18,18 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/max8649.h>
 #include <linux/mfd/max8925.h>
+#include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/addr-map.h>
 #include <mach/mfp-mmp2.h>
 #include <mach/mmp2.h>
-#include <mach/irqs.h>
 
 #include "common.h"
 
+#define JASPER_NR_IRQS          (IRQ_BOARD_START + 48)
+
 static unsigned long jasper_pin_config[] __initdata = {
         /* UART1 */
         GPIO29_UART1_RXD,
@@ -137,6 +139,7 @@ MACHINE_START(MARVELL_JASPER, "Jasper Development Platform")
         .phys_io        = APB_PHYS_BASE,
         .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
+        .nr_irqs        = JASPER_NR_IRQS,
         .init_irq       = mmp2_init_irq,
         .timer          = &mmp2_timer,
         .init_machine   = jasper_init,
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 652ae660634c..72b4e7631583 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -77,8 +77,10 @@ static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
 static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
 static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
 static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
+static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
 
 static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(lcd, LCD, 0x7f, 312000000);
 
 /* device and clock bindings */
 static struct clk_lookup pxa168_clkregs[] = {
@@ -96,6 +98,8 @@ static struct clk_lookup pxa168_clkregs[] = {
         INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
         INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
+        INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
 };
 
 static int __init pxa168_init(void)
@@ -132,6 +136,16 @@ struct sys_timer pxa168_timer = {
         .init   = pxa168_timer_init,
 };
 
+void pxa168_clear_keypad_wakeup(void)
+{
+        uint32_t val;
+        uint32_t mask = APMU_PXA168_KP_WAKE_CLR;
+
+        /* wake event clear is needed in order to clear keypad interrupt */
+        val = __raw_readl(APMU_WAKE_CLR);
+        __raw_writel(val |  mask, APMU_WAKE_CLR);
+}
+
 /* on-chip devices */
 PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
 PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
@@ -147,3 +161,5 @@ PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55);
 PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57);
 PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59);
 PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
+PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
+PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
new file mode 100644
index 000000000000..a4a375c58e0c
--- /dev/null
+++ b/arch/arm/mach-mmp/teton_bga.c
@@ -0,0 +1,91 @@
+/*
+ *  linux/arch/arm/mach-mmp/teton_bga.c
+ *
+ *  Support for the Marvell PXA168 Teton BGA Development Platform.
+ *
+ *  Author: Mark F. Brown <mark.brown314@gmail.com>
+ *
+ *  This code is based on aspenite.c
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <plat/pxa27x_keypad.h>
+#include <linux/i2c.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/addr-map.h>
+#include <mach/mfp-pxa168.h>
+#include <mach/pxa168.h>
+#include <mach/teton_bga.h>
+
+#include "common.h"
+
+static unsigned long teton_bga_pin_config[] __initdata = {
+        /* UART1 */
+        GPIO107_UART1_TXD,
+        GPIO108_UART1_RXD,
+
+        /* Keypad */
+        GPIO109_KP_MKIN1,
+        GPIO110_KP_MKIN0,
+        GPIO111_KP_MKOUT7,
+        GPIO112_KP_MKOUT6,
+
+        /* I2C Bus */
+        GPIO105_CI2C_SDA,
+        GPIO106_CI2C_SCL,
+
+        /* RTC */
+        GPIO78_GPIO,
+};
+
+static unsigned int teton_bga_matrix_key_map[] = {
+        KEY(0, 6, KEY_ESC),
+        KEY(0, 7, KEY_ENTER),
+        KEY(1, 6, KEY_LEFT),
+        KEY(1, 7, KEY_RIGHT),
+};
+
+static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = {
+        .matrix_key_rows        = 2,
+        .matrix_key_cols        = 8,
+        .matrix_key_map         = teton_bga_matrix_key_map,
+        .matrix_key_map_size    = ARRAY_SIZE(teton_bga_matrix_key_map),
+        .debounce_interval      = 30,
+};
+
+static struct i2c_board_info teton_bga_i2c_info[] __initdata = {
+        {
+                I2C_BOARD_INFO("ds1337", 0x68),
+                .irq = gpio_to_irq(RTC_INT_GPIO)
+        },
+};
+
+static void __init teton_bga_init(void)
+{
+        mfp_config(ARRAY_AND_SIZE(teton_bga_pin_config));
+
+        /* on-chip devices */
+        pxa168_add_uart(1);
+        pxa168_add_keypad(&teton_bga_keypad_info);
+        pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(teton_bga_i2c_info));
+}
+
+MACHINE_START(TETON_BGA, "PXA168-based Teton BGA Development Platform")
+        .phys_io        = APB_PHYS_BASE,
+        .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
+        .map_io         = mmp_map_io,
+        .nr_irqs        = IRQ_BOARD_START,
+        .init_irq       = pxa168_init_irq,
+        .timer          = &pxa168_timer,
+        .init_machine   = teton_bga_init,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index ee65e05f0cf1..54571139dc4b 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -14,6 +14,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/onenand.h>
+#include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -24,6 +25,8 @@
 
 #include "common.h"
 
+#define TTCDKB_NR_IRQS          (IRQ_BOARD_START + 24)
+
 static unsigned long ttc_dkb_pin_config[] __initdata = {
         /* UART2 */
         GPIO47_UART2_RXD,
@@ -125,6 +128,7 @@ MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform")
         .phys_io        = APB_PHYS_BASE,
         .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
+        .nr_irqs        = TTCDKB_NR_IRQS,
         .init_irq       = pxa910_init_irq,
         .timer          = &pxa910_timer,
         .init_machine   = ttc_dkb_init,
diff --git a/arch/arm/mach-msm/include/mach/vmalloc.h b/arch/arm/mach-msm/include/mach/vmalloc.h
index 05f81fd8623c..31a32ad062dc 100644
--- a/arch/arm/mach-msm/include/mach/vmalloc.h
+++ b/arch/arm/mach-msm/include/mach/vmalloc.h
@@ -16,7 +16,7 @@
 #ifndef __ASM_ARCH_MSM_VMALLOC_H
 #define __ASM_ARCH_MSM_VMALLOC_H
 
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
 
 #endif
 
diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
index c71a7bc19284..aa57e35ce3cd 100644
--- a/arch/arm/mach-mx25/Kconfig
+++ b/arch/arm/mach-mx25/Kconfig
@@ -12,6 +12,8 @@ config MACH_EUKREA_CPUIMX25
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_FLEXCAN
+        select IMX_HAVE_PLATFORM_ESDHC
         select MXC_ULPI if USB_ULPI
 
 choice
@@ -20,8 +22,8 @@ choice
         default MACH_EUKREA_MBIMXSD25_BASEBOARD
 
 config MACH_EUKREA_MBIMXSD25_BASEBOARD
-        prompt "Eukrea MBIMXSD development board"
-        bool
+        bool "Eukrea MBIMXSD development board"
+        select IMX_HAVE_PLATFORM_IMX_SSI
         help
           This adds board specific devices that can be found on Eukrea's
           MBIMXSD evaluation board.
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 40c7cc41cee3..2179713873c2 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -139,6 +139,16 @@ static unsigned long get_rate_lcdc(struct clk *clk)
         return get_rate_per(7);
 }
 
+static unsigned long get_rate_esdhc1(struct clk *clk)
+{
+        return get_rate_per(3);
+}
+
+static unsigned long get_rate_esdhc2(struct clk *clk)
+{
+        return get_rate_per(4);
+}
+
 static unsigned long get_rate_csi(struct clk *clk)
 {
         return get_rate_per(0);
@@ -213,6 +223,12 @@ DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi2_clk,  0, CCM_CGCR1,  6, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(esdhc1_ahb_clk, 0, CCM_CGCR0, 21, get_rate_esdhc1,  NULL, NULL);
+DEFINE_CLOCK(esdhc1_per_clk, 0, CCM_CGCR0,  3, get_rate_esdhc1,  NULL,
+                &esdhc1_ahb_clk);
+DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2,  NULL, NULL);
+DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0,  4, get_rate_esdhc2,  NULL,
+                &esdhc2_ahb_clk);
 DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL,        NULL, NULL);
 DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL,       NULL, NULL);
 DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0,  7, NULL,       NULL, &lcdc_ahb_clk);
@@ -238,6 +254,10 @@ DEFINE_CLOCK(lcdc_clk,	 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
 DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR2, 19, get_rate_ipg, NULL,  NULL);
 DEFINE_CLOCK(ssi1_clk,  0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
 DEFINE_CLOCK(ssi2_clk,  1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
+DEFINE_CLOCK(esdhc1_clk,  0, CCM_CGCR1, 13, get_rate_esdhc1, NULL,
+                &esdhc1_per_clk);
+DEFINE_CLOCK(esdhc2_clk,  1, CCM_CGCR1, 14, get_rate_esdhc2, NULL,
+                &esdhc2_per_clk);
 DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
 DEFINE_CLOCK(csi_clk,    0, CCM_CGCR1,  4, get_rate_csi, NULL,  &csi_per_clk);
 DEFINE_CLOCK(can1_clk,   0, CCM_CGCR1,  2, get_rate_ipg, NULL, NULL);
@@ -261,9 +281,9 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
         _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
-        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
-        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
-        _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
+        _REGISTER_CLOCK("imx25-cspi.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("imx25-cspi.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("imx25-cspi.2", NULL, cspi3_clk)
         _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
         _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
         _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
@@ -279,6 +299,8 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
         _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
         _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
         _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h
index d86a7c3ca8b0..733aaee5bae8 100644
--- a/arch/arm/mach-mx25/devices-imx25.h
+++ b/arch/arm/mach-mx25/devices-imx25.h
@@ -9,35 +9,47 @@
 #include <mach/mx25.h>
 #include <mach/devices-common.h>
 
+extern const struct imx_fec_data imx25_fec_data __initconst;
+#define imx25_add_fec(pdata)    \
+        imx_add_fec(&imx25_fec_data, pdata)
+
 #define imx25_add_flexcan0(pdata)       \
         imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata)
 #define imx25_add_flexcan1(pdata)       \
         imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata)
 
-#define imx25_add_imx_i2c0(pdata)       \
-        imx_add_imx_i2c(0, MX25_I2C1_BASE_ADDR, SZ_16K, MX25_INT_I2C1, pdata)
-#define imx25_add_imx_i2c1(pdata)       \
-        imx_add_imx_i2c(1, MX25_I2C2_BASE_ADDR, SZ_16K, MX25_INT_I2C2, pdata)
-#define imx25_add_imx_i2c2(pdata)       \
-        imx_add_imx_i2c(2, MX25_I2C3_BASE_ADDR, SZ_16K, MX25_INT_I2C3, pdata)
-
-#define imx25_add_imx_uart0(pdata)      \
-        imx_add_imx_uart_1irq(0, MX25_UART1_BASE_ADDR, SZ_16K, MX25_INT_UART1, pdata)
-#define imx25_add_imx_uart1(pdata)      \
-        imx_add_imx_uart_1irq(1, MX25_UART2_BASE_ADDR, SZ_16K, MX25_INT_UART2, pdata)
-#define imx25_add_imx_uart2(pdata)      \
-        imx_add_imx_uart_1irq(2, MX25_UART3_BASE_ADDR, SZ_16K, MX25_INT_UART3, pdata)
-#define imx25_add_imx_uart3(pdata)      \
-        imx_add_imx_uart_1irq(3, MX25_UART4_BASE_ADDR, SZ_16K, MX25_INT_UART4, pdata)
-#define imx25_add_imx_uart4(pdata)      \
-        imx_add_imx_uart_1irq(4, MX25_UART5_BASE_ADDR, SZ_16K, MX25_INT_UART5, pdata)
+extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
+#define imx25_add_imx_i2c(id, pdata)    \
+        imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata)
+#define imx25_add_imx_i2c0(pdata)       imx25_add_imx_i2c(0, pdata)
+#define imx25_add_imx_i2c1(pdata)       imx25_add_imx_i2c(1, pdata)
+#define imx25_add_imx_i2c2(pdata)       imx25_add_imx_i2c(2, pdata)
+
+extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst;
+#define imx25_add_imx_ssi(id, pdata)    \
+        imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
+
+extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst;
+#define imx25_add_imx_uart(id, pdata)   \
+        imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata)
+#define imx25_add_imx_uart0(pdata)      imx25_add_imx_uart(0, pdata)
+#define imx25_add_imx_uart1(pdata)      imx25_add_imx_uart(1, pdata)
+#define imx25_add_imx_uart2(pdata)      imx25_add_imx_uart(2, pdata)
+#define imx25_add_imx_uart3(pdata)      imx25_add_imx_uart(3, pdata)
+#define imx25_add_imx_uart4(pdata)      imx25_add_imx_uart(4, pdata)
 
+extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst;
 #define imx25_add_mxc_nand(pdata)       \
-        imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata)
-
-#define imx25_add_spi_imx0(pdata)       \
-        imx_add_spi_imx(0, MX25_CSPI1_BASE_ADDR, SZ_16K, MX25_INT_CSPI1, pdata)
-#define imx25_add_spi_imx1(pdata)       \
-        imx_add_spi_imx(1, MX25_CSPI2_BASE_ADDR, SZ_16K, MX25_INT_CSPI2, pdata)
-#define imx25_add_spi_imx2(pdata)       \
-        imx_add_spi_imx(2, MX25_CSPI3_BASE_ADDR, SZ_16K, MX25_INT_CSPI3, pdata)
+        imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
+
+extern const struct imx_spi_imx_data imx25_spi_imx_data[] __initconst;
+#define imx25_add_spi_imx(id, pdata)    \
+        imx_add_spi_imx(&imx25_spi_imx_data[id], pdata)
+#define imx25_add_spi_imx0(pdata)       imx25_add_spi_imx(0, pdata)
+#define imx25_add_spi_imx1(pdata)       imx25_add_spi_imx(1, pdata)
+#define imx25_add_spi_imx2(pdata)       imx25_add_spi_imx(2, pdata)
+
+#define imx25_add_esdhc0(pdata) \
+        imx_add_esdhc(0, MX25_ESDHC1_BASE_ADDR, SZ_16K, MX25_INT_MMC_SDHC1, pdata)
+#define imx25_add_esdhc1(pdata) \
+        imx_add_esdhc(1, MX25_ESDHC2_BASE_ADDR, SZ_16K, MX25_INT_MMC_SDHC2, pdata)
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 3468eb15b236..1d0eb3e85941 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -208,26 +208,6 @@ int __init imx25_register_gpios(void)
         return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
 }
 
-static struct resource mx25_fec_resources[] = {
-        {
-                .start  = MX25_FEC_BASE_ADDR,
-                .end    = MX25_FEC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = MX25_INT_FEC,
-                .end    = MX25_INT_FEC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mx25_fec_device = {
-        .name   = "fec",
-        .id     = 0,
-        .num_resources  = ARRAY_SIZE(mx25_fec_resources),
-        .resource       = mx25_fec_resources,
-};
-
 static struct resource mx25_rtc_resources[] = {
         {
                 .start  = MX25_DRYICE_BASE_ADDR,
@@ -305,44 +285,6 @@ struct platform_device mx25_kpp_device = {
         .resource       = mx25_kpp_resources,
 };
 
-static struct resource imx_ssi_resources0[] = {
-        {
-                .start  = MX25_SSI1_BASE_ADDR,
-                .end    = MX25_SSI1_BASE_ADDR + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = MX25_INT_SSI1,
-                .end    = MX25_INT_SSI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource imx_ssi_resources1[] = {
-        {
-                .start  = MX25_SSI2_BASE_ADDR,
-                .end    = MX25_SSI2_BASE_ADDR + 0x3fff,
-                .flags  = IORESOURCE_MEM
-        }, {
-                .start  = MX25_INT_SSI2,
-                .end    = MX25_INT_SSI2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_ssi_device0 = {
-        .name = "imx-ssi",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(imx_ssi_resources0),
-        .resource = imx_ssi_resources0,
-};
-
-struct platform_device imx_ssi_device1 = {
-        .name = "imx-ssi",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(imx_ssi_resources1),
-        .resource = imx_ssi_resources1,
-};
-
 static struct resource mx25_csi_resources[] = {
         {
                 .start  = MX25_CSI_BASE_ADDR,
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index 4aceb68e35a7..7b70a43c3a4b 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -6,11 +6,8 @@ extern struct platform_device mxc_pwm_device1;
 extern struct platform_device mxc_pwm_device2;
 extern struct platform_device mxc_pwm_device3;
 extern struct platform_device mxc_keypad_device;
-extern struct platform_device mx25_fec_device;
 extern struct platform_device mx25_rtc_device;
 extern struct platform_device mx25_fb_device;
 extern struct platform_device mxc_wdt;
 extern struct platform_device mx25_kpp_device;
-extern struct platform_device imx_ssi_device0;
-extern struct platform_device imx_ssi_device1;
 extern struct platform_device mx25_csi_device;
diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
index 4aaadc753d3e..c1fe048c445e 100644
--- a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
@@ -34,7 +34,6 @@
 #include <mach/mx25.h>
 #include <mach/imx-uart.h>
 #include <mach/imxfb.h>
-#include <mach/ssi.h>
 #include <mach/audmux.h>
 
 #include "devices-imx25.h"
@@ -90,6 +89,9 @@ static struct pad_desc eukrea_mbimxsd_pads[] = {
         MX25_PAD_KPP_COL2__AUD5_TXC,
         MX25_PAD_KPP_COL1__AUD5_RXD,
         MX25_PAD_KPP_COL0__AUD5_TXD,
+        /* CAN */
+        MX25_PAD_GPIO_D__CAN2_RX,
+        MX25_PAD_GPIO_C__CAN2_TX,
 };
 
 #define GPIO_LED1       83
@@ -205,7 +207,8 @@ static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
         },
 };
 
-struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
+static const
+struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
         .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
 };
 
@@ -239,7 +242,10 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
 
         imx25_add_imx_uart1(&uart_pdata);
         mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata);
-        mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
+        imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
+
+        imx25_add_flexcan1(NULL);
+        imx25_add_esdhc0(NULL);
 
         gpio_request(GPIO_LED1, "LED1");
         gpio_direction_output(GPIO_LED1, 1);
diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-mx25/mach-cpuimx25.c
index e064bb3d6919..21d9b9e9c92c 100644
--- a/arch/arm/mach-mx25/mach-cpuimx25.c
+++ b/arch/arm/mach-mx25/mach-cpuimx25.c
@@ -23,7 +23,6 @@
 #include <linux/clk.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
-#include <linux/fec.h>
 #include <linux/platform_device.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
@@ -67,7 +66,7 @@ static struct pad_desc eukrea_cpuimx25_pads[] = {
         MX25_PAD_I2C1_DAT__I2C1_DAT,
 };
 
-static struct fec_platform_data mx25_fec_pdata = {
+static const struct fec_platform_data mx25_fec_pdata __initconst = {
         .phy    = PHY_INTERFACE_MODE_RMII,
 };
 
@@ -129,7 +128,7 @@ static void __init eukrea_cpuimx25_init(void)
         imx25_add_imx_uart0(&uart_pdata);
         imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
         mxc_register_device(&mx25_rtc_device, NULL);
-        mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
+        imx25_add_fec(&mx25_fec_pdata);
 
         i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
                                 ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
diff --git a/arch/arm/mach-mx25/mach-mx25_3ds.c b/arch/arm/mach-mx25/mach-mx25_3ds.c
index 62bc21f11a71..bd1805698631 100644
--- a/arch/arm/mach-mx25/mach-mx25_3ds.c
+++ b/arch/arm/mach-mx25/mach-mx25_3ds.c
@@ -28,7 +28,6 @@
 #include <linux/clk.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
-#include <linux/fec.h>
 #include <linux/platform_device.h>
 #include <linux/input/matrix_keypad.h>
 
@@ -99,7 +98,7 @@ static struct pad_desc mx25pdk_pads[] = {
         MX25_PAD_KPP_COL3__KPP_COL3,
 };
 
-static struct fec_platform_data mx25_fec_pdata = {
+static const struct fec_platform_data mx25_fec_pdata __initconst = {
         .phy    = PHY_INTERFACE_MODE_RMII,
 };
 
@@ -192,7 +191,7 @@ static void __init mx25pdk_init(void)
         mxc_register_device(&mxc_wdt, NULL);
 
         mx25pdk_fec_reset();
-        mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
+        imx25_add_fec(&mx25_fec_pdata);
         mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
 }
 
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 85beece802aa..096fd33f8ab9 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -9,6 +9,7 @@ config ARCH_MX35
         bool
         select ARCH_MXC_IOMUX_V3
         select ARCH_MXC_AUDMUX_V2
+        select HAVE_EPIT
 
 comment "MX3 platforms:"
 
@@ -16,6 +17,7 @@ config MACH_MX31ADS
         bool "Support MX31ADS platforms"
         select ARCH_MX31
         select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
         default y
         help
@@ -117,9 +119,11 @@ config MACH_PCM043
         bool "Support Phytec pcm043 (i.MX35) platforms"
         select ARCH_MX35
         select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_FLEXCAN
+        select IMX_HAVE_PLATFORM_ESDHC
         select MXC_ULPI if USB_ULPI
         help
           Include support for Phytec pcm043 platform. This includes
@@ -140,6 +144,7 @@ config MACH_MX35_3DS
         bool "Support MX35PDK platform"
         select ARCH_MX35
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
         default n
         help
           Include support for MX35PDK platform. This includes specific
@@ -159,6 +164,8 @@ config MACH_EUKREA_CPUIMX35
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_FLEXCAN
+        select IMX_HAVE_PLATFORM_ESDHC
         select MXC_ULPI if USB_ULPI
         help
           Include support for Eukrea CPUIMX35 platform. This includes
@@ -170,8 +177,8 @@ choice
         default MACH_EUKREA_MBIMXSD35_BASEBOARD
 
 config MACH_EUKREA_MBIMXSD35_BASEBOARD
-        prompt "Eukrea MBIMXSD development board"
-        bool
+        bool "Eukrea MBIMXSD development board"
+        select IMX_HAVE_PLATFORM_IMX_SSI
         help
           This adds board specific devices that can be found on Eukrea's
           MBIMXSD evaluation board.
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 2bd7beceb991..8a182d0a3fcf 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -7,7 +7,6 @@
 obj-y                           := mm.o devices.o cpu.o
 CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
 CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
-CFLAGS_cpu.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
 obj-$(CONFIG_ARCH_MX31)         += clock-imx31.o iomux-imx31.o
 obj-$(CONFIG_ARCH_MX35)         += clock-imx35.o
 obj-$(CONFIG_MACH_MX31ADS)      += mach-mx31ads.o
diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c
index 9a9eb6de6127..109e98f323e0 100644
--- a/arch/arm/mach-mx3/clock-imx31.c
+++ b/arch/arm/mach-mx3/clock-imx31.c
@@ -477,7 +477,7 @@ DEFINE_CLOCK(epit1_clk,   0, MXC_CCM_CGR0,  6, NULL, NULL, &perclk_clk);
 DEFINE_CLOCK(epit2_clk,   1, MXC_CCM_CGR0,  8, NULL, NULL, &perclk_clk);
 DEFINE_CLOCK(iim_clk,     0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(ata_clk,     0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(sdma_clk1,   0, MXC_CCM_CGR0, 14, NULL, &sdma_clk1, &ahb_clk);
+DEFINE_CLOCK(sdma_clk1,   0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk);
 DEFINE_CLOCK(cspi3_clk,   2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(rng_clk,     0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(uart1_clk,   0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
@@ -525,9 +525,9 @@ DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);
 
 static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "emi", emi_clk)
-        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
-        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
-        _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
+        _REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
         _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
         _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
@@ -564,7 +564,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "ata", ata_clk)
         _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
         _REGISTER_CLOCK(NULL, "rng", rng_clk)
-        _REGISTER_CLOCK(NULL, "sdma_ahb", sdma_clk1)
+        _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk1)
         _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
         _REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
         _REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 7a62e744a8b0..61e4a318980a 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -364,8 +364,8 @@ DEFINE_CLOCK(cspi2_clk,  1, CCM_CGR0, 12, get_rate_ipg, NULL);
 DEFINE_CLOCK(ect_clk,    0, CCM_CGR0, 14, get_rate_ipg, NULL);
 DEFINE_CLOCK(edio_clk,   0, CCM_CGR0, 16, NULL, NULL);
 DEFINE_CLOCK(emi_clk,    0, CCM_CGR0, 18, get_rate_ipg, NULL);
-DEFINE_CLOCK(epit1_clk,  0, CCM_CGR0, 20, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(epit2_clk,  1, CCM_CGR0, 22, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(epit1_clk,  0, CCM_CGR0, 20, get_rate_ipg, NULL);
+DEFINE_CLOCK(epit2_clk,  1, CCM_CGR0, 22, get_rate_ipg, NULL);
 DEFINE_CLOCK(esai_clk,   0, CCM_CGR0, 24, NULL, NULL);
 DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL);
 DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL);
@@ -451,17 +451,17 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "ata", ata_clk)
         _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
         _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
-        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
-        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
         _REGISTER_CLOCK(NULL, "ect", ect_clk)
         _REGISTER_CLOCK(NULL, "edio", edio_clk)
         _REGISTER_CLOCK(NULL, "emi", emi_clk)
-        _REGISTER_CLOCK(NULL, "epit", epit1_clk)
-        _REGISTER_CLOCK(NULL, "epit", epit2_clk)
+        _REGISTER_CLOCK("imx-epit.0", NULL, epit1_clk)
+        _REGISTER_CLOCK("imx-epit.1", NULL, epit2_clk)
         _REGISTER_CLOCK(NULL, "esai", esai_clk)
-        _REGISTER_CLOCK(NULL, "sdhc", esdhc1_clk)
-        _REGISTER_CLOCK(NULL, "sdhc", esdhc2_clk)
-        _REGISTER_CLOCK(NULL, "sdhc", esdhc3_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
         _REGISTER_CLOCK(NULL, "gpio", gpio1_clk)
         _REGISTER_CLOCK(NULL, "gpio", gpio2_clk)
@@ -482,7 +482,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
         _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
         _REGISTER_CLOCK(NULL, "scc", scc_clk)
-        _REGISTER_CLOCK(NULL, "sdma", sdma_clk)
+        _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
         _REGISTER_CLOCK(NULL, "spba", spba_clk)
         _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
@@ -535,8 +535,16 @@ int __init mx35_clocks_init()
         __raw_writel(cgr2, CCM_BASE + CCM_CGR2);
         __raw_writel(cgr3, CCM_BASE + CCM_CGR3);
 
+        clk_enable(&iim_clk);
+        mx35_read_cpu_rev();
+
+#ifdef CONFIG_MXC_USE_EPIT
+        epit_timer_init(&epit1_clk,
+                        MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
+#else
         mxc_timer_init(&gpt_clk,
                         MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
+#endif
 
         return 0;
 }
diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c
index 861afe0fe3ad..d00a75457812 100644
--- a/arch/arm/mach-mx3/cpu.c
+++ b/arch/arm/mach-mx3/cpu.c
@@ -25,15 +25,15 @@ struct mx3_cpu_type {
 };
 
 static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
-        { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = CHIP_REV_1_0   },
-        { .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = CHIP_REV_1_1   },
-        { .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = CHIP_REV_1_1   },
-        { .srev = 0x12, .name = "i.MX31",    .v = "1.15", .rev = CHIP_REV_1_1   },
-        { .srev = 0x13, .name = "i.MX31L",   .v = "1.15", .rev = CHIP_REV_1_1   },
-        { .srev = 0x14, .name = "i.MX31",    .v = "1.2",  .rev = CHIP_REV_1_2   },
-        { .srev = 0x15, .name = "i.MX31L",   .v = "1.2",  .rev = CHIP_REV_1_2   },
-        { .srev = 0x28, .name = "i.MX31",    .v = "2.0",  .rev = CHIP_REV_2_0   },
-        { .srev = 0x29, .name = "i.MX31L",   .v = "2.0",  .rev = CHIP_REV_2_0   },
+        { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = MX3x_CHIP_REV_1_0 },
+        { .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = MX3x_CHIP_REV_1_1 },
+        { .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = MX3x_CHIP_REV_1_1 },
+        { .srev = 0x12, .name = "i.MX31",    .v = "1.15", .rev = MX3x_CHIP_REV_1_1 },
+        { .srev = 0x13, .name = "i.MX31L",   .v = "1.15", .rev = MX3x_CHIP_REV_1_1 },
+        { .srev = 0x14, .name = "i.MX31",    .v = "1.2",  .rev = MX3x_CHIP_REV_1_2 },
+        { .srev = 0x15, .name = "i.MX31L",   .v = "1.2",  .rev = MX3x_CHIP_REV_1_2 },
+        { .srev = 0x28, .name = "i.MX31",    .v = "2.0",  .rev = MX3x_CHIP_REV_2_0 },
+        { .srev = 0x29, .name = "i.MX31L",   .v = "2.0",  .rev = MX3x_CHIP_REV_2_0 },
 };
 
 void __init mx31_read_cpu_rev(void)
@@ -41,7 +41,7 @@ void __init mx31_read_cpu_rev(void)
         u32 i, srev;
 
         /* read SREV register from IIM module */
-        srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR + MXC_IIMSREV));
+        srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
 
         for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
                 if (srev == mx31_cpu_type[i].srev) {
@@ -55,3 +55,30 @@ void __init mx31_read_cpu_rev(void)
 
         printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
 }
+
+unsigned int mx35_cpu_rev;
+EXPORT_SYMBOL(mx35_cpu_rev);
+
+void __init mx35_read_cpu_rev(void)
+{
+        u32 rev;
+        char *srev = "unknown";
+
+        rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
+        switch (rev) {
+        case 0x00:
+                mx35_cpu_rev = MX3x_CHIP_REV_1_0;
+                srev = "1.0";
+                break;
+        case 0x10:
+                mx35_cpu_rev = MX3x_CHIP_REV_2_0;
+                srev = "2.0";
+                break;
+        case 0x11:
+                mx35_cpu_rev = MX3x_CHIP_REV_2_1;
+                srev = "2.1";
+                break;
+        }
+
+        printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
+}
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
index 3b1a44a20585..de9598590eba 100644
--- a/arch/arm/mach-mx3/devices-imx31.h
+++ b/arch/arm/mach-mx3/devices-imx31.h
@@ -9,30 +9,33 @@
 #include <mach/mx31.h>
 #include <mach/devices-common.h>
 
-#define imx31_add_imx_i2c0(pdata)       \
-        imx_add_imx_i2c(0, MX31_I2C1_BASE_ADDR, SZ_4K, MX31_INT_I2C1, pdata)
-#define imx31_add_imx_i2c1(pdata)       \
-        imx_add_imx_i2c(1, MX31_I2C2_BASE_ADDR, SZ_4K, MX31_INT_I2C2, pdata)
-#define imx31_add_imx_i2c2(pdata)       \
-        imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3, pdata)
+extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
+#define imx31_add_imx_i2c(id, pdata)    \
+        imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
+#define imx31_add_imx_i2c0(pdata)       imx31_add_imx_i2c(0, pdata)
+#define imx31_add_imx_i2c1(pdata)       imx31_add_imx_i2c(1, pdata)
+#define imx31_add_imx_i2c2(pdata)       imx31_add_imx_i2c(2, pdata)
 
-#define imx31_add_imx_uart0(pdata)      \
-        imx_add_imx_uart_1irq(0, MX31_UART1_BASE_ADDR, SZ_16K, MX31_INT_UART1, pdata)
-#define imx31_add_imx_uart1(pdata)      \
-        imx_add_imx_uart_1irq(1, MX31_UART2_BASE_ADDR, SZ_16K, MX31_INT_UART2, pdata)
-#define imx31_add_imx_uart2(pdata)      \
-        imx_add_imx_uart_1irq(2, MX31_UART3_BASE_ADDR, SZ_16K, MX31_INT_UART3, pdata)
-#define imx31_add_imx_uart3(pdata)      \
-        imx_add_imx_uart_1irq(3, MX31_UART4_BASE_ADDR, SZ_16K, MX31_INT_UART4, pdata)
-#define imx31_add_imx_uart4(pdata)      \
-        imx_add_imx_uart_1irq(4, MX31_UART5_BASE_ADDR, SZ_16K, MX31_INT_UART5, pdata)
+extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst;
+#define imx31_add_imx_ssi(id, pdata)    \
+        imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
 
+extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
+#define imx31_add_imx_uart(id, pdata)   \
+        imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata)
+#define imx31_add_imx_uart0(pdata)      imx31_add_imx_uart(0, pdata)
+#define imx31_add_imx_uart1(pdata)      imx31_add_imx_uart(1, pdata)
+#define imx31_add_imx_uart2(pdata)      imx31_add_imx_uart(2, pdata)
+#define imx31_add_imx_uart3(pdata)      imx31_add_imx_uart(3, pdata)
+#define imx31_add_imx_uart4(pdata)      imx31_add_imx_uart(4, pdata)
+
+extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst;
 #define imx31_add_mxc_nand(pdata)       \
-        imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata)
+        imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
 
-#define imx31_add_spi_imx0(pdata)       \
-        imx_add_spi_imx(0, MX31_CSPI1_BASE_ADDR, SZ_4K, MX31_INT_CSPI1, pdata)
-#define imx31_add_spi_imx1(pdata)       \
-        imx_add_spi_imx(1, MX31_CSPI2_BASE_ADDR, SZ_4K, MX31_INT_CSPI2, pdata)
-#define imx31_add_spi_imx2(pdata)       \
-        imx_add_spi_imx(2, MX31_CSPI3_BASE_ADDR, SZ_4K, MX31_INT_CSPI3, pdata)
+extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst;
+#define imx31_add_cspi(id, pdata)       \
+        imx_add_spi_imx(&imx31_cspi_data[id], pdata)
+#define imx31_add_spi_imx0(pdata)       imx31_add_cspi(0, pdata)
+#define imx31_add_spi_imx1(pdata)       imx31_add_cspi(1, pdata)
+#define imx31_add_spi_imx2(pdata)       imx31_add_cspi(2, pdata)
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
index f6a431a4c3d2..509b346b7fef 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -9,29 +9,46 @@
 #include <mach/mx35.h>
 #include <mach/devices-common.h>
 
+extern const struct imx_fec_data imx35_fec_data __initconst;
+#define imx35_add_fec(pdata)    \
+        imx_add_fec(&imx35_fec_data, pdata)
+
 #define imx35_add_flexcan0(pdata)       \
         imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata)
 #define imx35_add_flexcan1(pdata)       \
         imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata)
 
-#define imx35_add_imx_i2c0(pdata)       \
-        imx_add_imx_i2c(0, MX35_I2C1_BASE_ADDR, SZ_4K, MX35_INT_I2C1, pdata)
-#define imx35_add_imx_i2c1(pdata)       \
-        imx_add_imx_i2c(1, MX35_I2C2_BASE_ADDR, SZ_4K, MX35_INT_I2C2, pdata)
-#define imx35_add_imx_i2c2(pdata)       \
-        imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata)
+extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
+#define imx35_add_imx_i2c(id, pdata)    \
+        imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata)
+#define imx35_add_imx_i2c0(pdata)       imx35_add_imx_i2c(0, pdata)
+#define imx35_add_imx_i2c1(pdata)       imx35_add_imx_i2c(1, pdata)
+#define imx35_add_imx_i2c2(pdata)       imx35_add_imx_i2c(2, pdata)
+
+extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
+#define imx35_add_imx_ssi(id, pdata)    \
+        imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
 
-#define imx35_add_imx_uart0(pdata)      \
-        imx_add_imx_uart_1irq(0, MX35_UART1_BASE_ADDR, SZ_16K, MX35_INT_UART1, pdata)
-#define imx35_add_imx_uart1(pdata)      \
-        imx_add_imx_uart_1irq(1, MX35_UART2_BASE_ADDR, SZ_16K, MX35_INT_UART2, pdata)
-#define imx35_add_imx_uart2(pdata)      \
-        imx_add_imx_uart_1irq(2, MX35_UART3_BASE_ADDR, SZ_16K, MX35_INT_UART3, pdata)
+extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst;
+#define imx35_add_imx_uart(id, pdata)   \
+        imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata)
+#define imx35_add_imx_uart0(pdata)      imx35_add_imx_uart(0, pdata)
+#define imx35_add_imx_uart1(pdata)      imx35_add_imx_uart(1, pdata)
+#define imx35_add_imx_uart2(pdata)      imx35_add_imx_uart(2, pdata)
 
+extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst;
 #define imx35_add_mxc_nand(pdata)       \
-        imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata)
+        imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
+
+extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst;
+#define imx35_add_cspi(id, pdata)       \
+        imx_add_spi_imx(&imx35_cspi_data[id], pdata)
+#define imx35_add_spi_imx0(pdata)       imx35_add_cspi(0, pdata)
+#define imx35_add_spi_imx1(pdata)       imx35_add_cspi(1, pdata)
 
-#define imx35_add_spi_imx0(pdata)       \
-        imx_add_spi_imx(0, MX35_CSPI1_BASE_ADDR, SZ_4K, MX35_INT_CSPI1, pdata)
-#define imx35_add_spi_imx1(pdata)       \
-        imx_add_spi_imx(1, MX35_CSPI2_BASE_ADDR, SZ_4K, MX35_INT_CSPI2, pdata)
+#define imx35_add_esdhc0(pdata) \
+        imx_add_esdhc(0, MX35_ESDHC1_BASE_ADDR, SZ_16K, MX35_INT_MMC_SDHC1, pdata)
+#define imx35_add_esdhc1(pdata) \
+        imx_add_esdhc(1, MX35_ESDHC2_BASE_ADDR, SZ_16K, MX35_INT_MMC_SDHC2, pdata)
+#define imx35_add_esdhc2(pdata) \
+        imx_add_esdhc(2, MX35_ESDHC3_BASE_ADDR, SZ_16K, MX35_INT_MMC_SDHC3, pdata)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index a4fd1a26fc91..f4dff11aaee7 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -281,65 +281,6 @@ struct platform_device mxc_usbh2 = {
         .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
 };
 
-#if defined(CONFIG_ARCH_MX35)
-static struct resource mxc_fec_resources[] = {
-        {
-                .start  = MXC_FEC_BASE_ADDR,
-                .end    = MXC_FEC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = MXC_INT_FEC,
-                .end    = MXC_INT_FEC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_fec_device = {
-        .name = "fec",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_fec_resources),
-        .resource = mxc_fec_resources,
-};
-#endif
-
-static struct resource imx_ssi_resources0[] = {
-        {
-                .start  = SSI1_BASE_ADDR,
-                .end    = SSI1_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = MX31_INT_SSI1,
-                .end    = MX31_INT_SSI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource imx_ssi_resources1[] = {
-        {
-                .start  = SSI2_BASE_ADDR,
-                .end    = SSI2_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM
-        }, {
-                .start  = MX31_INT_SSI2,
-                .end    = MX31_INT_SSI2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_ssi_device0 = {
-        .name = "imx-ssi",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(imx_ssi_resources0),
-        .resource = imx_ssi_resources0,
-};
-
-struct platform_device imx_ssi_device1 = {
-        .name = "imx-ssi",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(imx_ssi_resources1),
-        .resource = imx_ssi_resources1,
-};
-
 static struct resource imx_wdt_resources[] = {
         {
                 .flags = IORESOURCE_MEM,
@@ -410,10 +351,6 @@ static int __init mx3_devices_init(void)
                 mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
                 mxc_usbh1_resources[1].start = MXC_INT_USBHS;
                 mxc_usbh1_resources[1].end = MXC_INT_USBHS;
-                imx_ssi_resources0[1].start = MX35_INT_SSI1;
-                imx_ssi_resources0[1].end = MX35_INT_SSI1;
-                imx_ssi_resources1[1].start = MX35_INT_SSI2;
-                imx_ssi_resources1[1].end = MX35_INT_SSI2;
                 imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
                 imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
         }
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index e5535234839f..585f814473d5 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -2,7 +2,6 @@ extern struct platform_device mxc_w1_master_device;
 extern struct platform_device mx3_ipu;
 extern struct platform_device mx3_fb;
 extern struct platform_device mx3_camera;
-extern struct platform_device mxc_fec_device;
 extern struct platform_device mxcsdhc_device0;
 extern struct platform_device mxcsdhc_device1;
 extern struct platform_device mxc_otg_udc_device;
@@ -10,9 +9,6 @@ extern struct platform_device mxc_otg_host;
 extern struct platform_device mxc_usbh1;
 extern struct platform_device mxc_usbh2;
 extern struct platform_device mxc_rnga_device;
-extern struct platform_device imx_ssi_device0;
-extern struct platform_device imx_ssi_device1;
-extern struct platform_device imx_ssi_device1;
 extern struct platform_device imx_wdt_device0;
 extern struct platform_device imx_rtc_device0;
 extern struct platform_device imx_kpp_device;
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
index f8f15e3ac7a0..886959906fbc 100644
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -43,7 +43,6 @@
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
 #include <mach/audmux.h>
-#include <mach/ssi.h>
 
 #include "devices-imx35.h"
 #include "devices.h"
@@ -120,6 +119,16 @@ static struct pad_desc eukrea_mbimxsd_pads[] = {
         MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
         MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
         MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
+        /* CAN2 */
+        MX35_PAD_TX5_RX0__CAN2_TXCAN,
+        MX35_PAD_TX4_RX1__CAN2_RXCAN,
+        /* SDCARD */
+        MX35_PAD_SD1_CMD__ESDHC1_CMD,
+        MX35_PAD_SD1_CLK__ESDHC1_CLK,
+        MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+        MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+        MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+        MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
 };
 
 #define GPIO_LED1       (2 * 32 + 29)
@@ -206,7 +215,8 @@ static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
         },
 };
 
-struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
+static const
+struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
         .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
 };
 
@@ -242,7 +252,10 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
         mxc_register_device(&mx3_ipu, &mx3_ipu_data);
         mxc_register_device(&mx3_fb, &mx3fb_pdata);
 
-        mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
+        imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
+
+        imx35_add_flexcan1(NULL);
+        imx35_add_esdhc0(NULL);
 
         gpio_request(GPIO_LED1, "LED1");
         gpio_direction_output(GPIO_LED1, 1);
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
index 2a4f8b781ba4..6024bb958eea 100644
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -31,6 +31,7 @@
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
 #include <linux/fsl_devices.h>
+#include <linux/i2c-gpio.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -53,39 +54,16 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
 };
 
 static const struct imxi2c_platform_data
-eukrea_cpuimx35_i2c0_data __initconst = {
-        .bitrate = 50000,
+                eukrea_cpuimx35_i2c0_data __initconst = {
+        .bitrate =              100000,
 };
 
-#define TSC2007_IRQGPIO         (2 * 32 + 2)
-static int ts_get_pendown_state(void)
-{
-        int val = 0;
-        gpio_free(TSC2007_IRQGPIO);
-        gpio_request(TSC2007_IRQGPIO, NULL);
-        gpio_direction_input(TSC2007_IRQGPIO);
-
-        val = gpio_get_value(TSC2007_IRQGPIO);
-
-        gpio_free(TSC2007_IRQGPIO);
-        gpio_request(TSC2007_IRQGPIO, NULL);
-
-        return val ? 0 : 1;
-}
-
-static int ts_init(void)
-{
-        gpio_request(TSC2007_IRQGPIO, NULL);
-        return 0;
-}
-
 static struct tsc2007_platform_data tsc2007_info = {
         .model                  = 2007,
         .x_plate_ohms           = 180,
-        .get_pendown_state      = ts_get_pendown_state,
-        .init_platform_hw       = ts_init,
 };
 
+#define TSC2007_IRQGPIO         (2 * 32 + 2)
 static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("pcf8563", 0x51),
@@ -98,7 +76,6 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
 };
 
 static struct platform_device *devices[] __initdata = {
-        &mxc_fec_device,
         &imx_wdt_device0,
 };
 
@@ -135,18 +112,18 @@ static struct pad_desc eukrea_cpuimx35_pads[] = {
 };
 
 static const struct mxc_nand_platform_data
-eukrea_cpuimx35_nand_board_info __initconst = {
+                eukrea_cpuimx35_nand_board_info __initconst = {
         .width          = 1,
         .hw_ecc         = 1,
         .flash_bbt      = 1,
 };
 
-static struct mxc_usbh_platform_data otg_pdata = {
+static struct mxc_usbh_platform_data __maybe_unused otg_pdata = {
         .portsc = MXC_EHCI_MODE_UTMI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 
-static struct mxc_usbh_platform_data usbh1_pdata = {
+static struct mxc_usbh_platform_data __maybe_unused usbh1_pdata = {
         .portsc = MXC_EHCI_MODE_SERIAL,
         .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
                   MXC_EHCI_IPPUE_DOWN,
@@ -180,6 +157,7 @@ static void __init mxc_board_init(void)
         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
                         ARRAY_SIZE(eukrea_cpuimx35_pads));
 
+        imx35_add_fec(NULL);
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         imx35_add_imx_uart0(&uart_pdata);
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index 94b3e7c42404..96cedc4a47f5 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -517,7 +517,7 @@ static unsigned int ssi_pins[] = {
 
 static void mxc_init_audio(void)
 {
-        mxc_register_device(&imx_ssi_device0, NULL);
+        imx31_add_imx_ssi(0, NULL);
         mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
 }
 
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
index 1c30d7212f17..91bb06552af1 100644
--- a/arch/arm/mach-mx3/mach-mx35_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -1,5 +1,6 @@
 /*
  * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix
  *
  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  *
@@ -27,6 +28,8 @@
 #include <linux/gpio.h>
 #include <linux/fsl_devices.h>
 
+#include <linux/mtd/physmap.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -35,6 +38,7 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
+#include <mach/mxc_ehci.h>
 
 #include "devices-imx35.h"
 #include "devices.h"
@@ -43,8 +47,34 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
+static struct physmap_flash_data mx35pdk_flash_data = {
+        .width  = 2,
+};
+
+static struct resource mx35pdk_flash_resource = {
+        .start  = MX35_CS0_BASE_ADDR,
+        .end    = MX35_CS0_BASE_ADDR + SZ_64M - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device mx35pdk_flash = {
+        .name   = "physmap-flash",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &mx35pdk_flash_data,
+        },
+        .resource = &mx35pdk_flash_resource,
+        .num_resources = 1,
+};
+
+static const struct mxc_nand_platform_data mx35pdk_nand_board_info __initconst = {
+        .width = 1,
+        .hw_ecc = 1,
+        .flash_bbt = 1,
+};
+
 static struct platform_device *devices[] __initdata = {
-        &mxc_fec_device,
+        &mx35pdk_flash,
 };
 
 static struct pad_desc mx35pdk_pads[] = {
@@ -75,14 +105,24 @@ static struct pad_desc mx35pdk_pads[] = {
         /* USBOTG */
         MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
         MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
+        /* USBH1 */
+        MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
+        MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
 };
 
 /* OTG config */
-static struct fsl_usb2_platform_data usb_pdata = {
+static struct fsl_usb2_platform_data usb_otg_pdata = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 };
 
+/* USB HOST config */
+static struct mxc_usbh_platform_data usb_host_pdata = {
+        .portsc         = MXC_EHCI_MODE_SERIAL,
+        .flags          = MXC_EHCI_INTERFACE_SINGLE_UNI |
+                          MXC_EHCI_INTERNAL_PHY,
+};
+
 /*
  * Board specific initialization.
  */
@@ -90,11 +130,16 @@ static void __init mxc_board_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
 
+        imx35_add_fec(NULL);
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         imx35_add_imx_uart0(&uart_pdata);
 
-        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
+        mxc_register_device(&mxc_otg_udc_device, &usb_otg_pdata);
+
+        mxc_register_device(&mxc_usbh1, &usb_host_pdata);
+
+        imx35_add_mxc_nand(&mx35pdk_nand_board_info);
 }
 
 static void __init mx35pdk_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 28886f0e62f9..e790a00cf99f 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -42,7 +42,6 @@
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 #include <mach/audmux.h>
-#include <mach/ssi.h>
 
 #include "devices-imx35.h"
 #include "devices.h"
@@ -141,7 +140,6 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
 
 static struct platform_device *devices[] __initdata = {
         &pcm043_flash,
-        &mxc_fec_device,
         &imx_wdt_device0,
 };
 
@@ -217,6 +215,13 @@ static struct pad_desc pcm043_pads[] = {
         /* CAN2 */
         MX35_PAD_TX5_RX0__CAN2_TXCAN,
         MX35_PAD_TX4_RX1__CAN2_RXCAN,
+        /* esdhc */
+        MX35_PAD_SD1_CMD__ESDHC1_CMD,
+        MX35_PAD_SD1_CLK__ESDHC1_CLK,
+        MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+        MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+        MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+        MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
 };
 
 #define AC97_GPIO_TXFS  (1 * 32 + 31)
@@ -293,7 +298,7 @@ err1:
         mdelay(1);
 }
 
-static struct imx_ssi_platform_data pcm043_ssi_pdata = {
+static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
         .ac97_reset = pcm043_ac97_cold_reset,
         .ac97_warm_reset = pcm043_ac97_warm_reset,
         .flags = IMX_SSI_USE_AC97,
@@ -357,11 +362,12 @@ static void __init mxc_board_init(void)
                         MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
                         MXC_AUDMUX_V2_PDCR_RXDSEL(3));
 
+        imx35_add_fec(NULL);
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         imx35_add_imx_uart0(&uart_pdata);
         imx35_add_mxc_nand(&pcm037_nand_board_info);
-        mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata);
+        imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
 
         imx35_add_imx_uart1(&uart_pdata);
 
@@ -389,6 +395,7 @@ static void __init mxc_board_init(void)
                 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
 
         imx35_add_flexcan1(NULL);
+        imx35_add_esdhc0(NULL);
 }
 
 static void __init pcm043_timer_init(void)
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 20e48c0195c4..b4ffc531a82c 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -110,6 +110,24 @@ void __init mx35_init_irq(void)
 static int mxc_init_l2x0(void)
 {
         void __iomem *l2x0_base;
+        void __iomem *clkctl_base;
+/*
+ * First of all, we must repair broken chip settings. There are some
+ * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
+ * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
+ * Workaraound is to setup the correct register setting prior enabling the
+ * L2 cache. This should not hurt already working CPUs, as they are using the
+ * same value
+ */
+#define L2_MEM_VAL 0x10
+
+        clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
+        if (clkctl_base != NULL) {
+                writel(0x00000515, clkctl_base + L2_MEM_VAL);
+                iounmap(clkctl_base);
+        } else {
+                pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
+        }
 
         l2x0_base = ioremap(L2CC_BASE_ADDR, 4096);
         if (IS_ERR(l2x0_base)) {
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 0848db5dd364..fad31cc5004b 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -5,11 +5,14 @@ config ARCH_MX51
         default y
         select MXC_TZIC
         select ARCH_MXC_IOMUX_V3
+        select ARCH_MXC_AUDMUX_V2
 
 comment "MX5 platforms:"
 
 config MACH_MX51_BABBAGE
         bool "Support MX51 BABBAGE platforms"
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for MX51 Babbage platform, also known as MX51EVK in
           u-boot. This includes specific configurations for the board and its
@@ -17,6 +20,8 @@ config MACH_MX51_BABBAGE
 
 config MACH_MX51_3DS
         bool "Support MX51PDK (3DS)"
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_DEBUG_BOARD
         help
           Include support for MX51PDK (3DS) platform. This includes specific
@@ -24,6 +29,8 @@ config MACH_MX51_3DS
 
 config MACH_EUKREA_CPUIMX51
         bool "Support Eukrea CPUIMX51 module"
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for Eukrea CPUIMX51 platform. This includes
           specific configurations for the module and its peripherals.
@@ -42,4 +49,11 @@ config MACH_EUKREA_MBIMX51_BASEBOARD
 
 endchoice
 
+config MACH_MX51_EFIKAMX
+        bool "Support MX51 Genesi Efika MX nettop"
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Include support for Genesi Efika MX nettop. This includes specific
+          configurations for the board and its peripherals.
+
 endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 86c66e7f52f3..d1aac9c3d33c 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
 obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
+obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index 623607a20f57..61f051043bbc 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -28,9 +28,7 @@
 #include <mach/eukrea-baseboards.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx51.h>
-#include <mach/i2c.h>
 #include <mach/mxc_ehci.h>
 
 #include <asm/irq.h>
@@ -39,6 +37,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
+#include "devices-imx51.h"
 #include "devices.h"
 
 #define CPUIMX51_USBH1_STP      (0*32 + 27)
@@ -109,7 +108,6 @@ static struct platform_device serial_device = {
 #endif
 
 static struct platform_device *devices[] __initdata = {
-        &mxc_fec_device,
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
         &serial_device,
 #endif
@@ -148,11 +146,12 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
         MX51_PAD_USBH1_STP__USBH1_STP,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct imxi2c_platform_data eukrea_cpuimx51_i2c_data = {
+static const
+struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -239,7 +238,7 @@ static void __init eukrea_cpuimx51_init(void)
         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
                                         ARRAY_SIZE(eukrea_cpuimx51_pads));
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx51_add_imx_uart(0, &uart_pdata);
         gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
         gpio_direction_input(CPUIMX51_QUARTA_GPIO);
         gpio_free(CPUIMX51_QUARTA_GPIO);
@@ -253,9 +252,10 @@ static void __init eukrea_cpuimx51_init(void)
         gpio_direction_input(CPUIMX51_QUARTD_GPIO);
         gpio_free(CPUIMX51_QUARTD_GPIO);
 
+        imx51_add_fec(NULL);
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        mxc_register_device(&mxc_i2c_device1, &eukrea_cpuimx51_i2c_data);
+        imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
         i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
                                 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
 
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index f95c2fd94667..ed08a2352a1a 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -13,6 +13,7 @@
 #include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/spi/spi.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -21,12 +22,13 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx51.h>
-#include <mach/imx-uart.h>
 #include <mach/3ds_debugboard.h>
 
+#include "devices-imx51.h"
 #include "devices.h"
 
 #define EXPIO_PARENT_INT        (MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
+#define MX51_3DS_ECSPI2_CS      (GPIO_PORTC + 28)
 
 static struct pad_desc mx51_3ds_pads[] = {
         /* UART1 */
@@ -61,19 +63,25 @@ static struct pad_desc mx51_3ds_pads[] = {
         MX51_PAD_KEY_COL3__KEY_COL3,
         MX51_PAD_KEY_COL4__KEY_COL4,
         MX51_PAD_KEY_COL5__KEY_COL5,
+
+        /* eCSPI2 */
+        MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
+        MX51_PAD_NANDF_RB3__ECSPI2_MISO,
+        MX51_PAD_NANDF_D15__ECSPI2_MOSI,
+        MX51_PAD_NANDF_D12__GPIO_3_28,
 };
 
 /* Serial ports */
 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static inline void mxc_init_imx_uart(void)
 {
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_imx_uart(1, &uart_pdata);
+        imx51_add_imx_uart(2, &uart_pdata);
 }
 #else /* !SERIAL_IMX */
 static inline void mxc_init_imx_uart(void)
@@ -127,6 +135,26 @@ static inline void mxc_init_keypad(void)
 }
 #endif
 
+static int mx51_3ds_spi2_cs[] = {
+        MXC_SPI_CS(0),
+        MX51_3DS_ECSPI2_CS,
+};
+
+static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = {
+        .chipselect     = mx51_3ds_spi2_cs,
+        .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs),
+};
+
+static struct spi_board_info mx51_3ds_spi_nor_device[] = {
+        {
+         .modalias = "m25p80",
+         .max_speed_hz = 25000000,      /* max spi clock (SCK) speed in HZ */
+         .bus_num = 1,
+         .chip_select = 1,
+         .mode = SPI_MODE_0,
+         .platform_data = NULL,},
+};
+
 /*
  * Board specific initialization.
  */
@@ -136,6 +164,10 @@ static void __init mxc_board_init(void)
                                         ARRAY_SIZE(mx51_3ds_pads));
         mxc_init_imx_uart();
 
+        imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
+        spi_register_board_info(mx51_3ds_spi_nor_device,
+                                ARRAY_SIZE(mx51_3ds_spi_nor_device));
+
         if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
                 printk(KERN_WARNING "Init of the debugboard failed, all "
                                     "devices on the board are unusable.\n");
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 6e384d92e625..23ee4a447406 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -17,12 +17,11 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/fsl_devices.h>
+#include <linux/fec.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx51.h>
-#include <mach/i2c.h>
 #include <mach/mxc_ehci.h>
 
 #include <asm/irq.h>
@@ -31,11 +30,13 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
+#include "devices-imx51.h"
 #include "devices.h"
 
 #define BABBAGE_USB_HUB_RESET   (0*32 + 7)      /* GPIO_1_7 */
 #define BABBAGE_USBH1_STP       (0*32 + 27)     /* GPIO_1_27 */
-#define BABBAGE_PHY_RESET (1*32 +5)     /* GPIO_2_5 */
+#define BABBAGE_PHY_RESET       (1*32 + 5)      /* GPIO_2_5 */
+#define BABBAGE_FEC_PHY_RESET   (1*32 + 14)     /* GPIO_2_14 */
 
 /* USB_CTRL_1 */
 #define MX51_USB_CTRL_1_OFFSET                  0x10
@@ -45,10 +46,6 @@
 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
 #define MX51_USB_PLL_DIV_24_MHZ 0x02
 
-static struct platform_device *devices[] __initdata = {
-        &mxc_fec_device,
-};
-
 static struct pad_desc mx51babbage_pads[] = {
         /* UART1 */
         MX51_PAD_UART1_RXD__UART1_RXD,
@@ -93,19 +90,41 @@ static struct pad_desc mx51babbage_pads[] = {
 
         /* USB HUB reset line*/
         MX51_PAD_GPIO_1_7__GPIO_1_7,
+
+        /* FEC */
+        MX51_PAD_EIM_EB2__FEC_MDIO,
+        MX51_PAD_EIM_EB3__FEC_RDAT1,
+        MX51_PAD_EIM_CS2__FEC_RDAT2,
+        MX51_PAD_EIM_CS3__FEC_RDAT3,
+        MX51_PAD_EIM_CS4__FEC_RX_ER,
+        MX51_PAD_EIM_CS5__FEC_CRS,
+        MX51_PAD_NANDF_RB2__FEC_COL,
+        MX51_PAD_NANDF_RB3__FEC_RXCLK,
+        MX51_PAD_NANDF_RB6__FEC_RDAT0,
+        MX51_PAD_NANDF_RB7__FEC_TDAT0,
+        MX51_PAD_NANDF_CS2__FEC_TX_ER,
+        MX51_PAD_NANDF_CS3__FEC_MDC,
+        MX51_PAD_NANDF_CS4__FEC_TDAT1,
+        MX51_PAD_NANDF_CS5__FEC_TDAT2,
+        MX51_PAD_NANDF_CS6__FEC_TDAT3,
+        MX51_PAD_NANDF_CS7__FEC_TX_EN,
+        MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
+
+        /* FEC PHY reset line */
+        MX51_PAD_EIM_A20__GPIO_2_14,
 };
 
 /* Serial ports */
 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static inline void mxc_init_imx_uart(void)
 {
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_imx_uart(1, &uart_pdata);
+        imx51_add_imx_uart(2, &uart_pdata);
 }
 #else /* !SERIAL_IMX */
 static inline void mxc_init_imx_uart(void)
@@ -113,7 +132,7 @@ static inline void mxc_init_imx_uart(void)
 }
 #endif /* SERIAL_IMX */
 
-static struct imxi2c_platform_data babbage_i2c_data = {
+static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -171,6 +190,22 @@ static inline void babbage_usbhub_reset(void)
         gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
 }
 
+static inline void babbage_fec_reset(void)
+{
+        int ret;
+
+        /* reset FEC PHY */
+        ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset");
+        if (ret) {
+                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
+                return;
+        }
+        gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0);
+        gpio_set_value(BABBAGE_FEC_PHY_RESET, 0);
+        msleep(1);
+        gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
+}
+
 /* This function is board specific as the bit mask for the plldiv will also
 be different for other Freescale SoCs, thus a common bitmask is not
 possible and cannot get place in /plat-mxc/ehci.c.*/
@@ -178,7 +213,7 @@ static int initialize_otg_port(struct platform_device *pdev)
 {
         u32 v;
         void __iomem *usb_base;
-        u32 usbother_base;
+        void __iomem *usbother_base;
 
         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -196,7 +231,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
 {
         u32 v;
         void __iomem *usb_base;
-        u32 usbother_base;
+        void __iomem *usbother_base;
 
         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -250,10 +285,11 @@ static void __init mxc_board_init(void)
         mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
                                         ARRAY_SIZE(mx51babbage_pads));
         mxc_init_imx_uart();
-        platform_add_devices(devices, ARRAY_SIZE(devices));
+        babbage_fec_reset();
+        imx51_add_fec(NULL);
 
-        mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data);
-        mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data);
+        imx51_add_imx_i2c(0, &babbage_i2c_data);
+        imx51_add_imx_i2c(1, &babbage_i2c_data);
         mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
 
         if (otg_mode_host)
@@ -283,7 +319,7 @@ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
         /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
         .phys_io = MX51_AIPS1_BASE_ADDR,
         .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
-        .boot_params = PHYS_OFFSET + 0x100,
+        .boot_params = MX51_PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
         .init_irq = mx51_init_irq,
         .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
new file mode 100644
index 000000000000..b00502acdc15
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2010 Linaro Limited
+ *
+ * based on code from the following
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
+ * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/fsl_devices.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+#include <mach/i2c.h>
+#include <mach/mxc_ehci.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-imx51.h"
+#include "devices.h"
+
+#define MX51_USB_PLL_DIV_24_MHZ 0x01
+
+static struct pad_desc mx51efikamx_pads[] = {
+        /* UART1 */
+        MX51_PAD_UART1_RXD__UART1_RXD,
+        MX51_PAD_UART1_TXD__UART1_TXD,
+        MX51_PAD_UART1_RTS__UART1_RTS,
+        MX51_PAD_UART1_CTS__UART1_CTS,
+};
+
+/* Serial ports */
+#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
+static const struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static inline void mxc_init_imx_uart(void)
+{
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_imx_uart(1, &uart_pdata);
+        imx51_add_imx_uart(2, &uart_pdata);
+}
+#else /* !SERIAL_IMX */
+static inline void mxc_init_imx_uart(void)
+{
+}
+#endif /* SERIAL_IMX */
+
+/* This function is board specific as the bit mask for the plldiv will also
+ * be different for other Freescale SoCs, thus a common bitmask is not
+ * possible and cannot get place in /plat-mxc/ehci.c.
+ */
+static int initialize_otg_port(struct platform_device *pdev)
+{
+        u32 v;
+        void __iomem *usb_base;
+        void __iomem *usbother_base;
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
+
+        /* Set the PHY clock to 19.2MHz */
+        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
+        v |= MX51_USB_PLL_DIV_24_MHZ;
+        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        iounmap(usb_base);
+        return 0;
+}
+
+static struct mxc_usbh_platform_data dr_utmi_config = {
+        .init   = initialize_otg_port,
+        .portsc = MXC_EHCI_UTMI_16BIT,
+        .flags  = MXC_EHCI_INTERNAL_PHY,
+};
+
+static void __init mxc_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
+                                        ARRAY_SIZE(mx51efikamx_pads));
+        mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+        mxc_init_imx_uart();
+}
+
+static void __init mx51_efikamx_timer_init(void)
+{
+        mx51_clocks_init(32768, 24000000, 22579200, 24576000);
+}
+
+static struct sys_timer mxc_timer = {
+        .init   = mx51_efikamx_timer_init,
+};
+
+MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
+        /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
+        .phys_io = MX51_AIPS1_BASE_ADDR,
+        .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params = MX51_PHYS_OFFSET + 0x100,
+        .map_io = mx51_map_io,
+        .init_irq = mx51_init_irq,
+        .init_machine =  mxc_board_init,
+        .timer = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index 57c10a9926cc..21cecc040172 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -41,34 +41,36 @@ static struct clk usboh3_clk;
 
 #define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
 
-static int _clk_ccgr_enable(struct clk *clk)
+static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
 {
-        u32 reg;
+        u32 reg = __raw_readl(clk->enable_reg);
+
+        reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
+        reg |= mode << clk->enable_shift;
 
-        reg = __raw_readl(clk->enable_reg);
-        reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift;
         __raw_writel(reg, clk->enable_reg);
+}
 
+static int _clk_ccgr_enable(struct clk *clk)
+{
+        _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
         return 0;
 }
 
 static void _clk_ccgr_disable(struct clk *clk)
 {
-        u32 reg;
-        reg = __raw_readl(clk->enable_reg);
-        reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
-        __raw_writel(reg, clk->enable_reg);
+        _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
+}
 
+static int _clk_ccgr_enable_inrun(struct clk *clk)
+{
+        _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
+        return 0;
 }
 
 static void _clk_ccgr_disable_inwait(struct clk *clk)
 {
-        u32 reg;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
-        reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
-        __raw_writel(reg, clk->enable_reg);
+        _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
 }
 
 /*
@@ -571,6 +573,64 @@ static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
         return 0;
 }
 
+#define clk_nfc_set_parent      NULL
+
+static unsigned long clk_nfc_get_rate(struct clk *clk)
+{
+        unsigned long rate;
+        u32 reg, div;
+
+        reg = __raw_readl(MXC_CCM_CBCDR);
+        div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
+               MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
+        rate = clk_get_rate(clk->parent) / div;
+        WARN_ON(rate == 0);
+        return rate;
+}
+
+static unsigned long clk_nfc_round_rate(struct clk *clk,
+                                                unsigned long rate)
+{
+        u32 div;
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+
+        if (!rate)
+                return -EINVAL;
+
+        div = parent_rate / rate;
+
+        if (parent_rate % rate)
+                div++;
+
+        if (div > 8)
+                return -EINVAL;
+
+        return parent_rate / div;
+
+}
+
+static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg, div;
+
+        div = clk_get_rate(clk->parent) / rate;
+        if (div == 0)
+                div++;
+        if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
+                return -EINVAL;
+
+        reg = __raw_readl(MXC_CCM_CBCDR);
+        reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
+        reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
+        __raw_writel(reg, MXC_CCM_CBCDR);
+
+        while (__raw_readl(MXC_CCM_CDHIPR) &
+                        MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
+        }
+
+        return 0;
+}
+
 static unsigned long clk_usboh3_get_rate(struct clk *clk)
 {
         u32 reg, prediv, podf;
@@ -620,6 +680,17 @@ static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
         return ckih2_reference;
 }
 
+static unsigned long clk_emi_slow_get_rate(struct clk *clk)
+{
+        u32 reg, div;
+
+        reg = __raw_readl(MXC_CCM_CBCDR);
+        div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
+               MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
+
+        return clk_get_rate(clk->parent) / div;
+}
+
 /* External high frequency clock */
 static struct clk ckih_clk = {
         .get_rate = get_high_reference_clock_rate,
@@ -762,45 +833,105 @@ static struct clk kpp_clk = {
         .id = 0,
 };
 
-#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)     \
+static struct clk emi_slow_clk = {
+        .parent = &pll2_sw_clk,
+        .enable_reg = MXC_CCM_CCGR5,
+        .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+        .enable = _clk_ccgr_enable,
+        .disable = _clk_ccgr_disable_inwait,
+        .get_rate = clk_emi_slow_get_rate,
+};
+
+#define DEFINE_CLOCK1(name, i, er, es, pfx, p, s)       \
         static struct clk name = {                      \
                 .id             = i,                    \
                 .enable_reg     = er,                   \
                 .enable_shift   = es,                   \
-                .get_rate       = gr,                   \
-                .set_rate       = sr,                   \
+                .get_rate       = pfx##_get_rate,       \
+                .set_rate       = pfx##_set_rate,       \
+                .round_rate     = pfx##_round_rate,     \
+                .set_parent     = pfx##_set_parent,     \
                 .enable         = _clk_ccgr_enable,     \
                 .disable        = _clk_ccgr_disable,    \
                 .parent         = p,                    \
                 .secondary      = s,                    \
         }
 
-/* DEFINE_CLOCK(name, id, enable_reg, enable_shift,
-   get_rate, set_rate, parent, secondary); */
+/* eCSPI */
+static unsigned long clk_ecspi_get_rate(struct clk *clk)
+{
+        u32 reg, pred, podf;
+
+        reg = __raw_readl(MXC_CCM_CSCDR2);
+
+        pred = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >>
+                        MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
+        podf = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >>
+                        MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
+
+        return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent),
+                        (pred + 1) * (podf + 1));
+}
+
+static int clk_ecspi_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg, mux;
+
+        mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+                        &lp_apm_clk);
+
+        reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK;
+        reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
+        __raw_writel(reg, MXC_CCM_CSCMR1);
+
+        return 0;
+}
+
+static struct clk ecspi_main_clk = {
+        .parent = &pll3_sw_clk,
+        .get_rate = clk_ecspi_get_rate,
+        .set_parent = clk_ecspi_set_parent,
+};
+
+#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s)          \
+        static struct clk name = {                                      \
+                .id             = i,                                    \
+                .enable_reg     = er,                                   \
+                .enable_shift   = es,                                   \
+                .get_rate       = gr,                                   \
+                .set_rate       = sr,                                   \
+                .enable         = e,                                    \
+                .disable        = d,                                    \
+                .parent         = p,                                    \
+                .secondary      = s,                                    \
+        }
+
+#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)                     \
+        DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
 
 /* Shared peripheral bus arbiter */
 DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
         NULL,  NULL, &ipg_clk, NULL);
 
 /* UART */
-DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
-        NULL,  NULL, &uart_root_clk, NULL);
-DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
-        NULL,  NULL, &uart_root_clk, NULL);
-DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
-        NULL,  NULL, &uart_root_clk, NULL);
 DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
 DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
 DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
         NULL,  NULL, &ipg_clk, &spba_clk);
+DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
+        NULL,  NULL, &uart_root_clk, &uart1_ipg_clk);
+DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
+        NULL,  NULL, &uart_root_clk, &uart2_ipg_clk);
+DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
+        NULL,  NULL, &uart_root_clk, &uart3_ipg_clk);
 
 /* GPT */
-DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
-        NULL,  NULL, &ipg_clk, NULL);
 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
         NULL,  NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
+        NULL,  NULL, &ipg_clk, &gpt_ipg_clk);
 
 /* I2C */
 DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
@@ -814,6 +945,42 @@ DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
         NULL,  NULL, &ipg_clk, NULL);
 
+/* NFC */
+DEFINE_CLOCK1(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
+        clk_nfc, &emi_slow_clk, NULL);
+
+/* SSI */
+DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
+        NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
+        NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
+DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
+        NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
+        NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
+
+/* eCSPI */
+DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
+                NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
+                &ipg_clk, &spba_clk);
+DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
+                NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
+DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
+                NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
+                &ipg_clk, &aips_tz2_clk);
+DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
+                NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
+
+/* CSPI */
+DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
+                NULL, NULL, &ipg_clk, &aips_tz2_clk);
+DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
+                NULL, NULL, &ipg_clk, &cspi_ipg_clk);
+
+/* SDMA */
+DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
+                NULL, NULL, &ahb_clk, NULL);
+
 #define _REGISTER_CLOCK(d, n, c) \
        { \
                 .dev_id = d, \
@@ -837,6 +1004,16 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
         _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
+        _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
+        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+        _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
+        _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
+        _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
+        _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
+        _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
+        _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
+        _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
 };
 
 static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index 2d37785e3857..eaacb6e9b5d0 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -70,6 +70,25 @@ int mx51_revision(void)
 }
 EXPORT_SYMBOL(mx51_revision);
 
+#ifdef CONFIG_NEON
+
+/*
+ * All versions of the silicon before Rev. 3 have broken NEON implementations.
+ * Dependent on link order - so the assumption is that vfp_init is called
+ * before us.
+ */
+static int __init mx51_neon_fixup(void)
+{
+        if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) {
+                elf_hwcap &= ~HWCAP_NEON;
+                pr_info("Turning off NEON support, detected broken NEON implementation\n");
+        }
+        return 0;
+}
+
+late_initcall(mx51_neon_fixup);
+#endif
+
 static int __init post_cpu_init(void)
 {
         unsigned int reg;
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
new file mode 100644
index 000000000000..c233379256b8
--- /dev/null
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx51.h>
+#include <mach/devices-common.h>
+
+extern const struct imx_fec_data imx51_fec_data __initconst;
+#define imx51_add_fec(pdata)    \
+        imx_add_fec(&imx51_fec_data, pdata)
+
+extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst;
+#define imx51_add_imx_i2c(id, pdata)    \
+        imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
+
+extern const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst;
+#define imx51_add_imx_ssi(id, pdata)    \
+        imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
+
+extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst;
+#define imx51_add_imx_uart(id, pdata)   \
+        imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
+
+extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst;
+#define imx51_add_mxc_nand(pdata)       \
+        imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
+
+extern const struct imx_spi_imx_data imx51_cspi_data __initconst;
+#define imx51_add_cspi(pdata)   \
+        imx_add_spi_imx(&imx51_cspi_data, pdata)
+
+extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
+#define imx51_add_ecspi(id, pdata)      \
+        imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 1920ff4963b2..4c7be87a7c9d 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -17,120 +17,6 @@
 #include <mach/imx-uart.h>
 #include <mach/irqs.h>
 
-static struct resource uart0[] = {
-        {
-                .start = MX51_UART1_BASE_ADDR,
-                .end = MX51_UART1_BASE_ADDR + 0xfff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX51_MXC_INT_UART1,
-                .end = MX51_MXC_INT_UART1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device0 = {
-        .name = "imx-uart",
-        .id = 0,
-        .resource = uart0,
-        .num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
-        {
-                .start = MX51_UART2_BASE_ADDR,
-                .end = MX51_UART2_BASE_ADDR + 0xfff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX51_MXC_INT_UART2,
-                .end = MX51_MXC_INT_UART2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device1 = {
-        .name = "imx-uart",
-        .id = 1,
-        .resource = uart1,
-        .num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
-        {
-                .start = MX51_UART3_BASE_ADDR,
-                .end = MX51_UART3_BASE_ADDR + 0xfff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX51_MXC_INT_UART3,
-                .end = MX51_MXC_INT_UART3,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device2 = {
-        .name = "imx-uart",
-        .id = 2,
-        .resource = uart2,
-        .num_resources = ARRAY_SIZE(uart2),
-};
-
-static struct resource mxc_fec_resources[] = {
-        {
-                .start  = MX51_MXC_FEC_BASE_ADDR,
-                .end    = MX51_MXC_FEC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = MX51_MXC_INT_FEC,
-                .end    = MX51_MXC_INT_FEC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_fec_device = {
-        .name = "fec",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_fec_resources),
-        .resource = mxc_fec_resources,
-};
-
-static struct resource mxc_i2c0_resources[] = {
-        {
-                .start = MX51_I2C1_BASE_ADDR,
-                .end = MX51_I2C1_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX51_MXC_INT_I2C1,
-                .end = MX51_MXC_INT_I2C1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_i2c_device0 = {
-        .name = "imx-i2c",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
-        .resource = mxc_i2c0_resources,
-};
-
-static struct resource mxc_i2c1_resources[] = {
-        {
-                .start = MX51_I2C2_BASE_ADDR,
-                .end = MX51_I2C2_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX51_MXC_INT_I2C2,
-                .end = MX51_MXC_INT_I2C2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_i2c_device1 = {
-        .name = "imx-i2c",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
-        .resource = mxc_i2c1_resources,
-};
-
 static struct resource mxc_hsi2c_resources[] = {
         {
                 .start = MX51_HSI2C_DMA_BASE_ADDR,
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index e509cfaad1d4..af1d07c0bbc1 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -1,12 +1,6 @@
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-extern struct platform_device mxc_fec_device;
 extern struct platform_device mxc_usbdr_host_device;
 extern struct platform_device mxc_usbh1_device;
 extern struct platform_device mxc_usbdr_udc_device;
 extern struct platform_device mxc_wdt;
-extern struct platform_device mxc_i2c_device0;
-extern struct platform_device mxc_i2c_device1;
 extern struct platform_device mxc_hsi2c_device;
 extern struct platform_device mxc_keypad_device;
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index ffa93d1d6ef8..d0e417ce2c08 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -30,6 +30,7 @@
 
 #include <asm/mach/arch.h>
 
+#include "devices-imx51.h"
 #include "devices.h"
 
 #define MBIMX51_TSC2007_GPIO    (2*32 + 30)
@@ -114,7 +115,7 @@ static struct pad_desc mbimx51_pads[] = {
         MX51_PAD_KEY_COL3__KEY_COL3,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -172,8 +173,8 @@ void __init eukrea_mbimx51_baseboard_init(void)
         mxc_iomux_v3_setup_multiple_pads(mbimx51_pads,
                                         ARRAY_SIZE(mbimx51_pads));
 
-        mxc_register_device(&mxc_uart_device1, NULL);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+        imx51_add_imx_uart(1, NULL);
+        imx51_add_imx_uart(2, &uart_pdata);
 
         gpio_request(MBIMX51_LED0, "LED0");
         gpio_direction_output(MBIMX51_LED0, 1);
diff --git a/arch/arm/mach-netx/include/mach/vmalloc.h b/arch/arm/mach-netx/include/mach/vmalloc.h
index 25d5cc676e0f..7cca3574308f 100644
--- a/arch/arm/mach-netx/include/mach/vmalloc.h
+++ b/arch/arm/mach-netx/include/mach/vmalloc.h
@@ -16,4 +16,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
diff --git a/arch/arm/mach-omap1/include/mach/vmalloc.h b/arch/arm/mach-omap1/include/mach/vmalloc.h
index 1b2af14df151..b001f67d695b 100644
--- a/arch/arm/mach-omap1/include/mach/vmalloc.h
+++ b/arch/arm/mach-omap1/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
-#define VMALLOC_END     (PAGE_OFFSET + 0x18000000)
+#define VMALLOC_END     0xd8000000
diff --git a/arch/arm/mach-omap2/include/mach/vmalloc.h b/arch/arm/mach-omap2/include/mach/vmalloc.h
index 9ce9b6e8ad23..4da31e997efe 100644
--- a/arch/arm/mach-omap2/include/mach/vmalloc.h
+++ b/arch/arm/mach-omap2/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x38000000)
+#define VMALLOC_END       0xf8000000
diff --git a/arch/arm/mach-pnx4008/include/mach/vmalloc.h b/arch/arm/mach-pnx4008/include/mach/vmalloc.h
index 2ad398378aed..31b65ee07b0b 100644
--- a/arch/arm/mach-pnx4008/include/mach/vmalloc.h
+++ b/arch/arm/mach-pnx4008/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
  * area for the same reason. ;)
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 7aefb9074852..dd235ecc9d6c 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -8,19 +8,16 @@ config ARCH_LUBBOCK
         bool "Intel DBPXA250 Development Platform (aka Lubbock)"
         select PXA25x
         select SA1111
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_MAINSTONE
         bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)"
         select PXA27x
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_ZYLONITE
         bool
         select PXA3xx
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_ZYLONITE300
         bool "PXA3xx Development Platform (aka Zylonite) PXA300/310"
@@ -44,6 +41,10 @@ config MACH_TAVOREVB
         select PXA3xx
         select CPU_PXA930
 
+config MACH_TAVOREVB3
+        bool "PXA95x Development Platform (aka TavorEVB III)"
+        select CPU_PXA950
+
 config MACH_SAAR
         bool "PXA930 Handheld Platform (aka SAAR)"
         select PXA3xx
@@ -61,7 +62,6 @@ config ARCH_VIPER
         select ISA
         select I2C_GPIO
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
         select PXA_HAVE_ISA_IRQS
         select ARCOM_PCMCIA
 
@@ -69,7 +69,6 @@ config MACH_ARCOM_ZEUS
         bool "Arcom/Eurotech ZEUS SBC"
         select PXA27x
         select ISA
-        select PXA_HAVE_BOARD_IRQS
         select PXA_HAVE_ISA_IRQS
         select ARCOM_PCMCIA
 
@@ -77,7 +76,6 @@ config MACH_BALLOON3
         bool "Balloon 3 board"
         select PXA27x
         select IWMMXT
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_CSB726
         bool "Enable Cogent CSB726 System On a Module"
@@ -140,13 +138,11 @@ config MACH_INTELMOTE2
         bool "Intel Mote 2 Platform"
         select PXA27x
         select IWMMXT
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_STARGATE2
         bool "Intel Stargate 2 Platform"
         select PXA27x
         select IWMMXT
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_XCEP
         bool "Iskratel Electronics XCEP"
@@ -206,13 +202,11 @@ config MACH_LOGICPD_PXA270
         bool "LogicPD PXA270 Card Engine Development Platform"
         select PXA27x
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_PCM027
         bool "Phytec phyCORE-PXA270 CPU module (PCM-027)"
         select PXA27x
         select IWMMXT
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_PCM990_BASEBOARD
         bool "PHYTEC PCM-990 development board"
@@ -247,7 +241,6 @@ config MACH_COLIBRI_PXA270_INCOME
         depends on MACH_COLIBRI
         select PXA27x
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_COLIBRI300
         bool "Toradex Colibri PXA300/310"
@@ -274,7 +267,6 @@ config MACH_H4700
         select PXA27x
         select IWMMXT
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_H5000
         bool "HP iPAQ h5000"
@@ -289,7 +281,6 @@ config MACH_MAGICIAN
         select PXA27x
         select IWMMXT
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_MIOA701
         bool "Mitac Mio A701 Support"
@@ -307,7 +298,6 @@ config PXA_EZX
         select PXA27x
         select IWMMXT
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_EZX_A780
         bool "Motorola EZX A780"
@@ -478,7 +468,6 @@ config MACH_POODLE
         depends on PXA_SHARPSL
         select PXA25x
         select SHARP_LOCOMO
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_CORGI
         bool "Enable Sharp SL-C700 (Corgi) Support"
@@ -523,7 +512,6 @@ config MACH_TOSA
         bool "Enable Sharp SL-6000x (Tosa) Support"
         depends on PXA_SHARPSL
         select PXA25x
-        select PXA_HAVE_BOARD_IRQS
 
 config TOSA_BT
         tristate "Control the state of built-in bluetooth chip on Sharp SL-6000"
@@ -552,7 +540,6 @@ config MACH_ICONTROL
 config ARCH_PXA_ESERIES
         bool "PXA based Toshiba e-series PDAs"
         select PXA25x
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_E330
         bool "Toshiba e330"
@@ -606,7 +593,6 @@ config MACH_ZIPIT2
         bool "Zipit Z2 Handheld"
         select PXA27x
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 endmenu
 
@@ -643,6 +629,7 @@ config CPU_PXA300
 config CPU_PXA310
         bool
         select CPU_PXA300
+        select PXA310_ULPI if USB_ULPI
         help
           PXA310 (codename Monahans-LV)
 
@@ -692,10 +679,10 @@ config SHARPSL_PM_MAX1111
         select HWMON
         select SENSORS_MAX1111
 
-config PXA_HAVE_BOARD_IRQS
+config PXA_HAVE_ISA_IRQS
         bool
 
-config PXA_HAVE_ISA_IRQS
+config PXA310_ULPI
         bool
 
 endif
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 85c7fb324dbb..e2f89c2c6f49 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -18,7 +18,7 @@ endif
 # SoC-specific code
 obj-$(CONFIG_PXA25x)            += mfp-pxa2xx.o pxa2xx.o pxa25x.o
 obj-$(CONFIG_PXA27x)            += mfp-pxa2xx.o pxa2xx.o pxa27x.o
-obj-$(CONFIG_PXA3xx)            += mfp-pxa3xx.o pxa3xx.o smemc.o
+obj-$(CONFIG_PXA3xx)            += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
 obj-$(CONFIG_CPU_PXA300)        += pxa300.o
 obj-$(CONFIG_CPU_PXA320)        += pxa320.o
 obj-$(CONFIG_CPU_PXA930)        += pxa930.o
@@ -32,6 +32,7 @@ obj-$(CONFIG_MACH_ZYLONITE300)	+= zylonite.o zylonite_pxa300.o
 obj-$(CONFIG_MACH_ZYLONITE320)  += zylonite.o zylonite_pxa320.o
 obj-$(CONFIG_MACH_LITTLETON)    += littleton.o
 obj-$(CONFIG_MACH_TAVOREVB)     += tavorevb.o
+obj-$(CONFIG_MACH_TAVOREVB3)    += tavorevb3.o
 obj-$(CONFIG_MACH_SAAR)         += saar.o
 
 # 3rd Party Dev Platforms
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index 9041340fee1d..79d0f6cf53d7 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -68,42 +68,6 @@ static unsigned long balloon3_pin_config[] __initdata = {
 
         /* Reset, configured as GPIO wakeup source */
         GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
-
-        /* LEDs */
-        GPIO9_GPIO,     /* NAND activity LED */
-        GPIO10_GPIO,    /* Heartbeat LED */
-
-        /* AC97 */
-        GPIO28_AC97_BITCLK,
-        GPIO29_AC97_SDATA_IN_0,
-        GPIO30_AC97_SDATA_OUT,
-        GPIO31_AC97_SYNC,
-        GPIO113_AC97_nRESET,
-        GPIO95_GPIO,
-
-        /* MMC */
-        GPIO32_MMC_CLK,
-        GPIO92_MMC_DAT_0,
-        GPIO109_MMC_DAT_1,
-        GPIO110_MMC_DAT_2,
-        GPIO111_MMC_DAT_3,
-        GPIO112_MMC_CMD,
-
-        /* USB Host */
-        GPIO88_USBH1_PWR,
-        GPIO89_USBH1_PEN,
-
-        /* PC Card */
-        GPIO48_nPOE,
-        GPIO49_nPWE,
-        GPIO50_nPIOR,
-        GPIO51_nPIOW,
-        GPIO85_nPCE_1,
-        GPIO54_nPCE_2,
-        GPIO79_PSKTSEL,
-        GPIO55_nPREG,
-        GPIO56_nPWAIT,
-        GPIO57_nIOIS16,
 };
 
 /******************************************************************************
@@ -132,6 +96,34 @@ int __init parse_balloon3_features(char *arg)
 early_param("balloon3_features", parse_balloon3_features);
 
 /******************************************************************************
+ * Compact Flash slot
+ ******************************************************************************/
+#if     defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
+static unsigned long balloon3_cf_pin_config[] __initdata = {
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO85_nPCE_1,
+        GPIO54_nPCE_2,
+        GPIO79_PSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+};
+
+static void __init balloon3_cf_init(void)
+{
+        if (!balloon3_has(BALLOON3_FEATURE_CF))
+                return;
+
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_cf_pin_config));
+}
+#else
+static inline void balloon3_cf_init(void) {}
+#endif
+
+/******************************************************************************
  * NOR Flash
  ******************************************************************************/
 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
@@ -179,6 +171,15 @@ static inline void balloon3_nor_init(void) {}
  ******************************************************************************/
 #if     defined(CONFIG_TOUCHSCREEN_UCB1400) || \
         defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
+static unsigned long balloon3_ac97_pin_config[] __initdata = {
+        GPIO28_AC97_BITCLK,
+        GPIO29_AC97_SDATA_IN_0,
+        GPIO30_AC97_SDATA_OUT,
+        GPIO31_AC97_SYNC,
+        GPIO113_AC97_nRESET,
+        GPIO95_GPIO,
+};
+
 static struct ucb1400_pdata vpac270_ucb1400_pdata = {
         .irq            = IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ),
 };
@@ -197,6 +198,7 @@ static void __init balloon3_ts_init(void)
         if (!balloon3_has(BALLOON3_FEATURE_AUDIO))
                 return;
 
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_ac97_pin_config));
         pxa_set_ac97_info(NULL);
         platform_device_register(&balloon3_ucb1400_device);
 }
@@ -208,6 +210,11 @@ static inline void balloon3_ts_init(void) {}
  * Framebuffer
  ******************************************************************************/
 #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static unsigned long balloon3_lcd_pin_config[] __initdata = {
+        GPIOxx_LCD_TFT_16BPP,
+        GPIO99_GPIO,
+};
+
 static struct pxafb_mode_info balloon3_lcd_modes[] = {
         {
                 .pixclock               = 38000,
@@ -242,6 +249,8 @@ static void __init balloon3_lcd_init(void)
         if (!balloon3_has(BALLOON3_FEATURE_TOPPOLY))
                 return;
 
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_lcd_pin_config));
+
         ret = gpio_request(BALLOON3_GPIO_RUN_BACKLIGHT, "BKL-ON");
         if (ret) {
                 pr_err("Requesting BKL-ON GPIO failed!\n");
@@ -271,6 +280,15 @@ static inline void balloon3_lcd_init(void) {}
  * SD/MMC card controller
  ******************************************************************************/
 #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
+static unsigned long balloon3_mmc_pin_config[] __initdata = {
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+};
+
 static struct pxamci_platform_data balloon3_mci_platform_data = {
         .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
         .gpio_card_detect       = -1,
@@ -281,6 +299,7 @@ static struct pxamci_platform_data balloon3_mci_platform_data = {
 
 static void __init balloon3_mmc_init(void)
 {
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_mmc_pin_config));
         pxa_set_mci_info(&balloon3_mci_platform_data);
 }
 #else
@@ -339,6 +358,11 @@ static inline void balloon3_irda_init(void) {}
  * USB Host
  ******************************************************************************/
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static unsigned long balloon3_uhc_pin_config[] __initdata = {
+        GPIO88_USBH1_PWR,
+        GPIO89_USBH1_PEN,
+};
+
 static struct pxaohci_platform_data balloon3_ohci_info = {
         .port_mode      = PMM_PERPORT_MODE,
         .flags          = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
@@ -348,6 +372,7 @@ static void __init balloon3_uhc_init(void)
 {
         if (!balloon3_has(BALLOON3_FEATURE_OHCI))
                 return;
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_uhc_pin_config));
         pxa_set_ohci_info(&balloon3_ohci_info);
 }
 #else
@@ -358,6 +383,11 @@ static inline void balloon3_uhc_init(void) {}
  * LEDs
  ******************************************************************************/
 #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+static unsigned long balloon3_led_pin_config[] __initdata = {
+        GPIO9_GPIO,     /* NAND activity LED */
+        GPIO10_GPIO,    /* Heartbeat LED */
+};
+
 struct gpio_led balloon3_gpio_leds[] = {
         {
                 .name                   = "balloon3:green:idle",
@@ -436,6 +466,7 @@ static struct platform_device balloon3_pcf_leds = {
 
 static void __init balloon3_leds_init(void)
 {
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_led_pin_config));
         platform_device_register(&balloon3_leds);
         platform_device_register(&balloon3_pcf_leds);
 }
@@ -757,6 +788,7 @@ static void __init balloon3_init(void)
         balloon3_ts_init();
         balloon3_udc_init();
         balloon3_uhc_init();
+        balloon3_cf_init();
 }
 
 static struct map_desc balloon3_io_desc[] __initdata = {
@@ -779,6 +811,7 @@ MACHINE_START(BALLOON3, "Balloon3")
         .phys_io        = 0x40000000,
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = balloon3_map_io,
+        .nr_irqs        = BALLOON3_NR_IRQS,
         .init_irq       = balloon3_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = balloon3_init,
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index bff6e78f033d..ad40e7b141e0 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -33,6 +33,9 @@
 extern void cmx255_init(void);
 extern void cmx270_init(void);
 
+/* reserve IRQs for IT8152 */
+#define CMX2XX_NR_IRQS          (IRQ_BOARD_START + 40)
+
 /* virtual addresses for statically mapped regions */
 #define CMX2XX_VIRT_BASE        (0xe8000000)
 #define CMX2XX_IT8152_VIRT      (CMX2XX_VIRT_BASE)
@@ -514,6 +517,7 @@ MACHINE_START(ARMCORE, "Compulab CM-X2XX")
         .phys_io        = 0x40000000,
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = cmx2xx_map_io,
+        .nr_irqs        = CMX2XX_NR_IRQS,
         .init_irq       = cmx2xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = cmx2xx_init,
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index c70e6c2f4e7c..8e0b5622b277 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -19,6 +19,7 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
 
 #include <linux/gpio.h>
 #include <linux/dm9000.h>
@@ -50,6 +51,7 @@
 #include <plat/i2c.h>
 #include <plat/pxa3xx_nand.h>
 #include <mach/audio.h>
+#include <mach/pxa3xx-u2d.h>
 
 #include <asm/mach/map.h>
 
@@ -68,6 +70,8 @@
 #define GPIO97_RTC_RD           (97)
 #define GPIO98_RTC_IO           (98)
 
+#define GPIO_ULPI_PHY_RST       (127)
+
 static mfp_cfg_t cm_x3xx_mfp_cfg[] __initdata = {
         /* LCD */
         GPIO54_LCD_LDD_0,
@@ -472,6 +476,78 @@ static void __init cm_x300_init_mmc(void)
 static inline void cm_x300_init_mmc(void) {}
 #endif
 
+#if defined(CONFIG_PXA310_ULPI)
+static struct clk *pout_clk;
+
+static int cm_x300_ulpi_phy_reset(void)
+{
+        int err;
+
+        /* reset the PHY */
+        err = gpio_request(GPIO_ULPI_PHY_RST, "ulpi reset");
+        if (err) {
+                pr_err("%s: failed to request ULPI reset GPIO: %d\n",
+                       __func__, err);
+                return err;
+        }
+
+        gpio_direction_output(GPIO_ULPI_PHY_RST, 0);
+        msleep(10);
+        gpio_set_value(GPIO_ULPI_PHY_RST, 1);
+        msleep(10);
+
+        gpio_free(GPIO_ULPI_PHY_RST);
+
+        return 0;
+}
+
+static inline int cm_x300_u2d_init(struct device *dev)
+{
+        int err = 0;
+
+        if (cpu_is_pxa310()) {
+                /* CLK_POUT is connected to the ULPI PHY */
+                pout_clk = clk_get(NULL, "CLK_POUT");
+                if (IS_ERR(pout_clk)) {
+                        err = PTR_ERR(pout_clk);
+                        pr_err("%s: failed to get CLK_POUT: %d\n",
+                               __func__, err);
+                        return err;
+                }
+                clk_enable(pout_clk);
+
+                err = cm_x300_ulpi_phy_reset();
+                if (err) {
+                        clk_disable(pout_clk);
+                        clk_put(pout_clk);
+                }
+        }
+
+        return err;
+}
+
+static void cm_x300_u2d_exit(struct device *dev)
+{
+        if (cpu_is_pxa310()) {
+                clk_disable(pout_clk);
+                clk_put(pout_clk);
+        }
+}
+
+static struct pxa3xx_u2d_platform_data cm_x300_u2d_platform_data = {
+        .ulpi_mode      = ULPI_SER_6PIN,
+        .init           = cm_x300_u2d_init,
+        .exit           = cm_x300_u2d_exit,
+};
+
+static void cm_x300_init_u2d(void)
+{
+        pxa3xx_set_u2d_info(&cm_x300_u2d_platform_data);
+}
+#else
+static inline void cm_x300_init_u2d(void) {}
+#endif
+
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
 static int cm_x300_ohci_init(struct device *dev)
 {
@@ -754,6 +830,7 @@ static void __init cm_x300_init(void)
         cm_x300_init_da9030();
         cm_x300_init_dm9000();
         cm_x300_init_lcd();
+        cm_x300_init_u2d();
         cm_x300_init_ohci();
         cm_x300_init_mmc();
         cm_x300_init_nand();
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 50d5939a78f1..58093d9e07be 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -312,8 +312,7 @@ static int pxa_set_target(struct cpufreq_policy *policy,
         freqs.cpu = policy->cpu;
 
         if (freq_debug)
-                pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, "
-                         "(SDRAM %d Mhz)\n",
+                pr_debug("Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
                          freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
                          (new_freq_mem / 2000) : (new_freq_mem / 1000));
 
diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
index 0a0d0fe99220..88fbec05ec50 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa3xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
@@ -159,7 +159,7 @@ static int pxa3xx_cpufreq_verify(struct cpufreq_policy *policy)
 
 static unsigned int pxa3xx_cpufreq_get(unsigned int cpu)
 {
-        return get_clk_frequency_khz(0);
+        return pxa3xx_get_clk_frequency_khz(0);
 }
 
 static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy,
@@ -212,7 +212,8 @@ static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
         policy->cpuinfo.min_freq = 104000;
         policy->cpuinfo.max_freq = (cpu_is_pxa320()) ? 806000 : 624000;
         policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
-        policy->cur = policy->min = policy->max = get_clk_frequency_khz(0);
+        policy->max = pxa3xx_get_clk_frequency_khz(0);
+        policy->cur = policy->min = policy->max;
 
         if (cpu_is_pxa300() || cpu_is_pxa310())
                 ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa300_freqs));
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 65447dc736c2..08b410343870 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -6,11 +6,12 @@
 
 #include <asm/pmu.h>
 #include <mach/udc.h>
+#include <mach/pxa3xx-u2d.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/irda.h>
 #include <mach/ohci.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/pxa2xx_spi.h>
 #include <mach/camera.h>
 #include <mach/audio.h>
@@ -134,6 +135,33 @@ struct platform_device pxa27x_device_udc = {
         }
 };
 
+#ifdef CONFIG_PXA3xx
+static struct resource pxa3xx_u2d_resources[] = {
+        [0] = {
+                .start  = 0x54100000,
+                .end    = 0x54100fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_USB2,
+                .end    = IRQ_USB2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa3xx_device_u2d = {
+        .name           = "pxa3xx-u2d",
+        .id             = -1,
+        .resource       = pxa3xx_u2d_resources,
+        .num_resources  = ARRAY_SIZE(pxa3xx_u2d_resources),
+};
+
+void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
+{
+        pxa_register_device(&pxa3xx_device_u2d, info);
+}
+#endif /* CONFIG_PXA3xx */
+
 static struct resource pxafb_resources[] = {
         [0] = {
                 .start  = 0x44000000,
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 50353ea49ba4..715e8bd02e24 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -4,6 +4,7 @@ extern struct platform_device pxa3xx_device_mci2;
 extern struct platform_device pxa3xx_device_mci3;
 extern struct platform_device pxa25x_device_udc;
 extern struct platform_device pxa27x_device_udc;
+extern struct platform_device pxa3xx_device_u2d;
 extern struct platform_device pxa_device_fb;
 extern struct platform_device pxa_device_ffuart;
 extern struct platform_device pxa_device_btuart;
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 0517c17978f3..51286a738a3b 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -43,7 +43,7 @@
 #include <mach/pxafb.h>
 #include <mach/ohci.h>
 #include <mach/mmc.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <plat/i2c.h>
 #include <mach/camera.h>
 #include <mach/pxa2xx_spi.h>
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 349212a1cbd3..4971ce119501 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -29,6 +29,7 @@
 
 #include <mach/pxa25x.h>
 #include <mach/eseries-gpio.h>
+#include <mach/eseries-irq.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
 #include <mach/udc.h>
@@ -183,6 +184,7 @@ MACHINE_START(E330, "Toshiba e330")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e330_init,
@@ -233,6 +235,7 @@ MACHINE_START(E350, "Toshiba e350")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e350_init,
@@ -356,6 +359,7 @@ MACHINE_START(E400, "Toshiba e400")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e400_init,
@@ -545,6 +549,7 @@ MACHINE_START(E740, "Toshiba e740")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e740_init,
@@ -737,6 +742,7 @@ MACHINE_START(E750, "Toshiba e750")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e750_init,
@@ -933,6 +939,7 @@ MACHINE_START(E800, "Toshiba e800")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e800_init,
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 626c82b13970..f997e8455557 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -32,12 +32,14 @@
 #include <mach/ohci.h>
 #include <plat/i2c.h>
 #include <mach/hardware.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/camera.h>
 
 #include "devices.h"
 #include "generic.h"
 
+#define EZX_NR_IRQS                     (IRQ_BOARD_START + 24)
+
 #define GPIO12_A780_FLIP_LID            12
 #define GPIO15_A1200_FLIP_LID           15
 #define GPIO15_A910_FLIP_LID            15
@@ -800,6 +802,7 @@ MACHINE_START(EZX_A780, "Motorola EZX A780")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = a780_init,
@@ -866,6 +869,7 @@ MACHINE_START(EZX_E680, "Motorola EZX E680")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = e680_init,
@@ -932,6 +936,7 @@ MACHINE_START(EZX_A1200, "Motorola EZX A1200")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = a1200_init,
@@ -1124,6 +1129,7 @@ MACHINE_START(EZX_A910, "Motorola EZX A910")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = a910_init,
@@ -1190,6 +1196,7 @@ MACHINE_START(EZX_E6, "Motorola EZX E6")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = e6_init,
@@ -1230,6 +1237,7 @@ MACHINE_START(EZX_E2, "Motorola EZX E2")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = e2_init,
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index baabb3ce088e..6451e9c3a93f 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -66,8 +66,7 @@ unsigned int get_clk_frequency_khz(int info)
                 return pxa25x_get_clk_frequency_khz(info);
         else if (cpu_is_pxa27x())
                 return pxa27x_get_clk_frequency_khz(info);
-        else
-                return pxa3xx_get_clk_frequency_khz(info);
+        return 0;
 }
 EXPORT_SYMBOL(get_clk_frequency_khz);
 
@@ -80,8 +79,7 @@ unsigned int get_memclk_frequency_10khz(void)
                 return pxa25x_get_memclk_frequency_10khz();
         else if (cpu_is_pxa27x())
                 return pxa27x_get_memclk_frequency_10khz();
-        else
-                return pxa3xx_get_memclk_frequency_10khz();
+        return 0;
 }
 EXPORT_SYMBOL(get_memclk_frequency_10khz);
 
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index c6305c5b8a72..4b1ad2769ed7 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -54,11 +54,9 @@ static inline void pxa2xx_clear_reset_status(unsigned int mask) {}
 
 #ifdef CONFIG_PXA3xx
 extern unsigned pxa3xx_get_clk_frequency_khz(int);
-extern unsigned pxa3xx_get_memclk_frequency_10khz(void);
 extern void pxa3xx_clear_reset_status(unsigned int);
 #else
 #define pxa3xx_get_clk_frequency_khz(x)         (0)
-#define pxa3xx_get_memclk_frequency_10khz()     (0)
 static inline void pxa3xx_clear_reset_status(unsigned int mask) {}
 #endif
 
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 848c861dd23f..10104f16e6e4 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -874,6 +874,7 @@ MACHINE_START(H4700, "HP iPAQ HX4700")
         .io_pg_offst  = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params  = 0xa0000100,
         .map_io       = pxa_map_io,
+        .nr_irqs      = HX4700_NR_IRQS,
         .init_irq     = pxa27x_init_irq,
         .init_machine = hx4700_init,
         .timer        = &pxa_timer,
diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
index eec92e6fd7cf..561562b4360b 100644
--- a/arch/arm/mach-pxa/include/mach/balloon3.h
+++ b/arch/arm/mach-pxa/include/mach/balloon3.h
@@ -174,6 +174,8 @@ enum balloon3_features {
 #define BALLOON3_CODEC_IRQ      IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ)
 #define BALLOON3_S0_CD_IRQ      IRQ_GPIO(BALLOON3_GPIO_S0_CD)
 
+#define BALLOON3_NR_IRQS        (IRQ_BOARD_START + 4)
+
 extern int balloon3_has(enum balloon3_features feature);
 
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/eseries-irq.h b/arch/arm/mach-pxa/include/mach/eseries-irq.h
index f2a93d5e31d3..de292b269c63 100644
--- a/arch/arm/mach-pxa/include/mach/eseries-irq.h
+++ b/arch/arm/mach-pxa/include/mach/eseries-irq.h
@@ -25,3 +25,4 @@
 #define TMIO_SD_IRQ     IRQ_TMIO(1)
 #define TMIO_USB_IRQ    IRQ_TMIO(2)
 
+#define ESERIES_NR_IRQS (IRQ_BOARD_START + 16)
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 7f64d24cd564..814f1458a06a 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -264,23 +264,35 @@
  * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
  * == 0x3 for pxa300/pxa310/pxa320
  */
+#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
 #define __cpu_is_pxa2xx(id)                             \
         ({                                              \
                 unsigned int _id = (id) >> 13 & 0x7;    \
                 _id <= 0x2;                             \
          })
+#else
+#define __cpu_is_pxa2xx(id)     (0)
+#endif
 
+#ifdef CONFIG_PXA3xx
 #define __cpu_is_pxa3xx(id)                             \
         ({                                              \
                 unsigned int _id = (id) >> 13 & 0x7;    \
                 _id == 0x3;                             \
          })
+#else
+#define __cpu_is_pxa3xx(id)     (0)
+#endif
 
+#if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935)
 #define __cpu_is_pxa93x(id)                             \
         ({                                              \
                 unsigned int _id = (id) >> 4 & 0xfff;   \
                 _id == 0x683 || _id == 0x693;           \
          })
+#else
+#define __cpu_is_pxa93x(id)     (0)
+#endif
 
 #define cpu_is_pxa2xx()                                 \
         ({                                              \
@@ -309,7 +321,7 @@ extern unsigned long get_clock_tick_rate(void);
 #define PCIBIOS_MIN_IO          0
 #define PCIBIOS_MIN_MEM         0
 #define pcibios_assign_all_busses()     1
+#define ARCH_HAS_DMA_SET_COHERENT_MASK
 #endif
 
-
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-pxa/include/mach/hx4700.h b/arch/arm/mach-pxa/include/mach/hx4700.h
index 9eaeed1f87f1..37408449ec25 100644
--- a/arch/arm/mach-pxa/include/mach/hx4700.h
+++ b/arch/arm/mach-pxa/include/mach/hx4700.h
@@ -17,6 +17,7 @@
 
 #define HX4700_ASIC3_GPIO_BASE  NR_BUILTIN_GPIO
 #define HX4700_EGPIO_BASE       (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS)
+#define HX4700_NR_IRQS          (IRQ_BOARD_START + 70)
 
 /*
  * PXA GPIOs
diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h
index 262691fb97d8..fdca3be47d9b 100644
--- a/arch/arm/mach-pxa/include/mach/io.h
+++ b/arch/arm/mach-pxa/include/mach/io.h
@@ -6,6 +6,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
+#include <mach/hardware.h>
+
 #define IO_SPACE_LIMIT 0xffffffff
 
 /*
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index ffc8314520f2..d372caa75dc7 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -117,48 +117,12 @@
 /*
  * The following interrupts are for board specific purposes. Since
  * the kernel can only run on one machine at a time, we can re-use
- * these.  There will be 16 IRQs by default.  If it is not enough,
- * IRQ_BOARD_END is allowed be customized for each board, but keep
- * the numbers within sensible limits and in descending order, so
- * when multiple config options are selected, the maximum will be
- * used.
+ * these.
+ * By default, no board IRQ is reserved. It should be finished in
+ * custom board since sparse IRQ is already enabled.
  */
 #define IRQ_BOARD_START         (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
 
-#if defined(CONFIG_MACH_H4700)
-#define IRQ_BOARD_END           (IRQ_BOARD_START + 70)
-#elif defined(CONFIG_MACH_ZYLONITE)
-#define IRQ_BOARD_END           (IRQ_BOARD_START + 32)
-#elif defined(CONFIG_PXA_EZX)
-#define IRQ_BOARD_END           (IRQ_BOARD_START + 23)
-#else
-#define IRQ_BOARD_END           (IRQ_BOARD_START + 16)
-#endif
-
-/*
- * Figure out the MAX IRQ number.
- *
- * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
- * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
- * Otherwise, we have the standard IRQs only.
- */
-#ifdef CONFIG_SA1111
-#define NR_IRQS                 (IRQ_BOARD_END + 55)
-#elif defined(CONFIG_PXA_HAVE_BOARD_IRQS)
-#define NR_IRQS                 (IRQ_BOARD_END)
-#else
 #define NR_IRQS                 (IRQ_BOARD_START)
-#endif
-
-/* add IT8152 IRQs beyond BOARD_END */
-#ifdef CONFIG_PCI_HOST_ITE8152
-#define IT8152_LAST_IRQ         (IRQ_BOARD_END + 40)
-
-#if NR_IRQS < (IT8152_LAST_IRQ+1)
-#undef NR_IRQS
-#define NR_IRQS (IT8152_LAST_IRQ+1)
-#endif
-
-#endif /* CONFIG_PCI_HOST_ITE8152 */
 
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h
index 6c9b21c51322..2a5726c15e0e 100644
--- a/arch/arm/mach-pxa/include/mach/littleton.h
+++ b/arch/arm/mach-pxa/include/mach/littleton.h
@@ -10,4 +10,6 @@
 #define EXT0_GPIO_BASE  (NR_BUILTIN_GPIO)
 #define EXT0_GPIO(x)    (EXT0_GPIO_BASE + (x))
 
+#define LITTLETON_NR_IRQS       (IRQ_BOARD_START + 8)
+
 #endif /* __ASM_ARCH_LITTLETON_H */
diff --git a/arch/arm/mach-pxa/include/mach/lpd270.h b/arch/arm/mach-pxa/include/mach/lpd270.h
index 0e6440c81683..cd070092b6eb 100644
--- a/arch/arm/mach-pxa/include/mach/lpd270.h
+++ b/arch/arm/mach-pxa/include/mach/lpd270.h
@@ -38,5 +38,6 @@
 #define LPD270_USBC_IRQ         LPD270_IRQ(2)
 #define LPD270_ETHERNET_IRQ     LPD270_IRQ(3)
 #define LPD270_AC97_IRQ         LPD270_IRQ(4)
+#define LPD270_NR_IRQS          (IRQ_BOARD_START + 5)
 
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h
index a0d4247f08fc..2a086e8373eb 100644
--- a/arch/arm/mach-pxa/include/mach/lubbock.h
+++ b/arch/arm/mach-pxa/include/mach/lubbock.h
@@ -45,6 +45,9 @@
 #define LUBBOCK_USB_DISC_IRQ    LUBBOCK_IRQ(6)  /* usb disconnect */
 #define LUBBOCK_LAST_IRQ        LUBBOCK_IRQ(6)
 
+#define LUBBOCK_SA1111_IRQ_BASE (IRQ_BOARD_START + 16)
+#define LUBBOCK_NR_IRQS         (IRQ_BOARD_START + 16 + 55)
+
 #ifndef __ASSEMBLY__
 extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h
index 20ef37d4a9a7..0a2efcf7947c 100644
--- a/arch/arm/mach-pxa/include/mach/magician.h
+++ b/arch/arm/mach-pxa/include/mach/magician.h
@@ -71,6 +71,8 @@
 #define IRQ_MAGICIAN_BT         (IRQ_BOARD_START + 2)
 #define IRQ_MAGICIAN_VBUS       (IRQ_BOARD_START + 3)
 
+#define MAGICIAN_NR_IRQS        (IRQ_BOARD_START + 8)
+
 /*
  * CPLD EGPIOs
  */
diff --git a/arch/arm/mach-pxa/include/mach/mainstone.h b/arch/arm/mach-pxa/include/mach/mainstone.h
index 86e623abd64d..4c2d11cd824d 100644
--- a/arch/arm/mach-pxa/include/mach/mainstone.h
+++ b/arch/arm/mach-pxa/include/mach/mainstone.h
@@ -134,4 +134,6 @@
 #define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
 #define MAINSTONE_S1_IRQ        MAINSTONE_IRQ(15)
 
+#define MAINSTONE_NR_IRQS       (IRQ_BOARD_START + 16)
+
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
index 0d119d3b9221..04f7c97044f3 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
@@ -69,6 +69,7 @@
 #define nBE0_GPIO_60            MFP_CFG(nBE0, AF0)
 #define nBE1_GPIO_61            MFP_CFG(nBE1, AF0)
 #define RDY_GPIO_62             MFP_CFG(RDY, AF0)
+#define PMIC_INT_GPIO83         MFP_CFG_LPM(PMIC_INT, AF0, PULL_HIGH)
 
 /* Chip Select */
 #define DF_nCS0_nCS2            MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH)
@@ -92,6 +93,9 @@
 #define GPIO63_CI2C_SCL         MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH)
 #define GPIO64_CI2C_SDA         MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH)
 
+#define GPIO73_CI2C_SCL         MFP_CFG_LPM(GPIO73, AF1, PULL_HIGH)
+#define GPIO74_CI2C_SDA         MFP_CFG_LPM(GPIO74, AF1, PULL_HIGH)
+
 #define GPIO77_CI2C_SCL         MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH)
 #define GPIO78_CI2C_SDA         MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH)
 
@@ -345,6 +349,9 @@
 #define GPIO69_UART1_CTS        MFP_CFG(GPIO69, AF2)
 #define GPIO70_UART1_RTS        MFP_CFG(GPIO70, AF2)
 
+#define GPIO53_UART1_TXD        MFP_CFG(GPIO53, AF2)
+#define GPIO54_UART1_RXD        MFP_CFG(GPIO54, AF2)
+
 /* UART2 - BTUART */
 #define GPIO91_UART2_RXD        MFP_CFG(GPIO91, AF1)
 #define GPIO92_UART2_TXD        MFP_CFG(GPIO92, AF1)
diff --git a/arch/arm/mach-pxa/include/mach/pcm027.h b/arch/arm/mach-pxa/include/mach/pcm027.h
index 04083263167e..4bac588478a8 100644
--- a/arch/arm/mach-pxa/include/mach/pcm027.h
+++ b/arch/arm/mach-pxa/include/mach/pcm027.h
@@ -30,6 +30,8 @@
 #define PCM027_MMCDET_IRQ      PCM027_IRQ(2)
 #define PCM027_PM_5V_IRQ       PCM027_IRQ(3)
 
+#define PCM027_NR_IRQS          (IRQ_BOARD_START + 32)
+
 /* I2C RTC */
 #define PCM027_RTC_IRQ_GPIO     0
 #define PCM027_RTC_IRQ          IRQ_GPIO(PCM027_RTC_IRQ_GPIO)
diff --git a/arch/arm/mach-pxa/include/mach/poodle.h b/arch/arm/mach-pxa/include/mach/poodle.h
index 0b3e6d051c64..83d1cfd00fc9 100644
--- a/arch/arm/mach-pxa/include/mach/poodle.h
+++ b/arch/arm/mach-pxa/include/mach/poodle.h
@@ -85,6 +85,8 @@
 #define POODLE_LOCOMO_GPIO_232VCC_ON   LOCOMO_GPIO(12)
 #define POODLE_LOCOMO_GPIO_JK_B        LOCOMO_GPIO(13)
 
+#define POODLE_NR_IRQS          (IRQ_BOARD_START + 4)   /* 4 for LoCoMo */
+
 extern struct platform_device poodle_locomo_device;
 
 #endif /* __ASM_ARCH_POODLE_H  */
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h b/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h
new file mode 100644
index 000000000000..9d82cb65ea56
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h
@@ -0,0 +1,35 @@
+/*
+ * PXA3xx U2D header
+ *
+ * Copyright (C) 2010 CompuLab Ltd.
+ *
+ * Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __PXA310_U2D__
+#define __PXA310_U2D__
+
+#include <linux/usb/ulpi.h>
+
+struct pxa3xx_u2d_platform_data {
+
+#define ULPI_SER_6PIN   (1 << 0)
+#define ULPI_SER_3PIN   (1 << 1)
+        unsigned int ulpi_mode;
+
+        int (*init)(struct device *);
+        void (*exit)(struct device *);
+};
+
+
+/* Start PXA3xx U2D host */
+int pxa3xx_u2d_start_hc(struct usb_bus *host);
+/* Stop PXA3xx U2D host */
+void pxa3xx_u2d_stop_hc(struct usb_bus *host);
+
+extern void pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info);
+
+#endif /* __PXA310_U2D__ */
diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h
index 1bbd1f2e4beb..1272c4b56ceb 100644
--- a/arch/arm/mach-pxa/include/mach/tosa.h
+++ b/arch/arm/mach-pxa/include/mach/tosa.h
@@ -20,6 +20,7 @@
 /* Jacket Scoop */
 #define TOSA_SCOOP_PHYS         (PXA_CS5_PHYS + 0x00800000)
 
+#define TOSA_NR_IRQS            (IRQ_BOARD_START + TC6393XB_NR_IRQS)
 /*
  * SCOOP2 internal GPIOs
  */
diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h
index 6e119976003e..faa408ab7ad7 100644
--- a/arch/arm/mach-pxa/include/mach/zeus.h
+++ b/arch/arm/mach-pxa/include/mach/zeus.h
@@ -15,6 +15,8 @@
 #ifndef _MACH_ZEUS_H
 #define _MACH_ZEUS_H
 
+#define ZEUS_NR_IRQS            (IRQ_BOARD_START + 48)
+
 /* Physical addresses */
 #define ZEUS_FLASH_PHYS         PXA_CS0_PHYS
 #define ZEUS_ETH0_PHYS          PXA_CS1_PHYS
diff --git a/arch/arm/mach-pxa/include/mach/zylonite.h b/arch/arm/mach-pxa/include/mach/zylonite.h
index 9edf645368d6..ea24998b923c 100644
--- a/arch/arm/mach-pxa/include/mach/zylonite.h
+++ b/arch/arm/mach-pxa/include/mach/zylonite.h
@@ -5,6 +5,8 @@
 
 #define EXT_GPIO(x)             (128 + (x))
 
+#define ZYLONITE_NR_IRQS        (IRQ_BOARD_START + 32)
+
 /* the following variables are processor specific and initialized
  * by the corresponding zylonite_pxa3xx_init()
  */
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 9b9046185b00..eb5850624c1d 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -43,7 +43,7 @@
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/pxa2xx_spi.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/littleton.h>
 #include <plat/i2c.h>
 #include <plat/pxa3xx_nand.h>
@@ -441,6 +441,7 @@ MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleto
         .boot_params    = 0xa0000100,
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
+        .nr_irqs        = LITTLETON_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = littleton_init,
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index d279507fc748..fc9502ef4024 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -509,6 +509,7 @@ MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = lpd270_map_io,
+        .nr_irqs        = LPD270_NR_IRQS,
         .init_irq       = lpd270_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = lpd270_init,
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 330c3282856e..1956c23093d1 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -229,7 +229,7 @@ static struct resource sa1111_resources[] = {
 };
 
 static struct sa1111_platform_data sa1111_info = {
-        .irq_base       = IRQ_BOARD_END,
+        .irq_base       = LUBBOCK_SA1111_IRQ_BASE,
 };
 
 static struct platform_device sa1111_device = {
@@ -560,6 +560,7 @@ MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
         .phys_io        = 0x40000000,
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = lubbock_map_io,
+        .nr_irqs        = LUBBOCK_NR_IRQS,
         .init_irq       = lubbock_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = lubbock_init,
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index e81dd0c8e40d..42a0c2b41281 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -768,6 +768,7 @@ MACHINE_START(MAGICIAN, "HTC Magician")
         .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params = 0xa0000100,
         .map_io = pxa_map_io,
+        .nr_irqs = MAGICIAN_NR_IRQS,
         .init_irq = pxa27x_init_irq,
         .init_machine = magician_init,
         .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 5543c64da9ef..8b710024601c 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -50,7 +50,7 @@
 #include <mach/mmc.h>
 #include <mach/irda.h>
 #include <mach/ohci.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -628,6 +628,7 @@ MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
         .boot_params    = 0xa0000100,   /* BLOB boot parameter setting */
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = mainstone_map_io,
+        .nr_irqs        = MAINSTONE_NR_IRQS,
         .init_irq       = mainstone_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = mainstone_init,
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index dc66942ef9ab..ffb3f5a8a086 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -45,7 +45,7 @@
 
 #include <mach/pxa27x.h>
 #include <mach/regs-rtc.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/udc.h>
diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c
index 77ad6d34ab5b..405b92a29793 100644
--- a/arch/arm/mach-pxa/palm27x.c
+++ b/arch/arm/mach-pxa/palm27x.c
@@ -469,9 +469,13 @@ static struct i2c_board_info __initdata palm27x_pi2c_board_info[] = {
         },
 };
 
+static struct i2c_pxa_platform_data palm27x_i2c_power_info = {
+        .use_pio        = 1,
+};
+
 void __init palm27x_pmic_init(void)
 {
         i2c_register_board_info(1, ARRAY_AND_SIZE(palm27x_pi2c_board_info));
-        pxa27x_set_i2c_power_info(NULL);
+        pxa27x_set_i2c_power_info(&palm27x_i2c_power_info);
 }
 #endif
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 91038eeafe44..3ff0c4a1ca4c 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -39,7 +39,7 @@
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
 #include <mach/irda.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/palmasoc.h>
 #include <mach/palm27x.h>
 
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 1c281995f658..5b9f766d1468 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -39,7 +39,7 @@
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
 #include <mach/irda.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/udc.h>
 #include <mach/palmasoc.h>
 #include <mach/palm27x.h>
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index 52defd5e42e5..f685a600a181 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -39,7 +39,7 @@
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
 #include <mach/irda.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/udc.h>
 #include <mach/ohci.h>
 #include <mach/pxa2xx-regs.h>
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 144dc2b6911f..89a37922b9d3 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -43,7 +43,7 @@
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
 #include <mach/irda.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/udc.h>
 #include <mach/palmasoc.h>
 #include <mach/palm27x.h>
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 87e4b1044e0b..38f4425bfc95 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -41,7 +41,7 @@
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
 #include <mach/irda.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/udc.h>
 #include <mach/palmasoc.h>
 #include <mach/palm27x.h>
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index 2190af066470..90b08ba8ad1a 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -262,6 +262,7 @@ MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270")
         .phys_io        = 0x40000000,
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pcm027_map_io,
+        .nr_irqs        = PCM027_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = pcm027_init,
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 55e8fcde0141..c04e025cd790 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -469,6 +469,7 @@ MACHINE_START(POODLE, "SHARP Poodle")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .fixup          = fixup_poodle,
         .map_io         = pxa_map_io,
+        .nr_irqs        = POODLE_NR_IRQS,       /* 4 for LoCoMo */
         .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = poodle_init,
diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c
new file mode 100644
index 000000000000..ce7168b233e2
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c
@@ -0,0 +1,400 @@
+/*
+ * linux/arch/arm/mach-pxa/pxa3xx-ulpi.c
+ *
+ * code specific to pxa3xx aka Monahans
+ *
+ * Copyright (C) 2010 CompuLab Ltd.
+ *
+ * 2010-13-07: Igor Grinberg <grinberg@compulab.co.il>
+ *             initial version: pxa310 USB Host mode support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/usb.h>
+#include <linux/usb/otg.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-u2d.h>
+#include <mach/pxa3xx-u2d.h>
+
+struct pxa3xx_u2d_ulpi {
+        struct clk              *clk;
+        void __iomem            *mmio_base;
+
+        struct otg_transceiver  *otg;
+        unsigned int            ulpi_mode;
+};
+
+static struct pxa3xx_u2d_ulpi *u2d;
+
+static inline u32 u2d_readl(u32 reg)
+{
+        return __raw_readl(u2d->mmio_base + reg);
+}
+
+static inline void u2d_writel(u32 reg, u32 val)
+{
+        __raw_writel(val, u2d->mmio_base + reg);
+}
+
+#if defined(CONFIG_PXA310_ULPI)
+enum u2d_ulpi_phy_mode {
+        SYNCH           = 0,
+        CARKIT          = (1 << 0),
+        SER_3PIN        = (1 << 1),
+        SER_6PIN        = (1 << 2),
+        LOWPOWER        = (1 << 3),
+};
+
+static inline enum u2d_ulpi_phy_mode pxa310_ulpi_get_phymode(void)
+{
+        return (u2d_readl(U2DOTGUSR) >> 28) & 0xF;
+}
+
+static int pxa310_ulpi_poll(void)
+{
+        int timeout = 50000;
+
+        while (timeout--) {
+                if (!(u2d_readl(U2DOTGUCR) & U2DOTGUCR_RUN))
+                        return 0;
+
+                cpu_relax();
+        }
+
+        pr_warning("%s: ULPI access timed out!\n", __func__);
+
+        return -ETIMEDOUT;
+}
+
+static int pxa310_ulpi_read(struct otg_transceiver *otg, u32 reg)
+{
+        int err;
+
+        if (pxa310_ulpi_get_phymode() != SYNCH) {
+                pr_warning("%s: PHY is not in SYNCH mode!\n", __func__);
+                return -EBUSY;
+        }
+
+        u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | U2DOTGUCR_RNW | (reg << 16));
+        msleep(5);
+
+        err = pxa310_ulpi_poll();
+        if (err)
+                return err;
+
+        return u2d_readl(U2DOTGUCR) & U2DOTGUCR_RDATA;
+}
+
+static int pxa310_ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
+{
+        if (pxa310_ulpi_get_phymode() != SYNCH) {
+                pr_warning("%s: PHY is not in SYNCH mode!\n", __func__);
+                return -EBUSY;
+        }
+
+        u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | (reg << 16) | (val << 8));
+        msleep(5);
+
+        return pxa310_ulpi_poll();
+}
+
+struct otg_io_access_ops pxa310_ulpi_access_ops = {
+        .read   = pxa310_ulpi_read,
+        .write  = pxa310_ulpi_write,
+};
+
+static void pxa310_otg_transceiver_rtsm(void)
+{
+        u32 u2dotgcr;
+
+        /* put PHY to sync mode */
+        u2dotgcr = u2d_readl(U2DOTGCR);
+        u2dotgcr |=  U2DOTGCR_RTSM | U2DOTGCR_UTMID;
+        u2d_writel(U2DOTGCR, u2dotgcr);
+        msleep(10);
+
+        /* setup OTG sync mode */
+        u2dotgcr = u2d_readl(U2DOTGCR);
+        u2dotgcr |= U2DOTGCR_ULAF;
+        u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
+        u2d_writel(U2DOTGCR, u2dotgcr);
+}
+
+static int pxa310_start_otg_host_transcvr(struct usb_bus *host)
+{
+        int err;
+
+        pxa310_otg_transceiver_rtsm();
+
+        err = otg_init(u2d->otg);
+        if (err) {
+                pr_err("OTG transceiver init failed");
+                return err;
+        }
+
+        err = otg_set_vbus(u2d->otg, 1);
+        if (err) {
+                pr_err("OTG transceiver VBUS set failed");
+                return err;
+        }
+
+        err = otg_set_host(u2d->otg, host);
+        if (err)
+                pr_err("OTG transceiver Host mode set failed");
+
+        return err;
+}
+
+static int pxa310_start_otg_hc(struct usb_bus *host)
+{
+        u32 u2dotgcr;
+        int err;
+
+        /* disable USB device controller */
+        u2d_writel(U2DCR, u2d_readl(U2DCR) & ~U2DCR_UDE);
+        u2d_writel(U2DOTGCR, u2d_readl(U2DOTGCR) | U2DOTGCR_UTMID);
+        u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F);
+
+        err = pxa310_start_otg_host_transcvr(host);
+        if (err)
+                return err;
+
+        /* set xceiver mode */
+        if (u2d->ulpi_mode & ULPI_IC_6PIN_SERIAL)
+                u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) & ~U2DP3CR_P2SS);
+        else if (u2d->ulpi_mode & ULPI_IC_3PIN_SERIAL)
+                u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) | U2DP3CR_P2SS);
+
+        /* start OTG host controller */
+        u2dotgcr = u2d_readl(U2DOTGCR) | U2DOTGCR_SMAF;
+        u2d_writel(U2DOTGCR, u2dotgcr & ~(U2DOTGCR_ULAF | U2DOTGCR_CKAF));
+
+        return 0;
+}
+
+static void pxa310_stop_otg_hc(void)
+{
+        pxa310_otg_transceiver_rtsm();
+
+        otg_set_host(u2d->otg, NULL);
+        otg_set_vbus(u2d->otg, 0);
+        otg_shutdown(u2d->otg);
+}
+
+static void pxa310_u2d_setup_otg_hc(void)
+{
+        u32 u2dotgcr;
+
+        u2dotgcr = u2d_readl(U2DOTGCR);
+        u2dotgcr |= U2DOTGCR_ULAF | U2DOTGCR_UTMID;
+        u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
+        u2d_writel(U2DOTGCR, u2dotgcr);
+        msleep(5);
+        u2d_writel(U2DOTGCR, u2dotgcr | U2DOTGCR_ULE);
+        msleep(5);
+        u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F);
+}
+
+static int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata)
+{
+        unsigned int ulpi_mode = ULPI_OTG_DRVVBUS;
+
+        if (pdata) {
+                if (pdata->ulpi_mode & ULPI_SER_6PIN)
+                        ulpi_mode |= ULPI_IC_6PIN_SERIAL;
+                else if (pdata->ulpi_mode & ULPI_SER_3PIN)
+                        ulpi_mode |= ULPI_IC_3PIN_SERIAL;
+        }
+
+        u2d->ulpi_mode = ulpi_mode;
+
+        u2d->otg = otg_ulpi_create(&pxa310_ulpi_access_ops, ulpi_mode);
+        if (!u2d->otg)
+                return -ENOMEM;
+
+        u2d->otg->io_priv = u2d->mmio_base;
+
+        return 0;
+}
+
+static void pxa310_otg_exit(void)
+{
+        kfree(u2d->otg);
+}
+#else
+static inline void pxa310_u2d_setup_otg_hc(void) {}
+static inline int pxa310_start_otg_hc(struct usb_bus *host)
+{
+        return 0;
+}
+static inline void pxa310_stop_otg_hc(void) {}
+static inline int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata)
+{
+        return 0;
+}
+static inline void pxa310_otg_exit(void) {}
+#endif /* CONFIG_PXA310_ULPI */
+
+int pxa3xx_u2d_start_hc(struct usb_bus *host)
+{
+        int err = 0;
+
+        /* In case the PXA3xx ULPI isn't used, do nothing. */
+        if (!u2d)
+                return 0;
+
+        clk_enable(u2d->clk);
+
+        if (cpu_is_pxa310()) {
+                pxa310_u2d_setup_otg_hc();
+                err = pxa310_start_otg_hc(host);
+        }
+
+        return err;
+}
+
+void pxa3xx_u2d_stop_hc(struct usb_bus *host)
+{
+        /* In case the PXA3xx ULPI isn't used, do nothing. */
+        if (!u2d)
+                return;
+
+        if (cpu_is_pxa310())
+                pxa310_stop_otg_hc();
+
+        clk_disable(u2d->clk);
+}
+
+static int pxa3xx_u2d_probe(struct platform_device *pdev)
+{
+        struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data;
+        struct resource *r;
+        int err;
+
+        u2d = kzalloc(sizeof(struct pxa3xx_u2d_ulpi), GFP_KERNEL);
+        if (!u2d) {
+                dev_err(&pdev->dev, "failed to allocate memory\n");
+                return -ENOMEM;
+        }
+
+        u2d->clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(u2d->clk)) {
+                dev_err(&pdev->dev, "failed to get u2d clock\n");
+                err = PTR_ERR(u2d->clk);
+                goto err_free_mem;
+        }
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!r) {
+                dev_err(&pdev->dev, "no IO memory resource defined\n");
+                err = -ENODEV;
+                goto err_put_clk;
+        }
+
+        r = request_mem_region(r->start, resource_size(r), pdev->name);
+        if (!r) {
+                dev_err(&pdev->dev, "failed to request memory resource\n");
+                err = -EBUSY;
+                goto err_put_clk;
+        }
+
+        u2d->mmio_base = ioremap(r->start, resource_size(r));
+        if (!u2d->mmio_base) {
+                dev_err(&pdev->dev, "ioremap() failed\n");
+                err = -ENODEV;
+                goto err_free_res;
+        }
+
+        if (pdata->init) {
+                err = pdata->init(&pdev->dev);
+                if (err)
+                        goto err_free_io;
+        }
+
+        /* Only PXA310 U2D has OTG functionality */
+        if (cpu_is_pxa310()) {
+                err = pxa310_otg_init(pdata);
+                if (err)
+                        goto err_free_plat;
+        }
+
+        platform_set_drvdata(pdev, &u2d);
+
+        return 0;
+
+err_free_plat:
+        if (pdata->exit)
+                pdata->exit(&pdev->dev);
+err_free_io:
+        iounmap(u2d->mmio_base);
+err_free_res:
+        release_mem_region(r->start, resource_size(r));
+err_put_clk:
+        clk_put(u2d->clk);
+err_free_mem:
+        kfree(u2d);
+        return err;
+}
+
+static int pxa3xx_u2d_remove(struct platform_device *pdev)
+{
+        struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data;
+        struct resource *r;
+
+        if (cpu_is_pxa310()) {
+                pxa310_stop_otg_hc();
+                pxa310_otg_exit();
+        }
+
+        if (pdata->exit)
+                pdata->exit(&pdev->dev);
+
+        platform_set_drvdata(pdev, NULL);
+        iounmap(u2d->mmio_base);
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(r->start, resource_size(r));
+
+        clk_put(u2d->clk);
+
+        kfree(u2d);
+
+        return 0;
+}
+
+static struct platform_driver pxa3xx_u2d_ulpi_driver = {
+        .driver         = {
+                .name   = "pxa3xx-u2d",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = pxa3xx_u2d_probe,
+        .remove         = pxa3xx_u2d_remove,
+};
+
+static int pxa3xx_u2d_ulpi_init(void)
+{
+        return platform_driver_register(&pxa3xx_u2d_ulpi_driver);
+}
+module_init(pxa3xx_u2d_ulpi_init);
+
+static void __exit pxa3xx_u2d_ulpi_exit(void)
+{
+        platform_driver_unregister(&pxa3xx_u2d_ulpi_driver);
+}
+module_exit(pxa3xx_u2d_ulpi_exit);
+
+MODULE_DESCRIPTION("PXA3xx U2D ULPI driver");
+MODULE_AUTHOR("Igor Grinberg");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index fa0014847c71..c85c3a7abd31 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -98,23 +98,6 @@ unsigned int pxa3xx_get_clk_frequency_khz(int info)
         return CLK / 1000;
 }
 
-/*
- * Return the current static memory controller clock frequency
- * in units of 10kHz
- */
-unsigned int pxa3xx_get_memclk_frequency_10khz(void)
-{
-        unsigned long acsr;
-        unsigned int smcfs, clk = 0;
-
-        acsr = ACSR;
-
-        smcfs = (acsr >> 23) & 0x7;
-        clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
-
-        return (clk / 10000);
-}
-
 void pxa3xx_clear_reset_status(unsigned int mask)
 {
         /* RESET_STATUS_* has a 1:1 mapping with ARSR */
@@ -265,7 +248,7 @@ static struct clk_lookup pxa3xx_clkregs[] = {
         INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
         INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
         INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
-        INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"),
+        INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
         INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
         INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
         INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c
index 064292008288..7d29dd3af79d 100644
--- a/arch/arm/mach-pxa/pxa930.c
+++ b/arch/arm/mach-pxa/pxa930.c
@@ -192,7 +192,7 @@ static struct mfp_addr_map pxa935_mfp_addr_map[] __initdata = {
 
 static int __init pxa930_init(void)
 {
-        if (cpu_is_pxa930() || cpu_is_pxa935()) {
+        if (cpu_is_pxa930() || cpu_is_pxa935() || cpu_is_pxa950()) {
                 mfp_init_base(io_p2v(MFPR_BASE));
                 mfp_init_addr(pxa930_mfp_addr_map);
         }
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index a654d1e6b38a..62de07341cc6 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -56,6 +56,8 @@
 #include "devices.h"
 #include "generic.h"
 
+#define STARGATE_NR_IRQS        (IRQ_BOARD_START + 8)
+
 /* Bluetooth */
 #define SG2_BT_RESET            81
 
@@ -1011,6 +1013,7 @@ MACHINE_START(STARGATE2, "Stargate 2")
         .phys_io = 0x40000000,
         .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io = pxa_map_io,
+        .nr_irqs = STARGATE_NR_IRQS,
         .init_irq = pxa27x_init_irq,
         .timer = &pxa_timer,
         .init_machine = stargate2_init,
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index f02dcb5b4e97..0f440c9d7cbd 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -25,7 +25,7 @@
 
 #include <mach/pxa930.h>
 #include <mach/pxafb.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c
new file mode 100644
index 000000000000..5eeba64515e4
--- /dev/null
+++ b/arch/arm/mach-pxa/tavorevb3.c
@@ -0,0 +1,136 @@
+/*
+ *  linux/arch/arm/mach-pxa/tavorevb3.c
+ *
+ *  Support for the Marvell EVB3 Development Platform.
+ *
+ *  Copyright:  (C) Copyright 2008-2010 Marvell International Ltd.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/mfd/88pm860x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/pxa930.h>
+
+#include <plat/i2c.h>
+
+#include "devices.h"
+#include "generic.h"
+
+#define TAVOREVB3_NR_IRQS       (IRQ_BOARD_START + 24)
+
+static mfp_cfg_t evb3_mfp_cfg[] __initdata = {
+        /* UART */
+        GPIO53_UART1_TXD,
+        GPIO54_UART1_RXD,
+
+        /* PMIC */
+        PMIC_INT_GPIO83,
+};
+
+#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
+static struct pm860x_touch_pdata evb3_touch = {
+        .gpadc_prebias  = 1,
+        .slot_cycle     = 1,
+        .tsi_prebias    = 6,
+        .pen_prebias    = 16,
+        .pen_prechg     = 2,
+        .res_x          = 300,
+};
+
+static struct pm860x_backlight_pdata evb3_backlight[] = {
+        {
+                .id     = PM8606_ID_BACKLIGHT,
+                .iset   = PM8606_WLED_CURRENT(24),
+                .flags  = PM8606_BACKLIGHT1,
+        },
+        {},
+};
+
+static struct pm860x_led_pdata evb3_led[] = {
+        {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED1_RED,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED1_GREEN,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED1_BLUE,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED2_RED,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED2_GREEN,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED2_BLUE,
+        },
+};
+
+static struct pm860x_platform_data evb3_pm8607_info = {
+        .touch                          = &evb3_touch,
+        .backlight                      = &evb3_backlight[0],
+        .led                            = &evb3_led[0],
+        .companion_addr                 = 0x10,
+        .irq_mode                       = 0,
+        .irq_base                       = IRQ_BOARD_START,
+
+        .i2c_port                       = GI2C_PORT,
+};
+
+static struct i2c_board_info evb3_i2c_info[] = {
+        {
+                .type           = "88PM860x",
+                .addr           = 0x34,
+                .platform_data  = &evb3_pm8607_info,
+                .irq            = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)),
+        },
+};
+
+static void __init evb3_init_i2c(void)
+{
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(evb3_i2c_info));
+}
+#else
+static inline void evb3_init_i2c(void) {}
+#endif
+
+static void __init evb3_init(void)
+{
+        /* initialize MFP configurations */
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(evb3_mfp_cfg));
+
+        pxa_set_ffuart_info(NULL);
+
+        evb3_init_i2c();
+}
+
+MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)")
+        .phys_io        = 0x40000000,
+        .boot_params    = 0xa0000100,
+        .map_io         = pxa_map_io,
+        .nr_irqs        = TAVOREVB3_NR_IRQS,
+        .init_irq       = pxa3xx_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = evb3_init,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 83cc3a18c2e9..3a06e98b4920 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -956,6 +956,7 @@ MACHINE_START(TOSA, "SHARP Tosa")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .fixup          = fixup_tosa,
         .map_io         = pxa_map_io,
+        .nr_irqs        = TOSA_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .init_machine   = tosa_init,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index c9b747cedea8..37d6173bbb66 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -240,6 +240,7 @@ static void __init vpac270_onenand_init(void) {}
 #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
 static struct pxamci_platform_data vpac270_mci_platform_data = {
         .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
+        .gpio_power             = -1,
         .gpio_card_detect       = GPIO53_VPAC270_SD_DETECT_N,
         .gpio_card_ro           = GPIO52_VPAC270_SD_READONLY,
         .detect_delay_ms        = 200,
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index f0d02288b4ca..8c44bc4381ba 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -37,7 +37,7 @@
 #include <mach/z2.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/pxa2xx_spi.h>
 
 #include <plat/i2c.h>
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 03b9cb910e08..9da2b624ba20 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -904,6 +904,7 @@ MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
         .io_pg_offst    = ((io_p2v(0x40000000) >> 18) & 0xfffc),
         .boot_params    = 0xa0000100,
         .map_io         = zeus_map_io,
+        .nr_irqs        = ZEUS_NR_IRQS,
         .init_irq       = zeus_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = zeus_init,
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index c479cbecf784..69df3edcdd98 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -30,7 +30,7 @@
 #include <mach/zylonite.h>
 #include <mach/mmc.h>
 #include <mach/ohci.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <plat/pxa3xx_nand.h>
 
 #include "devices.h"
@@ -415,6 +415,7 @@ MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
         .boot_params    = 0xa0000100,
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ZYLONITE_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = zylonite_init,
diff --git a/arch/arm/mach-rpc/include/mach/vmalloc.h b/arch/arm/mach-rpc/include/mach/vmalloc.h
index 9a96fd69e705..3bcd86fadb81 100644
--- a/arch/arm/mach-rpc/include/mach/vmalloc.h
+++ b/arch/arm/mach-rpc/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x1c000000)
+#define VMALLOC_END       0xdc000000
diff --git a/arch/arm/mach-shark/include/mach/vmalloc.h b/arch/arm/mach-shark/include/mach/vmalloc.h
index f6c6837c5451..8e845b6a7cb5 100644
--- a/arch/arm/mach-shark/include/mach/vmalloc.h
+++ b/arch/arm/mach-shark/include/mach/vmalloc.h
@@ -1,4 +1,4 @@
 /*
  * arch/arm/mach-shark/include/mach/vmalloc.h
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
diff --git a/arch/arm/mach-tcc8k/Kconfig b/arch/arm/mach-tcc8k/Kconfig
new file mode 100644
index 000000000000..ad86415d1577
--- /dev/null
+++ b/arch/arm/mach-tcc8k/Kconfig
@@ -0,0 +1,11 @@
+if ARCH_TCC8K
+
+comment "TCC8000 systems:"
+
+config MACH_TCC8000_SDK
+        bool "Telechips TCC8000-SDK development kit"
+        default y
+        help
+          Support for the Telechips TCC8000-SDK board.
+
+endif
diff --git a/arch/arm/mach-tcc8k/Makefile b/arch/arm/mach-tcc8k/Makefile
new file mode 100644
index 000000000000..9bacf31e49ba
--- /dev/null
+++ b/arch/arm/mach-tcc8k/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for TCC8K boards and common files.
+#
+
+# Common support
+obj-y += clock.o irq.o time.o io.o devices.o
+
+# Board specific support
+obj-$(CONFIG_MACH_TCC8000_SDK) += board-tcc8000-sdk.o
diff --git a/arch/arm/mach-tcc8k/Makefile.boot b/arch/arm/mach-tcc8k/Makefile.boot
new file mode 100644
index 000000000000..f135c9deae10
--- /dev/null
+++ b/arch/arm/mach-tcc8k/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y           := 0x20008000
+params_phys-y           := 0x20000100
+initrd_phys-y           := 0x20800000
diff --git a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
new file mode 100644
index 000000000000..4e42555b2009
--- /dev/null
+++ b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-types.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+
+#include <mach/clock.h>
+
+#include "common.h"
+
+#define XI_FREQUENCY    12000000
+#define XTI_FREQUENCY   32768
+
+#ifdef CONFIG_MTD_NAND_TCC
+/* NAND */
+static struct tcc_nand_platform_data tcc8k_sdk_nand_data = {
+        .width = 1,
+        .hw_ecc = 0,
+};
+#endif
+
+static void __init tcc8k_init(void)
+{
+#ifdef CONFIG_MTD_NAND_TCC
+        tcc_nand_device.dev.platform_data = &tcc8k_sdk_nand_data;
+        platform_device_register(&tcc_nand_device);
+#endif
+}
+
+static void __init tcc8k_init_timer(void)
+{
+        tcc_clocks_init(XI_FREQUENCY, XTI_FREQUENCY);
+}
+
+static struct sys_timer tcc8k_timer = {
+        .init   = tcc8k_init_timer,
+};
+
+static void __init tcc8k_map_io(void)
+{
+        tcc8k_map_common_io();
+}
+
+MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board")
+        .phys_io        = 0x90000000,
+        .io_pg_offst    = ((0xf1000000) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x00000100,
+        .map_io         = tcc8k_map_io,
+        .init_irq       = tcc8k_init_irq,
+        .init_machine   = tcc8k_init,
+        .timer          = &tcc8k_timer,
+MACHINE_END
diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c
new file mode 100644
index 000000000000..ba32a15127ab
--- /dev/null
+++ b/arch/arm/mach-tcc8k/clock.c
@@ -0,0 +1,567 @@
+/*
+ * Lowlevel clock handling for Telechips TCC8xxx SoCs
+ *
+ * Copyright (C) 2010 by Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPL v2
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+
+#include <asm/clkdev.h>
+
+#include <mach/clock.h>
+#include <mach/irqs.h>
+#include <mach/tcc8k-regs.h>
+
+#include "common.h"
+
+#define BCLKCTR0        (CKC_BASE + BCLKCTR0_OFFS)
+#define BCLKCTR1        (CKC_BASE + BCLKCTR1_OFFS)
+
+#define ACLKREF         (CKC_BASE + ACLKREF_OFFS)
+#define ACLKUART0       (CKC_BASE + ACLKUART0_OFFS)
+#define ACLKUART1       (CKC_BASE + ACLKUART1_OFFS)
+#define ACLKUART2       (CKC_BASE + ACLKUART2_OFFS)
+#define ACLKUART3       (CKC_BASE + ACLKUART3_OFFS)
+#define ACLKUART4       (CKC_BASE + ACLKUART4_OFFS)
+#define ACLKI2C         (CKC_BASE + ACLKI2C_OFFS)
+#define ACLKADC         (CKC_BASE + ACLKADC_OFFS)
+#define ACLKUSBH        (CKC_BASE + ACLKUSBH_OFFS)
+#define ACLKLCD         (CKC_BASE + ACLKLCD_OFFS)
+#define ACLKSDH0        (CKC_BASE + ACLKSDH0_OFFS)
+#define ACLKSDH1        (CKC_BASE + ACLKSDH1_OFFS)
+#define ACLKSPI0        (CKC_BASE + ACLKSPI0_OFFS)
+#define ACLKSPI1        (CKC_BASE + ACLKSPI1_OFFS)
+#define ACLKSPDIF       (CKC_BASE + ACLKSPDIF_OFFS)
+#define ACLKC3DEC       (CKC_BASE + ACLKC3DEC_OFFS)
+#define ACLKCAN0        (CKC_BASE + ACLKCAN0_OFFS)
+#define ACLKCAN1        (CKC_BASE + ACLKCAN1_OFFS)
+#define ACLKGSB0        (CKC_BASE + ACLKGSB0_OFFS)
+#define ACLKGSB1        (CKC_BASE + ACLKGSB1_OFFS)
+#define ACLKGSB2        (CKC_BASE + ACLKGSB2_OFFS)
+#define ACLKGSB3        (CKC_BASE + ACLKGSB3_OFFS)
+#define ACLKUSBH        (CKC_BASE + ACLKUSBH_OFFS)
+#define ACLKTCT         (CKC_BASE + ACLKTCT_OFFS)
+#define ACLKTCX         (CKC_BASE + ACLKTCX_OFFS)
+#define ACLKTCZ         (CKC_BASE + ACLKTCZ_OFFS)
+
+/* Crystal frequencies */
+static unsigned long xi_rate, xti_rate;
+
+static void __iomem *pll_cfg_addr(int pll)
+{
+        switch (pll) {
+        case 0: return (CKC_BASE + PLL0CFG_OFFS);
+        case 1: return (CKC_BASE + PLL1CFG_OFFS);
+        case 2: return (CKC_BASE + PLL2CFG_OFFS);
+        default:
+                BUG();
+        }
+}
+
+static int pll_enable(int pll, int enable)
+{
+        u32 reg;
+        void __iomem *addr = pll_cfg_addr(pll);
+
+        reg = __raw_readl(addr);
+        if (enable)
+                reg &= ~PLLxCFG_PD;
+        else
+                reg |= PLLxCFG_PD;
+
+        __raw_writel(reg, addr);
+        return 0;
+}
+
+static int xi_enable(int enable)
+{
+        u32 reg;
+
+        reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
+        if (enable)
+                reg |= CLKCTRL_XE;
+        else
+                reg &= ~CLKCTRL_XE;
+
+        __raw_writel(reg, CKC_BASE + CLKCTRL_OFFS);
+        return 0;
+}
+
+static int root_clk_enable(enum root_clks src)
+{
+        switch (src) {
+        case CLK_SRC_PLL0: return pll_enable(0, 1);
+        case CLK_SRC_PLL1: return pll_enable(1, 1);
+        case CLK_SRC_PLL2: return pll_enable(2, 1);
+        case CLK_SRC_XI: return xi_enable(1);
+        default:
+                BUG();
+        }
+        return 0;
+}
+
+static int root_clk_disable(enum root_clks root_src)
+{
+        switch (root_src) {
+        case CLK_SRC_PLL0: return pll_enable(0, 0);
+        case CLK_SRC_PLL1: return pll_enable(1, 0);
+        case CLK_SRC_PLL2: return pll_enable(2, 0);
+        case CLK_SRC_XI: return xi_enable(0);
+        default:
+                BUG();
+        }
+        return 0;
+}
+
+static int enable_clk(struct clk *clk)
+{
+        u32 reg;
+
+        if (clk->root_id != CLK_SRC_NOROOT)
+                return root_clk_enable(clk->root_id);
+
+        if (clk->aclkreg) {
+                reg = __raw_readl(clk->aclkreg);
+                reg |= ACLK_EN;
+                __raw_writel(reg, clk->aclkreg);
+        }
+        if (clk->bclkctr) {
+                reg = __raw_readl(clk->bclkctr);
+                reg |= 1 << clk->bclk_shift;
+                __raw_writel(reg, clk->bclkctr);
+        }
+        return 0;
+}
+
+static void disable_clk(struct clk *clk)
+{
+        u32 reg;
+
+        if (clk->root_id != CLK_SRC_NOROOT) {
+                root_clk_disable(clk->root_id);
+                return;
+        }
+
+        if (clk->bclkctr) {
+                reg = __raw_readl(clk->bclkctr);
+                reg &= ~(1 << clk->bclk_shift);
+                __raw_writel(reg, clk->bclkctr);
+        }
+        if (clk->aclkreg) {
+                reg = __raw_readl(clk->aclkreg);
+                reg &= ~ACLK_EN;
+                __raw_writel(reg, clk->aclkreg);
+        }
+}
+
+static unsigned long get_rate_pll(int pll)
+{
+        u32 reg;
+        unsigned long s, m, p;
+        void __iomem *addr = pll_cfg_addr(pll);
+
+        reg = __raw_readl(addr);
+        s = (reg >> 16) & 0x07;
+        m = (reg >> 8) & 0xff;
+        p = reg & 0x3f;
+
+        return (m * xi_rate) / (p * (1 << s));
+}
+
+static unsigned long get_rate_pll_div(int pll)
+{
+        u32 reg;
+        unsigned long div = 0;
+        void __iomem *addr;
+
+        switch (pll) {
+        case 0:
+                addr = CKC_BASE + CLKDIVC0_OFFS;
+                reg = __raw_readl(addr);
+                if (reg & CLKDIVC0_P0E)
+                        div = (reg >> 24) & 0x3f;
+                break;
+        case 1:
+                addr = CKC_BASE + CLKDIVC0_OFFS;
+                reg = __raw_readl(addr);
+                if (reg & CLKDIVC0_P1E)
+                        div = (reg >> 16) & 0x3f;
+                break;
+        case 2:
+                addr = CKC_BASE + CLKDIVC1_OFFS;
+                reg = __raw_readl(addr);
+                if (reg & CLKDIVC1_P2E)
+                        div = __raw_readl(addr) & 0x3f;
+                break;
+        }
+        return get_rate_pll(pll) / (div + 1);
+}
+
+static unsigned long get_rate_xi_div(void)
+{
+        unsigned long div = 0;
+        u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
+
+        if (reg & CLKDIVC0_XE)
+                div = (reg >> 8) & 0x3f;
+
+        return xi_rate / (div + 1);
+}
+
+static unsigned long get_rate_xti_div(void)
+{
+        unsigned long div = 0;
+        u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
+
+        if (reg & CLKDIVC0_XTE)
+                div = reg & 0x3f;
+
+        return xti_rate / (div + 1);
+}
+
+static unsigned long root_clk_get_rate(enum root_clks src)
+{
+        switch (src) {
+        case CLK_SRC_PLL0: return get_rate_pll(0);
+        case CLK_SRC_PLL1: return get_rate_pll(1);
+        case CLK_SRC_PLL2: return get_rate_pll(2);
+        case CLK_SRC_PLL0DIV: return get_rate_pll_div(0);
+        case CLK_SRC_PLL1DIV: return get_rate_pll_div(1);
+        case CLK_SRC_PLL2DIV: return get_rate_pll_div(2);
+        case CLK_SRC_XI: return xi_rate;
+        case CLK_SRC_XTI: return xti_rate;
+        case CLK_SRC_XIDIV: return get_rate_xi_div();
+        case CLK_SRC_XTIDIV: return get_rate_xti_div();
+        default: return 0;
+        }
+}
+
+static unsigned long aclk_get_rate(struct clk *clk)
+{
+        u32 reg;
+        unsigned long div;
+        unsigned int src;
+
+        reg = __raw_readl(clk->aclkreg);
+        div = reg & 0x0fff;
+        src = (reg >> ACLK_SEL_SHIFT) & CLK_SRC_MASK;
+        return root_clk_get_rate(src) / (div + 1);
+}
+
+static unsigned long aclk_best_div(struct clk *clk, unsigned long rate)
+{
+        unsigned long div, src, freq, r1, r2;
+
+        src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
+        src &= CLK_SRC_MASK;
+        freq = root_clk_get_rate(src);
+        div = freq / rate + 1;
+        r1 = freq / div;
+        r2 = freq / (div + 1);
+        if (r2 >= rate)
+                return div + 1;
+        if ((rate - r2) < (r1 - rate))
+                return div + 1;
+
+        return div;
+}
+
+static unsigned long aclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int src;
+
+        src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
+        src &= CLK_SRC_MASK;
+
+        return root_clk_get_rate(src) / aclk_best_div(clk, rate);
+}
+
+static int aclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK;
+        reg |= aclk_best_div(clk, rate);
+        return 0;
+}
+
+static unsigned long get_rate_sys(struct clk *clk)
+{
+        unsigned int src;
+
+        src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK;
+                return root_clk_get_rate(src);
+}
+
+static unsigned long get_rate_bus(struct clk *clk)
+{
+        unsigned int div;
+
+        div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff;
+        return get_rate_sys(clk) / (div + 1);
+}
+
+static unsigned long get_rate_cpu(struct clk *clk)
+{
+        unsigned int reg, div, fsys, fbus;
+
+        fbus = get_rate_bus(clk);
+        reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
+        if (reg & (1 << 29))
+                return fbus;
+        fsys = get_rate_sys(clk);
+        div = (reg >> 16) & 0x0f;
+        return fbus + ((fsys - fbus) * (div + 1)) / 16;
+}
+
+static unsigned long get_rate_root(struct clk *clk)
+{
+        return root_clk_get_rate(clk->root_id);
+}
+
+static int aclk_set_parent(struct clk *clock, struct clk *parent)
+{
+        u32 reg;
+
+        if (clock->parent == parent)
+                return 0;
+
+        clock->parent = parent;
+
+        if (!parent)
+                return 0;
+
+        if (parent->root_id == CLK_SRC_NOROOT)
+                return 0;
+        reg = __raw_readl(clock->aclkreg);
+        reg &= ~ACLK_SEL_MASK;
+        reg |= (parent->root_id << ACLK_SEL_SHIFT) & ACLK_SEL_MASK;
+        __raw_writel(reg, clock->aclkreg);
+
+        return 0;
+}
+
+#define DEFINE_ROOT_CLOCK(name, ri, p)  \
+        static struct clk name = {              \
+                .root_id = ri,                  \
+                .get_rate = get_rate_root,                      \
+                .enable = enable_clk,           \
+                .disable = disable_clk,         \
+                .parent = p,                    \
+        };
+
+#define DEFINE_SPECIAL_CLOCK(name, gr, p)       \
+        static struct clk name = {              \
+                .root_id = CLK_SRC_NOROOT,      \
+                .get_rate = gr,                 \
+                .parent = p,                    \
+        };
+
+#define DEFINE_ACLOCK(name, bc, bs, ar)         \
+        static struct clk name = {              \
+                .root_id = CLK_SRC_NOROOT,      \
+                .bclkctr = bc,                  \
+                .bclk_shift = bs,               \
+                .aclkreg = ar,                  \
+                .get_rate = aclk_get_rate,      \
+                .set_rate = aclk_set_rate,      \
+                .round_rate = aclk_round_rate,  \
+                .enable = enable_clk,           \
+                .disable = disable_clk,         \
+                .set_parent = aclk_set_parent,  \
+        };
+
+#define DEFINE_BCLOCK(name, bc, bs, gr, p)      \
+        static struct clk name = {              \
+                .root_id = CLK_SRC_NOROOT,      \
+                .bclkctr = bc,                  \
+                .bclk_shift = bs,               \
+                .get_rate = gr,                 \
+                .enable = enable_clk,           \
+                .disable = disable_clk,         \
+                .parent = p,                    \
+        };
+
+DEFINE_ROOT_CLOCK(xi, CLK_SRC_XI, NULL)
+DEFINE_ROOT_CLOCK(xti, CLK_SRC_XTI, NULL)
+DEFINE_ROOT_CLOCK(xidiv, CLK_SRC_XIDIV, &xi)
+DEFINE_ROOT_CLOCK(xtidiv, CLK_SRC_XTIDIV, &xti)
+DEFINE_ROOT_CLOCK(pll0, CLK_SRC_PLL0, &xi)
+DEFINE_ROOT_CLOCK(pll1, CLK_SRC_PLL1, &xi)
+DEFINE_ROOT_CLOCK(pll2, CLK_SRC_PLL2, &xi)
+DEFINE_ROOT_CLOCK(pll0div, CLK_SRC_PLL0DIV, &pll0)
+DEFINE_ROOT_CLOCK(pll1div, CLK_SRC_PLL1DIV, &pll1)
+DEFINE_ROOT_CLOCK(pll2div, CLK_SRC_PLL2DIV, &pll2)
+
+/* The following 3 clocks are special and are initialized explicitly later */
+DEFINE_SPECIAL_CLOCK(sys, get_rate_sys, NULL)
+DEFINE_SPECIAL_CLOCK(bus, get_rate_bus, &sys)
+DEFINE_SPECIAL_CLOCK(cpu, get_rate_cpu, &sys)
+
+DEFINE_ACLOCK(tct, NULL, 0, ACLKTCT)
+DEFINE_ACLOCK(tcx, NULL, 0, ACLKTCX)
+DEFINE_ACLOCK(tcz, NULL, 0, ACLKTCZ)
+DEFINE_ACLOCK(ref, NULL, 0, ACLKREF)
+DEFINE_ACLOCK(uart0, BCLKCTR0, 5, ACLKUART0)
+DEFINE_ACLOCK(uart1, BCLKCTR0, 23, ACLKUART1)
+DEFINE_ACLOCK(uart2, BCLKCTR0, 6, ACLKUART2)
+DEFINE_ACLOCK(uart3, BCLKCTR0, 8, ACLKUART3)
+DEFINE_ACLOCK(uart4, BCLKCTR1, 6, ACLKUART4)
+DEFINE_ACLOCK(i2c, BCLKCTR0, 7, ACLKI2C)
+DEFINE_ACLOCK(adc, BCLKCTR0, 10, ACLKADC)
+DEFINE_ACLOCK(usbh0, BCLKCTR0, 11, ACLKUSBH)
+DEFINE_ACLOCK(lcd, BCLKCTR0, 13, ACLKLCD)
+DEFINE_ACLOCK(sd0, BCLKCTR0, 17, ACLKSDH0)
+DEFINE_ACLOCK(sd1, BCLKCTR1, 5, ACLKSDH1)
+DEFINE_ACLOCK(spi0, BCLKCTR0, 24, ACLKSPI0)
+DEFINE_ACLOCK(spi1, BCLKCTR0, 30, ACLKSPI1)
+DEFINE_ACLOCK(spdif, BCLKCTR1, 2, ACLKSPDIF)
+DEFINE_ACLOCK(c3dec, BCLKCTR1, 9, ACLKC3DEC)
+DEFINE_ACLOCK(can0, BCLKCTR1, 10, ACLKCAN0)
+DEFINE_ACLOCK(can1, BCLKCTR1, 11, ACLKCAN1)
+DEFINE_ACLOCK(gsb0, BCLKCTR1, 13, ACLKGSB0)
+DEFINE_ACLOCK(gsb1, BCLKCTR1, 14, ACLKGSB1)
+DEFINE_ACLOCK(gsb2, BCLKCTR1, 15, ACLKGSB2)
+DEFINE_ACLOCK(gsb3, BCLKCTR1, 16, ACLKGSB3)
+DEFINE_ACLOCK(usbh1, BCLKCTR1, 20, ACLKUSBH)
+
+DEFINE_BCLOCK(dai0, BCLKCTR0, 0, NULL, NULL)
+DEFINE_BCLOCK(pic, BCLKCTR0, 1, NULL, NULL)
+DEFINE_BCLOCK(tc, BCLKCTR0, 2, NULL, NULL)
+DEFINE_BCLOCK(gpio, BCLKCTR0, 3, NULL, NULL)
+DEFINE_BCLOCK(usbd, BCLKCTR0, 4, NULL, NULL)
+DEFINE_BCLOCK(ecc, BCLKCTR0, 9, NULL, NULL)
+DEFINE_BCLOCK(gdma0, BCLKCTR0, 12, NULL, NULL)
+DEFINE_BCLOCK(rtc, BCLKCTR0, 15, NULL, NULL)
+DEFINE_BCLOCK(nfc, BCLKCTR0, 16, NULL, NULL)
+DEFINE_BCLOCK(g2d, BCLKCTR0, 18, NULL, NULL)
+DEFINE_BCLOCK(gdma1, BCLKCTR0, 22, NULL, NULL)
+DEFINE_BCLOCK(mscl, BCLKCTR0, 25, NULL, NULL)
+DEFINE_BCLOCK(bdma, BCLKCTR1, 0, NULL, NULL)
+DEFINE_BCLOCK(adma0, BCLKCTR1, 1, NULL, NULL)
+DEFINE_BCLOCK(scfg, BCLKCTR1, 3, NULL, NULL)
+DEFINE_BCLOCK(cid, BCLKCTR1, 4, NULL, NULL)
+DEFINE_BCLOCK(dai1, BCLKCTR1, 7, NULL, NULL)
+DEFINE_BCLOCK(adma1, BCLKCTR1, 8, NULL, NULL)
+DEFINE_BCLOCK(gps, BCLKCTR1, 12, NULL, NULL)
+DEFINE_BCLOCK(gdma2, BCLKCTR1, 17, NULL, NULL)
+DEFINE_BCLOCK(gdma3, BCLKCTR1, 18, NULL, NULL)
+DEFINE_BCLOCK(ddrc, BCLKCTR1, 19, NULL, NULL)
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK(NULL, "bus", bus)
+        _REGISTER_CLOCK(NULL, "cpu", cpu)
+        _REGISTER_CLOCK(NULL, "tct", tct)
+        _REGISTER_CLOCK(NULL, "tcx", tcx)
+        _REGISTER_CLOCK(NULL, "tcz", tcz)
+        _REGISTER_CLOCK(NULL, "ref", ref)
+        _REGISTER_CLOCK(NULL, "dai0", dai0)
+        _REGISTER_CLOCK(NULL, "pic", pic)
+        _REGISTER_CLOCK(NULL, "tc", tc)
+        _REGISTER_CLOCK(NULL, "gpio", gpio)
+        _REGISTER_CLOCK(NULL, "usbd", usbd)
+        _REGISTER_CLOCK("tcc-uart.0", NULL, uart0)
+        _REGISTER_CLOCK("tcc-uart.2", NULL, uart2)
+        _REGISTER_CLOCK("tcc-i2c", NULL, i2c)
+        _REGISTER_CLOCK("tcc-uart.3", NULL, uart3)
+        _REGISTER_CLOCK(NULL, "ecc", ecc)
+        _REGISTER_CLOCK(NULL, "adc", adc)
+        _REGISTER_CLOCK("tcc-usbh.0", "usb", usbh0)
+        _REGISTER_CLOCK(NULL, "gdma0", gdma0)
+        _REGISTER_CLOCK(NULL, "lcd", lcd)
+        _REGISTER_CLOCK(NULL, "rtc", rtc)
+        _REGISTER_CLOCK(NULL, "nfc", nfc)
+        _REGISTER_CLOCK("tcc-mmc.0", NULL, sd0)
+        _REGISTER_CLOCK(NULL, "g2d", g2d)
+        _REGISTER_CLOCK(NULL, "gdma1", gdma1)
+        _REGISTER_CLOCK("tcc-uart.1", NULL, uart1)
+        _REGISTER_CLOCK("tcc-spi.0", NULL, spi0)
+        _REGISTER_CLOCK(NULL, "mscl", mscl)
+        _REGISTER_CLOCK("tcc-spi.1", NULL, spi1)
+        _REGISTER_CLOCK(NULL, "bdma", bdma)
+        _REGISTER_CLOCK(NULL, "adma0", adma0)
+        _REGISTER_CLOCK(NULL, "spdif", spdif)
+        _REGISTER_CLOCK(NULL, "scfg", scfg)
+        _REGISTER_CLOCK(NULL, "cid", cid)
+        _REGISTER_CLOCK("tcc-mmc.1", NULL, sd1)
+        _REGISTER_CLOCK("tcc-uart.4", NULL, uart4)
+        _REGISTER_CLOCK(NULL, "dai1", dai1)
+        _REGISTER_CLOCK(NULL, "adma1", adma1)
+        _REGISTER_CLOCK(NULL, "c3dec", c3dec)
+        _REGISTER_CLOCK("tcc-can.0", NULL, can0)
+        _REGISTER_CLOCK("tcc-can.1", NULL, can1)
+        _REGISTER_CLOCK(NULL, "gps", gps)
+        _REGISTER_CLOCK("tcc-gsb.0", NULL, gsb0)
+        _REGISTER_CLOCK("tcc-gsb.1", NULL, gsb1)
+        _REGISTER_CLOCK("tcc-gsb.2", NULL, gsb2)
+        _REGISTER_CLOCK("tcc-gsb.3", NULL, gsb3)
+        _REGISTER_CLOCK(NULL, "gdma2", gdma2)
+        _REGISTER_CLOCK(NULL, "gdma3", gdma3)
+        _REGISTER_CLOCK(NULL, "ddrc", ddrc)
+        _REGISTER_CLOCK("tcc-usbh.1", "usb", usbh1)
+};
+
+static struct clk *root_clk_by_index(enum root_clks src)
+{
+        switch (src) {
+        case CLK_SRC_PLL0: return &pll0;
+        case CLK_SRC_PLL1: return &pll1;
+        case CLK_SRC_PLL2: return &pll2;
+        case CLK_SRC_PLL0DIV: return &pll0div;
+        case CLK_SRC_PLL1DIV: return &pll1div;
+        case CLK_SRC_PLL2DIV: return &pll2div;
+        case CLK_SRC_XI: return &xi;
+        case CLK_SRC_XTI: return &xti;
+        case CLK_SRC_XIDIV: return &xidiv;
+        case CLK_SRC_XTIDIV: return &xtidiv;
+        default: return NULL;
+        }
+}
+
+static void find_aclk_parent(struct clk *clk)
+{
+        unsigned int src;
+        struct clk *clock;
+
+        if (!clk->aclkreg)
+                return;
+
+        src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
+        src &= CLK_SRC_MASK;
+
+        clock = root_clk_by_index(src);
+        if (!clock)
+                return;
+
+        clk->parent = clock;
+        clk->set_parent = aclk_set_parent;
+}
+
+void __init tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq)
+{
+        int i;
+
+        xi_rate = xi_freq;
+        xti_rate = xti_freq;
+
+        /* fixup parents and add the clock */
+        for (i = 0; i < ARRAY_SIZE(lookups); i++) {
+                find_aclk_parent(lookups[i].clk);
+                clkdev_add(&lookups[i]);
+        }
+        tcc8k_timer_init(&tcz, (void __iomem *)TIMER_BASE, INT_TC32);
+}
diff --git a/arch/arm/mach-tcc8k/common.h b/arch/arm/mach-tcc8k/common.h
new file mode 100644
index 000000000000..705690add395
--- /dev/null
+++ b/arch/arm/mach-tcc8k/common.h
@@ -0,0 +1,15 @@
+#ifndef MACH_TCC8K_COMMON_H
+#define MACH_TCC8K_COMMON_H
+
+#include <linux/platform_device.h>
+
+extern struct platform_device tcc_nand_device;
+
+struct clk;
+
+extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq);
+extern void tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq);
+extern void tcc8k_init_irq(void);
+extern void tcc8k_map_common_io(void);
+
+#endif
diff --git a/arch/arm/mach-tcc8k/devices.c b/arch/arm/mach-tcc8k/devices.c
new file mode 100644
index 000000000000..6722ad7c2836
--- /dev/null
+++ b/arch/arm/mach-tcc8k/devices.c
@@ -0,0 +1,239 @@
+/*
+ * linux/arch/arm/mach-tcc8k/devices.c
+ *
+ * Copyright (C) Telechips, Inc.
+ * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of GPL v2.
+ *
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/tcc8k-regs.h>
+#include <mach/irqs.h>
+
+#include "common.h"
+
+static u64 tcc8k_dmamask = DMA_BIT_MASK(32);
+
+#ifdef CONFIG_MTD_NAND_TCC
+/* NAND controller */
+static struct resource tcc_nand_resources[] = {
+        {
+                .start  = (resource_size_t)NFC_BASE,
+                .end    = (resource_size_t)NFC_BASE + 0x7f,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = INT_NFC,
+                .end    = INT_NFC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device tcc_nand_device = {
+        .name = "tcc_nand",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(tcc_nand_resources),
+        .resource = tcc_nand_resources,
+};
+#endif
+
+#ifdef CONFIG_MMC_TCC8K
+/* MMC controller */
+static struct resource tcc8k_mmc0_resource[] = {
+        {
+                .start = INT_SD0,
+                .end   = INT_SD0,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource tcc8k_mmc1_resource[] = {
+        {
+                .start = INT_SD1,
+                .end   = INT_SD1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device tcc8k_mmc0_device = {
+        .name           = "tcc-mmc",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(tcc8k_mmc0_resource),
+        .resource       = tcc8k_mmc0_resource,
+        .dev            = {
+                .dma_mask               = &tcc8k_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        }
+};
+
+struct platform_device tcc8k_mmc1_device = {
+        .name           = "tcc-mmc",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(tcc8k_mmc1_resource),
+        .resource       = tcc8k_mmc1_resource,
+        .dev            = {
+                .dma_mask               = &tcc8k_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        }
+};
+
+static inline void tcc8k_init_mmc(void)
+{
+        u32 reg = __raw_readl(GPIOPS_BASE + GPIOPS_FS1_OFFS);
+
+        reg |= GPIOPS_FS1_SDH0_BITS | GPIOPS_FS1_SDH1_BITS;
+        __raw_writel(reg, GPIOPS_BASE + GPIOPS_FS1_OFFS);
+
+        platform_device_register(&tcc8k_mmc0_device);
+        platform_device_register(&tcc8k_mmc1_device);
+}
+#else
+static inline void tcc8k_init_mmc(void) { }
+#endif
+
+#ifdef CONFIG_USB_OHCI_HCD
+static int tcc8k_ohci_init(struct device *dev)
+{
+        u32 reg;
+
+        /* Use GPIO PK19 as VBUS control output */
+        reg = __raw_readl(GPIOPK_BASE + GPIOPK_FS0_OFFS);
+        reg &= ~(1 << 19);
+        __raw_writel(reg, GPIOPK_BASE + GPIOPK_FS0_OFFS);
+        reg = __raw_readl(GPIOPK_BASE + GPIOPK_FS1_OFFS);
+        reg &= ~(1 << 19);
+        __raw_writel(reg, GPIOPK_BASE + GPIOPK_FS1_OFFS);
+
+        reg = __raw_readl(GPIOPK_BASE + GPIOPK_DOE_OFFS);
+        reg |= (1 << 19);
+        __raw_writel(reg, GPIOPK_BASE + GPIOPK_DOE_OFFS);
+        /* Turn on VBUS */
+        reg = __raw_readl(GPIOPK_BASE + GPIOPK_DAT_OFFS);
+        reg |= (1 << 19);
+        __raw_writel(reg, GPIOPK_BASE + GPIOPK_DAT_OFFS);
+
+        return 0;
+}
+
+static struct resource tcc8k_ohci0_resources[] = {
+        [0] = {
+                .start = (resource_size_t)USBH0_BASE,
+                .end   = (resource_size_t)USBH0_BASE + 0x5c,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = INT_USBH0,
+                .end   = INT_USBH0,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static struct resource tcc8k_ohci1_resources[] = {
+        [0] = {
+                .start = (resource_size_t)USBH1_BASE,
+                .end   = (resource_size_t)USBH1_BASE + 0x5c,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = INT_USBH1,
+                .end   = INT_USBH1,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static struct tccohci_platform_data tcc8k_ohci0_platform_data = {
+        .controller     = 0,
+        .port_mode      = PMM_PERPORT_MODE,
+        .init           = tcc8k_ohci_init,
+};
+
+static struct tccohci_platform_data tcc8k_ohci1_platform_data = {
+        .controller     = 1,
+        .port_mode      = PMM_PERPORT_MODE,
+        .init           = tcc8k_ohci_init,
+};
+
+static struct platform_device ohci0_device = {
+        .name = "tcc-ohci",
+        .id = 0,
+        .dev = {
+                .dma_mask = &tcc8k_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &tcc8k_ohci0_platform_data,
+        },
+        .num_resources  = ARRAY_SIZE(tcc8k_ohci0_resources),
+        .resource       = tcc8k_ohci0_resources,
+};
+
+static struct platform_device ohci1_device = {
+        .name = "tcc-ohci",
+        .id = 1,
+        .dev = {
+                .dma_mask = &tcc8k_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &tcc8k_ohci1_platform_data,
+        },
+        .num_resources  = ARRAY_SIZE(tcc8k_ohci1_resources),
+        .resource       = tcc8k_ohci1_resources,
+};
+
+static void __init tcc8k_init_usbhost(void)
+{
+        platform_device_register(&ohci0_device);
+        platform_device_register(&ohci1_device);
+}
+#else
+static void __init tcc8k_init_usbhost(void) { }
+#endif
+
+/* USB device controller*/
+#ifdef CONFIG_USB_GADGET_TCC8K
+static struct resource udc_resources[] = {
+        [0] = {
+                .start = INT_USBD,
+                .end   = INT_USBD,
+                .flags = IORESOURCE_IRQ,
+        },
+        [1] = {
+                .start = INT_UDMA,
+                .end   = INT_UDMA,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tcc8k_udc_device = {
+        .name = "tcc-udc",
+        .id = 0,
+        .resource = udc_resources,
+        .num_resources = ARRAY_SIZE(udc_resources),
+        .dev = {
+                 .dma_mask = &tcc8k_dmamask,
+                 .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+static void __init tcc8k_init_usb_gadget(void)
+{
+        platform_device_register(&tcc8k_udc_device);
+}
+#else
+static void __init tcc8k_init_usb_gadget(void) { }
+#endif  /* CONFIG_USB_GADGET_TCC83X */
+
+static int __init tcc8k_init_devices(void)
+{
+        tcc8k_init_mmc();
+        tcc8k_init_usbhost();
+        tcc8k_init_usb_gadget();
+        return 0;
+}
+
+arch_initcall(tcc8k_init_devices);
diff --git a/arch/arm/mach-tcc8k/io.c b/arch/arm/mach-tcc8k/io.c
new file mode 100644
index 000000000000..9b39d7fa658f
--- /dev/null
+++ b/arch/arm/mach-tcc8k/io.c
@@ -0,0 +1,62 @@
+/*
+ * linux/arch/arm/mach-tcc8k/io.c
+ *
+ * (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * derived from TCC83xx io.c
+ * Copyright (C) Telechips, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/tcc8k-regs.h>
+
+/*
+ * The machine specific code may provide the extra mapping besides the
+ * default mapping provided here.
+ */
+static struct map_desc tcc8k_io_desc[] __initdata = {
+        {
+                .virtual        = (unsigned long)CS1_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CS1_BASE),
+                .length         = CS1_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)AHB_PERI_BASE_VIRT,
+                .pfn            = __phys_to_pfn(AHB_PERI_BASE),
+                .length         = AHB_PERI_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)APB0_PERI_BASE_VIRT,
+                .pfn            = __phys_to_pfn(APB0_PERI_BASE),
+                .length         = APB0_PERI_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)APB1_PERI_BASE_VIRT,
+                .pfn            = __phys_to_pfn(APB1_PERI_BASE),
+                .length         = APB1_PERI_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)EXT_MEM_CTRL_BASE_VIRT,
+                .pfn            = __phys_to_pfn(EXT_MEM_CTRL_BASE),
+                .length         = EXT_MEM_CTRL_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+/*
+ * Maps common IO regions for tcc8k.
+ *
+ */
+void __init tcc8k_map_common_io(void)
+{
+        iotable_init(tcc8k_io_desc, ARRAY_SIZE(tcc8k_io_desc));
+}
diff --git a/arch/arm/mach-tcc8k/irq.c b/arch/arm/mach-tcc8k/irq.c
new file mode 100644
index 000000000000..34575c4963f0
--- /dev/null
+++ b/arch/arm/mach-tcc8k/irq.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) Telechips, Inc.
+ * Copyright (C) 2009-2010 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GNU GPL version 2.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+
+#include <mach/tcc8k-regs.h>
+#include <mach/irqs.h>
+
+#include "common.h"
+
+/* Disable IRQ */
+static void tcc8000_mask_ack_irq0(unsigned int irq)
+{
+        PIC0_IEN &= ~(1 << irq);
+        PIC0_CREQ |=  (1 << irq);
+}
+
+static void tcc8000_mask_ack_irq1(unsigned int irq)
+{
+        PIC1_IEN &= ~(1 << (irq - 32));
+        PIC1_CREQ |= (1 << (irq - 32));
+}
+
+static void tcc8000_mask_irq0(unsigned int irq)
+{
+        PIC0_IEN &= ~(1 << irq);
+}
+
+static void tcc8000_mask_irq1(unsigned int irq)
+{
+        PIC1_IEN &= ~(1 << (irq - 32));
+}
+
+static void tcc8000_ack_irq0(unsigned int irq)
+{
+        PIC0_CREQ |=  (1 << irq);
+}
+
+static void tcc8000_ack_irq1(unsigned int irq)
+{
+        PIC1_CREQ |= (1 << (irq - 32));
+}
+
+/* Enable IRQ */
+static void tcc8000_unmask_irq0(unsigned int irq)
+{
+        PIC0_IEN |= (1 << irq);
+        PIC0_INTOEN |= (1 << irq);
+}
+
+static void tcc8000_unmask_irq1(unsigned int irq)
+{
+        PIC1_IEN |= (1 << (irq - 32));
+        PIC1_INTOEN |= (1 << (irq - 32));
+}
+
+static struct irq_chip tcc8000_irq_chip0 = {
+        .name           = "tcc_irq0",
+        .mask           = tcc8000_mask_irq0,
+        .ack            = tcc8000_ack_irq0,
+        .mask_ack       = tcc8000_mask_ack_irq0,
+        .unmask         = tcc8000_unmask_irq0,
+};
+
+static struct irq_chip tcc8000_irq_chip1 = {
+        .name           = "tcc_irq1",
+        .mask           = tcc8000_mask_irq1,
+        .ack            = tcc8000_ack_irq1,
+        .mask_ack       = tcc8000_mask_ack_irq1,
+        .unmask         = tcc8000_unmask_irq1,
+};
+
+void __init tcc8k_init_irq(void)
+{
+        int irqno;
+
+        /* Mask and clear all interrupts */
+        PIC0_IEN = 0x00000000;
+        PIC0_CREQ = 0xffffffff;
+        PIC1_IEN = 0x00000000;
+        PIC1_CREQ = 0xffffffff;
+
+        PIC0_MEN0 = 0x00000003;
+        PIC1_MEN1 = 0x00000003;
+        PIC1_MEN = 0x00000003;
+
+        /* let all IRQs be level triggered */
+        PIC0_TMODE = 0xffffffff;
+        PIC1_TMODE = 0xffffffff;
+        /* all IRQs are IRQs (not FIQs) */
+        PIC0_IRQSEL = 0xffffffff;
+        PIC1_IRQSEL = 0xffffffff;
+
+        for (irqno = 0; irqno < NR_IRQS; irqno++) {
+                if (irqno < 32)
+                        set_irq_chip(irqno, &tcc8000_irq_chip0);
+                else
+                        set_irq_chip(irqno, &tcc8000_irq_chip1);
+                set_irq_handler(irqno, handle_level_irq);
+                set_irq_flags(irqno, IRQF_VALID);
+        }
+}
diff --git a/arch/arm/mach-tcc8k/time.c b/arch/arm/mach-tcc8k/time.c
new file mode 100644
index 000000000000..78d06008841d
--- /dev/null
+++ b/arch/arm/mach-tcc8k/time.c
@@ -0,0 +1,149 @@
+/*
+ * TCC8000 system timer setup
+ *
+ * (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPL version 2.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+
+#include <asm/mach/time.h>
+
+#include <mach/tcc8k-regs.h>
+#include <mach/irqs.h>
+
+#include "common.h"
+
+static void __iomem *timer_base;
+
+static cycle_t tcc_get_cycles(struct clocksource *cs)
+{
+        return __raw_readl(timer_base + TC32MCNT_OFFS);
+}
+
+static struct clocksource clocksource_tcc = {
+        .name           = "tcc_tc32",
+        .rating         = 200,
+        .read           = tcc_get_cycles,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .shift          = 28,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static int tcc_set_next_event(unsigned long evt,
+                              struct clock_event_device *unused)
+{
+        unsigned long reg = __raw_readl(timer_base + TC32MCNT_OFFS);
+
+        __raw_writel(reg + evt, timer_base + TC32CMP0_OFFS);
+        return 0;
+}
+
+static void tcc_set_mode(enum clock_event_mode mode,
+                                struct clock_event_device *evt)
+{
+        unsigned long tc32irq;
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_ONESHOT:
+                tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
+                tc32irq |= TC32IRQ_IRQEN0;
+                __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
+                break;
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+                tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
+                tc32irq &= ~TC32IRQ_IRQEN0;
+                __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
+                break;
+        case CLOCK_EVT_MODE_PERIODIC:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+
+static irqreturn_t tcc8k_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = dev_id;
+
+        /* Acknowledge TC32 interrupt by reading TC32IRQ */
+        __raw_readl(timer_base + TC32IRQ_OFFS);
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct clock_event_device clockevent_tcc = {
+        .name           = "tcc_timer1",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .set_mode       = tcc_set_mode,
+        .set_next_event = tcc_set_next_event,
+        .rating         = 200,
+};
+
+static struct irqaction tcc8k_timer_irq = {
+        .name           = "TC32_timer",
+        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .handler        = tcc8k_timer_interrupt,
+        .dev_id         = &clockevent_tcc,
+};
+
+static int __init tcc_clockevent_init(struct clk *clock)
+{
+        unsigned int c = clk_get_rate(clock);
+
+        clocksource_tcc.mult = clocksource_hz2mult(c,
+                                        clocksource_tcc.shift);
+        clocksource_register(&clocksource_tcc);
+
+        clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC,
+                                        clockevent_tcc.shift);
+        clockevent_tcc.max_delta_ns =
+                        clockevent_delta2ns(0xfffffffe, &clockevent_tcc);
+        clockevent_tcc.min_delta_ns =
+                        clockevent_delta2ns(0xff, &clockevent_tcc);
+
+        clockevent_tcc.cpumask = cpumask_of(0);
+
+        clockevents_register_device(&clockevent_tcc);
+
+        return 0;
+}
+
+void __init tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq)
+{
+        u32 reg;
+
+        timer_base = base;
+        tcc8k_timer_irq.irq = irq;
+
+        /* Enable clocks */
+        clk_enable(clock);
+
+        /* Initialize 32-bit timer */
+        reg = __raw_readl(timer_base + TC32EN_OFFS);
+        reg &= ~TC32EN_ENABLE; /* Disable timer */
+        __raw_writel(reg, timer_base + TC32EN_OFFS);
+        /* Free running timer, counting from 0 to 0xffffffff */
+        __raw_writel(0, timer_base + TC32EN_OFFS);
+        __raw_writel(0, timer_base + TC32LDV_OFFS);
+        reg = __raw_readl(timer_base + TC32IRQ_OFFS);
+        reg |= TC32IRQ_IRQEN0; /* irq at match with CMP0 */
+        __raw_writel(reg, timer_base + TC32IRQ_OFFS);
+
+        __raw_writel(TC32EN_ENABLE, timer_base + TC32EN_OFFS);
+
+        tcc_clockevent_init(clock);
+        setup_irq(irq, &tcc8k_timer_irq);
+}
diff --git a/arch/arm/mach-u300/include/mach/gpio.h b/arch/arm/mach-u300/include/mach/gpio.h
index 7b1fc984abb6..d5a71abcbaea 100644
--- a/arch/arm/mach-u300/include/mach/gpio.h
+++ b/arch/arm/mach-u300/include/mach/gpio.h
@@ -273,6 +273,9 @@ extern void gpio_pullup(unsigned gpio, int value);
 extern int gpio_get_value(unsigned gpio);
 extern void gpio_set_value(unsigned gpio, int value);
 
+#define gpio_get_value_cansleep gpio_get_value
+#define gpio_set_value_cansleep gpio_set_value
+
 /* wrappers to sleep-enable the previous two functions */
 static inline unsigned gpio_to_irq(unsigned gpio)
 {
diff --git a/arch/arm/mach-versatile/include/mach/vmalloc.h b/arch/arm/mach-versatile/include/mach/vmalloc.h
index 427e3612db5d..ebd8a2543d3b 100644
--- a/arch/arm/mach-versatile/include/mach/vmalloc.h
+++ b/arch/arm/mach-versatile/include/mach/vmalloc.h
@@ -18,4 +18,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define VMALLOC_END             (PAGE_OFFSET + 0x18000000)
+#define VMALLOC_END             0xd8000000
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 577df6cccb08..efb127022d42 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -227,7 +227,13 @@ static void ct_ca9x4_init(void)
         int i;
 
 #ifdef CONFIG_CACHE_L2X0
-        l2x0_init(MMIO_P2V(CT_CA9X4_L2CC), 0x00000000, 0xfe0fffff);
+        void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
+
+        /* set RAM latencies to 1 cycle for this core tile. */
+        writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
+        writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
+
+        l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
 #endif
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index d073b64ae87e..724ba3bce72c 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -885,8 +885,23 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 
         if (ai_usermode & UM_SIGNAL)
                 force_sig(SIGBUS, current);
-        else
-                set_cr(cr_no_alignment);
+        else {
+                /*
+                 * We're about to disable the alignment trap and return to
+                 * user space.  But if an interrupt occurs before actually
+                 * reaching user space, then the IRQ vector entry code will
+                 * notice that we were still in kernel space and therefore
+                 * the alignment trap won't be re-enabled in that case as it
+                 * is presumed to be always on from kernel space.
+                 * Let's prevent that race by disabling interrupts here (they
+                 * are disabled on the way back to user space anyway in
+                 * entry-common.S) and disable the alignment trap only if
+                 * there is no work pending for this thread.
+                 */
+                raw_local_irq_disable();
+                if (!(current_thread_info()->flags & _TIF_WORK_MASK))
+                        set_cr(cr_no_alignment);
+        }
 
         return 0;
 }
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index 4f5b39687df5..b0a98305055c 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -144,3 +144,25 @@ int valid_mmap_phys_addr_range(unsigned long pfn, size_t size)
 {
         return !(pfn + (size >> PAGE_SHIFT) > 0x00100000);
 }
+
+#ifdef CONFIG_STRICT_DEVMEM
+
+#include <linux/ioport.h>
+
+/*
+ * devmem_is_allowed() checks to see if /dev/mem access to a certain
+ * address is valid. The argument is a physical page number.
+ * We mimic x86 here by disallowing access to system RAM as well as
+ * device-exclusive MMIO regions. This effectively disable read()/write()
+ * on /dev/mem.
+ */
+int devmem_is_allowed(unsigned long pfn)
+{
+        if (iomem_is_exclusive(pfn << PAGE_SHIFT))
+                return 0;
+        if (!page_is_ram(pfn))
+                return 1;
+        return 0;
+}
+
+#endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6e1c4f6a2b3f..6a3a2d0cd6db 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -15,6 +15,7 @@
 #include <linux/nodemask.h>
 #include <linux/memblock.h>
 #include <linux/sort.h>
+#include <linux/fs.h>
 
 #include <asm/cputype.h>
 #include <asm/sections.h>
@@ -246,6 +247,9 @@ static struct mem_type mem_types[] = {
                 .domain    = DOMAIN_USER,
         },
         [MT_MEMORY] = {
+                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+                                L_PTE_USER | L_PTE_EXEC,
+                .prot_l1   = PMD_TYPE_TABLE,
                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
                 .domain    = DOMAIN_KERNEL,
         },
@@ -254,6 +258,9 @@ static struct mem_type mem_types[] = {
                 .domain    = DOMAIN_KERNEL,
         },
         [MT_MEMORY_NONCACHED] = {
+                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+                                L_PTE_USER | L_PTE_EXEC | L_PTE_MT_BUFFERABLE,
+                .prot_l1   = PMD_TYPE_TABLE,
                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
                 .domain    = DOMAIN_KERNEL,
         },
@@ -411,9 +418,12 @@ static void __init build_mem_type_table(void)
          * Enable CPU-specific coherency if supported.
          * (Only available on XSC3 at the moment.)
          */
-        if (arch_is_coherent() && cpu_is_xsc3())
+        if (arch_is_coherent() && cpu_is_xsc3()) {
                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-
+                mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
+                mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+                mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
+        }
         /*
          * ARMv6 and above have extended page tables.
          */
@@ -438,7 +448,9 @@ static void __init build_mem_type_table(void)
                 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
                 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+                mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+                mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 #endif
         }
 
@@ -475,6 +487,8 @@ static void __init build_mem_type_table(void)
         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
+        mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
+        mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
         mem_types[MT_ROM].prot_sect |= cp->pmd;
 
         switch (cp->pmd) {
@@ -498,6 +512,19 @@ static void __init build_mem_type_table(void)
         }
 }
 
+#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                              unsigned long size, pgprot_t vma_prot)
+{
+        if (!pfn_valid(pfn))
+                return pgprot_noncached(vma_prot);
+        else if (file->f_flags & O_SYNC)
+                return pgprot_writecombine(vma_prot);
+        return vma_prot;
+}
+EXPORT_SYMBOL(phys_mem_access_prot);
+#endif
+
 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 
 static void __init *early_alloc(unsigned long sz)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d99ee9..7563ff0141bd 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -186,13 +186,14 @@ cpu_v7_name:
  *      It is assumed that:
  *      - cache type register is implemented
  */
-__v7_setup:
+__v7_ca9mp_setup:
 #ifdef CONFIG_SMP
         mrc     p15, 0, r0, c1, c0, 1
         tst     r0, #(1 << 6)                   @ SMP/nAMP mode enabled?
         orreq   r0, r0, #(1 << 6) | (1 << 0)    @ Enable SMP/nAMP mode and
         mcreq   p15, 0, r0, c1, c0, 1           @ TLB ops broadcasting
 #endif
+__v7_setup:
         adr     r12, __v7_setup_stack           @ the local stack
         stmia   r12, {r0-r5, r7, r9, r11, lr}
         bl      v7_flush_dcache_all
@@ -201,11 +202,16 @@ __v7_setup:
         mrc     p15, 0, r0, c0, c0, 0           @ read main ID register
         and     r10, r0, #0xff000000            @ ARM?
         teq     r10, #0x41000000
-        bne     2f
+        bne     3f
         and     r5, r0, #0x00f00000             @ variant
         and     r6, r0, #0x0000000f             @ revision
-        orr     r0, r6, r5, lsr #20-4           @ combine variant and revision
+        orr     r6, r6, r5, lsr #20-4           @ combine variant and revision
+        ubfx    r0, r0, #4, #12                 @ primary part number
 
+        /* Cortex-A8 Errata */
+        ldr     r10, =0x00000c08                @ Cortex-A8 primary part number
+        teq     r0, r10
+        bne     2f
 #ifdef CONFIG_ARM_ERRATA_430973
         teq     r5, #0x00100000                 @ only present in r1p*
         mrceq   p15, 0, r10, c1, c0, 1          @ read aux control register
@@ -213,21 +219,42 @@ __v7_setup:
         mcreq   p15, 0, r10, c1, c0, 1          @ write aux control register
 #endif
 #ifdef CONFIG_ARM_ERRATA_458693
-        teq     r0, #0x20                       @ only present in r2p0
+        teq     r6, #0x20                       @ only present in r2p0
         mrceq   p15, 0, r10, c1, c0, 1          @ read aux control register
         orreq   r10, r10, #(1 << 5)             @ set L1NEON to 1
         orreq   r10, r10, #(1 << 9)             @ set PLDNOP to 1
         mcreq   p15, 0, r10, c1, c0, 1          @ write aux control register
 #endif
 #ifdef CONFIG_ARM_ERRATA_460075
-        teq     r0, #0x20                       @ only present in r2p0
+        teq     r6, #0x20                       @ only present in r2p0
         mrceq   p15, 1, r10, c9, c0, 2          @ read L2 cache aux ctrl register
         tsteq   r10, #1 << 22
         orreq   r10, r10, #(1 << 22)            @ set the Write Allocate disable bit
         mcreq   p15, 1, r10, c9, c0, 2          @ write the L2 cache aux ctrl register
 #endif
+        b       3f
+
+        /* Cortex-A9 Errata */
+2:      ldr     r10, =0x00000c09                @ Cortex-A9 primary part number
+        teq     r0, r10
+        bne     3f
+#ifdef CONFIG_ARM_ERRATA_742230
+        cmp     r6, #0x22                       @ only present up to r2p2
+        mrcle   p15, 0, r10, c15, c0, 1         @ read diagnostic register
+        orrle   r10, r10, #1 << 4               @ set bit #4
+        mcrle   p15, 0, r10, c15, c0, 1         @ write diagnostic register
+#endif
+#ifdef CONFIG_ARM_ERRATA_742231
+        teq     r6, #0x20                       @ present in r2p0
+        teqne   r6, #0x21                       @ present in r2p1
+        teqne   r6, #0x22                       @ present in r2p2
+        mrceq   p15, 0, r10, c15, c0, 1         @ read diagnostic register
+        orreq   r10, r10, #1 << 12              @ set bit #12
+        orreq   r10, r10, #1 << 22              @ set bit #22
+        mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
+#endif
 
-2:      mov     r10, #0
+3:      mov     r10, #0
 #ifdef HARVARD_CACHE
         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
 #endif
@@ -323,6 +350,29 @@ cpu_elf_name:
 
         .section ".proc.info.init", #alloc, #execinstr
 
+        .type   __v7_ca9mp_proc_info, #object
+__v7_ca9mp_proc_info:
+        .long   0x410fc090              @ Required ID value
+        .long   0xff0ffff0              @ Mask for ID
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ | \
+                PMD_FLAGS
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_XN | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        b       __v7_ca9mp_setup
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   cpu_v7_name
+        .long   v7_processor_functions
+        .long   v7wbi_tlb_fns
+        .long   v6_user_fns
+        .long   v7_cache_fns
+        .size   __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
+
         /*
          * Match any ARMv7 processor core.
          */
diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c
index 0691176899ff..72e09eb642dd 100644
--- a/arch/arm/oprofile/common.c
+++ b/arch/arm/oprofile/common.c
@@ -102,6 +102,7 @@ static int op_create_counter(int cpu, int event)
         if (IS_ERR(pevent)) {
                 ret = PTR_ERR(pevent);
         } else if (pevent->state != PERF_EVENT_STATE_ACTIVE) {
+                perf_event_release_kernel(pevent);
                 pr_warning("oprofile: failed to enable event %d "
                                 "on CPU %d\n", event, cpu);
                 ret = -EBUSY;
@@ -365,6 +366,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
         ret = init_driverfs();
         if (ret) {
                 kfree(counter_config);
+                counter_config = NULL;
                 return ret;
         }
 
@@ -402,7 +404,6 @@ void oprofile_arch_exit(void)
         struct perf_event *event;
 
         if (*perf_events) {
-                exit_driverfs();
                 for_each_possible_cpu(cpu) {
                         for (id = 0; id < perf_num_counters; ++id) {
                                 event = perf_events[cpu][id];
@@ -413,8 +414,10 @@ void oprofile_arch_exit(void)
                 }
         }
 
-        if (counter_config)
+        if (counter_config) {
                 kfree(counter_config);
+                exit_driverfs();
+        }
 }
 #else
 int __init oprofile_arch_init(struct oprofile_operations *ops)
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 6785db4179b8..95f8d614d4fc 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -92,6 +92,18 @@ config MXC_DEBUG_BOARD
           data/address de-multiplexing and decode, signal level shift,
           interrupt control and various board functions.
 
+config HAVE_EPIT
+        bool
+
+config MXC_USE_EPIT
+        bool "Use EPIT instead of GPT"
+        depends on HAVE_EPIT
+        help
+          Use EPIT as the system timer on systems that have it. Normally you
+          don't have a reason to do so as the EPIT has the same features and
+          uses the same clocks as the GPT. Anyway, on some systems the GPT
+          may be in use for other purposes.
+
 config MXC_ULPI
         bool
 
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 78d405ed8616..bb3443f9751a 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
 obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
+obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index f9e7cdbd0005..62920490c0d6 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -186,7 +186,13 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
 static int mxc_audmux_v2_init(void)
 {
         int ret;
-
+#if defined(CONFIG_ARCH_MX5)
+        if (cpu_is_mx51()) {
+                audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR);
+                ret = 0;
+                return ret;
+        }
+#endif
 #if defined(CONFIG_ARCH_MX3)
         if (cpu_is_mx31())
                 audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index 9ab784b776f9..404799487f17 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -1,3 +1,10 @@
+config IMX_HAVE_PLATFORM_ESDHC
+        bool
+
+config IMX_HAVE_PLATFORM_FEC
+        bool
+        default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51
+
 config IMX_HAVE_PLATFORM_FLEXCAN
         select HAVE_CAN_FLEXCAN
         bool
@@ -5,6 +12,9 @@ config IMX_HAVE_PLATFORM_FLEXCAN
 config IMX_HAVE_PLATFORM_IMX_I2C
         bool
 
+config IMX_HAVE_PLATFORM_IMX_SSI
+        bool
+
 config IMX_HAVE_PLATFORM_IMX_UART
         bool
 
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index 347da5161f7e..0a3c1f089413 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -1,8 +1,9 @@
-ifdef CONFIG_CAN_FLEXCAN
-# the ifdef can be removed once the flexcan driver has been merged
-obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) +=  platform-flexcan.o
-endif
+obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
+obj-y += platform-imx-dma.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-esdhc.c b/arch/arm/plat-mxc/devices/platform-esdhc.c
new file mode 100644
index 000000000000..68db2a22d2cd
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-esdhc.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <mach/devices-common.h>
+#include <mach/esdhc.h>
+
+struct platform_device *__init imx_add_esdhc(int id,
+                resource_size_t iobase, resource_size_t iosize,
+                resource_size_t irq,
+                const struct esdhc_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = iobase,
+                        .end = iobase + iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irq,
+                        .end = irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("sdhci-esdhc-imx", id, res,
+                        ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c
new file mode 100644
index 000000000000..11d087f4e219
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-fec.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_fec_data_entry_single(soc)                                  \
+        {                                                               \
+                .iobase = soc ## _FEC_BASE_ADDR,                        \
+                .irq = soc ## _INT_FEC,                                 \
+        }
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_fec_data imx25_fec_data __initconst =
+        imx_fec_data_entry_single(MX25);
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_fec_data imx27_fec_data __initconst =
+        imx_fec_data_entry_single(MX27);
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_ARCH_MX35
+const struct imx_fec_data imx35_fec_data __initconst =
+        imx_fec_data_entry_single(MX35);
+#endif
+
+#ifdef CONFIG_ARCH_MX51
+const struct imx_fec_data imx51_fec_data __initconst =
+        imx_fec_data_entry_single(MX51);
+#endif
+
+struct platform_device *__init imx_add_fec(
+                const struct imx_fec_data *data,
+                const struct fec_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_4K,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("fec", 0 /* -1? */,
+                        res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c
new file mode 100644
index 000000000000..02d989018059
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/compiler.h>
+#include <linux/err.h>
+#include <linux/init.h>
+
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+#ifdef SDMA_IS_MERGED
+#include <mach/sdma.h>
+#else
+struct sdma_platform_data {
+        int sdma_version;
+        char *cpu_name;
+        int to_version;
+};
+#endif
+
+struct imx_imx_sdma_data {
+        resource_size_t iobase;
+        resource_size_t irq;
+        struct sdma_platform_data pdata;
+};
+
+#define imx_imx_sdma_data_entry_single(soc, _sdma_version, _cpu_name, _to_version)\
+        {                                                               \
+                .iobase = soc ## _SDMA ## _BASE_ADDR,                   \
+                .irq = soc ## _INT_SDMA,                                \
+                .pdata = {                                              \
+                        .sdma_version = _sdma_version,                  \
+                        .cpu_name = _cpu_name,                          \
+                        .to_version = _to_version,                      \
+                },                                                      \
+        }
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst =
+        imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0);
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_ARCH_MX31
+struct imx_imx_sdma_data imx31_imx_sdma_data __initdata =
+        imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0);
+#endif /* ifdef CONFIG_ARCH_MX31 */
+
+#ifdef CONFIG_ARCH_MX35
+struct imx_imx_sdma_data imx35_imx_sdma_data __initdata =
+        imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0);
+#endif /* ifdef CONFIG_ARCH_MX35 */
+
+#ifdef CONFIG_ARCH_MX51
+const struct imx_imx_sdma_data imx51_imx_sdma_data __initconst =
+        imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0);
+#endif /* ifdef CONFIG_ARCH_MX51 */
+
+static struct platform_device __init __maybe_unused *imx_add_imx_sdma(
+                const struct imx_imx_sdma_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_4K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("imx-sdma", -1,
+                        res, ARRAY_SIZE(res),
+                        &data->pdata, sizeof(data->pdata));
+}
+
+static struct platform_device __init __maybe_unused *imx_add_imx_dma(void)
+{
+        return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0);
+}
+
+static int __init imxXX_add_imx_dma(void)
+{
+        struct platform_device *ret;
+
+#if defined(CONFIG_SOC_IMX21) || defined(CONFIG_SOC_IMX27)
+        if (cpu_is_mx21() || cpu_is_mx27())
+                ret = imx_add_imx_dma();
+        else
+#endif
+
+#if defined(CONFIG_ARCH_MX25)
+        if (cpu_is_mx25())
+                ret = imx_add_imx_sdma(&imx25_imx_sdma_data);
+        else
+#endif
+
+#if defined(CONFIG_ARCH_MX31)
+        if (cpu_is_mx31()) {
+                imx31_imx_sdma_data.pdata.to_version = mx31_revision() >> 4;
+                ret = imx_add_imx_sdma(&imx31_imx_sdma_data);
+        } else
+#endif
+
+#if defined(CONFIG_ARCH_MX35)
+        if (cpu_is_mx35()) {
+                imx35_imx_sdma_data.pdata.to_version = mx35_revision() >> 4;
+                ret = imx_add_imx_sdma(&imx35_imx_sdma_data);
+        } else
+#endif
+
+#if defined(CONFIG_ARCH_MX51)
+        if (cpu_is_mx51())
+                ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
+        else
+#endif
+                ret = ERR_PTR(-ENODEV);
+
+        if (IS_ERR(ret))
+                return PTR_ERR(ret);
+
+        return 0;
+}
+arch_initcall(imxXX_add_imx_dma);
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index d0af9f7d8aed..ca988d40a3d7 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -6,24 +6,94 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
+#include <mach/hardware.h>
 #include <mach/devices-common.h>
 
-struct platform_device *__init imx_add_imx_i2c(int id,
-                resource_size_t iobase, resource_size_t iosize, int irq,
+#define imx_imx_i2c_data_entry_single(soc, _id, _hwid, _size)           \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _I2C ## _hwid ## _BASE_ADDR,           \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_I2C ## _hwid,                        \
+        }
+
+#define imx_imx_i2c_data_entry(soc, _id, _hwid, _size)                  \
+        [_id] = imx_imx_i2c_data_entry_single(soc, _id, _hwid, _size)
+
+#ifdef CONFIG_SOC_IMX1
+const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst =
+        imx_imx_i2c_data_entry_single(MX1, 0, , SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX1 */
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
+        imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX21 */
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
+#define imx25_imx_i2c_data_entry(_id, _hwid)                            \
+        imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K)
+        imx25_imx_i2c_data_entry(0, 1),
+        imx25_imx_i2c_data_entry(1, 2),
+        imx25_imx_i2c_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
+#define imx27_imx_i2c_data_entry(_id, _hwid)                            \
+        imx_imx_i2c_data_entry(MX27, _id, _hwid, SZ_4K)
+        imx27_imx_i2c_data_entry(0, 1),
+        imx27_imx_i2c_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_ARCH_MX31
+const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = {
+#define imx31_imx_i2c_data_entry(_id, _hwid)                            \
+        imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K)
+        imx31_imx_i2c_data_entry(0, 1),
+        imx31_imx_i2c_data_entry(1, 2),
+        imx31_imx_i2c_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX31 */
+
+#ifdef CONFIG_ARCH_MX35
+const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
+#define imx35_imx_i2c_data_entry(_id, _hwid)                            \
+        imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K)
+        imx35_imx_i2c_data_entry(0, 1),
+        imx35_imx_i2c_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX35 */
+
+#ifdef CONFIG_ARCH_MX51
+const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
+#define imx51_imx_i2c_data_entry(_id, _hwid)                            \
+        imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K)
+        imx51_imx_i2c_data_entry(0, 1),
+        imx51_imx_i2c_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX51 */
+
+struct platform_device *__init imx_add_imx_i2c(
+                const struct imx_imx_i2c_data *data,
                 const struct imxi2c_platform_data *pdata)
 {
         struct resource res[] = {
                 {
-                        .start = iobase,
-                        .end = iobase + iosize - 1,
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
                         .flags = IORESOURCE_MEM,
                 }, {
-                        .start = irq,
-                        .end = irq,
+                        .start = data->irq,
+                        .end = data->irq,
                         .flags = IORESOURCE_IRQ,
                 },
         };
 
-        return imx_add_platform_device("imx-i2c", id, res, ARRAY_SIZE(res),
+        return imx_add_platform_device("imx-i2c", data->id,
+                        res, ARRAY_SIZE(res),
                         pdata, sizeof(*pdata));
 }
diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
new file mode 100644
index 000000000000..38a7a0b8f2f1
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_imx_ssi_data_entry(soc, _id, _hwid, _size)                  \
+        [_id] = {                                                       \
+                .id = _id,                                              \
+                .iobase = soc ## _SSI ## _hwid ## _BASE_ADDR,           \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_SSI ## _hwid,                        \
+                .dmatx0 = soc ## _DMA_REQ_SSI ## _hwid ## _TX0,         \
+                .dmarx0 = soc ## _DMA_REQ_SSI ## _hwid ## _RX0,         \
+                .dmatx1 = soc ## _DMA_REQ_SSI ## _hwid ## _TX1,         \
+                .dmarx1 = soc ## _DMA_REQ_SSI ## _hwid ## _RX1,         \
+        }
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = {
+#define imx21_imx_ssi_data_entry(_id, _hwid)                            \
+        imx_imx_ssi_data_entry(MX21, _id, _hwid, SZ_4K)
+        imx21_imx_ssi_data_entry(0, 1),
+        imx21_imx_ssi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX21 */
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = {
+#define imx25_imx_ssi_data_entry(_id, _hwid)                            \
+        imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K)
+        imx25_imx_ssi_data_entry(0, 1),
+        imx25_imx_ssi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
+#define imx27_imx_ssi_data_entry(_id, _hwid)                            \
+        imx_imx_ssi_data_entry(MX27, _id, _hwid, SZ_4K)
+        imx27_imx_ssi_data_entry(0, 1),
+        imx27_imx_ssi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_ARCH_MX31
+const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = {
+#define imx31_imx_ssi_data_entry(_id, _hwid)                            \
+        imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K)
+        imx31_imx_ssi_data_entry(0, 1),
+        imx31_imx_ssi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX31 */
+
+#ifdef CONFIG_ARCH_MX35
+const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = {
+#define imx35_imx_ssi_data_entry(_id, _hwid)                            \
+        imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K)
+        imx35_imx_ssi_data_entry(0, 1),
+        imx35_imx_ssi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX35 */
+
+#ifdef CONFIG_ARCH_MX51
+const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = {
+#define imx51_imx_ssi_data_entry(_id, _hwid)                            \
+        imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K)
+        imx51_imx_ssi_data_entry(0, 1),
+        imx51_imx_ssi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX51 */
+
+struct platform_device *__init imx_add_imx_ssi(
+                const struct imx_imx_ssi_data *data,
+                const struct imx_ssi_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+#define DMARES(_name) {                                                 \
+        .name = #_name,                                                 \
+        .start = data->dma ## _name,                                    \
+        .end = data->dma ## _name,                                      \
+        .flags = IORESOURCE_DMA,                                        \
+}
+                DMARES(tx0),
+                DMARES(rx0),
+                DMARES(tx1),
+                DMARES(rx1),
+        };
+
+        return imx_add_platform_device("imx-ssi", data->id,
+                        res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
index fa3dff1433e8..2039640adf27 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-uart.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -6,55 +6,148 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
+#include <mach/hardware.h>
 #include <mach/devices-common.h>
 
-struct platform_device *__init imx_add_imx_uart_3irq(int id,
-                resource_size_t iobase, resource_size_t iosize,
-                resource_size_t irqrx, resource_size_t irqtx,
-                resource_size_t irqrts,
+#define imx_imx_uart_3irq_data_entry(soc, _id, _hwid, _size)            \
+        [_id] = {                                                       \
+                .id = _id,                                              \
+                .iobase = soc ## _UART ## _hwid ## _BASE_ADDR,          \
+                .iosize = _size,                                        \
+                .irqrx = soc ## _INT_UART ## _hwid ## RX,               \
+                .irqtx = soc ## _INT_UART ## _hwid ## TX,               \
+                .irqrts = soc ## _INT_UART ## _hwid ## RTS,             \
+        }
+
+#define imx_imx_uart_1irq_data_entry(soc, _id, _hwid, _size)            \
+        [_id] = {                                                       \
+                .id = _id,                                              \
+                .iobase = soc ## _UART ## _hwid ## _BASE_ADDR,          \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_UART ## _hwid,                       \
+        }
+
+#ifdef CONFIG_SOC_IMX1
+const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst = {
+#define imx1_imx_uart_data_entry(_id, _hwid)                            \
+        imx_imx_uart_3irq_data_entry(MX1, _id, _hwid, 0xd0)
+        imx1_imx_uart_data_entry(0, 1),
+        imx1_imx_uart_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX1 */
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
+#define imx21_imx_uart_data_entry(_id, _hwid)                           \
+        imx_imx_uart_1irq_data_entry(MX21, _id, _hwid, SZ_4K)
+        imx21_imx_uart_data_entry(0, 1),
+        imx21_imx_uart_data_entry(1, 2),
+        imx21_imx_uart_data_entry(2, 3),
+        imx21_imx_uart_data_entry(3, 4),
+};
+#endif
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
+#define imx25_imx_uart_data_entry(_id, _hwid)                           \
+        imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K)
+        imx25_imx_uart_data_entry(0, 1),
+        imx25_imx_uart_data_entry(1, 2),
+        imx25_imx_uart_data_entry(2, 3),
+        imx25_imx_uart_data_entry(3, 4),
+        imx25_imx_uart_data_entry(4, 5),
+};
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
+#define imx27_imx_uart_data_entry(_id, _hwid)                           \
+        imx_imx_uart_1irq_data_entry(MX27, _id, _hwid, SZ_4K)
+        imx27_imx_uart_data_entry(0, 1),
+        imx27_imx_uart_data_entry(1, 2),
+        imx27_imx_uart_data_entry(2, 3),
+        imx27_imx_uart_data_entry(3, 4),
+        imx27_imx_uart_data_entry(4, 5),
+        imx27_imx_uart_data_entry(5, 6),
+};
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_ARCH_MX31
+const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
+#define imx31_imx_uart_data_entry(_id, _hwid)                           \
+        imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K)
+        imx31_imx_uart_data_entry(0, 1),
+        imx31_imx_uart_data_entry(1, 2),
+        imx31_imx_uart_data_entry(2, 3),
+        imx31_imx_uart_data_entry(3, 4),
+        imx31_imx_uart_data_entry(4, 5),
+};
+#endif /* ifdef CONFIG_ARCH_MX31 */
+
+#ifdef CONFIG_ARCH_MX35
+const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
+#define imx35_imx_uart_data_entry(_id, _hwid)                           \
+        imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K)
+        imx35_imx_uart_data_entry(0, 1),
+        imx35_imx_uart_data_entry(1, 2),
+        imx35_imx_uart_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX35 */
+
+#ifdef CONFIG_ARCH_MX51
+const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
+#define imx51_imx_uart_data_entry(_id, _hwid)                           \
+        imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K)
+        imx51_imx_uart_data_entry(0, 1),
+        imx51_imx_uart_data_entry(1, 2),
+        imx51_imx_uart_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX51 */
+
+struct platform_device *__init imx_add_imx_uart_3irq(
+                const struct imx_imx_uart_3irq_data *data,
                 const struct imxuart_platform_data *pdata)
 {
         struct resource res[] = {
                 {
-                        .start = iobase,
-                        .end = iobase + iosize - 1,
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
                         .flags = IORESOURCE_MEM,
                 }, {
-                        .start = irqrx,
-                        .end = irqrx,
+                        .start = data->irqrx,
+                        .end = data->irqrx,
                         .flags = IORESOURCE_IRQ,
                 }, {
-                        .start = irqtx,
-                        .end = irqtx,
+                        .start = data->irqtx,
+                        .end = data->irqtx,
                         .flags = IORESOURCE_IRQ,
                 }, {
-                        .start = irqrts,
-                        .end = irqrx,
+                        .start = data->irqrts,
+                        .end = data->irqrx,
                         .flags = IORESOURCE_IRQ,
                 },
         };
 
-        return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata));
+        return imx_add_platform_device("imx-uart", data->id, res,
+                        ARRAY_SIZE(res), pdata, sizeof(*pdata));
 }
 
-struct platform_device *__init imx_add_imx_uart_1irq(int id,
-                resource_size_t iobase, resource_size_t iosize,
-                resource_size_t irq,
+struct platform_device *__init imx_add_imx_uart_1irq(
+                const struct imx_imx_uart_1irq_data *data,
                 const struct imxuart_platform_data *pdata)
 {
         struct resource res[] = {
                 {
-                        .start = iobase,
-                        .end = iobase + iosize - 1,
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
                         .flags = IORESOURCE_MEM,
                 }, {
-                        .start = irq,
-                        .end = irq,
+                        .start = data->irq,
+                        .end = data->irq,
                         .flags = IORESOURCE_IRQ,
                 },
         };
 
-        return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res),
+        return imx_add_platform_device("imx-uart", data->id, res, ARRAY_SIZE(res),
                         pdata, sizeof(*pdata));
 }
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
index 1c286418d123..3fdcc32e3d67 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
@@ -7,38 +7,77 @@
  * Free Software Foundation.
  */
 #include <asm/sizes.h>
+#include <mach/hardware.h>
 #include <mach/devices-common.h>
 
-static struct platform_device *__init imx_add_mxc_nand(resource_size_t iobase,
-                int irq, const struct mxc_nand_platform_data *pdata,
-                resource_size_t iosize)
+#define imx_mxc_nand_data_entry_single(soc, _size)                      \
+        {                                                               \
+                .iobase = soc ## _NFC_BASE_ADDR,                        \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_NFC                                  \
+        }
+
+#define imx_mxc_nandv3_data_entry_single(soc, _size)                    \
+        {                                                               \
+                .id = -1,                                               \
+                .iobase = soc ## _NFC_BASE_ADDR,                        \
+                .iosize = _size,                                        \
+                .axibase = soc ## _NFC_AXI_BASE_ADDR,                   \
+                .irq = soc ## _INT_NFC                                  \
+        }
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
+        imx_mxc_nand_data_entry_single(MX21, SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX21 */
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst =
+        imx_mxc_nand_data_entry_single(MX25, SZ_8K);
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
+        imx_mxc_nand_data_entry_single(MX27, SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_ARCH_MX31
+const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst =
+        imx_mxc_nand_data_entry_single(MX31, SZ_4K);
+#endif
+
+#ifdef CONFIG_ARCH_MX35
+const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst =
+        imx_mxc_nand_data_entry_single(MX35, SZ_8K);
+#endif
+
+#ifdef CONFIG_ARCH_MX51
+const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst =
+        imx_mxc_nandv3_data_entry_single(MX51, SZ_16K);
+#endif
+
+struct platform_device *__init imx_add_mxc_nand(
+                const struct imx_mxc_nand_data *data,
+                const struct mxc_nand_platform_data *pdata)
 {
-        static int id = 0;
-        
+        /* AXI has to come first, that's how the mxc_nand driver expect it */
         struct resource res[] = {
                 {
-                        .start = iobase,
-                        .end = iobase + iosize - 1,
+                        .start = data->axibase,
+                        .end = data->axibase + SZ_16K - 1,
                         .flags = IORESOURCE_MEM,
                 }, {
-                        .start = irq,
-                        .end = irq,
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
                         .flags = IORESOURCE_IRQ,
                 },
         };
-
-        return imx_add_platform_device("mxc_nand", id++, res, ARRAY_SIZE(res),
+        return imx_add_platform_device("mxc_nand", data->id,
+                        res + !data->axibase,
+                        ARRAY_SIZE(res) - !data->axibase,
                         pdata, sizeof(*pdata));
 }
-
-struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
-                int irq, const struct mxc_nand_platform_data *pdata)
-{
-        return imx_add_mxc_nand(iobase, irq, pdata, SZ_4K);
-}
-
-struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
-                int irq, const struct mxc_nand_platform_data *pdata)
-{
-        return imx_add_mxc_nand(iobase, irq, pdata, SZ_8K);
-}
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 2831a6d3eb4b..e48340ec331e 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -6,25 +6,96 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
-#include <asm/sizes.h>
+#include <mach/hardware.h>
 #include <mach/devices-common.h>
 
-struct platform_device *__init imx_add_spi_imx(int id,
-                resource_size_t iobase, resource_size_t iosize, int irq,
+#define imx_spi_imx_data_entry_single(soc, type, _devid, _id, hwid, _size) \
+        {                                                               \
+                .devid = _devid,                                        \
+                .id = _id,                                              \
+                .iobase = soc ## _ ## type ## hwid ## _BASE_ADDR,       \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_ ## type ## hwid,                    \
+        }
+
+#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size)        \
+        [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size)
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
+#define imx21_cspi_data_entry(_id, _hwid)                            \
+        imx_spi_imx_data_entry(MX21, CSPI, "imx21-cspi", _id, _hwid, SZ_4K)
+        imx21_cspi_data_entry(0, 1),
+        imx21_cspi_data_entry(1, 2),
+#endif
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
+#define imx25_cspi_data_entry(_id, _hwid)                               \
+        imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K)
+        imx25_cspi_data_entry(0, 1),
+        imx25_cspi_data_entry(1, 2),
+        imx25_cspi_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
+#define imx27_cspi_data_entry(_id, _hwid)                               \
+        imx_spi_imx_data_entry(MX27, CSPI, "imx27-cspi", _id, _hwid, SZ_4K)
+        imx27_cspi_data_entry(0, 1),
+        imx27_cspi_data_entry(1, 2),
+        imx27_cspi_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_ARCH_MX31
+const struct imx_spi_imx_data imx31_cspi_data[] __initconst = {
+#define imx31_cspi_data_entry(_id, _hwid)                               \
+        imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K)
+        imx31_cspi_data_entry(0, 1),
+        imx31_cspi_data_entry(1, 2),
+        imx31_cspi_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX31 */
+
+#ifdef CONFIG_ARCH_MX35
+const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
+#define imx35_cspi_data_entry(_id, _hwid)                           \
+        imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K)
+        imx35_cspi_data_entry(0, 1),
+        imx35_cspi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX35 */
+
+#ifdef CONFIG_ARCH_MX51
+const struct imx_spi_imx_data imx51_cspi_data __initconst =
+        imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K);
+
+const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
+#define imx51_ecspi_data_entry(_id, _hwid)                              \
+        imx_spi_imx_data_entry(MX51, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K)
+        imx51_ecspi_data_entry(0, 1),
+        imx51_ecspi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX51 */
+
+struct platform_device *__init imx_add_spi_imx(
+                const struct imx_spi_imx_data *data,
                 const struct spi_imx_master *pdata)
 {
         struct resource res[] = {
                 {
-                        .start = iobase,
-                        .end = iobase + iosize - 1,
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
                         .flags = IORESOURCE_MEM,
                 }, {
-                        .start = irq,
-                        .end = irq,
+                        .start = data->irq,
+                        .end = data->irq,
                         .flags = IORESOURCE_IRQ,
                 },
         };
 
-        return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata));
+        return imx_add_platform_device(data->devid, data->id,
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
 }
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 35a064ff02ba..9915607683de 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -249,8 +249,8 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
 #ifdef CONFIG_ARCH_MX51
         if (cpu_is_mx51()) {
                 void __iomem *usb_base;
-                u32 usbotg_base;
-                u32 usbother_base;
+                void __iomem *usbotg_base;
+                void __iomem *usbother_base;
                 int ret = 0;
 
                 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c
new file mode 100644
index 000000000000..ee9582f4972e
--- /dev/null
+++ b/arch/arm/plat-mxc/epit.c
@@ -0,0 +1,242 @@
+/*
+ *  linux/arch/arm/plat-mxc/epit.c
+ *
+ *  Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#define EPITCR          0x00
+#define EPITSR          0x04
+#define EPITLR          0x08
+#define EPITCMPR        0x0c
+#define EPITCNR         0x10
+
+#define EPITCR_EN                       (1 << 0)
+#define EPITCR_ENMOD                    (1 << 1)
+#define EPITCR_OCIEN                    (1 << 2)
+#define EPITCR_RLD                      (1 << 3)
+#define EPITCR_PRESC(x)                 (((x) & 0xfff) << 4)
+#define EPITCR_SWR                      (1 << 16)
+#define EPITCR_IOVW                     (1 << 17)
+#define EPITCR_DBGEN                    (1 << 18)
+#define EPITCR_WAITEN                   (1 << 19)
+#define EPITCR_RES                      (1 << 20)
+#define EPITCR_STOPEN                   (1 << 21)
+#define EPITCR_OM_DISCON                (0 << 22)
+#define EPITCR_OM_TOGGLE                (1 << 22)
+#define EPITCR_OM_CLEAR                 (2 << 22)
+#define EPITCR_OM_SET                   (3 << 22)
+#define EPITCR_CLKSRC_OFF               (0 << 24)
+#define EPITCR_CLKSRC_PERIPHERAL        (1 << 24)
+#define EPITCR_CLKSRC_REF_HIGH          (1 << 24)
+#define EPITCR_CLKSRC_REF_LOW           (3 << 24)
+
+#define EPITSR_OCIF                     (1 << 0)
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+
+#include <mach/hardware.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+
+static struct clock_event_device clockevent_epit;
+static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
+
+static void __iomem *timer_base;
+
+static inline void epit_irq_disable(void)
+{
+        u32 val;
+
+        val = __raw_readl(timer_base + EPITCR);
+        val &= ~EPITCR_OCIEN;
+        __raw_writel(val, timer_base + EPITCR);
+}
+
+static inline void epit_irq_enable(void)
+{
+        u32 val;
+
+        val = __raw_readl(timer_base + EPITCR);
+        val |= EPITCR_OCIEN;
+        __raw_writel(val, timer_base + EPITCR);
+}
+
+static void epit_irq_acknowledge(void)
+{
+        __raw_writel(EPITSR_OCIF, timer_base + EPITSR);
+}
+
+static cycle_t epit_read(struct clocksource *cs)
+{
+        return 0 - __raw_readl(timer_base + EPITCNR);
+}
+
+static struct clocksource clocksource_epit = {
+        .name           = "epit",
+        .rating         = 200,
+        .read           = epit_read,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .shift          = 20,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static int __init epit_clocksource_init(struct clk *timer_clk)
+{
+        unsigned int c = clk_get_rate(timer_clk);
+
+        clocksource_epit.mult = clocksource_hz2mult(c,
+                                        clocksource_epit.shift);
+        clocksource_register(&clocksource_epit);
+
+        return 0;
+}
+
+/* clock event */
+
+static int epit_set_next_event(unsigned long evt,
+                              struct clock_event_device *unused)
+{
+        unsigned long tcmp;
+
+        tcmp = __raw_readl(timer_base + EPITCNR);
+
+        __raw_writel(tcmp - evt, timer_base + EPITCMPR);
+
+        return 0;
+}
+
+static void epit_set_mode(enum clock_event_mode mode,
+                                struct clock_event_device *evt)
+{
+        unsigned long flags;
+
+        /*
+         * The timer interrupt generation is disabled at least
+         * for enough time to call epit_set_next_event()
+         */
+        local_irq_save(flags);
+
+        /* Disable interrupt in GPT module */
+        epit_irq_disable();
+
+        if (mode != clockevent_mode) {
+                /* Set event time into far-far future */
+
+                /* Clear pending interrupt */
+                epit_irq_acknowledge();
+        }
+
+        /* Remember timer mode */
+        clockevent_mode = mode;
+        local_irq_restore(flags);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                printk(KERN_ERR "epit_set_mode: Periodic mode is not "
+                                "supported for i.MX EPIT\n");
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+        /*
+         * Do not put overhead of interrupt enable/disable into
+         * epit_set_next_event(), the core has about 4 minutes
+         * to call epit_set_next_event() or shutdown clock after
+         * mode switching
+         */
+                local_irq_save(flags);
+                epit_irq_enable();
+                local_irq_restore(flags);
+                break;
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_RESUME:
+                /* Left event sources disabled, no more interrupts appear */
+                break;
+        }
+}
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = &clockevent_epit;
+
+        epit_irq_acknowledge();
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction epit_timer_irq = {
+        .name           = "i.MX EPIT Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = epit_timer_interrupt,
+};
+
+static struct clock_event_device clockevent_epit = {
+        .name           = "epit",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .set_mode       = epit_set_mode,
+        .set_next_event = epit_set_next_event,
+        .rating         = 200,
+};
+
+static int __init epit_clockevent_init(struct clk *timer_clk)
+{
+        unsigned int c = clk_get_rate(timer_clk);
+
+        clockevent_epit.mult = div_sc(c, NSEC_PER_SEC,
+                                        clockevent_epit.shift);
+        clockevent_epit.max_delta_ns =
+                        clockevent_delta2ns(0xfffffffe, &clockevent_epit);
+        clockevent_epit.min_delta_ns =
+                        clockevent_delta2ns(0x800, &clockevent_epit);
+
+        clockevent_epit.cpumask = cpumask_of(0);
+
+        clockevents_register_device(&clockevent_epit);
+
+        return 0;
+}
+
+void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
+{
+        clk_enable(timer_clk);
+
+        timer_base = base;
+
+        /*
+         * Initialise to a known state (all timers off, and timing reset)
+         */
+        __raw_writel(0x0, timer_base + EPITCR);
+
+        __raw_writel(0xffffffff, timer_base + EPITLR);
+        __raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
+                        timer_base + EPITCR);
+
+        /* init and register the timer to the framework */
+        epit_clocksource_init(timer_clk);
+        epit_clockevent_init(timer_clk);
+
+        /* Make irqs happen */
+        setup_irq(irq, &epit_timer_irq);
+}
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 57ec4a896a5d..9d38da077edb 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -235,7 +235,7 @@ static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
         unsigned long flags;
 
         spin_lock_irqsave(&port->lock, flags);
-        l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
+        l = (__raw_readl(reg) & (~(1 << offset))) | (!!value << offset);
         __raw_writel(l, reg);
         spin_unlock_irqrestore(&port->lock, flags);
 }
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 2941472582d2..7a1e1f89ff09 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -32,6 +32,7 @@ extern void mx31_init_irq(void);
 extern void mx35_init_irq(void);
 extern void mx51_init_irq(void);
 extern void mxc91231_init_irq(void);
+extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
 extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
 extern int mx1_clocks_init(unsigned long fref);
 extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index c5f68c587309..049897880403 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -14,47 +14,101 @@ struct platform_device *imx_add_platform_device(const char *name, int id,
                 const struct resource *res, unsigned int num_resources,
                 const void *data, size_t size_data);
 
-#if defined (CONFIG_CAN_FLEXCAN) || defined (CONFIG_CAN_FLEXCAN_MODULE)
+#include <linux/fec.h>
+struct imx_fec_data {
+        resource_size_t iobase;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_fec(
+                const struct imx_fec_data *data,
+                const struct fec_platform_data *pdata);
+
 #include <linux/can/platform/flexcan.h>
 struct platform_device *__init imx_add_flexcan(int id,
                 resource_size_t iobase, resource_size_t iosize,
                 resource_size_t irq,
                 const struct flexcan_platform_data *pdata);
-#else
-/* the ifdef can be removed once the flexcan driver has been merged */
-struct flexcan_platform_data;
-static inline struct platform_device *__init imx_add_flexcan(int id,
-                resource_size_t iobase, resource_size_t iosize,
-                resource_size_t irq,
-                const struct flexcan_platform_data *pdata)
-{
-        return NULL;
-}
-#endif
 
 #include <mach/i2c.h>
-struct platform_device *__init imx_add_imx_i2c(int id,
-                resource_size_t iobase, resource_size_t iosize, int irq,
+struct imx_imx_i2c_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_imx_i2c(
+                const struct imx_imx_i2c_data *data,
                 const struct imxi2c_platform_data *pdata);
 
+#include <mach/ssi.h>
+struct imx_imx_ssi_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+        resource_size_t dmatx0;
+        resource_size_t dmarx0;
+        resource_size_t dmatx1;
+        resource_size_t dmarx1;
+};
+struct platform_device *__init imx_add_imx_ssi(
+                const struct imx_imx_ssi_data *data,
+                const struct imx_ssi_platform_data *pdata);
+
 #include <mach/imx-uart.h>
-struct platform_device *__init imx_add_imx_uart_3irq(int id,
-                resource_size_t iobase, resource_size_t iosize,
-                resource_size_t irqrx, resource_size_t irqtx,
-                resource_size_t irqrts,
+struct imx_imx_uart_3irq_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irqrx;
+        resource_size_t irqtx;
+        resource_size_t irqrts;
+};
+struct platform_device *__init imx_add_imx_uart_3irq(
+                const struct imx_imx_uart_3irq_data *data,
                 const struct imxuart_platform_data *pdata);
-struct platform_device *__init imx_add_imx_uart_1irq(int id,
-                resource_size_t iobase, resource_size_t iosize,
-                resource_size_t irq,
+
+struct imx_imx_uart_1irq_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_imx_uart_1irq(
+                const struct imx_imx_uart_1irq_data *data,
                 const struct imxuart_platform_data *pdata);
 
 #include <mach/mxc_nand.h>
-struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
-                int irq, const struct mxc_nand_platform_data *pdata);
-struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
-                int irq, const struct mxc_nand_platform_data *pdata);
+struct imx_mxc_nand_data {
+        /*
+         * id is traditionally 0, but -1 is more appropriate.  We use -1 for new
+         * machines but don't change existing devices as the nand device usually
+         * appears in the kernel command line to pass its partitioning.
+         */
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t axibase;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_mxc_nand(
+                const struct imx_mxc_nand_data *data,
+                const struct mxc_nand_platform_data *pdata);
 
 #include <mach/spi.h>
-struct platform_device *__init imx_add_spi_imx(int id,
-                resource_size_t iobase, resource_size_t iosize, int irq,
+struct imx_spi_imx_data {
+        const char *devid;
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        int irq;
+};
+struct platform_device *__init imx_add_spi_imx(
+                const struct imx_spi_imx_data *data,
                 const struct spi_imx_master *pdata);
+
+#include <mach/esdhc.h>
+struct platform_device *__init imx_add_esdhc(int id,
+                resource_size_t iobase, resource_size_t iosize,
+                resource_size_t irq,
+                const struct esdhc_platform_data *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/esdhc.h b/arch/arm/plat-mxc/include/mach/esdhc.h
new file mode 100644
index 000000000000..a48a9aaa56b1
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/esdhc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2010 Wolfram Sang <w.sang@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ */
+
+#ifndef __ASM_ARCH_IMX_ESDHC_H
+#define __ASM_ARCH_IMX_ESDHC_H
+
+struct esdhc_platform_data {
+        unsigned int wp_gpio;   /* write protect pin */
+};
+#endif /* __ASM_ARCH_IMX_ESDHC_H */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index 21bfa46785bb..5160f1073ec9 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -45,6 +45,15 @@ typedef enum iomux_config {
                                 PAD_CTL_PKE | PAD_CTL_HYS)
 #define MX51_GPIO_PAD_CTRL              (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
                                 PAD_CTL_SRE_FAST)
+#define MX51_ECSPI_PAD_CTRL     (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
+                                PAD_CTL_SRE_FAST)
+
+#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+                                        PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE)
+#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
+#define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE)
+#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 
 /*
  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
@@ -106,14 +115,20 @@ typedef enum iomux_config {
 #define MX51_PAD_EIM_EB0__EIM_EB0               IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_EB1__EIM_EB1               IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_EB2__GPIO_2_22             IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__FEC_MDIO              IOMUX_PAD(0x468, 0x0d4, 3, 0x0,   0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
 #define MX51_PAD_EIM_EB3__GPIO_2_23             IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__FEC_RDAT1             IOMUX_PAD(0x46c, 0x0d8, 3, 0x0,   0, MX51_PAD_CTRL_2)
 #define MX51_PAD_EIM_OE__GPIO_2_24              IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_CS0__GPIO_2_25             IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_CS1__GPIO_2_26             IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_CS2__GPIO_2_27             IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__FEC_RDAT2             IOMUX_PAD(0x47c, 0x0e8, 3, 0x0,   0, MX51_PAD_CTRL_2)
 #define MX51_PAD_EIM_CS3__GPIO_2_28             IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__FEC_RDAT3             IOMUX_PAD(0x480, 0x0ec, 3, 0x0,   0, MX51_PAD_CTRL_2)
 #define MX51_PAD_EIM_CS4__GPIO_2_29             IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__FEC_RX_ER             IOMUX_PAD(0x484, 0x0f0, 3, 0x0,   0, MX51_PAD_CTRL_2)
 #define MX51_PAD_EIM_CS5__GPIO_2_30             IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__FEC_CRS               IOMUX_PAD(0x488, 0x0f4, 3, 0x0,   0, MX51_PAD_CTRL_2)
 #define MX51_PAD_EIM_DTACK__GPIO_2_31           IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_LBA__GPIO_3_1              IOMUX_PAD(0x494, 0x0FC, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_CRE__GPIO_3_2              IOMUX_PAD(0x4A0, 0x100, 1, 0x0,   0, NO_PAD_CTRL)
@@ -126,18 +141,32 @@ typedef enum iomux_config {
 #define MX51_PAD_NANDF_RB0__GPIO_3_8            IOMUX_PAD(0x4F8, 0x11C, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB1__GPIO_3_9            IOMUX_PAD(0x4FC, 0x120, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__GPIO_3_10           IOMUX_PAD(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         IOMUX_PAD(0x500, 0x124, 2, 0x0,   0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__FEC_COL             IOMUX_PAD(0x500, 0x124, 1, 0x0,   0, MX51_PAD_CTRL_2)
 #define MX51_PAD_NANDF_RB3__GPIO_3_11           IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__ECSPI2_MISO         IOMUX_PAD(0x504, 0x128, 2, 0x0,   0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__FEC_RXCLK           IOMUX_PAD(0x504, 0x128, 1, 0x0,   0, MX51_PAD_CTRL_2)
+#define MX51_PAD_NANDF_RB6__FEC_RDAT0           IOMUX_PAD(0x5DC, 0x134, 1, 0x0,   0, MX51_PAD_CTRL_4)
+#define MX51_PAD_NANDF_RB7__FEC_TDAT0           IOMUX_PAD(0x5E0, 0x138, 1, 0x0,   0, MX51_PAD_CTRL_5)
 #define MX51_PAD_GPIO_NAND__GPIO_3_12           IOMUX_PAD(0x514, 0x12C, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_CS0__GPIO_3_16           IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_CS1__GPIO_3_17           IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_CS2__GPIO_3_18           IOMUX_PAD(0x520, 0x138, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__FEC_TX_ER           IOMUX_PAD(0x520, 0x138, 2, 0x0,   0, MX51_PAD_CTRL_5)
 #define MX51_PAD_NANDF_CS3__GPIO_3_19           IOMUX_PAD(0x524, 0x13C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__FEC_MDC             IOMUX_PAD(0x524, 0x13C, 2, 0x0,   0, MX51_PAD_CTRL_5)
 #define MX51_PAD_NANDF_CS4__GPIO_3_20           IOMUX_PAD(0x528, 0x140, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__FEC_TDAT1           IOMUX_PAD(0x528, 0x140, 2, 0x0,   0, MX51_PAD_CTRL_5)
 #define MX51_PAD_NANDF_CS5__GPIO_3_21           IOMUX_PAD(0x52C, 0x144, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__FEC_TDAT2           IOMUX_PAD(0x52C, 0x144, 2, 0x0,   0, MX51_PAD_CTRL_5)
 #define MX51_PAD_NANDF_CS6__GPIO_3_22           IOMUX_PAD(0x530, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__FEC_TDAT3           IOMUX_PAD(0x530, 0x148, 2, 0x0,   0, MX51_PAD_CTRL_5)
 #define MX51_PAD_NANDF_CS7__GPIO_3_23           IOMUX_PAD(0x534, 0x14C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__FEC_TX_EN           IOMUX_PAD(0x534, 0x14C, 1, 0x0,   0, MX51_PAD_CTRL_5)
 #define MX51_PAD_NANDF_RDY_INT__GPIO_3_24       IOMUX_PAD(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      IOMUX_PAD(0x538, 0x150, 1, 0x0,   0, MX51_PAD_CTRL_4)
 #define MX51_PAD_NANDF_D15__GPIO_3_25           IOMUX_PAD(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__ECSPI2_MOSI         IOMUX_PAD(0x53C, 0x154, 2, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_NANDF_D14__GPIO_3_26           IOMUX_PAD(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_D13__GPIO_3_27           IOMUX_PAD(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_D12__GPIO_3_28           IOMUX_PAD(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
@@ -185,15 +214,25 @@ typedef enum iomux_config {
 #define MX51_PAD_I2C1_CLK__HSI2C_CLK            IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_I2C1_DAT__GPIO_4_17            IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_I2C1_DAT__HSI2C_DAT            IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD       IOMUX_PAD(0x5F0, 0x200, IOMUX_CONFIG_SION, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_AUD3_BB_TXD__GPIO_4_18         IOMUX_PAD(0x5F0, 0x200, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD       IOMUX_PAD(0x5F4, 0x204, IOMUX_CONFIG_SION, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_AUD3_BB_RXD__GPIO_4_19         IOMUX_PAD(0x5F4, 0x204, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK         IOMUX_PAD(0x5F8, 0x208, IOMUX_CONFIG_SION, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_AUD3_BB_CK__GPIO_4_20          IOMUX_PAD(0x5F8, 0x208, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS         IOMUX_PAD(0x5FC, 0x20C, IOMUX_CONFIG_SION, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_AUD3_BB_FS__GPIO_4_21          IOMUX_PAD(0x5FC, 0x20C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        IOMUX_PAD(0x600, 0x210, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_CSPI1_MOSI__GPIO_4_22          IOMUX_PAD(0x600, 0x210, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO        IOMUX_PAD(0x604, 0x214, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_CSPI1_MISO__GPIO_4_23          IOMUX_PAD(0x604, 0x214, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0          IOMUX_PAD(0x608, 0x218, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_CSPI1_SS0__GPIO_4_24           IOMUX_PAD(0x608, 0x218, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1          IOMUX_PAD(0x60C, 0x21C, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_CSPI1_SS1__GPIO_4_25           IOMUX_PAD(0x60C, 0x21C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY          IOMUX_PAD(0x610, 0x220, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_CSPI1_RDY__GPIO_4_26           IOMUX_PAD(0x610, 0x220, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        IOMUX_PAD(0x614, 0x224, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_CSPI1_SCLK__GPIO_4_27          IOMUX_PAD(0x614, 0x224, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_UART1_RXD__UART1_RXD           IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
 #define MX51_PAD_UART1_TXD__UART1_TXD           IOMUX_PAD(0x61C, 0x22C, 0, 0x0,   0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
@@ -236,14 +275,14 @@ typedef enum iomux_config {
 #define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
 #define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
 #define MX51_PAD_DI1_PIN11__GPIO_3_0            IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN12__GPIO_3_1            IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN13__GPIO_3_2            IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D0_CS__GPIO_3_3            IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__GPIO_3_4            IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5       IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6       IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7       IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8        IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__GPIO_3_1            IOMUX_PAD(0x6AC, 0x2AC, 4, 0x978, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__GPIO_3_2            IOMUX_PAD(0x6B0, 0x2B0, 4, 0x97c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__GPIO_3_3            IOMUX_PAD(0x6B4, 0x2B4, 4, 0x980, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__GPIO_3_4            IOMUX_PAD(0x6B8, 0x2B8, 4, 0x984, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5       IOMUX_PAD(0x6BC, 0x2BC, 4, 0x988, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6       IOMUX_PAD(0x6C0, 0x2C0, 4, 0x98c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7       IOMUX_PAD(0x6C4, 0x2C4, 4, 0x990, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8        IOMUX_PAD(0x6C8, 0x2C8, 4, 0x994, 1, NO_PAD_CTRL)
 #define MX51_PAD_DISP1_DAT0__DISP1_DAT0         IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_DISP1_DAT1__DISP1_DAT1         IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_DISP1_DAT2__DISP1_DAT2         IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0,   0, NO_PAD_CTRL)
@@ -295,11 +334,17 @@ typedef enum iomux_config {
 #define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38C, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79C, 0x394, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__AUD5_RXFS             IOMUX_PAD(0x79C, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
 #define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7A0, 0x398, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__AUD5_RXC              IOMUX_PAD(0x7A0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
 #define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7A4, 0x39C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__AUD5_TXD            IOMUX_PAD(0x7A4, 0x39C, 1, 0x8d8, 2, NO_PAD_CTRL)
 #define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__AUD5_RXD            IOMUX_PAD(0x7A8, 0x3A0, 1, 0x8d4, 2, NO_PAD_CTRL)
 #define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__AUD5_TXC            IOMUX_PAD(0x7AC, 0x3A4, 1, 0x8e4, 2, NO_PAD_CTRL)
 #define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__AUD5_TXFS           IOMUX_PAD(0x7B0, 0x3A8, 1, 0x8e8, 2, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_0__GPIO_1_0             IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_1__GPIO_1_1             IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0,   0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index ed98b9c9f389..8bc59720b6e4 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -120,7 +120,7 @@
 #define MX21_INT_GPT1           26
 #define MX21_INT_WDOG           27
 #define MX21_INT_PCMCIA         28
-#define MX21_INT_NANDFC         29
+#define MX21_INT_NFC            29
 #define MX21_INT_BMI            30
 #define MX21_INT_CSI            31
 #define MX21_INT_DMACH0         32
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 4a6f800990f8..153dd1b2a473 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -50,6 +50,8 @@
 #define MX25_SSI1_BASE_ADDR             0x50034000
 #define MX25_NFC_BASE_ADDR              0xbb000000
 #define MX25_DRYICE_BASE_ADDR           0x53ffc000
+#define MX25_ESDHC1_BASE_ADDR           0x53fb4000
+#define MX25_ESDHC2_BASE_ADDR           0x53fb8000
 #define MX25_LCDC_BASE_ADDR             0x53fbc000
 #define MX25_KPP_BASE_ADDR              0x43fa8000
 #define MX25_OTG_BASE_ADDR              0x53ff4000
@@ -59,6 +61,8 @@
 #define MX25_INT_I2C1           3
 #define MX25_INT_I2C2           4
 #define MX25_INT_UART4          5
+#define MX25_INT_MMC_SDHC2      8
+#define MX25_INT_MMC_SDHC1      9
 #define MX25_INT_I2C3           10
 #define MX25_INT_SSI2           11
 #define MX25_INT_SSI1           12
@@ -69,7 +73,7 @@
 #define MX25_INT_KPP            24
 #define MX25_INT_DRYICE         25
 #define MX25_INT_UART2          32
-#define MX25_INT_NANDFC         33
+#define MX25_INT_NFC            33
 #define MX25_INT_LCDC           39
 #define MX25_INT_UART5          40
 #define MX25_INT_CAN1           43
@@ -77,4 +81,13 @@
 #define MX25_INT_UART1          45
 #define MX25_INT_FEC            57
 
+#define MX25_DMA_REQ_SSI2_RX1   22
+#define MX25_DMA_REQ_SSI2_TX1   23
+#define MX25_DMA_REQ_SSI2_RX0   24
+#define MX25_DMA_REQ_SSI2_TX0   25
+#define MX25_DMA_REQ_SSI1_RX1   26
+#define MX25_DMA_REQ_SSI1_TX1   27
+#define MX25_DMA_REQ_SSI1_RX0   28
+#define MX25_DMA_REQ_SSI1_TX0   29
+
 #endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index a8ab2e02a8ca..2237ba2e5351 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -167,7 +167,7 @@ static inline void mx27_setup_weimcs(size_t cs,
 #define MX27_INT_GPT1           26
 #define MX27_INT_WDOG           27
 #define MX27_INT_PCMCIA         28
-#define MX27_INT_NANDFC         29
+#define MX27_INT_NFC            29
 #define MX27_INT_ATA            30
 #define MX27_INT_CSI            31
 #define MX27_INT_DMACH0         32
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index afee3ab9d62e..03e2afabc9fc 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -168,7 +168,7 @@ static inline void mx31_setup_weimcs(size_t cs,
 #define MX31_INT_POWER_FAIL     30
 #define MX31_INT_CCM_DVFS       31
 #define MX31_INT_UART2          32
-#define MX31_INT_NANDFC         33
+#define MX31_INT_NFC            33
 #define MX31_INT_SDMA           34
 #define MX31_INT_USB1           35
 #define MX31_INT_USB2           36
@@ -197,6 +197,15 @@ static inline void mx31_setup_weimcs(size_t cs,
 #define MX31_INT_EXT_WDOG       62
 #define MX31_INT_EXT_TV         63
 
+#define MX31_DMA_REQ_SSI2_RX1   22
+#define MX31_DMA_REQ_SSI2_TX1   23
+#define MX31_DMA_REQ_SSI2_RX0   24
+#define MX31_DMA_REQ_SSI2_TX0   25
+#define MX31_DMA_REQ_SSI1_RX1   26
+#define MX31_DMA_REQ_SSI1_TX1   27
+#define MX31_DMA_REQ_SSI1_RX0   28
+#define MX31_DMA_REQ_SSI1_TX0   29
+
 #define MX31_PROD_SIGNATURE             0x1     /* For MX31 */
 
 /* silicon revisions specific to i.MX31 */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index af3038c12e39..cb071b7b17e5 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -1,5 +1,6 @@
 #ifndef __MACH_MX35_H__
 #define __MACH_MX35_H__
+
 /*
  * IRAM
  */
@@ -52,6 +53,9 @@
 #define MX35_GPIO3_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xa4000)
 #define MX35_SCC_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xac000)
 #define MX35_RNGA_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xb0000)
+#define MX35_ESDHC1_BASE_ADDR                   (MX35_AIPS2_BASE_ADDR + 0xb4000)
+#define MX35_ESDHC2_BASE_ADDR                   (MX35_AIPS2_BASE_ADDR + 0xb8000)
+#define MX35_ESDHC3_BASE_ADDR                   (MX35_AIPS2_BASE_ADDR + 0xbc000)
 #define MX35_IPU_CTRL_BASE_ADDR                 (MX35_AIPS2_BASE_ADDR + 0xc0000)
 #define MX35_AUDMUX_BASE_ADDR                   (MX35_AIPS2_BASE_ADDR + 0xc4000)
 #define MX35_GPIO1_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xcc000)
@@ -63,6 +67,8 @@
 #define MX35_CAN1_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xe4000)
 #define MX35_CAN2_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xe8000)
 #define MX35_RTIC_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xec000)
+#define MX35_IIM_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xf0000)
+
 #define MX35_OTG_BASE_ADDR              0x53ff4000
 
 #define MX35_ROMP_BASE_ADDR             0x60000000
@@ -145,7 +151,7 @@
 #define MX35_INT_GPT            29
 #define MX35_INT_POWER_FAIL     30
 #define MX35_INT_UART2          32
-#define MX35_INT_NANDFC         33
+#define MX35_INT_NFC            33
 #define MX35_INT_SDMA           34
 #define MX35_INT_USBHS          35
 #define MX35_INT_USBOTG         37
@@ -173,22 +179,18 @@
 #define MX35_INT_EXT_WDOG       62
 #define MX35_INT_EXT_TV         63
 
+#define MX35_DMA_REQ_SSI2_RX1   22
+#define MX35_DMA_REQ_SSI2_TX1   23
+#define MX35_DMA_REQ_SSI2_RX0   24
+#define MX35_DMA_REQ_SSI2_TX0   25
+#define MX35_DMA_REQ_SSI1_RX1   26
+#define MX35_DMA_REQ_SSI1_TX1   27
+#define MX35_DMA_REQ_SSI1_RX0   28
+#define MX35_DMA_REQ_SSI1_TX0   29
+
 #define MX35_PROD_SIGNATURE             0x1     /* For MX31 */
 
-/* silicon revisions specific to i.MX31 */
-#define MX35_CHIP_REV_1_0               0x10
-#define MX35_CHIP_REV_1_1               0x11
-#define MX35_CHIP_REV_1_2               0x12
-#define MX35_CHIP_REV_1_3               0x13
-#define MX35_CHIP_REV_2_0               0x20
-#define MX35_CHIP_REV_2_1               0x21
-#define MX35_CHIP_REV_2_2               0x22
-#define MX35_CHIP_REV_2_3               0x23
-#define MX35_CHIP_REV_3_0               0x30
-#define MX35_CHIP_REV_3_1               0x31
-#define MX35_CHIP_REV_3_2               0x32
-
-#define MX35_SYSTEM_REV_MIN             MX35_CHIP_REV_1_0
+#define MX35_SYSTEM_REV_MIN             MX3x_CHIP_REV_1_0
 #define MX35_SYSTEM_REV_NUM             3
 
 #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 7a356de385f5..d1bd26d7b8a6 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -240,7 +240,7 @@
 
 #define MX3x_PROD_SIGNATURE             0x1     /* For MX31 */
 
-/* silicon revisions specific to i.MX31 */
+/* silicon revisions specific to i.MX31 and i.MX35 */
 #define MX3x_CHIP_REV_1_0               0x10
 #define MX3x_CHIP_REV_1_1               0x11
 #define MX3x_CHIP_REV_1_2               0x12
@@ -267,6 +267,14 @@ static inline int mx31_revision(void)
 {
         return mx31_cpu_rev;
 }
+
+extern unsigned int mx35_cpu_rev;
+extern void mx35_read_cpu_rev(void);
+
+static inline int mx35_revision(void)
+{
+        return mx35_cpu_rev;
+}
 #endif
 
 #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
@@ -389,19 +397,6 @@ static inline int mx31_revision(void)
 #define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
 #define MXC_INT_EXT_TV MX3x_INT_EXT_TV
 #define PROD_SIGNATURE MX3x_PROD_SIGNATURE
-#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0
-#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1
-#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2
-#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3
-#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0
-#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1
-#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2
-#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3
-#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0
-#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1
-#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
-#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
-#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
 #endif
 
 #endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 5aad344d5651..c54b5c32d82e 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_ARCH_MXC_MX51_H__
-#define __ASM_ARCH_MXC_MX51_H__
+#ifndef __MACH_MX51_H__
+#define __MACH_MX51_H__
 
 /*
  * MX51 memory map:
@@ -7,24 +7,23 @@
  *
  * Virt         Phys            Size    What
  * ---------------------------------------------------------------------------
- * FA3E0000     1FFE0000        128K    IRAM (SCCv2 RAM)
+ * fa3e0000     1ffe0000        128K    IRAM (SCCv2 RAM)
  *              30000000        256M    GPU
  *              40000000        512M    IPU
- * FA200000     60000000        1M      DEBUG
- * FB100000     70000000        1M      SPBA 0
- * FB000000     73F00000        1M      AIPS 1
- * FB200000     83F00000        1M      AIPS 2
- *              8FFFC000        16K     TZIC (interrupt controller)
+ * fa200000     60000000        1M      DEBUG
+ * fb100000     70000000        1M      SPBA 0
+ * fb000000     73f00000        1M      AIPS 1
+ * fb200000     83f00000        1M      AIPS 2
+ *              8fffc000        16K     TZIC (interrupt controller)
  *              90000000        256M    CSD0 SDRAM/DDR
- *              A0000000        256M    CSD1 SDRAM/DDR
- *              B0000000        128M    CS0 Flash
- *              B8000000        128M    CS1 Flash
- *              C0000000        128M    CS2 Flash
- *              C8000000        64M     CS3 Flash
- *              CC000000        32M     CS4 SRAM
- *              CE000000        32M     CS5 SRAM
- *              CFFF0000        64K     NFC (NAND Flash AXI)
- *
+ *              a0000000        256M    CSD1 SDRAM/DDR
+ *              b0000000        128M    CS0 Flash
+ *              b8000000        128M    CS1 Flash
+ *              c0000000        128M    CS2 Flash
+ *              c8000000        64M     CS3 Flash
+ *              cc000000        32M     CS4 SRAM
+ *              ce000000        32M     CS5 SRAM
+ *              cfff0000        64K     NFC (NAND Flash AXI)
  */
 
 /*
@@ -36,65 +35,151 @@
 /*
  * IRAM
  */
-#define MX51_IRAM_BASE_ADDR             0x1FFE0000      /* internal ram */
-#define MX51_IRAM_BASE_ADDR_VIRT        0xFA3E0000
+#define MX51_IRAM_BASE_ADDR             0x1ffe0000      /* internal ram */
+#define MX51_IRAM_BASE_ADDR_VIRT        0xfa3e0000
 #define MX51_IRAM_PARTITIONS            16
-#define MX51_IRAM_PARTITIONS_TO1        12
 #define MX51_IRAM_SIZE          (MX51_IRAM_PARTITIONS * SZ_8K)  /* 128KB */
 
+#define MX51_GPU_BASE_ADDR              0x20000000
+#define MX51_GPU_CTRL_BASE_ADDR         0x30000000
+#define MX51_IPU_CTRL_BASE_ADDR         0x40000000
+
+#define MX51_DEBUG_BASE_ADDR            0x60000000
+#define MX51_DEBUG_BASE_ADDR_VIRT       0xfa200000
+#define MX51_DEBUG_SIZE                 SZ_1M
+
+#define MX51_ETB_BASE_ADDR              (MX51_DEBUG_BASE_ADDR + 0x01000)
+#define MX51_ETM_BASE_ADDR              (MX51_DEBUG_BASE_ADDR + 0x02000)
+#define MX51_TPIU_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x03000)
+#define MX51_CTI0_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x04000)
+#define MX51_CTI1_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x05000)
+#define MX51_CTI2_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x06000)
+#define MX51_CTI3_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x07000)
+#define MX51_CORTEX_DBG_BASE_ADDR       (MX51_DEBUG_BASE_ADDR + 0x08000)
+
 /*
- * NFC
+ * SPBA global module enabled #0
  */
-#define MX51_NFC_AXI_BASE_ADDR          0xCFFF0000      /* NAND flash AXI */
-#define MX51_NFC_AXI_SIZE               SZ_64K
+#define MX51_SPBA0_BASE_ADDR            0x70000000
+#define MX51_SPBA0_BASE_ADDR_VIRT       0xfb100000
+#define MX51_SPBA0_SIZE                 SZ_1M
+
+#define MX51_MMC_SDHC1_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x04000)
+#define MX51_MMC_SDHC2_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x08000)
+#define MX51_UART3_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x0c000)
+#define MX51_ECSPI1_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x10000)
+#define MX51_SSI2_BASE_ADDR             (MX51_SPBA0_BASE_ADDR + 0x14000)
+#define MX51_MMC_SDHC3_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x20000)
+#define MX51_MMC_SDHC4_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x24000)
+#define MX51_SPDIF_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x28000)
+#define MX51_ATA_DMA_BASE_ADDR          (MX51_SPBA0_BASE_ADDR + 0x30000)
+#define MX51_SLIM_DMA_BASE_ADDR         (MX51_SPBA0_BASE_ADDR + 0x34000)
+#define MX51_HSI2C_DMA_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x38000)
+#define MX51_SPBA_CTRL_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x3c000)
 
 /*
- * Graphics Memory of GPU
+ * AIPS 1
  */
-#define MX51_GPU_BASE_ADDR              0x20000000
-#define MX51_GPU2D_BASE_ADDR            0xD0000000
+#define MX51_AIPS1_BASE_ADDR            0x73f00000
+#define MX51_AIPS1_BASE_ADDR_VIRT       0xfb000000
+#define MX51_AIPS1_SIZE                 SZ_1M
+
+#define MX51_OTG_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x80000)
+#define MX51_GPIO1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x84000)
+#define MX51_GPIO2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x88000)
+#define MX51_GPIO3_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x8c000)
+#define MX51_GPIO4_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x90000)
+#define MX51_KPP_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x94000)
+#define MX51_WDOG_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0x98000)
+#define MX51_WDOG2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x9c000)
+#define MX51_GPT1_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xa0000)
+#define MX51_SRTC_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xa4000)
+#define MX51_IOMUXC_BASE_ADDR           (MX51_AIPS1_BASE_ADDR + 0xa8000)
+#define MX51_EPIT1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xac000)
+#define MX51_EPIT2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xb0000)
+#define MX51_PWM1_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xb4000)
+#define MX51_PWM2_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xb8000)
+#define MX51_UART1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xbc000)
+#define MX51_UART2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xc0000)
+#define MX51_SRC_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0xd0000)
+#define MX51_CCM_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0xd4000)
+#define MX51_GPC_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0xd8000)
 
-#define MX51_TZIC_BASE_ADDR_TO1         0x8FFFC000
-#define MX51_TZIC_BASE_ADDR             0xE0000000
+/*
+ * AIPS 2
+ */
+#define MX51_AIPS2_BASE_ADDR            0x83f00000
+#define MX51_AIPS2_BASE_ADDR_VIRT       0xfb200000
+#define MX51_AIPS2_SIZE                 SZ_1M
 
-#define MX51_DEBUG_BASE_ADDR            0x60000000
-#define MX51_DEBUG_BASE_ADDR_VIRT       0xFA200000
-#define MX51_DEBUG_SIZE                 SZ_1M
-#define MX51_ETB_BASE_ADDR              (MX51_DEBUG_BASE_ADDR + 0x00001000)
-#define MX51_ETM_BASE_ADDR              (MX51_DEBUG_BASE_ADDR + 0x00002000)
-#define MX51_TPIU_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x00003000)
-#define MX51_CTI0_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x00004000)
-#define MX51_CTI1_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x00005000)
-#define MX51_CTI2_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x00006000)
-#define MX51_CTI3_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x00007000)
-#define MX51_CORTEX_DBG_BASE_ADDR       (MX51_DEBUG_BASE_ADDR + 0x00008000)
+#define MX51_PLL1_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0x80000)
+#define MX51_PLL2_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0x84000)
+#define MX51_PLL3_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0x88000)
+#define MX51_AHBMAX_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0x94000)
+#define MX51_IIM_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0x98000)
+#define MX51_CSU_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0x9c000)
+#define MX51_ARM_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xa0000)
+#define MX51_OWIRE_BASE_ADDR            (MX51_AIPS2_BASE_ADDR + 0xa4000)
+#define MX51_FIRI_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xa8000)
+#define MX51_ECSPI2_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xac000)
+#define MX51_SDMA_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xb0000)
+#define MX51_SCC_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xb4000)
+#define MX51_ROMCP_BASE_ADDR            (MX51_AIPS2_BASE_ADDR + 0xb8000)
+#define MX51_RTIC_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xbc000)
+#define MX51_CSPI_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xc0000)
+#define MX51_I2C2_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xc4000)
+#define MX51_I2C1_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xc8000)
+#define MX51_SSI1_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xcc000)
+#define MX51_AUDMUX_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xd0000)
+#define MX51_M4IF_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xd8000)
+#define MX51_ESDCTL_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xd9000)
+#define MX51_WEIM_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xda000)
+#define MX51_NFC_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xdb000)
+#define MX51_EMI_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xdbf00)
+#define MX51_MIPI_HSC_BASE_ADDR         (MX51_AIPS2_BASE_ADDR + 0xdc000)
+#define MX51_ATA_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xe0000)
+#define MX51_SIM_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xe4000)
+#define MX51_SSI3BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xe8000)
+#define MX51_FEC_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xec000)
+#define MX51_TVE_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xf0000)
+#define MX51_VPU_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xf4000)
+#define MX51_SAHARA_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xf8000)
+
+#define MX51_CSD0_BASE_ADDR             0x90000000
+#define MX51_CSD1_BASE_ADDR             0xa0000000
+#define MX51_CS0_BASE_ADDR              0xb0000000
+#define MX51_CS1_BASE_ADDR              0xb8000000
+#define MX51_CS2_BASE_ADDR              0xc0000000
+#define MX51_CS3_BASE_ADDR              0xc8000000
+#define MX51_CS4_BASE_ADDR              0xcc000000
+#define MX51_CS5_BASE_ADDR              0xce000000
 
 /*
- * SPBA global module enabled #0
+ * NFC
  */
-#define MX51_SPBA0_BASE_ADDR            0x70000000
-#define MX51_SPBA0_BASE_ADDR_VIRT       0xFB100000
-#define MX51_SPBA0_SIZE                 SZ_1M
+#define MX51_NFC_AXI_BASE_ADDR          0xcfff0000      /* NAND flash AXI */
+#define MX51_NFC_AXI_SIZE               SZ_64K
+
+#define MX51_GPU2D_BASE_ADDR            0xd0000000
+#define MX51_TZIC_BASE_ADDR             0xe0000000
 
-#define MX51_MMC_SDHC1_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x00004000)
-#define MX51_MMC_SDHC2_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x00008000)
-#define MX51_UART3_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x0000C000)
-#define MX51_CSPI1_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x00010000)
-#define MX51_SSI2_BASE_ADDR             (MX51_SPBA0_BASE_ADDR + 0x00014000)
-#define MX51_MMC_SDHC3_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x00020000)
-#define MX51_MMC_SDHC4_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x00024000)
-#define MX51_SPDIF_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x00028000)
-#define MX51_ATA_DMA_BASE_ADDR          (MX51_SPBA0_BASE_ADDR + 0x00030000)
-#define MX51_SLIM_DMA_BASE_ADDR         (MX51_SPBA0_BASE_ADDR + 0x00034000)
-#define MX51_HSI2C_DMA_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x00038000)
-#define MX51_SPBA_CTRL_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x0003C000)
+#define MX51_IO_ADDRESS(x) (                                            \
+        IMX_IO_ADDRESS(x, MX51_IRAM) ?:                                 \
+        IMX_IO_ADDRESS(x, MX51_DEBUG) ?:                                \
+        IMX_IO_ADDRESS(x, MX51_SPBA0) ?:                                \
+        IMX_IO_ADDRESS(x, MX51_AIPS1) ?:                                \
+        IMX_IO_ADDRESS(x, MX51_AIPS2))
+
+/* This is currently used in <mach/debug-macro.S>, but should go away */
+#define MX51_AIPS1_IO_ADDRESS(x)  \
+        (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
 
 /*
  * defines for SPBA modules
  */
 #define MX51_SPBA_SDHC1 0x04
 #define MX51_SPBA_SDHC2 0x08
-#define MX51_SPBA_UART3 0x0C
+#define MX51_SPBA_UART3 0x0c
 #define MX51_SPBA_CSPI1 0x10
 #define MX51_SPBA_SSI2  0x14
 #define MX51_SPBA_SDHC3 0x20
@@ -103,35 +188,7 @@
 #define MX51_SPBA_ATA   0x30
 #define MX51_SPBA_SLIM  0x34
 #define MX51_SPBA_HSI2C 0x38
-#define MX51_SPBA_CTRL  0x3C
-
-/*
- * AIPS 1
- */
-#define MX51_AIPS1_BASE_ADDR    0x73F00000
-#define MX51_AIPS1_BASE_ADDR_VIRT       0xFB000000
-#define MX51_AIPS1_SIZE         SZ_1M
-
-#define MX51_OTG_BASE_ADDR      (MX51_AIPS1_BASE_ADDR + 0x00080000)
-#define MX51_GPIO1_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x00084000)
-#define MX51_GPIO2_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x00088000)
-#define MX51_GPIO3_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x0008C000)
-#define MX51_GPIO4_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x00090000)
-#define MX51_KPP_BASE_ADDR      (MX51_AIPS1_BASE_ADDR + 0x00094000)
-#define MX51_WDOG_BASE_ADDR     (MX51_AIPS1_BASE_ADDR + 0x00098000)
-#define MX51_WDOG2_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x0009C000)
-#define MX51_GPT1_BASE_ADDR     (MX51_AIPS1_BASE_ADDR + 0x000A0000)
-#define MX51_SRTC_BASE_ADDR     (MX51_AIPS1_BASE_ADDR + 0x000A4000)
-#define MX51_IOMUXC_BASE_ADDR   (MX51_AIPS1_BASE_ADDR + 0x000A8000)
-#define MX51_EPIT1_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x000AC000)
-#define MX51_EPIT2_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x000B0000)
-#define MX51_PWM1_BASE_ADDR     (MX51_AIPS1_BASE_ADDR + 0x000B4000)
-#define MX51_PWM2_BASE_ADDR     (MX51_AIPS1_BASE_ADDR + 0x000B8000)
-#define MX51_UART1_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x000BC000)
-#define MX51_UART2_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x000C0000)
-#define MX51_SRC_BASE_ADDR      (MX51_AIPS1_BASE_ADDR + 0x000D0000)
-#define MX51_CCM_BASE_ADDR      (MX51_AIPS1_BASE_ADDR + 0x000D4000)
-#define MX51_GPC_BASE_ADDR      (MX51_AIPS1_BASE_ADDR + 0x000D8000)
+#define MX51_SPBA_CTRL  0x3c
 
 /*
  * Defines for modules using static and dynamic DMA channels
@@ -164,282 +221,186 @@
 #define MX51_MXC_DMA_CHANNEL_ATA_TX     MXC_DMA_DYNAMIC_CHANNEL
 #define MX51_MXC_DMA_CHANNEL_MEMORY     MXC_DMA_DYNAMIC_CHANNEL
 
-/*
- * AIPS 2
- */
-#define MX51_AIPS2_BASE_ADDR            0x83F00000
-#define MX51_AIPS2_BASE_ADDR_VIRT       0xFB200000
-#define MX51_AIPS2_SIZE                 SZ_1M
-
-#define MX51_PLL1_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x00080000)
-#define MX51_PLL2_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x00084000)
-#define MX51_PLL3_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x00088000)
-#define MX51_AHBMAX_BASE_ADDR   (MX51_AIPS2_BASE_ADDR + 0x00094000)
-#define MX51_IIM_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x00098000)
-#define MX51_CSU_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x0009C000)
-#define MX51_ARM_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000A0000)
-#define MX51_OWIRE_BASE_ADDR    (MX51_AIPS2_BASE_ADDR + 0x000A4000)
-#define MX51_FIRI_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x000A8000)
-#define MX51_CSPI2_BASE_ADDR    (MX51_AIPS2_BASE_ADDR + 0x000AC000)
-#define MX51_SDMA_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x000B0000)
-#define MX51_SCC_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000B4000)
-#define MX51_ROMCP_BASE_ADDR    (MX51_AIPS2_BASE_ADDR + 0x000B8000)
-#define MX51_RTIC_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x000BC000)
-#define MX51_CSPI3_BASE_ADDR    (MX51_AIPS2_BASE_ADDR + 0x000C0000)
-#define MX51_I2C2_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x000C4000)
-#define MX51_I2C1_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x000C8000)
-#define MX51_SSI1_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x000CC000)
-#define MX51_AUDMUX_BASE_ADDR   (MX51_AIPS2_BASE_ADDR + 0x000D0000)
-#define MX51_M4IF_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x000D8000)
-#define MX51_ESDCTL_BASE_ADDR   (MX51_AIPS2_BASE_ADDR + 0x000D9000)
-#define MX51_WEIM_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x000DA000)
-#define MX51_NFC_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000DB000)
-#define MX51_EMI_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000DBF00)
-#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000)
-#define MX51_ATA_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000E0000)
-#define MX51_SIM_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000E4000)
-#define MX51_SSI3BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000E8000)
-#define MX51_MXC_FEC_BASE_ADDR  (MX51_AIPS2_BASE_ADDR + 0x000EC000)
-#define MX51_TVE_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000F0000)
-#define MX51_VPU_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000F4000)
-#define MX51_SAHARA_BASE_ADDR   (MX51_AIPS2_BASE_ADDR + 0x000F8000)
-
-/*
- * Memory regions and CS
- */
-#define MX51_GPU_CTRL_BASE_ADDR         0x30000000
-#define MX51_IPU_CTRL_BASE_ADDR         0x40000000
-#define MX51_CSD0_BASE_ADDR             0x90000000
-#define MX51_CSD1_BASE_ADDR             0xA0000000
-#define MX51_CS0_BASE_ADDR              0xB0000000
-#define MX51_CS1_BASE_ADDR              0xB8000000
-#define MX51_CS2_BASE_ADDR              0xC0000000
-#define MX51_CS3_BASE_ADDR              0xC8000000
-#define MX51_CS4_BASE_ADDR              0xCC000000
-#define MX51_CS5_BASE_ADDR              0xCE000000
-
-/* Does given address belongs to the specified memory region? */
-#define ADDRESS_IN_REGION(addr, start, size)                    \
-        (((addr) >= (start)) && ((addr) < (start)+(size)))
-
-/* Does given address belongs to the specified named `module'? */
-#define MX51_IS_MODULE(addr, module)                           \
-        ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \
-                                MX51_ ## module ## _SIZE)
-/*
- * This macro defines the physical to virtual address mapping for all the
- * peripheral modules. It is used by passing in the physical address as x
- * and returning the virtual address. If the physical address is not mapped,
- * it returns 0xDEADBEEF
- */
-
-#define MX51_IO_ADDRESS(x)                                      \
-        (void __iomem *)                                        \
-        (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) :    \
-        MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) :   \
-        MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) :   \
-        MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) :   \
-        MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
-        0xDEADBEEF)
-
-/*
- * define the address mapping macros: in physical address order
- */
-#define MX51_IRAM_IO_ADDRESS(x)  \
-        (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
-
-#define MX51_DEBUG_IO_ADDRESS(x)  \
-        (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
-
-#define MX51_SPBA0_IO_ADDRESS(x)  \
-        (((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT)
-
-#define MX51_AIPS1_IO_ADDRESS(x)  \
-        (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
-
-#define MX51_AIPS2_IO_ADDRESS(x)  \
-        (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
-
 #define MX51_IS_MEM_DEVICE_NONSHARED(x)         0
 
 /*
  * DMA request assignments
  */
-#define MX51_DMA_REQ_SSI3_TX1   47
-#define MX51_DMA_REQ_SSI3_RX1   46
-#define MX51_DMA_REQ_SPDIF      45
-#define MX51_DMA_REQ_UART3_TX   44
-#define MX51_DMA_REQ_UART3_RX   43
-#define MX51_DMA_REQ_SLIM_B_TX  42
-#define MX51_DMA_REQ_SDHC4      41
-#define MX51_DMA_REQ_SDHC3      40
-#define MX51_DMA_REQ_CSPI_TX    39
-#define MX51_DMA_REQ_CSPI_RX    38
-#define MX51_DMA_REQ_SSI3_TX2   37
-#define MX51_DMA_REQ_IPU        36
-#define MX51_DMA_REQ_SSI3_RX2   35
-#define MX51_DMA_REQ_EPIT2      34
-#define MX51_DMA_REQ_CTI2_1     33
-#define MX51_DMA_REQ_EMI_WR     32
-#define MX51_DMA_REQ_CTI2_0     31
-#define MX51_DMA_REQ_EMI_RD     30
-#define MX51_DMA_REQ_SSI1_TX1   29
-#define MX51_DMA_REQ_SSI1_RX1   28
-#define MX51_DMA_REQ_SSI1_TX2   27
-#define MX51_DMA_REQ_SSI1_RX2   26
-#define MX51_DMA_REQ_SSI2_TX1   25
-#define MX51_DMA_REQ_SSI2_RX1   24
-#define MX51_DMA_REQ_SSI2_TX2   23
-#define MX51_DMA_REQ_SSI2_RX2   22
-#define MX51_DMA_REQ_SDHC2      21
-#define MX51_DMA_REQ_SDHC1      20
-#define MX51_DMA_REQ_UART1_TX   19
-#define MX51_DMA_REQ_UART1_RX   18
-#define MX51_DMA_REQ_UART2_TX   17
-#define MX51_DMA_REQ_UART2_RX   16
-#define MX51_DMA_REQ_GPU        15
-#define MX51_DMA_REQ_EXTREQ1    14
-#define MX51_DMA_REQ_FIRI_TX    13
-#define MX51_DMA_REQ_FIRI_RX    12
-#define MX51_DMA_REQ_HS_I2C_RX  11
-#define MX51_DMA_REQ_HS_I2C_TX  10
-#define MX51_DMA_REQ_CSPI2_TX   9
-#define MX51_DMA_REQ_CSPI2_RX   8
-#define MX51_DMA_REQ_CSPI1_TX   7
-#define MX51_DMA_REQ_CSPI1_RX   6
-#define MX51_DMA_REQ_SLIM_B     5
-#define MX51_DMA_REQ_ATA_TX_END 4
-#define MX51_DMA_REQ_ATA_TX     3
-#define MX51_DMA_REQ_ATA_RX     2
-#define MX51_DMA_REQ_GPC        1
-#define MX51_DMA_REQ_VPU        0
+#define MX51_DMA_REQ_VPU                0
+#define MX51_DMA_REQ_GPC                1
+#define MX51_DMA_REQ_ATA_RX             2
+#define MX51_DMA_REQ_ATA_TX             3
+#define MX51_DMA_REQ_ATA_TX_END         4
+#define MX51_DMA_REQ_SLIM_B             5
+#define MX51_DMA_REQ_CSPI1_RX           6
+#define MX51_DMA_REQ_CSPI1_TX           7
+#define MX51_DMA_REQ_CSPI2_RX           8
+#define MX51_DMA_REQ_CSPI2_TX           9
+#define MX51_DMA_REQ_HS_I2C_TX          10
+#define MX51_DMA_REQ_HS_I2C_RX          11
+#define MX51_DMA_REQ_FIRI_RX            12
+#define MX51_DMA_REQ_FIRI_TX            13
+#define MX51_DMA_REQ_EXTREQ1            14
+#define MX51_DMA_REQ_GPU                15
+#define MX51_DMA_REQ_UART2_RX           16
+#define MX51_DMA_REQ_UART2_TX           17
+#define MX51_DMA_REQ_UART1_RX           18
+#define MX51_DMA_REQ_UART1_TX           19
+#define MX51_DMA_REQ_SDHC1              20
+#define MX51_DMA_REQ_SDHC2              21
+#define MX51_DMA_REQ_SSI2_RX1           22
+#define MX51_DMA_REQ_SSI2_TX1           23
+#define MX51_DMA_REQ_SSI2_RX0           24
+#define MX51_DMA_REQ_SSI2_TX0           25
+#define MX51_DMA_REQ_SSI1_RX1           26
+#define MX51_DMA_REQ_SSI1_TX1           27
+#define MX51_DMA_REQ_SSI1_RX0           28
+#define MX51_DMA_REQ_SSI1_TX0           29
+#define MX51_DMA_REQ_EMI_RD             30
+#define MX51_DMA_REQ_CTI2_0             31
+#define MX51_DMA_REQ_EMI_WR             32
+#define MX51_DMA_REQ_CTI2_1             33
+#define MX51_DMA_REQ_EPIT2              34
+#define MX51_DMA_REQ_SSI3_RX2           35
+#define MX51_DMA_REQ_IPU                36
+#define MX51_DMA_REQ_SSI3_TX2           37
+#define MX51_DMA_REQ_CSPI_RX            38
+#define MX51_DMA_REQ_CSPI_TX            39
+#define MX51_DMA_REQ_SDHC3              40
+#define MX51_DMA_REQ_SDHC4              41
+#define MX51_DMA_REQ_SLIM_B_TX          42
+#define MX51_DMA_REQ_UART3_RX           43
+#define MX51_DMA_REQ_UART3_TX           44
+#define MX51_DMA_REQ_SPDIF              45
+#define MX51_DMA_REQ_SSI3_RX1           46
+#define MX51_DMA_REQ_SSI3_TX1           47
 
 /*
  * Interrupt numbers
  */
-#define MX51_MXC_INT_BASE       0
-#define MX51_MXC_INT_RESV0      0
-#define MX51_MXC_INT_MMC_SDHC1  1
-#define MX51_MXC_INT_MMC_SDHC2  2
-#define MX51_MXC_INT_MMC_SDHC3  3
-#define MX51_MXC_INT_MMC_SDHC4  4
-#define MX51_MXC_INT_RESV5      5
-#define MX51_MXC_INT_SDMA       6
-#define MX51_MXC_INT_IOMUX      7
-#define MX51_MXC_INT_NFC        8
-#define MX51_MXC_INT_VPU        9
-#define MX51_MXC_INT_IPU_ERR    10
-#define MX51_MXC_INT_IPU_SYN    11
-#define MX51_MXC_INT_GPU        12
-#define MX51_MXC_INT_RESV13     13
-#define MX51_MXC_INT_USB_H1     14
-#define MX51_MXC_INT_EMI        15
-#define MX51_MXC_INT_USB_H2     16
-#define MX51_MXC_INT_USB_H3     17
-#define MX51_MXC_INT_USB_OTG    18
-#define MX51_MXC_INT_SAHARA_H0  19
-#define MX51_MXC_INT_SAHARA_H1  20
-#define MX51_MXC_INT_SCC_SMN    21
-#define MX51_MXC_INT_SCC_STZ    22
-#define MX51_MXC_INT_SCC_SCM    23
-#define MX51_MXC_INT_SRTC_NTZ   24
-#define MX51_MXC_INT_SRTC_TZ    25
-#define MX51_MXC_INT_RTIC       26
-#define MX51_MXC_INT_CSU        27
-#define MX51_MXC_INT_SLIM_B     28
-#define MX51_MXC_INT_SSI1       29
-#define MX51_MXC_INT_SSI2       30
-#define MX51_MXC_INT_UART1      31
-#define MX51_MXC_INT_UART2      32
-#define MX51_MXC_INT_UART3      33
-#define MX51_MXC_INT_RESV34     34
-#define MX51_MXC_INT_RESV35     35
-#define MX51_MXC_INT_CSPI1      36
-#define MX51_MXC_INT_CSPI2      37
-#define MX51_MXC_INT_CSPI       38
-#define MX51_MXC_INT_GPT        39
-#define MX51_MXC_INT_EPIT1      40
-#define MX51_MXC_INT_EPIT2      41
-#define MX51_MXC_INT_GPIO1_INT7 42
-#define MX51_MXC_INT_GPIO1_INT6 43
-#define MX51_MXC_INT_GPIO1_INT5 44
-#define MX51_MXC_INT_GPIO1_INT4 45
-#define MX51_MXC_INT_GPIO1_INT3 46
-#define MX51_MXC_INT_GPIO1_INT2 47
-#define MX51_MXC_INT_GPIO1_INT1 48
-#define MX51_MXC_INT_GPIO1_INT0 49
-#define MX51_MXC_INT_GPIO1_LOW  50
-#define MX51_MXC_INT_GPIO1_HIGH 51
-#define MX51_MXC_INT_GPIO2_LOW  52
-#define MX51_MXC_INT_GPIO2_HIGH 53
-#define MX51_MXC_INT_GPIO3_LOW  54
-#define MX51_MXC_INT_GPIO3_HIGH 55
-#define MX51_MXC_INT_GPIO4_LOW  56
-#define MX51_MXC_INT_GPIO4_HIGH 57
-#define MX51_MXC_INT_WDOG1      58
-#define MX51_MXC_INT_WDOG2      59
-#define MX51_MXC_INT_KPP        60
-#define MX51_MXC_INT_PWM1       61
-#define MX51_MXC_INT_I2C1       62
-#define MX51_MXC_INT_I2C2       63
-#define MX51_MXC_INT_HS_I2C     64
-#define MX51_MXC_INT_RESV65     65
-#define MX51_MXC_INT_RESV66     66
-#define MX51_MXC_INT_SIM_IPB    67
-#define MX51_MXC_INT_SIM_DAT    68
-#define MX51_MXC_INT_IIM        69
-#define MX51_MXC_INT_ATA        70
-#define MX51_MXC_INT_CCM1       71
-#define MX51_MXC_INT_CCM2       72
-#define MX51_MXC_INT_GPC1       73
-#define MX51_MXC_INT_GPC2       74
-#define MX51_MXC_INT_SRC        75
-#define MX51_MXC_INT_NM         76
-#define MX51_MXC_INT_PMU        77
-#define MX51_MXC_INT_CTI_IRQ    78
-#define MX51_MXC_INT_CTI1_TG0   79
-#define MX51_MXC_INT_CTI1_TG1   80
-#define MX51_MXC_INT_MCG_ERR    81
-#define MX51_MXC_INT_MCG_TMR    82
-#define MX51_MXC_INT_MCG_FUNC   83
-#define MX51_MXC_INT_GPU2_IRQ   84
-#define MX51_MXC_INT_GPU2_BUSY  85
-#define MX51_MXC_INT_RESV86     86
-#define MX51_MXC_INT_FEC        87
-#define MX51_MXC_INT_OWIRE      88
-#define MX51_MXC_INT_CTI1_TG2   89
-#define MX51_MXC_INT_SJC        90
-#define MX51_MXC_INT_SPDIF      91
-#define MX51_MXC_INT_TVE        92
-#define MX51_MXC_INT_FIRI       93
-#define MX51_MXC_INT_PWM2       94
-#define MX51_MXC_INT_SLIM_EXP   95
-#define MX51_MXC_INT_SSI3       96
-#define MX51_MXC_INT_EMI_BOOT   97
-#define MX51_MXC_INT_CTI1_TG3   98
-#define MX51_MXC_INT_SMC_RX     99
-#define MX51_MXC_INT_VPU_IDLE   100
-#define MX51_MXC_INT_EMI_NFC    101
-#define MX51_MXC_INT_GPU_IDLE   102
+#define MX51_MXC_INT_BASE               0
+#define MX51_MXC_INT_RESV0              0
+#define MX51_MXC_INT_MMC_SDHC1          1
+#define MX51_MXC_INT_MMC_SDHC2          2
+#define MX51_MXC_INT_MMC_SDHC3          3
+#define MX51_MXC_INT_MMC_SDHC4          4
+#define MX51_MXC_INT_RESV5              5
+#define MX51_INT_SDMA                   6
+#define MX51_MXC_INT_IOMUX              7
+#define MX51_INT_NFC                    8
+#define MX51_MXC_INT_VPU                9
+#define MX51_MXC_INT_IPU_ERR            10
+#define MX51_MXC_INT_IPU_SYN            11
+#define MX51_MXC_INT_GPU                12
+#define MX51_MXC_INT_RESV13             13
+#define MX51_MXC_INT_USB_H1             14
+#define MX51_MXC_INT_EMI                15
+#define MX51_MXC_INT_USB_H2             16
+#define MX51_MXC_INT_USB_H3             17
+#define MX51_MXC_INT_USB_OTG            18
+#define MX51_MXC_INT_SAHARA_H0          19
+#define MX51_MXC_INT_SAHARA_H1          20
+#define MX51_MXC_INT_SCC_SMN            21
+#define MX51_MXC_INT_SCC_STZ            22
+#define MX51_MXC_INT_SCC_SCM            23
+#define MX51_MXC_INT_SRTC_NTZ           24
+#define MX51_MXC_INT_SRTC_TZ            25
+#define MX51_MXC_INT_RTIC               26
+#define MX51_MXC_INT_CSU                27
+#define MX51_MXC_INT_SLIM_B             28
+#define MX51_INT_SSI1                   29
+#define MX51_INT_SSI2                   30
+#define MX51_INT_UART1                  31
+#define MX51_INT_UART2                  32
+#define MX51_INT_UART3                  33
+#define MX51_MXC_INT_RESV34             34
+#define MX51_MXC_INT_RESV35             35
+#define MX51_INT_ECSPI1                 36
+#define MX51_INT_ECSPI2                 37
+#define MX51_INT_CSPI                   38
+#define MX51_MXC_INT_GPT                39
+#define MX51_MXC_INT_EPIT1              40
+#define MX51_MXC_INT_EPIT2              41
+#define MX51_MXC_INT_GPIO1_INT7         42
+#define MX51_MXC_INT_GPIO1_INT6         43
+#define MX51_MXC_INT_GPIO1_INT5         44
+#define MX51_MXC_INT_GPIO1_INT4         45
+#define MX51_MXC_INT_GPIO1_INT3         46
+#define MX51_MXC_INT_GPIO1_INT2         47
+#define MX51_MXC_INT_GPIO1_INT1         48
+#define MX51_MXC_INT_GPIO1_INT0         49
+#define MX51_MXC_INT_GPIO1_LOW          50
+#define MX51_MXC_INT_GPIO1_HIGH         51
+#define MX51_MXC_INT_GPIO2_LOW          52
+#define MX51_MXC_INT_GPIO2_HIGH         53
+#define MX51_MXC_INT_GPIO3_LOW          54
+#define MX51_MXC_INT_GPIO3_HIGH         55
+#define MX51_MXC_INT_GPIO4_LOW          56
+#define MX51_MXC_INT_GPIO4_HIGH         57
+#define MX51_MXC_INT_WDOG1              58
+#define MX51_MXC_INT_WDOG2              59
+#define MX51_MXC_INT_KPP                60
+#define MX51_MXC_INT_PWM1               61
+#define MX51_INT_I2C1                   62
+#define MX51_INT_I2C2                   63
+#define MX51_MXC_INT_HS_I2C             64
+#define MX51_MXC_INT_RESV65             65
+#define MX51_MXC_INT_RESV66             66
+#define MX51_MXC_INT_SIM_IPB            67
+#define MX51_MXC_INT_SIM_DAT            68
+#define MX51_MXC_INT_IIM                69
+#define MX51_MXC_INT_ATA                70
+#define MX51_MXC_INT_CCM1               71
+#define MX51_MXC_INT_CCM2               72
+#define MX51_MXC_INT_GPC1               73
+#define MX51_MXC_INT_GPC2               74
+#define MX51_MXC_INT_SRC                75
+#define MX51_MXC_INT_NM                 76
+#define MX51_MXC_INT_PMU                77
+#define MX51_MXC_INT_CTI_IRQ            78
+#define MX51_MXC_INT_CTI1_TG0           79
+#define MX51_MXC_INT_CTI1_TG1           80
+#define MX51_MXC_INT_MCG_ERR            81
+#define MX51_MXC_INT_MCG_TMR            82
+#define MX51_MXC_INT_MCG_FUNC           83
+#define MX51_MXC_INT_GPU2_IRQ           84
+#define MX51_MXC_INT_GPU2_BUSY          85
+#define MX51_MXC_INT_RESV86             86
+#define MX51_INT_FEC                    87
+#define MX51_MXC_INT_OWIRE              88
+#define MX51_MXC_INT_CTI1_TG2           89
+#define MX51_MXC_INT_SJC                90
+#define MX51_MXC_INT_SPDIF              91
+#define MX51_MXC_INT_TVE                92
+#define MX51_MXC_INT_FIRI               93
+#define MX51_MXC_INT_PWM2               94
+#define MX51_MXC_INT_SLIM_EXP           95
+#define MX51_MXC_INT_SSI3               96
+#define MX51_MXC_INT_EMI_BOOT           97
+#define MX51_MXC_INT_CTI1_TG3           98
+#define MX51_MXC_INT_SMC_RX             99
+#define MX51_MXC_INT_VPU_IDLE           100
+#define MX51_MXC_INT_EMI_NFC            101
+#define MX51_MXC_INT_GPU_IDLE           102
 
 /* silicon revisions specific to i.MX51 */
-#define MX51_CHIP_REV_1_0       0x10
-#define MX51_CHIP_REV_1_1       0x11
-#define MX51_CHIP_REV_1_2       0x12
-#define MX51_CHIP_REV_1_3       0x13
-#define MX51_CHIP_REV_2_0       0x20
-#define MX51_CHIP_REV_2_1       0x21
-#define MX51_CHIP_REV_2_2       0x22
-#define MX51_CHIP_REV_2_3       0x23
-#define MX51_CHIP_REV_3_0       0x30
-#define MX51_CHIP_REV_3_1       0x31
-#define MX51_CHIP_REV_3_2       0x32
-
-/* Mandatory defines used globally */
+#define MX51_CHIP_REV_1_0               0x10
+#define MX51_CHIP_REV_1_1               0x11
+#define MX51_CHIP_REV_1_2               0x12
+#define MX51_CHIP_REV_1_3               0x13
+#define MX51_CHIP_REV_2_0               0x20
+#define MX51_CHIP_REV_2_1               0x21
+#define MX51_CHIP_REV_2_2               0x22
+#define MX51_CHIP_REV_2_3               0x23
+#define MX51_CHIP_REV_3_0               0x30
+#define MX51_CHIP_REV_3_1               0x31
+#define MX51_CHIP_REV_3_2               0x32
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-
 extern int mx51_revision(void);
 #endif
 
-#endif  /*  __ASM_ARCH_MXC_MX51_H__ */
+/* tape-out 1 defines */
+#define MX51_TZIC_BASE_ADDR_TO1         0x8fffc000
+
+#endif  /* ifndef __MACH_MX51_H__ */
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index ea3ca86c5283..aedf9c1d645e 100644
--- a/arch/arm/plat-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/mach-nomadik/timer.c
+ *  linux/arch/arm/plat-nomadik/timer.c
  *
  * Copyright (C) 2008 STMicroelectronics
  * Copyright (C) 2010 Alessandro Rubini
@@ -75,7 +75,7 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
                 cr = readl(mtu_base + MTU_CR(1));
                 writel(0, mtu_base + MTU_LR(1));
                 writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1));
-                writel(0x2, mtu_base + MTU_IMSC);
+                writel(1 << 1, mtu_base + MTU_IMSC);
                 break;
         case CLOCK_EVT_MODE_SHUTDOWN:
         case CLOCK_EVT_MODE_UNUSED:
@@ -131,25 +131,23 @@ void __init nmdk_timer_init(void)
 {
         unsigned long rate;
         struct clk *clk0;
-        struct clk *clk1;
-        u32 cr;
+        u32 cr = MTU_CRn_32BITS;
 
         clk0 = clk_get_sys("mtu0", NULL);
         BUG_ON(IS_ERR(clk0));
 
-        clk1 = clk_get_sys("mtu1", NULL);
-        BUG_ON(IS_ERR(clk1));
-
         clk_enable(clk0);
-        clk_enable(clk1);
 
         /*
-         * Tick rate is 2.4MHz for Nomadik and 110MHz for ux500:
-         * use a divide-by-16 counter if it's more than 16MHz
+         * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
+         * for ux500.
+         * Use a divide-by-16 counter if the tick rate is more than 32MHz.
+         * At 32 MHz, the timer (with 32 bit counter) can be programmed
+         * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
+         * with 16 gives too low timer resolution.
          */
-        cr = MTU_CRn_32BITS;;
         rate = clk_get_rate(clk0);
-        if (rate > 16 << 20) {
+        if (rate > 32000000) {
                 rate /= 16;
                 cr |= MTU_CRn_PRESCALE_16;
         } else {
@@ -170,15 +168,8 @@ void __init nmdk_timer_init(void)
                 pr_err("timer: failed to initialize clock source %s\n",
                        nmdk_clksrc.name);
 
-        /* Timer 1 is used for events, fix according to rate */
-        cr = MTU_CRn_32BITS;
-        rate = clk_get_rate(clk1);
-        if (rate > 16 << 20) {
-                rate /= 16;
-                cr |= MTU_CRn_PRESCALE_16;
-        } else {
-                cr |= MTU_CRn_PRESCALE_1;
-        }
+        /* Timer 1 is used for events */
+
         clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
 
         writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index e39a417a368d..a92cb499313f 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -33,7 +33,7 @@ config OMAP_DEBUG_DEVICES
 config OMAP_DEBUG_LEDS
         bool
         depends on OMAP_DEBUG_DEVICES
-        default y if LEDS
+        default y if LEDS_CLASS
 
 config OMAP_RESET_CLOCKS
         bool "Reset unused clocks during boot"
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index e31496e35b0f..0c8612fd8312 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -156,7 +156,7 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
                 /* Writing zero to RSYNC_ERR clears the IRQ */
                 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
         } else {
-                complete(&mcbsp_rx->tx_irq_completion);
+                complete(&mcbsp_rx->rx_irq_completion);
         }
 
         return IRQ_HANDLED;
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 226b2e858d6c..10b3b4c63372 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -220,20 +220,7 @@ void __init omap_map_sram(void)
         if (omap_sram_size == 0)
                 return;
 
-        if (cpu_is_omap24xx()) {
-                omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
-
-                base = OMAP2_SRAM_PA;
-                base = ROUND_DOWN(base, PAGE_SIZE);
-                omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
-        }
-
         if (cpu_is_omap34xx()) {
-                omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
-                base = OMAP3_SRAM_PA;
-                base = ROUND_DOWN(base, PAGE_SIZE);
-                omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
-
                 /*
                  * SRAM must be marked as non-cached on OMAP3 since the
                  * CORE DPLL M2 divider change code (in SRAM) runs with the
@@ -244,13 +231,11 @@ void __init omap_map_sram(void)
                 omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
         }
 
-        if (cpu_is_omap44xx()) {
-                omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA;
-                base = OMAP4_SRAM_PA;
-                base = ROUND_DOWN(base, PAGE_SIZE);
-                omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
-        }
-        omap_sram_io_desc[0].length = 1024 * 1024;      /* Use section desc */
+        omap_sram_io_desc[0].virtual = omap_sram_base;
+        base = omap_sram_start;
+        base = ROUND_DOWN(base, PAGE_SIZE);
+        omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
+        omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE);
         iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
 
         printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
index 7b4eadc6df3a..abcc36eb1242 100644
--- a/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h
+++ b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
@@ -25,6 +25,13 @@
  *
  * 4. matrix key and direct key will use the same debounce_interval by
  *    default, which should be sufficient in most cases
+ *
+ * pxa168 keypad platform specific parameter
+ *
+ * NOTE:
+ * clear_wakeup_event callback is a workaround required to clear the
+ * keypad interrupt. The keypad wake must be cleared in addition to
+ * reading the MI/DI bits in the KPC register.
  */
 struct pxa27x_keypad_platform_data {
 
@@ -52,6 +59,9 @@ struct pxa27x_keypad_platform_data {
 
         /* key debounce interval */
         unsigned int    debounce_interval;
+
+        /* clear wakeup event requirement for pxa168 */
+        void            (*clear_wakeup_event)(void);
 };
 
 extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
diff --git a/arch/arm/plat-tcc/Kconfig b/arch/arm/plat-tcc/Kconfig
new file mode 100644
index 000000000000..1bf499570f42
--- /dev/null
+++ b/arch/arm/plat-tcc/Kconfig
@@ -0,0 +1,20 @@
+if ARCH_TCC_926
+
+menu "Telechips ARM926-based CPUs"
+
+choice
+        prompt "Telechips CPU type:"
+        default ARCH_TCC8K
+
+config ARCH_TCC8K
+        bool TCC8000
+        select USB_ARCH_HAS_OHCI
+        help
+          Support for Telechips TCC8000 systems
+
+endchoice
+
+source "arch/arm/mach-tcc8k/Kconfig"
+
+endmenu
+endif
diff --git a/arch/arm/plat-tcc/Makefile b/arch/arm/plat-tcc/Makefile
new file mode 100644
index 000000000000..eceabc869b8f
--- /dev/null
+++ b/arch/arm/plat-tcc/Makefile
@@ -0,0 +1,3 @@
+# "Telechips Platform Common Modules"
+
+obj-y := clock.o system.o
diff --git a/arch/arm/plat-tcc/clock.c b/arch/arm/plat-tcc/clock.c
new file mode 100644
index 000000000000..f3ced10d5271
--- /dev/null
+++ b/arch/arm/plat-tcc/clock.c
@@ -0,0 +1,179 @@
+/*
+ * Clock framework for Telechips SoCs
+ * Based on arch/arm/plat-mxc/clock.c
+ *
+ * Copyright (C) 2004 - 2005 Nokia corporation
+ * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2010 Hans J. Koch, hjk@linutronix.de
+ *
+ * Licensed under the terms of the GPL v2.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/string.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+
+static DEFINE_MUTEX(clocks_mutex);
+
+/*-------------------------------------------------------------------------
+ * Standard clock functions defined in include/linux/clk.h
+ *-------------------------------------------------------------------------*/
+
+static void __clk_disable(struct clk *clk)
+{
+        BUG_ON(clk->refcount == 0);
+
+        if (!(--clk->refcount) && clk->disable) {
+                /* Unconditionally disable the clock in hardware */
+                clk->disable(clk);
+                /* recursively disable parents */
+                if (clk->parent)
+                        __clk_disable(clk->parent);
+        }
+}
+
+static int __clk_enable(struct clk *clk)
+{
+        int ret = 0;
+
+        if (clk->refcount++ == 0 && clk->enable) {
+                if (clk->parent)
+                        ret = __clk_enable(clk->parent);
+                if (ret)
+                        return ret;
+                else
+                        return clk->enable(clk);
+        }
+
+        return 0;
+}
+
+/* This function increments the reference count on the clock and enables the
+ * clock if not already enabled. The parent clock tree is recursively enabled
+ */
+int clk_enable(struct clk *clk)
+{
+        int ret = 0;
+
+        if (!clk)
+                return -EINVAL;
+
+        mutex_lock(&clocks_mutex);
+        ret = __clk_enable(clk);
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+/* This function decrements the reference count on the clock and disables
+ * the clock when reference count is 0. The parent clock tree is
+ * recursively disabled
+ */
+void clk_disable(struct clk *clk)
+{
+        if (!clk)
+                return;
+
+        mutex_lock(&clocks_mutex);
+        __clk_disable(clk);
+        mutex_unlock(&clocks_mutex);
+}
+EXPORT_SYMBOL_GPL(clk_disable);
+
+/* Retrieve the *current* clock rate. If the clock itself
+ * does not provide a special calculation routine, ask
+ * its parent and so on, until one is able to return
+ * a valid clock rate
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (!clk)
+                return 0UL;
+
+        if (clk->get_rate)
+                return clk->get_rate(clk);
+
+        return clk_get_rate(clk->parent);
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+/* Round the requested clock rate to the nearest supported
+ * rate that is less than or equal to the requested rate.
+ * This is dependent on the clock's current parent.
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (!clk)
+                return 0;
+        if (!clk->round_rate)
+                return 0;
+
+        return clk->round_rate(clk, rate);
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+/* Set the clock to the requested clock rate. The rate must
+ * match a supported rate exactly based on what clk_round_rate returns
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret = -EINVAL;
+
+        if (!clk)
+                return ret;
+        if (!clk->set_rate || !rate)
+                return ret;
+
+        mutex_lock(&clocks_mutex);
+        ret = clk->set_rate(clk, rate);
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+/* Set the clock's parent to another clock source */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        struct clk *old;
+        int ret = -EINVAL;
+
+        if (!clk)
+                return ret;
+        if (!clk->set_parent || !parent)
+                return ret;
+
+        mutex_lock(&clocks_mutex);
+        old = clk->parent;
+        if (clk->refcount)
+                __clk_enable(parent);
+        ret = clk->set_parent(clk, parent);
+        if (ret)
+                old = parent;
+        if (clk->refcount)
+                __clk_disable(old);
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_parent);
+
+/* Retrieve the clock's parent clock source */
+struct clk *clk_get_parent(struct clk *clk)
+{
+        if (!clk)
+                return NULL;
+
+        return clk->parent;
+}
+EXPORT_SYMBOL_GPL(clk_get_parent);
diff --git a/arch/arm/plat-tcc/include/mach/clkdev.h b/arch/arm/plat-tcc/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/plat-tcc/include/mach/clock.h b/arch/arm/plat-tcc/include/mach/clock.h
new file mode 100644
index 000000000000..a12f58ad71a8
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/clock.h
@@ -0,0 +1,48 @@
+/*
+ * Low level clock header file for Telechips TCC architecture
+ * (C) 2010 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the GPL v2.
+ */
+
+#ifndef __ASM_ARCH_TCC_CLOCK_H__
+#define __ASM_ARCH_TCC_CLOCK_H__
+
+#ifndef __ASSEMBLY__
+
+struct clk {
+        struct clk *parent;
+        /* id number of a root clock, 0 for normal clocks */
+        int root_id;
+        /* Reference count of clock enable/disable */
+        int refcount;
+        /* Address of associated BCLKCTRx register. Must be set. */
+        void __iomem *bclkctr;
+        /* Bit position for BCLKCTRx. Must be set. */
+        int bclk_shift;
+        /* Address of ACLKxxx register, if any. */
+        void __iomem *aclkreg;
+        /* get the current clock rate (always a fresh value) */
+        unsigned long (*get_rate) (struct clk *);
+        /* Function ptr to set the clock to a new rate. The rate must match a
+           supported rate returned from round_rate. Leave blank if clock is not
+           programmable */
+        int (*set_rate) (struct clk *, unsigned long);
+        /* Function ptr to round the requested clock rate to the nearest
+           supported rate that is less than or equal to the requested rate. */
+        unsigned long (*round_rate) (struct clk *, unsigned long);
+        /* Function ptr to enable the clock. Leave blank if clock can not
+           be gated. */
+        int (*enable) (struct clk *);
+        /* Function ptr to disable the clock. Leave blank if clock can not
+           be gated. */
+        void (*disable) (struct clk *);
+        /* Function ptr to set the parent clock of the clock. */
+        int (*set_parent) (struct clk *, struct clk *);
+};
+
+int clk_register(struct clk *clk);
+void clk_unregister(struct clk *clk);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/arch/arm/plat-tcc/include/mach/debug-macro.S b/arch/arm/plat-tcc/include/mach/debug-macro.S
new file mode 100644
index 000000000000..97537845df64
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/debug-macro.S
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 1994-1999 Russell King
+ * Copyright (C) 2008-2009 Telechips
+ * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+                .macro  addruart,rx,tmp
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x90000000        @ physical base address
+                movne   \rx, #0xF1000000        @ virtual base
+                orr     \rx, \rx, #0x00007000   @ UART0
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx, #0x44]
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:
+                ldr \rd, [\rx, #0x14]
+                tst \rd, #0x20
+
+                beq 1001b
+                .endm
diff --git a/arch/arm/plat-tcc/include/mach/entry-macro.S b/arch/arm/plat-tcc/include/mach/entry-macro.S
new file mode 100644
index 000000000000..748f401e4b6d
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/entry-macro.S
@@ -0,0 +1,68 @@
+/*
+ * include/asm-arm/arch-tcc83x/entry-macro.S
+ *
+ * Author : <linux@telechips.com>
+ * Created: June 10, 2008
+ * Description: Low-level IRQ helper macros for Telechips-based platforms
+ *
+ * Copyright (C) 2008-2009 Telechips
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+                ldr     \base, =0xF2003000 @ base address of PIC registers
+
+                @@ read MREQ register of PIC0
+
+                mov     \irqnr, #0
+                ldr     \irqstat, [\base, #0x00000014 ] @ lower 32 interrupts
+                cmp     \irqstat, #0
+                bne     1001f
+
+                @@ read MREQ register of PIC1
+
+                ldr     \irqstat, [\base, #0x00000094]  @ upper 32 interrupts
+                cmp     \irqstat, #0
+                beq     1002f
+                mov     \irqnr, #0x20
+
+1001:
+                movs    \tmp, \irqstat, lsl #16
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #16
+
+                movs    \tmp, \irqstat, lsl #8
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #8
+
+                movs    \tmp, \irqstat, lsl #4
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #4
+
+                movs    \tmp, \irqstat, lsl #2
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #2
+
+                movs    \tmp, \irqstat, lsl #1
+                addeq   \irqnr, \irqnr, #1
+                orrs    \base, \base, #1
+1002:
+                @@ exit here, Z flag unset if IRQ
+
+        .endm
diff --git a/arch/arm/plat-tcc/include/mach/hardware.h b/arch/arm/plat-tcc/include/mach/hardware.h
new file mode 100644
index 000000000000..e70d126ccaf3
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/hardware.h
@@ -0,0 +1,43 @@
+/*
+ * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
+ * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
+ *                          and Dirk Behme <dirk.behme@de.bosch.com>
+ * Rewritten by:    <linux@telechips.com>
+ * Description: Hardware definitions for TCC8300 processors and boards
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Copyright (C) 2008-2009 Telechips
+ *
+ * Modifications for mainline (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GNU Pulic License version 2.
+ */
+
+#ifndef __ASM_ARCH_TCC_HARDWARE_H
+#define __ASM_ARCH_TCC_HARDWARE_H
+
+#include <asm/sizes.h>
+#ifndef __ASSEMBLER__
+#include <asm/types.h>
+#endif
+#include <mach/io.h>
+
+/*
+ * ----------------------------------------------------------------------------
+ * Clocks
+ * ----------------------------------------------------------------------------
+ */
+#define CLKGEN_REG_BASE         0xfffece00
+#define ARM_CKCTL               (CLKGEN_REG_BASE + 0x0)
+#define ARM_IDLECT1             (CLKGEN_REG_BASE + 0x4)
+#define ARM_IDLECT2             (CLKGEN_REG_BASE + 0x8)
+#define ARM_EWUPCT              (CLKGEN_REG_BASE + 0xC)
+#define ARM_RSTCT1              (CLKGEN_REG_BASE + 0x10)
+#define ARM_RSTCT2              (CLKGEN_REG_BASE + 0x14)
+#define ARM_SYSST               (CLKGEN_REG_BASE + 0x18)
+#define ARM_IDLECT3             (CLKGEN_REG_BASE + 0x24)
+
+/* DPLL control registers */
+#define DPLL_CTL                0xfffecf00
+
+#endif  /* __ASM_ARCH_TCC_HARDWARE_H */
diff --git a/arch/arm/plat-tcc/include/mach/io.h b/arch/arm/plat-tcc/include/mach/io.h
new file mode 100644
index 000000000000..3e911d3ea0f1
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/io.h
@@ -0,0 +1,23 @@
+/*
+ * IO definitions for TCC8000 processors and boards
+ *
+ * Copyright (C) 1997-1999 Russell King
+ * Copyright (C) 2008-2009 Telechips
+ * Copyright (C) 2010 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GNU Public License version 2.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)                 __typesafe_io(a)
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/arch/arm/plat-tcc/include/mach/irqs.h b/arch/arm/plat-tcc/include/mach/irqs.h
new file mode 100644
index 000000000000..da863894d498
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/irqs.h
@@ -0,0 +1,83 @@
+/*
+ * IRQ definitions for TCC8xxx
+ *
+ * Copyright (C) 2008-2009 Telechips
+ * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPL v2.
+ *
+ */
+
+#ifndef __ASM_ARCH_TCC_IRQS_H
+#define __ASM_ARCH_TCC_IRQS_H
+
+#define NR_IRQS 64
+
+/* PIC0 interrupts */
+#define INT_ADMA1       0
+#define INT_BDMA        1
+#define INT_ADMA0       2
+#define INT_GDMA1       3
+#define INT_I2S0RX      4
+#define INT_I2S0TX      5
+#define INT_TC          6
+#define INT_UART0       7
+#define INT_USBD        8
+#define INT_SPI0TX      9
+#define INT_UDMA        10
+#define INT_LIRQ        11
+#define INT_GDMA2       12
+#define INT_GDMA0       13
+#define INT_TC32        14
+#define INT_LCD         15
+#define INT_ADC         16
+#define INT_I2C         17
+#define INT_RTCP        18
+#define INT_RTCA        19
+#define INT_NFC         20
+#define INT_SD0         21
+#define INT_GSB0        22
+#define INT_PK          23
+#define INT_USBH0       24
+#define INT_USBH1       25
+#define INT_G2D         26
+#define INT_ECC         27
+#define INT_SPI0RX      28
+#define INT_UART1       29
+#define INT_MSCL        30
+#define INT_GSB1        31
+/* PIC1 interrupts */
+#define INT_E0          32
+#define INT_E1          33
+#define INT_E2          34
+#define INT_E3          35
+#define INT_E4          36
+#define INT_E5          37
+#define INT_E6          38
+#define INT_E7          39
+#define INT_UART2       40
+#define INT_UART3       41
+#define INT_SPI1TX      42
+#define INT_SPI1RX      43
+#define INT_GSB2        44
+#define INT_SPDIF       45
+#define INT_CDIF        46
+#define INT_VBON        47
+#define INT_VBOFF       48
+#define INT_SD1         49
+#define INT_UART4       50
+#define INT_GDMA3       51
+#define INT_I2S1RX      52
+#define INT_I2S1TX      53
+#define INT_CAN0        54
+#define INT_CAN1        55
+#define INT_GSB3        56
+#define INT_KRST        57
+#define INT_UNUSED      58
+#define INT_SD0D3       59
+#define INT_SD1D3       60
+#define INT_GPS0        61
+#define INT_GPS1        62
+#define INT_GPS2        63
+
+#endif  /* ASM_ARCH_TCC_IRQS_H */
diff --git a/arch/arm/plat-tcc/include/mach/memory.h b/arch/arm/plat-tcc/include/mach/memory.h
new file mode 100644
index 000000000000..cd91ba8a670b
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/memory.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Copyright (C) 2008-2009 Telechips
+ * Copyright (C) 2010 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPL v2.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET             UL(0x20000000)
+
+#endif
diff --git a/arch/arm/plat-tcc/include/mach/system.h b/arch/arm/plat-tcc/include/mach/system.h
new file mode 100644
index 000000000000..909e6035d843
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/system.h
@@ -0,0 +1,31 @@
+/*
+ * Author: <linux@telechips.com>
+ * Created: June 10, 2008
+ * Description: LINUX SYSTEM FUNCTIONS for TCC83x
+ *
+ * Copyright (C) 2008-2009 Telechips
+ *
+ * Licensed under the terms of the GPL v2.
+ *
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <linux/clk.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+extern void plat_tcc_reboot(void);
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+        plat_tcc_reboot();
+}
+
+#endif
diff --git a/arch/arm/plat-tcc/include/mach/tcc8k-regs.h b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
new file mode 100644
index 000000000000..1d9428295332
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
@@ -0,0 +1,807 @@
+/*
+ * Telechips TCC8000 register definitions
+ *
+ * (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPLv2.
+ */
+
+#ifndef TCC8K_REGS_H
+#define TCC8K_REGS_H
+
+#include <linux/types.h>
+
+#define EXT_SDRAM_BASE          0x20000000
+#define INT_SRAM_BASE           0x30000000
+#define INT_SRAM_SIZE           SZ_32K
+#define CS0_BASE                0x40000000
+#define CS1_BASE                0x50000000
+#define CS1_SIZE                SZ_64K
+#define CS2_BASE                0x60000000
+#define CS3_BASE                0x70000000
+#define AHB_PERI_BASE           0x80000000
+#define AHB_PERI_SIZE           SZ_64K
+#define APB0_PERI_BASE          0x90000000
+#define APB0_PERI_SIZE          SZ_128K
+#define APB1_PERI_BASE          0x98000000
+#define APB1_PERI_SIZE          SZ_128K
+#define DATA_TCM_BASE           0xa0000000
+#define DATA_TCM_SIZE           SZ_8K
+#define EXT_MEM_CTRL_BASE       0xf0000000
+#define EXT_MEM_CTRL_SIZE       SZ_4K
+
+#define CS1_BASE_VIRT           (void __iomem *)0xf7000000
+#define AHB_PERI_BASE_VIRT      (void __iomem *)0xf4000000
+#define APB0_PERI_BASE_VIRT     (void __iomem *)0xf1000000
+#define APB1_PERI_BASE_VIRT     (void __iomem *)0xf2000000
+#define EXT_MEM_CTRL_BASE_VIRT  (void __iomem *)0xf3000000
+#define INT_SRAM_BASE_VIRT      (void __iomem *)0xf5000000
+#define DATA_TCM_BASE_VIRT      (void __iomem *)0xf6000000
+
+#define __REG(x)     (*((volatile u32 *)(x)))
+
+/* USB Device Controller Registers */
+#define UDC_BASE        (AHB_PERI_BASE_VIRT + 0x8000)
+#define UDC_BASE_PHYS   (AHB_PERI_BASE + 0x8000)
+
+#define UDC_IR_OFFS             0x00
+#define UDC_EIR_OFFS            0x04
+#define UDC_EIER_OFFS           0x08
+#define UDC_FAR_OFFS            0x0c
+#define UDC_FNR_OFFS            0x10
+#define UDC_EDR_OFFS            0x14
+#define UDC_RT_OFFS             0x18
+#define UDC_SSR_OFFS            0x1c
+#define UDC_SCR_OFFS            0x20
+#define UDC_EP0SR_OFFS          0x24
+#define UDC_EP0CR_OFFS          0x28
+
+#define UDC_ESR_OFFS            0x2c
+#define UDC_ECR_OFFS            0x30
+#define UDC_BRCR_OFFS           0x34
+#define UDC_BWCR_OFFS           0x38
+#define UDC_MPR_OFFS            0x3c
+#define UDC_DCR_OFFS            0x40
+#define UDC_DTCR_OFFS           0x44
+#define UDC_DFCR_OFFS           0x48
+#define UDC_DTTCR1_OFFS         0x4c
+#define UDC_DTTCR2_OFFS         0x50
+#define UDC_ESR2_OFFS           0x54
+
+#define UDC_SCR2_OFFS           0x58
+#define UDC_EP0BUF_OFFS         0x60
+#define UDC_EP1BUF_OFFS         0x64
+#define UDC_EP2BUF_OFFS         0x68
+#define UDC_EP3BUF_OFFS         0x6c
+#define UDC_PLICR_OFFS          0xa0
+#define UDC_PCR_OFFS            0xa4
+
+#define UDC_UPCR0_OFFS          0xc8
+#define UDC_UPCR1_OFFS          0xcc
+#define UDC_UPCR2_OFFS          0xd0
+#define UDC_UPCR3_OFFS          0xd4
+
+/* Bits in UDC_EIR */
+#define UDC_EIR_EP0I            (1 << 0)
+#define UDC_EIR_EP1I            (1 << 1)
+#define UDC_EIR_EP2I            (1 << 2)
+#define UDC_EIR_EP3I            (1 << 3)
+#define UDC_EIR_EPI_MASK        0x0f
+
+/* Bits in UDC_EIER */
+#define UDC_EIER_EP0IE          (1 << 0)
+#define UDC_EIER_EP1IE          (1 << 1)
+#define UDC_EIER_EP2IE          (1 << 2)
+#define UDC_EIER_EP3IE          (1 << 3)
+
+/* Bits in UDC_FNR */
+#define UDC_FNR_FN_MASK         0x7ff
+#define UDC_FNR_SM              (1 << 13)
+#define UDC_FNR_FTL             (1 << 14)
+
+/* Bits in UDC_SSR */
+#define UDC_SSR_HFRES           (1 << 0)
+#define UDC_SSR_HFSUSP          (1 << 1)
+#define UDC_SSR_HFRM            (1 << 2)
+#define UDC_SSR_SDE             (1 << 3)
+#define UDC_SSR_HSP             (1 << 4)
+#define UDC_SSR_DM              (1 << 5)
+#define UDC_SSR_DP              (1 << 6)
+#define UDC_SSR_TBM             (1 << 7)
+#define UDC_SSR_VBON            (1 << 8)
+#define UDC_SSR_VBOFF           (1 << 9)
+#define UDC_SSR_EOERR           (1 << 10)
+#define UDC_SSR_DCERR           (1 << 11)
+#define UDC_SSR_TCERR           (1 << 12)
+#define UDC_SSR_BSERR           (1 << 13)
+#define UDC_SSR_TMERR           (1 << 14)
+#define UDC_SSR_BAERR           (1 << 15)
+
+/* Bits in UDC_SCR */
+#define UDC_SCR_HRESE           (1 << 0)
+#define UDC_SCR_HSSPE           (1 << 1)
+#define UDC_SCR_RRDE            (1 << 5)
+#define UDC_SCR_SPDEN           (1 << 6)
+#define UDC_SCR_DIEN            (1 << 12)
+
+/* Bits in UDC_EP0SR */
+#define UDC_EP0SR_RSR           (1 << 0)
+#define UDC_EP0SR_TST           (1 << 1)
+#define UDC_EP0SR_SHT           (1 << 4)
+#define UDC_EP0SR_LWO           (1 << 6)
+
+/* Bits in UDC_EP0CR */
+#define UDC_EP0CR_ESS           (1 << 1)
+
+/* Bits in UDC_ESR */
+#define UDC_ESR_RPS             (1 << 0)
+#define UDC_ESR_TPS             (1 << 1)
+#define UDC_ESR_LWO             (1 << 4)
+#define UDC_ESR_FFS             (1 << 6)
+
+/* Bits in UDC_ECR */
+#define UDC_ECR_ESS             (1 << 1)
+#define UDC_ECR_CDP             (1 << 2)
+
+#define UDC_ECR_FLUSH           (1 << 6)
+#define UDC_ECR_DUEN            (1 << 7)
+
+/* Bits in UDC_UPCR0 */
+#define UDC_UPCR0_VBD           (1 << 1)
+#define UDC_UPCR0_VBDS          (1 << 6)
+#define UDC_UPCR0_RCD_12        (0x0 << 9)
+#define UDC_UPCR0_RCD_24        (0x1 << 9)
+#define UDC_UPCR0_RCD_48        (0x2 << 9)
+#define UDC_UPCR0_RCS_EXT       (0x1 << 11)
+#define UDC_UPCR0_RCS_XTAL      (0x0 << 11)
+
+/* Bits in UDC_UPCR1 */
+#define UDC_UPCR1_CDT(x)        ((x) << 0)
+#define UDC_UPCR1_OTGT(x)       ((x) << 3)
+#define UDC_UPCR1_SQRXT(x)      ((x) << 8)
+#define UDC_UPCR1_TXFSLST(x)    ((x) << 12)
+
+/* Bits in UDC_UPCR2 */
+#define UDC_UPCR2_TP            (1 << 0)
+#define UDC_UPCR2_TXRT(x)       ((x) << 2)
+#define UDC_UPCR2_TXVRT(x)      ((x) << 5)
+#define UDC_UPCR2_OPMODE(x)     ((x) << 9)
+#define UDC_UPCR2_XCVRSEL(x)    ((x) << 12)
+#define UDC_UPCR2_TM            (1 << 14)
+
+/* USB Host Controller registers */
+#define USBH0_BASE      (AHB_PERI_BASE_VIRT + 0xb000)
+#define USBH1_BASE      (AHB_PERI_BASE_VIRT + 0xb800)
+
+#define OHCI_INT_ENABLE_OFFS    0x10
+
+#define RH_DESCRIPTOR_A_OFFS    0x48
+#define RH_DESCRIPTOR_B_OFFS    0x4c
+
+#define USBHTCFG0_OFFS          0x100
+#define USBHHCFG0_OFFS          0x104
+#define USBHHCFG1_OFFS          0x104
+
+/* DMA controller registers */
+#define DMAC0_BASE      (AHB_PERI_BASE + 0x4000)
+#define DMAC1_BASE      (AHB_PERI_BASE + 0xa000)
+#define DMAC2_BASE      (AHB_PERI_BASE + 0x4800)
+#define DMAC3_BASE      (AHB_PERI_BASE + 0xa800)
+
+#define DMAC_CH_OFFSET(ch)      (ch * 0x30)
+
+#define ST_SADR_OFFS            0x00
+#define SPARAM_OFFS             0x04
+#define C_SADR_OFFS             0x0c
+#define ST_DADR_OFFS            0x10
+#define DPARAM_OFFS             0x14
+#define C_DADR_OFFS             0x1c
+#define HCOUNT_OFFS             0x20
+#define CHCTRL_OFFS             0x24
+#define RPTCTRL_OFFS            0x28
+#define EXTREQ_A_OFFS           0x2c
+
+/* Bits in CHCTRL register */
+#define CHCTRL_EN               (1 << 0)
+
+#define CHCTRL_IEN              (1 << 2)
+#define CHCTRL_FLAG             (1 << 3)
+#define CHCTRL_WSIZE8           (0 << 4)
+#define CHCTRL_WSIZE16          (1 << 4)
+#define CHCTRL_WSIZE32          (2 << 4)
+
+#define CHCTRL_BSIZE1           (0 << 6)
+#define CHCTRL_BSIZE2           (1 << 6)
+#define CHCTRL_BSIZE4           (2 << 6)
+#define CHCTRL_BSIZE8           (3 << 6)
+
+#define CHCTRL_TYPE_SINGLE_E    (0 << 8)
+#define CHCTRL_TYPE_HW          (1 << 8)
+#define CHCTRL_TYPE_SW          (2 << 8)
+#define CHCTRL_TYPE_SINGLE_L    (3 << 8)
+
+#define CHCTRL_BST              (1 << 10)
+
+/* Use DMA controller 0, channel 2 for USB */
+#define USB_DMA_BASE            (DMAC0_BASE + DMAC_CH_OFFSET(2))
+
+/* NAND flash controller registers */
+#define NFC_BASE        (AHB_PERI_BASE_VIRT + 0xd000)
+#define NFC_BASE_PHYS   (AHB_PERI_BASE + 0xd000)
+
+#define NFC_CMD_OFFS            0x00
+#define NFC_LADDR_OFFS          0x04
+#define NFC_BADDR_OFFS          0x08
+#define NFC_SADDR_OFFS          0x0c
+#define NFC_WDATA_OFFS          0x10
+#define NFC_LDATA_OFFS          0x20
+#define NFC_SDATA_OFFS          0x40
+#define NFC_CTRL_OFFS           0x50
+#define NFC_PSTART_OFFS         0x54
+#define NFC_RSTART_OFFS         0x58
+#define NFC_DSIZE_OFFS          0x5c
+#define NFC_IREQ_OFFS           0x60
+#define NFC_RST_OFFS            0x64
+#define NFC_CTRL1_OFFS          0x68
+#define NFC_MDATA_OFFS          0x70
+
+#define NFC_WDATA_PHYS_ADDR     (NFC_BASE_PHYS + NFC_WDATA_OFFS)
+
+/* Bits in NFC_CTRL */
+#define NFC_CTRL_BHLD_MASK      (0xf << 0)
+#define NFC_CTRL_BPW_MASK       (0xf << 4)
+#define NFC_CTRL_BSTP_MASK      (0xf << 8)
+#define NFC_CTRL_CADDR_MASK     (0x7 << 12)
+#define NFC_CTRL_CADDR_1        (0x0 << 12)
+#define NFC_CTRL_CADDR_2        (0x1 << 12)
+#define NFC_CTRL_CADDR_3        (0x2 << 12)
+#define NFC_CTRL_CADDR_4        (0x3 << 12)
+#define NFC_CTRL_CADDR_5        (0x4 << 12)
+#define NFC_CTRL_MSK            (1 << 15)
+#define NFC_CTRL_PSIZE256       (0 << 16)
+#define NFC_CTRL_PSIZE512       (1 << 16)
+#define NFC_CTRL_PSIZE1024      (2 << 16)
+#define NFC_CTRL_PSIZE2048      (3 << 16)
+#define NFC_CTRL_PSIZE4096      (4 << 16)
+#define NFC_CTRL_PSIZE_MASK     (7 << 16)
+#define NFC_CTRL_BSIZE1         (0 << 19)
+#define NFC_CTRL_BSIZE2         (1 << 19)
+#define NFC_CTRL_BSIZE4         (2 << 19)
+#define NFC_CTRL_BSIZE8         (3 << 19)
+#define NFC_CTRL_BSIZE_MASK     (3 << 19)
+#define NFC_CTRL_RDY            (1 << 21)
+#define NFC_CTRL_CS0SEL         (1 << 22)
+#define NFC_CTRL_CS1SEL         (1 << 23)
+#define NFC_CTRL_CS2SEL         (1 << 24)
+#define NFC_CTRL_CS3SEL         (1 << 25)
+#define NFC_CTRL_CSMASK         (0xf << 22)
+#define NFC_CTRL_BW             (1 << 26)
+#define NFC_CTRL_FS             (1 << 27)
+#define NFC_CTRL_DEN            (1 << 28)
+#define NFC_CTRL_READ_IEN       (1 << 29)
+#define NFC_CTRL_PROG_IEN       (1 << 30)
+#define NFC_CTRL_RDY_IEN        (1 << 31)
+
+/* Bits in NFC_IREQ */
+#define NFC_IREQ_IRQ0           (1 << 0)
+#define NFC_IREQ_IRQ1           (1 << 1)
+#define NFC_IREQ_IRQ2           (1 << 2)
+
+#define NFC_IREQ_FLAG0          (1 << 4)
+#define NFC_IREQ_FLAG1          (1 << 5)
+#define NFC_IREQ_FLAG2          (1 << 6)
+
+/* MMC controller registers */
+#define MMC0_BASE       (AHB_PERI_BASE_VIRT + 0xe000)
+#define MMC1_BASE       (AHB_PERI_BASE_VIRT + 0xe800)
+
+/* UART base addresses */
+
+#define UART0_BASE      (APB0_PERI_BASE_VIRT + 0x07000)
+#define UART0_BASE_PHYS (APB0_PERI_BASE + 0x07000)
+#define UART1_BASE      (APB0_PERI_BASE_VIRT + 0x08000)
+#define UART1_BASE_PHYS (APB0_PERI_BASE + 0x08000)
+#define UART2_BASE      (APB0_PERI_BASE_VIRT + 0x09000)
+#define UART2_BASE_PHYS (APB0_PERI_BASE + 0x09000)
+#define UART3_BASE      (APB0_PERI_BASE_VIRT + 0x0a000)
+#define UART3_BASE_PHYS (APB0_PERI_BASE + 0x0a000)
+#define UART4_BASE      (APB0_PERI_BASE_VIRT + 0x15000)
+#define UART4_BASE_PHYS (APB0_PERI_BASE + 0x15000)
+
+#define UART_BASE       UART0_BASE
+#define UART_BASE_PHYS  UART0_BASE_PHYS
+
+/* ECC controller */
+#define ECC_CTR_BASE    (APB0_PERI_BASE_VIRT + 0xd000)
+
+#define ECC_CTRL_OFFS           0x00
+#define ECC_BASE_OFFS           0x04
+#define ECC_MASK_OFFS           0x08
+#define ECC_CLEAR_OFFS          0x0c
+#define ECC4_0_OFFS             0x10
+#define ECC4_1_OFFS             0x14
+
+#define ECC_EADDR0_OFFS         0x50
+
+#define ECC_ERRNUM_OFFS         0x90
+#define ECC_IREQ_OFFS           0x94
+
+/* Bits in ECC_CTRL */
+#define ECC_CTRL_ECC4_DIEN      (1 << 28)
+#define ECC_CTRL_ECC8_DIEN      (1 << 29)
+#define ECC_CTRL_ECC12_DIEN     (1 << 30)
+#define ECC_CTRL_ECC_DISABLE    0x0
+#define ECC_CTRL_ECC_SLC_ENC    0x8
+#define ECC_CTRL_ECC_SLC_DEC    0x9
+#define ECC_CTRL_ECC4_ENC       0xa
+#define ECC_CTRL_ECC4_DEC       0xb
+#define ECC_CTRL_ECC8_ENC       0xc
+#define ECC_CTRL_ECC8_DEC       0xd
+#define ECC_CTRL_ECC12_ENC      0xe
+#define ECC_CTRL_ECC12_DEC      0xf
+
+/* Bits in ECC_IREQ */
+#define ECC_IREQ_E4DI           (1 << 4)
+
+#define ECC_IREQ_E4DF           (1 << 20)
+#define ECC_IREQ_E4EF           (1 << 21)
+
+/* Interrupt controller */
+
+#define PIC0_BASE       (APB1_PERI_BASE_VIRT + 0x3000)
+#define PIC0_BASE_PHYS  (APB1_PERI_BASE + 0x3000)
+
+#define PIC0_IEN_OFFS           0x00
+#define PIC0_CREQ_OFFS          0x04
+#define PIC0_IREQ_OFFS          0x08
+#define PIC0_IRQSEL_OFFS        0x0c
+#define PIC0_SRC_OFFS           0x10
+#define PIC0_MREQ_OFFS          0x14
+#define PIC0_TSTREQ_OFFS        0x18
+#define PIC0_POL_OFFS           0x1c
+#define PIC0_IRQ_OFFS           0x20
+#define PIC0_FIQ_OFFS           0x24
+#define PIC0_MIRQ_OFFS          0x28
+#define PIC0_MFIQ_OFFS          0x2c
+#define PIC0_TMODE_OFFS         0x30
+#define PIC0_SYNC_OFFS          0x34
+#define PIC0_WKUP_OFFS          0x38
+#define PIC0_TMODEA_OFFS        0x3c
+#define PIC0_INTOEN_OFFS        0x40
+#define PIC0_MEN0_OFFS          0x44
+#define PIC0_MEN_OFFS           0x48
+
+#define PIC0_IEN                __REG(PIC0_BASE + PIC0_IEN_OFFS)
+#define PIC0_IEN_PHYS           __REG(PIC0_BASE_PHYS + PIC0_IEN_OFFS)
+#define PIC0_CREQ               __REG(PIC0_BASE + PIC0_CREQ_OFFS)
+#define PIC0_CREQ_PHYS          __REG(PIC0_BASE_PHYS + PIC0_CREQ_OFFS)
+#define PIC0_IREQ               __REG(PIC0_BASE + PIC0_IREQ_OFFS)
+#define PIC0_IRQSEL             __REG(PIC0_BASE + PIC0_IRQSEL_OFFS)
+#define PIC0_IRQSEL_PHYS        __REG(PIC0_BASE_PHYS + PIC0_IRQSEL_OFFS)
+#define PIC0_SRC                __REG(PIC0_BASE + PIC0_SRC_OFFS)
+#define PIC0_MREQ               __REG(PIC0_BASE + PIC0_MREQ_OFFS)
+#define PIC0_TSTREQ             __REG(PIC0_BASE + PIC0_TSTREQ_OFFS)
+#define PIC0_POL                __REG(PIC0_BASE + PIC0_POL_OFFS)
+#define PIC0_IRQ                __REG(PIC0_BASE + PIC0_IRQ_OFFS)
+#define PIC0_FIQ                __REG(PIC0_BASE + PIC0_FIQ_OFFS)
+#define PIC0_MIRQ               __REG(PIC0_BASE + PIC0_MIRQ_OFFS)
+#define PIC0_MFIQ               __REG(PIC0_BASE + PIC0_MFIQ_OFFS)
+#define PIC0_TMODE              __REG(PIC0_BASE + PIC0_TMODE_OFFS)
+#define PIC0_TMODE_PHYS         __REG(PIC0_BASE_PHYS + PIC0_TMODE_OFFS)
+#define PIC0_SYNC               __REG(PIC0_BASE + PIC0_SYNC_OFFS)
+#define PIC0_WKUP               __REG(PIC0_BASE + PIC0_WKUP_OFFS)
+#define PIC0_TMODEA             __REG(PIC0_BASE + PIC0_TMODEA_OFFS)
+#define PIC0_INTOEN             __REG(PIC0_BASE + PIC0_INTOEN_OFFS)
+#define PIC0_MEN0               __REG(PIC0_BASE + PIC0_MEN0_OFFS)
+#define PIC0_MEN                __REG(PIC0_BASE + PIC0_MEN_OFFS)
+
+#define PIC1_BASE       (APB1_PERI_BASE_VIRT + 0x3080)
+
+#define PIC1_IEN_OFFS           0x00
+#define PIC1_CREQ_OFFS          0x04
+#define PIC1_IREQ_OFFS          0x08
+#define PIC1_IRQSEL_OFFS        0x0c
+#define PIC1_SRC_OFFS           0x10
+#define PIC1_MREQ_OFFS          0x14
+#define PIC1_TSTREQ_OFFS        0x18
+#define PIC1_POL_OFFS           0x1c
+#define PIC1_IRQ_OFFS           0x20
+#define PIC1_FIQ_OFFS           0x24
+#define PIC1_MIRQ_OFFS          0x28
+#define PIC1_MFIQ_OFFS          0x2c
+#define PIC1_TMODE_OFFS         0x30
+#define PIC1_SYNC_OFFS          0x34
+#define PIC1_WKUP_OFFS          0x38
+#define PIC1_TMODEA_OFFS        0x3c
+#define PIC1_INTOEN_OFFS        0x40
+#define PIC1_MEN1_OFFS          0x44
+#define PIC1_MEN_OFFS           0x48
+
+#define PIC1_IEN        __REG(PIC1_BASE + PIC1_IEN_OFFS)
+#define PIC1_CREQ       __REG(PIC1_BASE + PIC1_CREQ_OFFS)
+#define PIC1_IREQ       __REG(PIC1_BASE + PIC1_IREQ_OFFS)
+#define PIC1_IRQSEL     __REG(PIC1_BASE + PIC1_IRQSEL_OFFS)
+#define PIC1_SRC        __REG(PIC1_BASE + PIC1_SRC_OFFS)
+#define PIC1_MREQ       __REG(PIC1_BASE + PIC1_MREQ_OFFS)
+#define PIC1_TSTREQ     __REG(PIC1_BASE + PIC1_TSTREQ_OFFS)
+#define PIC1_POL        __REG(PIC1_BASE + PIC1_POL_OFFS)
+#define PIC1_IRQ        __REG(PIC1_BASE + PIC1_IRQ_OFFS)
+#define PIC1_FIQ        __REG(PIC1_BASE + PIC1_FIQ_OFFS)
+#define PIC1_MIRQ       __REG(PIC1_BASE + PIC1_MIRQ_OFFS)
+#define PIC1_MFIQ       __REG(PIC1_BASE + PIC1_MFIQ_OFFS)
+#define PIC1_TMODE      __REG(PIC1_BASE + PIC1_TMODE_OFFS)
+#define PIC1_SYNC       __REG(PIC1_BASE + PIC1_SYNC_OFFS)
+#define PIC1_WKUP       __REG(PIC1_BASE + PIC1_WKUP_OFFS)
+#define PIC1_TMODEA     __REG(PIC1_BASE + PIC1_TMODEA_OFFS)
+#define PIC1_INTOEN     __REG(PIC1_BASE + PIC1_INTOEN_OFFS)
+#define PIC1_MEN1       __REG(PIC1_BASE + PIC1_MEN1_OFFS)
+#define PIC1_MEN        __REG(PIC1_BASE + PIC1_MEN_OFFS)
+
+/* Timer registers */
+#define TIMER_BASE              (APB1_PERI_BASE_VIRT + 0x4000)
+#define TIMER_BASE_PHYS         (APB1_PERI_BASE + 0x4000)
+
+#define TWDCFG_OFFS             0x70
+
+#define TC32EN_OFFS             0x80
+#define TC32LDV_OFFS            0x84
+#define TC32CMP0_OFFS           0x88
+#define TC32CMP1_OFFS           0x8c
+#define TC32PCNT_OFFS           0x90
+#define TC32MCNT_OFFS           0x94
+#define TC32IRQ_OFFS            0x98
+
+/* Bits in TC32EN */
+#define TC32EN_PRESCALE_MASK    0x00ffffff
+#define TC32EN_ENABLE           (1 << 24)
+#define TC32EN_LOADZERO         (1 << 25)
+#define TC32EN_STOPMODE         (1 << 26)
+#define TC32EN_LDM0             (1 << 28)
+#define TC32EN_LDM1             (1 << 29)
+
+/* Bits in TC32IRQ */
+#define TC32IRQ_MSTAT_MASK      0x0000001f
+#define TC32IRQ_RSTAT_MASK      (0x1f << 8)
+#define TC32IRQ_IRQEN0          (1 << 16)
+#define TC32IRQ_IRQEN1          (1 << 17)
+#define TC32IRQ_IRQEN2          (1 << 18)
+#define TC32IRQ_IRQEN3          (1 << 19)
+#define TC32IRQ_IRQEN4          (1 << 20)
+#define TC32IRQ_RSYNC           (1 << 30)
+#define TC32IRQ_IRQCLR          (1 << 31)
+
+/* GPIO registers */
+#define GPIOPD_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOPD_DAT_OFFS         0x00
+#define GPIOPD_DOE_OFFS         0x04
+#define GPIOPD_FS0_OFFS         0x08
+#define GPIOPD_FS1_OFFS         0x0c
+#define GPIOPD_FS2_OFFS         0x10
+#define GPIOPD_RPU_OFFS         0x30
+#define GPIOPD_RPD_OFFS         0x34
+#define GPIOPD_DV0_OFFS         0x38
+#define GPIOPD_DV1_OFFS         0x3c
+
+#define GPIOPS_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOPS_DAT_OFFS         0x40
+#define GPIOPS_DOE_OFFS         0x44
+#define GPIOPS_FS0_OFFS         0x48
+#define GPIOPS_FS1_OFFS         0x4c
+#define GPIOPS_FS2_OFFS         0x50
+#define GPIOPS_FS3_OFFS         0x54
+#define GPIOPS_RPU_OFFS         0x70
+#define GPIOPS_RPD_OFFS         0x74
+#define GPIOPS_DV0_OFFS         0x78
+#define GPIOPS_DV1_OFFS         0x7c
+
+#define GPIOPS_FS1_SDH0_BITS    0x000000ff
+#define GPIOPS_FS1_SDH1_BITS    0x0000ff00
+
+#define GPIOPU_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOPU_DAT_OFFS         0x80
+#define GPIOPU_DOE_OFFS         0x84
+#define GPIOPU_FS0_OFFS         0x88
+#define GPIOPU_FS1_OFFS         0x8c
+#define GPIOPU_FS2_OFFS         0x90
+#define GPIOPU_RPU_OFFS         0xb0
+#define GPIOPU_RPD_OFFS         0xb4
+#define GPIOPU_DV0_OFFS         0xb8
+#define GPIOPU_DV1_OFFS         0xbc
+
+#define GPIOPU_FS0_TXD0         (1 << 0)
+#define GPIOPU_FS0_RXD0         (1 << 1)
+#define GPIOPU_FS0_CTS0         (1 << 2)
+#define GPIOPU_FS0_RTS0         (1 << 3)
+#define GPIOPU_FS0_TXD1         (1 << 4)
+#define GPIOPU_FS0_RXD1         (1 << 5)
+#define GPIOPU_FS0_CTS1         (1 << 6)
+#define GPIOPU_FS0_RTS1         (1 << 7)
+#define GPIOPU_FS0_TXD2         (1 << 8)
+#define GPIOPU_FS0_RXD2         (1 << 9)
+#define GPIOPU_FS0_CTS2         (1 << 10)
+#define GPIOPU_FS0_RTS2         (1 << 11)
+#define GPIOPU_FS0_TXD3         (1 << 12)
+#define GPIOPU_FS0_RXD3         (1 << 13)
+#define GPIOPU_FS0_CTS3         (1 << 14)
+#define GPIOPU_FS0_RTS3         (1 << 15)
+#define GPIOPU_FS0_TXD4         (1 << 16)
+#define GPIOPU_FS0_RXD4         (1 << 17)
+#define GPIOPU_FS0_CTS4         (1 << 18)
+#define GPIOPU_FS0_RTS4         (1 << 19)
+
+#define GPIOFC_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOFC_DAT_OFFS         0xc0
+#define GPIOFC_DOE_OFFS         0xc4
+#define GPIOFC_FS0_OFFS         0xc8
+#define GPIOFC_FS1_OFFS         0xcc
+#define GPIOFC_FS2_OFFS         0xd0
+#define GPIOFC_FS3_OFFS         0xd4
+#define GPIOFC_RPU_OFFS         0xf0
+#define GPIOFC_RPD_OFFS         0xf4
+#define GPIOFC_DV0_OFFS         0xf8
+#define GPIOFC_DV1_OFFS         0xfc
+
+#define GPIOFD_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOFD_DAT_OFFS         0x100
+#define GPIOFD_DOE_OFFS         0x104
+#define GPIOFD_FS0_OFFS         0x108
+#define GPIOFD_FS1_OFFS         0x10c
+#define GPIOFD_FS2_OFFS         0x110
+#define GPIOFD_RPU_OFFS         0x130
+#define GPIOFD_RPD_OFFS         0x134
+#define GPIOFD_DV0_OFFS         0x138
+#define GPIOFD_DV1_OFFS         0x13c
+
+#define GPIOLC_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOLC_DAT_OFFS         0x140
+#define GPIOLC_DOE_OFFS         0x144
+#define GPIOLC_FS0_OFFS         0x148
+#define GPIOLC_FS1_OFFS         0x14c
+#define GPIOLC_RPU_OFFS         0x170
+#define GPIOLC_RPD_OFFS         0x174
+#define GPIOLC_DV0_OFFS         0x178
+#define GPIOLC_DV1_OFFS         0x17c
+
+#define GPIOLD_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOLD_DAT_OFFS         0x180
+#define GPIOLD_DOE_OFFS         0x184
+#define GPIOLD_FS0_OFFS         0x188
+#define GPIOLD_FS1_OFFS         0x18c
+#define GPIOLD_FS2_OFFS         0x190
+#define GPIOLD_RPU_OFFS         0x1b0
+#define GPIOLD_RPD_OFFS         0x1b4
+#define GPIOLD_DV0_OFFS         0x1b8
+#define GPIOLD_DV1_OFFS         0x1bc
+
+#define GPIOAD_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOAD_DAT_OFFS         0x1c0
+#define GPIOAD_DOE_OFFS         0x1c4
+#define GPIOAD_FS0_OFFS         0x1c8
+#define GPIOAD_RPU_OFFS         0x1f0
+#define GPIOAD_RPD_OFFS         0x1f4
+#define GPIOAD_DV0_OFFS         0x1f8
+#define GPIOAD_DV1_OFFS         0x1fc
+
+#define GPIOXC_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOXC_DAT_OFFS         0x200
+#define GPIOXC_DOE_OFFS         0x204
+#define GPIOXC_FS0_OFFS         0x208
+#define GPIOXC_RPU_OFFS         0x230
+#define GPIOXC_RPD_OFFS         0x234
+#define GPIOXC_DV0_OFFS         0x238
+#define GPIOXC_DV1_OFFS         0x23c
+
+#define GPIOXC_FS0              __REG(GPIOXC_BASE + GPIOXC_FS0_OFFS)
+
+#define GPIOXC_FS0_CS0          (1 << 26)
+#define GPIOXC_FS0_CS1          (1 << 27)
+
+#define GPIOXD_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOXD_DAT_OFFS         0x240
+#define GPIOXD_FS0_OFFS         0x248
+#define GPIOXD_RPU_OFFS         0x270
+#define GPIOXD_RPD_OFFS         0x274
+#define GPIOXD_DV0_OFFS         0x278
+#define GPIOXD_DV1_OFFS         0x27c
+
+#define GPIOPK_BASE             (APB1_PERI_BASE_VIRT + 0x1c000)
+
+#define GPIOPK_RST_OFFS         0x008
+#define GPIOPK_DAT_OFFS         0x100
+#define GPIOPK_DOE_OFFS         0x104
+#define GPIOPK_FS0_OFFS         0x108
+#define GPIOPK_FS1_OFFS         0x10c
+#define GPIOPK_FS2_OFFS         0x110
+#define GPIOPK_IRQST_OFFS       0x210
+#define GPIOPK_IRQEN_OFFS       0x214
+#define GPIOPK_IRQPOL_OFFS      0x218
+#define GPIOPK_IRQTM0_OFFS      0x21c
+#define GPIOPK_IRQTM1_OFFS      0x220
+#define GPIOPK_CTL_OFFS         0x22c
+
+#define PMGPIO_BASE             (APB1_PERI_BASE_VIRT + 0x10000)
+#define BACKUP_RAM_BASE         PMGPIO_BASE
+
+#define PMGPIO_DAT_OFFS         0x800
+#define PMGPIO_DOE_OFFS         0x804
+#define PMGPIO_FS0_OFFS         0x808
+#define PMGPIO_RPU_OFFS         0x810
+#define PMGPIO_RPD_OFFS         0x814
+#define PMGPIO_DV0_OFFS         0x818
+#define PMGPIO_DV1_OFFS         0x81c
+#define PMGPIO_EE0_OFFS         0x820
+#define PMGPIO_EE1_OFFS         0x824
+#define PMGPIO_CTL_OFFS         0x828
+#define PMGPIO_DI_OFFS          0x82c
+#define PMGPIO_STR_OFFS         0x830
+#define PMGPIO_STF_OFFS         0x834
+#define PMGPIO_POL_OFFS         0x838
+#define PMGPIO_APB_OFFS         0x800
+
+/* Clock controller registers */
+#define CKC_BASE        ((void __iomem *)(APB1_PERI_BASE_VIRT + 0x6000))
+
+#define CLKCTRL_OFFS            0x00
+#define PLL0CFG_OFFS            0x04
+#define PLL1CFG_OFFS            0x08
+#define CLKDIVC0_OFFS           0x0c
+
+#define BCLKCTR0_OFFS           0x14
+#define SWRESET0_OFFS           0x18
+
+#define BCLKCTR1_OFFS           0x60
+#define SWRESET1_OFFS           0x64
+#define PWDCTL_OFFS             0x68
+#define PLL2CFG_OFFS            0x6c
+#define CLKDIVC1_OFFS           0x70
+
+#define ACLKREF_OFFS            0x80
+#define ACLKI2C_OFFS            0x84
+#define ACLKSPI0_OFFS           0x88
+#define ACLKSPI1_OFFS           0x8c
+#define ACLKUART0_OFFS          0x90
+#define ACLKUART1_OFFS          0x94
+#define ACLKUART2_OFFS          0x98
+#define ACLKUART3_OFFS          0x9c
+#define ACLKUART4_OFFS          0xa0
+#define ACLKTCT_OFFS            0xa4
+#define ACLKTCX_OFFS            0xa8
+#define ACLKTCZ_OFFS            0xac
+#define ACLKADC_OFFS            0xb0
+#define ACLKDAI0_OFFS           0xb4
+#define ACLKDAI1_OFFS           0xb8
+#define ACLKLCD_OFFS            0xbc
+#define ACLKSPDIF_OFFS          0xc0
+#define ACLKUSBH_OFFS           0xc4
+#define ACLKSDH0_OFFS           0xc8
+#define ACLKSDH1_OFFS           0xcc
+#define ACLKC3DEC_OFFS          0xd0
+#define ACLKEXT_OFFS            0xd4
+#define ACLKCAN0_OFFS           0xd8
+#define ACLKCAN1_OFFS           0xdc
+#define ACLKGSB0_OFFS           0xe0
+#define ACLKGSB1_OFFS           0xe4
+#define ACLKGSB2_OFFS           0xe8
+#define ACLKGSB3_OFFS           0xec
+
+#define PLLxCFG_PD              (1 << 31)
+
+/* CLKCTRL bits */
+#define CLKCTRL_XE              (1 << 31)
+
+/* CLKDIVCx bits */
+#define CLKDIVC0_XTE            (1 << 7)
+#define CLKDIVC0_XE             (1 << 15)
+#define CLKDIVC0_P1E            (1 << 23)
+#define CLKDIVC0_P0E            (1 << 31)
+
+#define CLKDIVC1_P2E            (1 << 7)
+
+/* BCLKCTR0 clock bits */
+#define BCLKCTR0_USBD           (1 << 4)
+#define BCLKCTR0_ECC            (1 << 9)
+#define BCLKCTR0_USBH0          (1 << 11)
+#define BCLKCTR0_NFC            (1 << 16)
+
+/* BCLKCTR1 clock bits */
+#define BCLKCTR1_USBH1          (1 << 20)
+
+/* SWRESET0 bits */
+#define SWRESET0_USBD           (1 << 4)
+#define SWRESET0_USBH0          (1 << 11)
+
+/* SWRESET1 bits */
+#define SWRESET1_USBH1          (1 << 20)
+
+/* System clock sources.
+ * Note: These are the clock sources that serve as parents for
+ * all other clocks. They have no parents themselves.
+ *
+ * These values are used for struct clk->root_id. All clocks
+ * that are not system clock sources have this value set to
+ * CLK_SRC_NOROOT.
+ * The values for system clocks start with CLK_SRC_PLL0 == 0
+ * because this gives us exactly the values needed for the lower
+ * 4 bits of ACLK_* registers. Therefore, CLK_SRC_NOROOT is
+ * defined as -1 to not disturb the order.
+ */
+enum root_clks {
+        CLK_SRC_NOROOT = -1,
+        CLK_SRC_PLL0 = 0,
+        CLK_SRC_PLL1,
+        CLK_SRC_PLL0DIV,
+        CLK_SRC_PLL1DIV,
+        CLK_SRC_XI,
+        CLK_SRC_XIDIV,
+        CLK_SRC_XTI,
+        CLK_SRC_XTIDIV,
+        CLK_SRC_PLL2,
+        CLK_SRC_PLL2DIV,
+        CLK_SRC_PK0,
+        CLK_SRC_PK1,
+        CLK_SRC_PK2,
+        CLK_SRC_PK3,
+        CLK_SRC_PK4,
+        CLK_SRC_48MHZ
+};
+
+#define CLK_SRC_MASK            0xf
+
+/* Bits in ACLK* registers */
+#define ACLK_EN         (1 << 28)
+#define ACLK_SEL_SHIFT          24
+#define ACLK_SEL_MASK           0x0f000000
+#define ACLK_DIV_MASK           0x00000fff
+
+/* System configuration registers */
+
+#define SCFG_BASE               (APB1_PERI_BASE_VIRT + 0x13000)
+
+#define BMI_OFFS                0x00
+#define AHBCON0_OFFS            0x04
+#define APBPWE_OFFS             0x08
+#define DTCMWAIT_OFFS           0x0c
+#define ECCSEL_OFFS             0x10
+#define AHBCON1_OFFS            0x14
+#define SDHCFG_OFFS             0x18
+#define REMAP_OFFS              0x20
+#define LCDSIAE_OFFS            0x24
+#define XMCCFG_OFFS             0xe0
+#define IMCCFG_OFFS             0xe4
+
+/* Values for ECCSEL */
+#define ECCSEL_EXTMEM           0x0
+#define ECCSEL_DTCM             0x1
+#define ECCSEL_INT_SRAM         0x2
+#define ECCSEL_AHB              0x3
+
+/* Bits in XMCCFG */
+#define XMCCFG_NFCE             (1 << 1)
+#define XMCCFG_FDXD             (1 << 2)
+
+/* External memory controller registers */
+
+#define EMC_BASE                EXT_MEM_CTRL_BASE
+
+#define SDCFG_OFFS              0x00
+#define SDFSM_OFFS              0x04
+#define MCFG_OFFS               0x08
+
+#define CSCFG0_OFFS             0x10
+#define CSCFG1_OFFS             0x14
+#define CSCFG2_OFFS             0x18
+#define CSCFG3_OFFS             0x1c
+
+#define MCFG_SDEN               (1 << 4)
+
+#endif /* TCC8K_REGS_H */
diff --git a/arch/arm/plat-tcc/include/mach/timex.h b/arch/arm/plat-tcc/include/mach/timex.h
new file mode 100644
index 000000000000..057acbe651d9
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/timex.h
@@ -0,0 +1,5 @@
+/*
+ * A definition needed by arch core code.
+ *
+ */
+#define CLOCK_TICK_RATE         (HZ * 100000UL)
diff --git a/arch/arm/plat-tcc/include/mach/uncompress.h b/arch/arm/plat-tcc/include/mach/uncompress.h
new file mode 100644
index 000000000000..7a3e33a27a30
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/uncompress.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * This file is licensed under the terms of the GPL version 2.
+ */
+
+#include <linux/serial_reg.h>
+#include <linux/types.h>
+
+#include <mach/tcc8k-regs.h>
+
+unsigned int system_rev;
+
+#define ID_MASK                 0x7fff
+
+static void putc(int c)
+{
+        u32 *uart_lsr = (u32 *)(UART_BASE_PHYS + (UART_LSR << 2));
+        u32 *uart_tx = (u32 *)(UART_BASE_PHYS + (UART_TX << 2));
+
+        while (!(*uart_lsr & UART_LSR_THRE))
+                barrier();
+        *uart_tx = c;
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/plat-tcc/include/mach/vmalloc.h b/arch/arm/plat-tcc/include/mach/vmalloc.h
new file mode 100644
index 000000000000..99414d9c2b94
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/vmalloc.h
@@ -0,0 +1,10 @@
+/*
+ * Author: <linux@telechips.com>
+ * Created: June 10, 2008
+ *
+ * Copyright (C) 2000 Russell King.
+ * Copyright (C) 2008-2009 Telechips
+ *
+ * Licensed under the terms of the GPL v2.
+ */
+#define VMALLOC_END     0xf0000000UL
diff --git a/arch/arm/plat-tcc/system.c b/arch/arm/plat-tcc/system.c
new file mode 100644
index 000000000000..cc208fae3e7a
--- /dev/null
+++ b/arch/arm/plat-tcc/system.c
@@ -0,0 +1,25 @@
+/*
+ * System functions for Telechips TCCxxxx SoCs
+ *
+ * Copyright (C) Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPL v2.
+ *
+ */
+
+#include <linux/io.h>
+
+#include <mach/tcc8k-regs.h>
+
+/* System reboot */
+void plat_tcc_reboot(void)
+{
+        /* Make sure clocks are on */
+        __raw_writel(0xffffffff, CKC_BASE + BCLKCTR0_OFFS);
+
+        /* Enable watchdog reset */
+        __raw_writel(0x49, TIMER_BASE + TWDCFG_OFFS);
+        /* Wait for reset */
+        while(1)
+                ;
+}
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index f51572772e21..9ac87255a03a 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -90,6 +90,7 @@ config PLATFORM_AT32AP
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_ALLOCATOR
         select HAVE_FB_ATMEL
+        select HAVE_NET_MACB
 
 #
 # CPU types
diff --git a/arch/avr32/kernel/module.c b/arch/avr32/kernel/module.c
index 98f94d041d9c..a727f54d64d6 100644
--- a/arch/avr32/kernel/module.c
+++ b/arch/avr32/kernel/module.c
@@ -314,10 +314,9 @@ int module_finalize(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs,
         vfree(module->arch.syminfo);
         module->arch.syminfo = NULL;
 
-        return module_bug_finalize(hdr, sechdrs, module);
+        return 0;
 }
 
 void module_arch_cleanup(struct module *module)
 {
-        module_bug_cleanup(module);
 }
diff --git a/arch/h8300/kernel/module.c b/arch/h8300/kernel/module.c
index 0865e291c20d..db4953dc4e1b 100644
--- a/arch/h8300/kernel/module.c
+++ b/arch/h8300/kernel/module.c
@@ -112,10 +112,9 @@ int module_finalize(const Elf_Ehdr *hdr,
                     const Elf_Shdr *sechdrs,
                     struct module *me)
 {
-        return module_bug_finalize(hdr, sechdrs, me);
+        return 0;
 }
 
 void module_arch_cleanup(struct module *mod)
 {
-        module_bug_cleanup(mod);
 }
diff --git a/arch/m32r/include/asm/signal.h b/arch/m32r/include/asm/signal.h
index 9c1acb2b1a92..b2eeb0de1c8d 100644
--- a/arch/m32r/include/asm/signal.h
+++ b/arch/m32r/include/asm/signal.h
@@ -157,7 +157,6 @@ typedef struct sigaltstack {
 #undef __HAVE_ARCH_SIG_BITOPS
 
 struct pt_regs;
-extern int do_signal(struct pt_regs *regs, sigset_t *oldset);
 
 #define ptrace_signal_deliver(regs, cookie)     do { } while (0)
 
diff --git a/arch/m32r/include/asm/unistd.h b/arch/m32r/include/asm/unistd.h
index 76125777483c..c70545689da8 100644
--- a/arch/m32r/include/asm/unistd.h
+++ b/arch/m32r/include/asm/unistd.h
@@ -351,6 +351,7 @@
 #define __ARCH_WANT_SYS_OLD_GETRLIMIT /*will be unused*/
 #define __ARCH_WANT_SYS_OLDUMOUNT
 #define __ARCH_WANT_SYS_RT_SIGACTION
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
 
 #define __IGNORE_lchown
 #define __IGNORE_setuid
diff --git a/arch/m32r/kernel/entry.S b/arch/m32r/kernel/entry.S
index 403869833b98..225412bc227e 100644
--- a/arch/m32r/kernel/entry.S
+++ b/arch/m32r/kernel/entry.S
@@ -235,10 +235,9 @@ work_resched:
 work_notifysig:                         ; deal with pending signals and
                                         ; notify-resume requests
         mv      r0, sp                  ; arg1 : struct pt_regs *regs
-        ldi     r1, #0                  ; arg2 : sigset_t *oldset
-        mv      r2, r9                  ; arg3 : __u32 thread_info_flags
+        mv      r1, r9                  ; arg2 : __u32 thread_info_flags
         bl      do_notify_resume
-        bra     restore_all
+        bra     resume_userspace
 
         ; perform syscall exit tracing
         ALIGN
diff --git a/arch/m32r/kernel/ptrace.c b/arch/m32r/kernel/ptrace.c
index e555091eb97c..0021ade4cba8 100644
--- a/arch/m32r/kernel/ptrace.c
+++ b/arch/m32r/kernel/ptrace.c
@@ -592,16 +592,17 @@ void user_enable_single_step(struct task_struct *child)
 
         if (access_process_vm(child, pc&~3, &insn, sizeof(insn), 0)
             != sizeof(insn))
-                break;
+                return -EIO;
 
         compute_next_pc(insn, pc, &next_pc, child);
         if (next_pc & 0x80000000)
-                break;
+                return -EIO;
 
         if (embed_debug_trap(child, next_pc))
-                break;
+                return -EIO;
 
         invalidate_cache();
+        return 0;
 }
 
 void user_disable_single_step(struct task_struct *child)
diff --git a/arch/m32r/kernel/signal.c b/arch/m32r/kernel/signal.c
index 144b0f124fc7..7bbe38645ed5 100644
--- a/arch/m32r/kernel/signal.c
+++ b/arch/m32r/kernel/signal.c
@@ -28,37 +28,6 @@
 
 #define DEBUG_SIG 0
 
-#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
-
-int do_signal(struct pt_regs *, sigset_t *);
-
-asmlinkage int
-sys_rt_sigsuspend(sigset_t __user *unewset, size_t sigsetsize,
-                  unsigned long r2, unsigned long r3, unsigned long r4,
-                  unsigned long r5, unsigned long r6, struct pt_regs *regs)
-{
-        sigset_t newset;
-
-        /* XXX: Don't preclude handling different sized sigset_t's.  */
-        if (sigsetsize != sizeof(sigset_t))
-                return -EINVAL;
-
-        if (copy_from_user(&newset, unewset, sizeof(newset)))
-                return -EFAULT;
-        sigdelsetmask(&newset, sigmask(SIGKILL)|sigmask(SIGSTOP));
-
-        spin_lock_irq(&current->sighand->siglock);
-        current->saved_sigmask = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
-
-        current->state = TASK_INTERRUPTIBLE;
-        schedule();
-        set_thread_flag(TIF_RESTORE_SIGMASK);
-        return -ERESTARTNOHAND;
-}
-
 asmlinkage int
 sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss,
                 unsigned long r2, unsigned long r3, unsigned long r4,
@@ -218,7 +187,7 @@ get_sigframe(struct k_sigaction *ka, unsigned long sp, size_t frame_size)
         return (void __user *)((sp - frame_size) & -8ul);
 }
 
-static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
+static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
                            sigset_t *set, struct pt_regs *regs)
 {
         struct rt_sigframe __user *frame;
@@ -275,22 +244,34 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
                 current->comm, current->pid, frame, regs->pc);
 #endif
 
-        return;
+        return 0;
 
 give_sigsegv:
         force_sigsegv(sig, current);
+        return -EFAULT;
+}
+
+static int prev_insn(struct pt_regs *regs)
+{
+        u16 inst;
+        if (get_user(&inst, (u16 __user *)(regs->bpc - 2)))
+                return -EFAULT;
+        if ((inst & 0xfff0) == 0x10f0)  /* trap ? */
+                regs->bpc -= 2;
+        else
+                regs->bpc -= 4;
+        regs->syscall_nr = -1;
+        return 0;
 }
 
 /*
  * OK, we're invoking a handler
  */
 
-static void
+static int
 handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info,
               sigset_t *oldset, struct pt_regs *regs)
 {
-        unsigned short inst;
-
         /* Are we from a system call? */
         if (regs->syscall_nr >= 0) {
                 /* If so, check system call restarting.. */
@@ -308,16 +289,14 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info,
                         /* fallthrough */
                         case -ERESTARTNOINTR:
                                 regs->r0 = regs->orig_r0;
-                                inst = *(unsigned short *)(regs->bpc - 2);
-                                if ((inst & 0xfff0) == 0x10f0)  /* trap ? */
-                                        regs->bpc -= 2;
-                                else
-                                        regs->bpc -= 4;
+                                if (prev_insn(regs) < 0)
+                                        return -EFAULT;
                 }
         }
 
         /* Set up the stack frame */
-        setup_rt_frame(sig, ka, info, oldset, regs);
+        if (setup_rt_frame(sig, ka, info, oldset, regs))
+                return -EFAULT;
 
         spin_lock_irq(&current->sighand->siglock);
         sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
@@ -325,6 +304,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info,
                 sigaddset(&current->blocked,sig);
         recalc_sigpending();
         spin_unlock_irq(&current->sighand->siglock);
+        return 0;
 }
 
 /*
@@ -332,12 +312,12 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info,
  * want to handle. Thus you cannot kill init even with a SIGKILL even by
  * mistake.
  */
-int do_signal(struct pt_regs *regs, sigset_t *oldset)
+static void do_signal(struct pt_regs *regs)
 {
         siginfo_t info;
         int signr;
         struct k_sigaction ka;
-        unsigned short inst;
+        sigset_t *oldset;
 
         /*
          * We want the common case to go fast, which
@@ -346,12 +326,14 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset)
          * if so.
          */
         if (!user_mode(regs))
-                return 1;
+                return;
 
         if (try_to_freeze()) 
                 goto no_signal;
 
-        if (!oldset)
+        if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                oldset = &current->saved_sigmask;
+        else
                 oldset = &current->blocked;
 
         signr = get_signal_to_deliver(&info, &ka, regs, NULL);
@@ -363,8 +345,10 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset)
                  */
 
                 /* Whee!  Actually deliver the signal.  */
-                handle_signal(signr, &ka, &info, oldset, regs);
-                return 1;
+                if (handle_signal(signr, &ka, &info, oldset, regs) == 0)
+                        clear_thread_flag(TIF_RESTORE_SIGMASK);
+
+                return;
         }
 
  no_signal:
@@ -375,31 +359,24 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset)
                     regs->r0 == -ERESTARTSYS ||
                     regs->r0 == -ERESTARTNOINTR) {
                         regs->r0 = regs->orig_r0;
-                        inst = *(unsigned short *)(regs->bpc - 2);
-                        if ((inst & 0xfff0) == 0x10f0)  /* trap ? */
-                                regs->bpc -= 2;
-                        else
-                                regs->bpc -= 4;
-                }
-                if (regs->r0 == -ERESTART_RESTARTBLOCK){
+                        prev_insn(regs);
+                } else if (regs->r0 == -ERESTART_RESTARTBLOCK){
                         regs->r0 = regs->orig_r0;
                         regs->r7 = __NR_restart_syscall;
-                        inst = *(unsigned short *)(regs->bpc - 2);
-                        if ((inst & 0xfff0) == 0x10f0)  /* trap ? */
-                                regs->bpc -= 2;
-                        else
-                                regs->bpc -= 4;
+                        prev_insn(regs);
                 }
         }
-        return 0;
+        if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
+                clear_thread_flag(TIF_RESTORE_SIGMASK);
+                sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
+        }
 }
 
 /*
  * notification of userspace execution resumption
  * - triggered by current->work.notify_resume
  */
-void do_notify_resume(struct pt_regs *regs, sigset_t *oldset,
-                      __u32 thread_info_flags)
+void do_notify_resume(struct pt_regs *regs, __u32 thread_info_flags)
 {
         /* Pending single-step? */
         if (thread_info_flags & _TIF_SINGLESTEP)
@@ -407,7 +384,7 @@ void do_notify_resume(struct pt_regs *regs, sigset_t *oldset,
 
         /* deal with pending signal delivery */
         if (thread_info_flags & _TIF_SIGPENDING)
-                do_signal(regs,oldset);
+                do_signal(regs);
 
         if (thread_info_flags & _TIF_NOTIFY_RESUME) {
                 clear_thread_flag(TIF_NOTIFY_RESUME);
diff --git a/arch/m68k/mac/macboing.c b/arch/m68k/mac/macboing.c
index 8f0640847ad2..05285d08e547 100644
--- a/arch/m68k/mac/macboing.c
+++ b/arch/m68k/mac/macboing.c
@@ -162,7 +162,7 @@ static void mac_init_asc( void )
 void mac_mksound( unsigned int freq, unsigned int length )
 {
         __u32 cfreq = ( freq << 5 ) / 468;
-        __u32 flags;
+        unsigned long flags;
         int i;
 
         if ( mac_special_bell == NULL )
@@ -224,7 +224,7 @@ static void mac_nosound( unsigned long ignored )
  */
 static void mac_quadra_start_bell( unsigned int freq, unsigned int length, unsigned int volume )
 {
-        __u32 flags;
+        unsigned long flags;
 
         /* if the bell is already ringing, ring longer */
         if ( mac_bell_duration > 0 )
@@ -271,7 +271,7 @@ static void mac_quadra_start_bell( unsigned int freq, unsigned int length, unsig
 static void mac_quadra_ring_bell( unsigned long ignored )
 {
         int     i, count = mac_asc_samplespersec / HZ;
-        __u32 flags;
+        unsigned long flags;
 
         /*
          * we neither want a sound buffer overflow nor underflow, so we need to match
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3ad59dde4852..5526faabfc21 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -13,6 +13,7 @@ config MIPS
         select HAVE_KPROBES
         select HAVE_KRETPROBES
         select RTC_LIB if !MACH_LOONGSON
+        select GENERIC_ATOMIC64 if !64BIT
 
 mainmenu "Linux/MIPS Kernel Configuration"
 
@@ -1646,8 +1647,16 @@ config MIPS_MT_SMP
         select SYS_SUPPORTS_SMP
         select SMP_UP
         help
-          This is a kernel model which is also known a VSMP or lately
-          has been marketesed into SMVP.
+          This is a kernel model which is known a VSMP but lately has been
+          marketesed into SMVP.
+          Virtual SMP uses the processor's VPEs  to implement virtual
+          processors. In currently available configuration of the 34K processor
+          this allows for a dual processor. Both processors will share the same
+          primary caches; each will obtain the half of the TLB for it's own
+          exclusive use. For a layman this model can be described as similar to
+          what Intel calls Hyperthreading.
+
+          For further information see http://www.linux-mips.org/wiki/34K#VSMP
 
 config MIPS_MT_SMTC
         bool "SMTC: Use all TCs on all VPEs for SMP"
@@ -1664,6 +1673,14 @@ config MIPS_MT_SMTC
         help
           This is a kernel model which is known a SMTC or lately has been
           marketesed into SMVP.
+          is presenting the available TC's of the core as processors to Linux.
+          On currently available 34K processors this means a Linux system will
+          see up to 5 processors. The implementation of the SMTC kernel differs
+          significantly from VSMP and cannot efficiently coexist in the same
+          kernel binary so the choice between VSMP and SMTC is a compile time
+          decision.
+
+          For further information see http://www.linux-mips.org/wiki/34K#SMTC
 
 endchoice
 
diff --git a/arch/mips/alchemy/common/prom.c b/arch/mips/alchemy/common/prom.c
index c29511b11d44..534021059629 100644
--- a/arch/mips/alchemy/common/prom.c
+++ b/arch/mips/alchemy/common/prom.c
@@ -43,7 +43,7 @@ int prom_argc;
 char **prom_argv;
 char **prom_envp;
 
-void prom_init_cmdline(void)
+void __init prom_init_cmdline(void)
 {
         int i;
 
@@ -104,7 +104,7 @@ static inline void str2eaddr(unsigned char *ea, unsigned char *str)
         }
 }
 
-int prom_get_ethernet_addr(char *ethernet_addr)
+int __init prom_get_ethernet_addr(char *ethernet_addr)
 {
         char *ethaddr_str;
 
@@ -123,7 +123,6 @@ int prom_get_ethernet_addr(char *ethernet_addr)
 
         return 0;
 }
-EXPORT_SYMBOL(prom_get_ethernet_addr);
 
 void __init prom_free_prom_memory(void)
 {
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index ed9bb709c9a3..5fd7f7a58b7e 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -59,7 +59,7 @@ $(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE
 hostprogs-y := calc_vmlinuz_load_addr
 
 VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
-                $(objtree)/$(KBUILD_IMAGE) $(VMLINUX_LOAD_ADDRESS))
+                $(obj)/vmlinux.bin $(VMLINUX_LOAD_ADDRESS))
 
 vmlinuzobjs-y += $(obj)/piggy.o
 
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 094c17e38e16..47323ca452dc 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -83,3 +83,7 @@ config ARCH_SPARSEMEM_ENABLE
         def_bool y
         select SPARSEMEM_STATIC
         depends on CPU_CAVIUM_OCTEON
+
+config CAVIUM_OCTEON_HELPER
+        def_bool y
+        depends on OCTEON_ETHERNET || PCI
diff --git a/arch/mips/cavium-octeon/cpu.c b/arch/mips/cavium-octeon/cpu.c
index c664c8cc2b42..a5b427909b5c 100644
--- a/arch/mips/cavium-octeon/cpu.c
+++ b/arch/mips/cavium-octeon/cpu.c
@@ -41,7 +41,7 @@ static int cnmips_cu2_call(struct notifier_block *nfb, unsigned long action,
         return NOTIFY_OK;               /* Let default notifier send signals */
 }
 
-static int cnmips_cu2_setup(void)
+static int __init cnmips_cu2_setup(void)
 {
         return cu2_notifier(cnmips_cu2_call, 0);
 }
diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile
index 2fd66db6939e..7f41c5be2190 100644
--- a/arch/mips/cavium-octeon/executive/Makefile
+++ b/arch/mips/cavium-octeon/executive/Makefile
@@ -11,4 +11,4 @@
 
 obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
 
-obj-$(CONFIG_PCI) += cvmx-helper-errata.o cvmx-helper-jtag.o
+obj-$(CONFIG_CAVIUM_OCTEON_HELPER) += cvmx-helper-errata.o cvmx-helper-jtag.o
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index c63c56bfd184..47d87da379f9 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -782,6 +782,10 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
  */
 #define atomic64_add_negative(i, v) (atomic64_add_return(i, (v)) < 0)
 
+#else /* !CONFIG_64BIT */
+
+#include <asm-generic/atomic64.h>
+
 #endif /* CONFIG_64BIT */
 
 /*
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index 2cb2f0c2c4f8..3532e2c5f098 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -24,7 +24,7 @@ extern int cu2_notifier_call_chain(unsigned long val, void *v);
 
 #define cu2_notifier(fn, pri)                                           \
 ({                                                                      \
-        static struct notifier_block fn##_nb __cpuinitdata = {          \
+        static struct notifier_block fn##_nb = {                        \
                 .notifier_call = fn,                                    \
                 .priority = pri                                         \
         };                                                              \
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index 9b9436a4d816..86548da650e7 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -321,6 +321,7 @@ struct gic_intrmask_regs {
  */
 struct gic_intr_map {
         unsigned int cpunum;    /* Directed to this CPU */
+#define GIC_UNUSED              0xdead                  /* Dummy data */
         unsigned int pin;       /* Directed to this Pin */
         unsigned int polarity;  /* Polarity : +/-       */
         unsigned int trigtype;  /* Trigger  : Edge/Levl */
diff --git a/arch/mips/include/asm/mach-tx49xx/kmalloc.h b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
index b74caf65482b..ff9a8b86cb93 100644
--- a/arch/mips/include/asm/mach-tx49xx/kmalloc.h
+++ b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
@@ -1,6 +1,6 @@
 #ifndef __ASM_MACH_TX49XX_KMALLOC_H
 #define __ASM_MACH_TX49XX_KMALLOC_H
 
-#define ARCH_KMALLOC_MINALIGN   L1_CACHE_BYTES
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
 
 #endif /* __ASM_MACH_TX49XX_KMALLOC_H */
diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h
index cea872fc6f5c..d11aa02a956a 100644
--- a/arch/mips/include/asm/mips-boards/maltaint.h
+++ b/arch/mips/include/asm/mips-boards/maltaint.h
@@ -88,9 +88,6 @@
 
 #define GIC_EXT_INTR(x)         x
 
-/* Dummy data */
-#define X                       0xdead
-
 /* External Interrupts used for IPI */
 #define GIC_IPI_EXT_INTR_RESCHED_VPE0   16
 #define GIC_IPI_EXT_INTR_CALLFNC_VPE0   17
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index a16beafcea91..e59cd1ac09c2 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -150,6 +150,20 @@ typedef struct { unsigned long pgprot; } pgprot_t;
     ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET)
 #endif
 #define __va(x)         ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
+
+/*
+ * RELOC_HIDE was originally added by 6007b903dfe5f1d13e0c711ac2894bdd4a61b1ad
+ * (lmo) rsp. 8431fd094d625b94d364fe393076ccef88e6ce18 (kernel.org).  The
+ * discussion can be found in lkml posting
+ * <a2ebde260608230500o3407b108hc03debb9da6e62c@mail.gmail.com> which is
+ * archived at http://lists.linuxcoding.com/kernel/2006-q3/msg17360.html
+ *
+ * It is unclear if the misscompilations mentioned in
+ * http://lkml.org/lkml/2010/8/8/138 also affect MIPS so we keep this one
+ * until GCC 3.x has been retired before we can apply
+ * https://patchwork.linux-mips.org/patch/1541/
+ */
+
 #define __pa_symbol(x)  __pa(RELOC_HIDE((unsigned long)(x), 0))
 
 #define pfn_to_kaddr(pfn)       __va((pfn) << PAGE_SHIFT)
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 2376f2e06e47..70df9c0d3c5b 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -146,7 +146,8 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define _TIF_LOAD_WATCH         (1<<TIF_LOAD_WATCH)
 
 /* work to do on interrupt/exception return */
-#define _TIF_WORK_MASK          (0x0000ffef & ~_TIF_SECCOMP)
+#define _TIF_WORK_MASK          (0x0000ffef &                           \
+                                        ~(_TIF_SECCOMP | _TIF_SYSCALL_AUDIT))
 /* work to do on any return to u-space */
 #define _TIF_ALLWORK_MASK       (0x8000ffff & ~_TIF_SECCOMP)
 
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index baa318a59c97..550725b881d5 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -356,16 +356,19 @@
 #define __NR_perf_event_open            (__NR_Linux + 333)
 #define __NR_accept4                    (__NR_Linux + 334)
 #define __NR_recvmmsg                   (__NR_Linux + 335)
+#define __NR_fanotify_init              (__NR_Linux + 336)
+#define __NR_fanotify_mark              (__NR_Linux + 337)
+#define __NR_prlimit64                  (__NR_Linux + 338)
 
 /*
  * Offset of the last Linux o32 flavoured syscall
  */
-#define __NR_Linux_syscalls             335
+#define __NR_Linux_syscalls             338
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 #define __NR_O32_Linux                  4000
-#define __NR_O32_Linux_syscalls         335
+#define __NR_O32_Linux_syscalls         338
 
 #if _MIPS_SIM == _MIPS_SIM_ABI64
 
@@ -668,16 +671,19 @@
 #define __NR_perf_event_open            (__NR_Linux + 292)
 #define __NR_accept4                    (__NR_Linux + 293)
 #define __NR_recvmmsg                   (__NR_Linux + 294)
+#define __NR_fanotify_init              (__NR_Linux + 295)
+#define __NR_fanotify_mark              (__NR_Linux + 296)
+#define __NR_prlimit64                  (__NR_Linux + 297)
 
 /*
  * Offset of the last Linux 64-bit flavoured syscall
  */
-#define __NR_Linux_syscalls             294
+#define __NR_Linux_syscalls             297
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
 
 #define __NR_64_Linux                   5000
-#define __NR_64_Linux_syscalls          294
+#define __NR_64_Linux_syscalls          297
 
 #if _MIPS_SIM == _MIPS_SIM_NABI32
 
@@ -985,16 +991,19 @@
 #define __NR_accept4                    (__NR_Linux + 297)
 #define __NR_recvmmsg                   (__NR_Linux + 298)
 #define __NR_getdents64                 (__NR_Linux + 299)
+#define __NR_fanotify_init              (__NR_Linux + 300)
+#define __NR_fanotify_mark              (__NR_Linux + 301)
+#define __NR_prlimit64                  (__NR_Linux + 302)
 
 /*
  * Offset of the last N32 flavoured syscall
  */
-#define __NR_Linux_syscalls             299
+#define __NR_Linux_syscalls             302
 
 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
 
 #define __NR_N32_Linux                  6000
-#define __NR_N32_Linux_syscalls         299
+#define __NR_N32_Linux_syscalls         302
 
 #ifdef __KERNEL__
 
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index b181f2f0ea8e..82ba9f62f49e 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -7,7 +7,6 @@
 #include <asm/io.h>
 #include <asm/gic.h>
 #include <asm/gcmpregs.h>
-#include <asm/mips-boards/maltaint.h>
 #include <asm/irq.h>
 #include <linux/hardirq.h>
 #include <asm-generic/bitops/find.h>
@@ -131,7 +130,7 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
         int             i;
 
         irq -= _irqbase;
-        pr_debug(KERN_DEBUG "%s(%d) called\n", __func__, irq);
+        pr_debug("%s(%d) called\n", __func__, irq);
         cpumask_and(&tmp, cpumask, cpu_online_mask);
         if (cpus_empty(tmp))
                 return -1;
@@ -222,7 +221,7 @@ static void __init gic_basic_init(int numintrs, int numvpes,
         /* Setup specifics */
         for (i = 0; i < mapsize; i++) {
                 cpu = intrmap[i].cpunum;
-                if (cpu == X)
+                if (cpu == GIC_UNUSED)
                         continue;
                 if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
                         continue;
diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c
index 1f4e2fa64140..f4546e97c60d 100644
--- a/arch/mips/kernel/kgdb.c
+++ b/arch/mips/kernel/kgdb.c
@@ -283,7 +283,7 @@ static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd,
         struct pt_regs *regs = args->regs;
         int trap = (regs->cp0_cause & 0x7c) >> 2;
 
-        /* Userpace events, ignore. */
+        /* Userspace events, ignore. */
         if (user_mode(regs))
                 return NOTIFY_DONE;
 
diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c
index 80e2ba694bab..29811f043399 100644
--- a/arch/mips/kernel/kspd.c
+++ b/arch/mips/kernel/kspd.c
@@ -251,7 +251,7 @@ void sp_work_handle_request(void)
                 memset(&tz, 0, sizeof(tz));
                 if ((ret.retval = sp_syscall(__NR_gettimeofday, (int)&tv,
                                              (int)&tz, 0, 0)) == 0)
-                ret.retval = tv.tv_sec;
+                        ret.retval = tv.tv_sec;
                 break;
 
         case MTSP_SYSCALL_EXIT:
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index c2dab140dc98..6343b4a5b835 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -341,3 +341,10 @@ asmlinkage long sys32_lookup_dcookie(u32 a0, u32 a1, char __user *buf,
 {
         return sys_lookup_dcookie(merge_64(a0, a1), buf, len);
 }
+
+SYSCALL_DEFINE6(32_fanotify_mark, int, fanotify_fd, unsigned int, flags,
+                u64, a3, u64, a4, int, dfd, const char  __user *, pathname)
+{
+        return sys_fanotify_mark(fanotify_fd, flags, merge_64(a3, a4),
+                                 dfd, pathname);
+}
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 17202bbe843f..584415eef8c9 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -583,7 +583,10 @@ einval:	li	v0, -ENOSYS
         sys     sys_rt_tgsigqueueinfo   4
         sys     sys_perf_event_open     5
         sys     sys_accept4             4
-        sys     sys_recvmmsg            5
+        sys     sys_recvmmsg            5       /* 4335 */
+        sys     sys_fanotify_init       2
+        sys     sys_fanotify_mark       6
+        sys     sys_prlimit64           4
         .endm
 
         /* We pre-compute the number of _instruction_ bytes needed to
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index a8a6c596eb04..5573f8e4e326 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -416,9 +416,12 @@ sys_call_table:
         PTR     sys_pipe2
         PTR     sys_inotify_init1
         PTR     sys_preadv
-        PTR     sys_pwritev                     /* 5390 */
+        PTR     sys_pwritev                     /* 5290 */
         PTR     sys_rt_tgsigqueueinfo
         PTR     sys_perf_event_open
         PTR     sys_accept4
-        PTR     sys_recvmmsg
+        PTR     sys_recvmmsg
+        PTR     sys_fanotify_init               /* 5295 */
+        PTR     sys_fanotify_mark
+        PTR     sys_prlimit64
         .size   sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index a3d66137731a..1e38ec97672e 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -419,5 +419,8 @@ EXPORT(sysn32_call_table)
         PTR     sys_perf_event_open
         PTR     sys_accept4
         PTR     compat_sys_recvmmsg
-        PTR     sys_getdents
+        PTR     sys_getdents64
+        PTR     sys_fanotify_init               /* 6300 */
+        PTR     sys_fanotify_mark
+        PTR     sys_prlimit64
         .size   sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 813689ef2384..171979fc98e5 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -538,5 +538,8 @@ sys_call_table:
         PTR     compat_sys_rt_tgsigqueueinfo
         PTR     sys_perf_event_open
         PTR     sys_accept4
-        PTR     compat_sys_recvmmsg
+        PTR     compat_sys_recvmmsg             /* 4335 */
+        PTR     sys_fanotify_init
+        PTR     sys_32_fanotify_mark
+        PTR     sys_prlimit64
         .size   sys_call_table,.-sys_call_table
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 7ba890860d98..469d4019f795 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -44,27 +44,39 @@ static inline int cpu_is_noncoherent_r10000(struct device *dev)
 
 static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp)
 {
+        gfp_t dma_flag;
+
         /* ignore region specifiers */
         gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
 
-#ifdef CONFIG_ZONE_DMA
+#ifdef CONFIG_ISA
         if (dev == NULL)
-                gfp |= __GFP_DMA;
-        else if (dev->coherent_dma_mask < DMA_BIT_MASK(24))
-                gfp |= __GFP_DMA;
+                dma_flag = __GFP_DMA;
         else
 #endif
-#ifdef CONFIG_ZONE_DMA32
+#if defined(CONFIG_ZONE_DMA32) && defined(CONFIG_ZONE_DMA)
              if (dev->coherent_dma_mask < DMA_BIT_MASK(32))
-                gfp |= __GFP_DMA32;
+                        dma_flag = __GFP_DMA;
+        else if (dev->coherent_dma_mask < DMA_BIT_MASK(64))
+                        dma_flag = __GFP_DMA32;
+        else
+#endif
+#if defined(CONFIG_ZONE_DMA32) && !defined(CONFIG_ZONE_DMA)
+             if (dev->coherent_dma_mask < DMA_BIT_MASK(64))
+                dma_flag = __GFP_DMA32;
+        else
+#endif
+#if defined(CONFIG_ZONE_DMA) && !defined(CONFIG_ZONE_DMA32)
+             if (dev->coherent_dma_mask < DMA_BIT_MASK(64))
+                dma_flag = __GFP_DMA;
         else
 #endif
-                ;
+                dma_flag = 0;
 
         /* Don't invoke OOM killer */
         gfp |= __GFP_NORETRY;
 
-        return gfp;
+        return gfp | dma_flag;
 }
 
 void *dma_alloc_noncoherent(struct device *dev, size_t size,
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index 1ef75cd80a0d..274af3be1442 100644
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -30,7 +30,7 @@
 #define tc_lsize        32
 
 extern unsigned long icache_way_size, dcache_way_size;
-unsigned long tcache_size;
+static unsigned long tcache_size;
 
 #include <asm/r4kcache.h>
 
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 15949b0be811..b79b24afe3a2 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -385,6 +385,8 @@ static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
  */
 
 #define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK
+#define X GIC_UNUSED
+
 static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
         { X, X,            X,           X,              0 },
         { X, X,            X,           X,              0 },
@@ -404,6 +406,7 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
         { X, X,            X,           X,              0 },
         /* The remainder of this table is initialised by fill_ipi_map */
 };
+#undef X
 
 /*
  * GCMP needs to be detected before any SMP initialisation
diff --git a/arch/mips/pci/pci-rc32434.c b/arch/mips/pci/pci-rc32434.c
index 71f7d27b0d4c..f31218e17d3c 100644
--- a/arch/mips/pci/pci-rc32434.c
+++ b/arch/mips/pci/pci-rc32434.c
@@ -118,7 +118,7 @@ static int __init rc32434_pcibridge_init(void)
         if (!((pcicvalue == PCIM_H_EA) ||
               (pcicvalue == PCIM_H_IA_FIX) ||
               (pcicvalue == PCIM_H_IA_RR))) {
-                pr_err(KERN_ERR "PCI init error!!!\n");
+                pr_err("PCI init error!!!\n");
                 /* Not in Host Mode, return ERROR */
                 return -1;
         }
diff --git a/arch/mips/pnx8550/common/reset.c b/arch/mips/pnx8550/common/reset.c
index fadd8744a6bc..e7a12ff304b9 100644
--- a/arch/mips/pnx8550/common/reset.c
+++ b/arch/mips/pnx8550/common/reset.c
@@ -22,29 +22,19 @@
  */
 #include <linux/kernel.h>
 
+#include <asm/processor.h>
 #include <asm/reboot.h>
 #include <glb.h>
 
 void pnx8550_machine_restart(char *command)
 {
-        char head[] = "************* Machine restart *************";
-        char foot[] = "*******************************************";
-
-        printk("\n\n");
-        printk("%s\n", head);
-        if (command != NULL)
-                printk("* %s\n", command);
-        printk("%s\n", foot);
-
         PNX8550_RST_CTL = PNX8550_RST_DO_SW_RST;
 }
 
 void pnx8550_machine_halt(void)
 {
-        printk("*** Machine halt. (Not implemented) ***\n");
-}
-
-void pnx8550_machine_power_off(void)
-{
-        printk("*** Machine power off.  (Not implemented) ***\n");
+        while (1) {
+                if (cpu_wait)
+                        cpu_wait();
+        }
 }
diff --git a/arch/mips/pnx8550/common/setup.c b/arch/mips/pnx8550/common/setup.c
index 64246c9c875c..43cb3945fdbf 100644
--- a/arch/mips/pnx8550/common/setup.c
+++ b/arch/mips/pnx8550/common/setup.c
@@ -44,7 +44,6 @@
 extern void __init board_setup(void);
 extern void pnx8550_machine_restart(char *);
 extern void pnx8550_machine_halt(void);
-extern void pnx8550_machine_power_off(void);
 extern struct resource ioport_resource;
 extern struct resource iomem_resource;
 extern char *prom_getcmdline(void);
@@ -100,7 +99,7 @@ void __init plat_mem_setup(void)
 
         _machine_restart = pnx8550_machine_restart;
         _machine_halt = pnx8550_machine_halt;
-        pm_power_off = pnx8550_machine_power_off;
+        pm_power_off = pnx8550_machine_halt;
 
         /* Clear the Global 2 Register, PCI Inta Output Enable Registers
            Bit 1:Enable DAC Powerdown
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
index 444b9f918fdf..7c2a2f7f8dc1 100644
--- a/arch/mn10300/Kconfig
+++ b/arch/mn10300/Kconfig
@@ -8,7 +8,6 @@ mainmenu "Linux Kernel Configuration"
 config MN10300
         def_bool y
         select HAVE_OPROFILE
-        select HAVE_ARCH_TRACEHOOK
 
 config AM33
         def_bool y
diff --git a/arch/mn10300/Kconfig.debug b/arch/mn10300/Kconfig.debug
index ff80e86b9bd2..ce83c74b3fd7 100644
--- a/arch/mn10300/Kconfig.debug
+++ b/arch/mn10300/Kconfig.debug
@@ -101,7 +101,7 @@ config GDBSTUB_DEBUG_BREAKPOINT
 
 choice
         prompt "GDB stub port"
-        default GDBSTUB_TTYSM0
+        default GDBSTUB_ON_TTYSM0
         depends on GDBSTUB
         help
           Select the serial port used for GDB-stub.
diff --git a/arch/mn10300/include/asm/bitops.h b/arch/mn10300/include/asm/bitops.h
index f49ac49e09ad..3f50e9661076 100644
--- a/arch/mn10300/include/asm/bitops.h
+++ b/arch/mn10300/include/asm/bitops.h
@@ -229,9 +229,9 @@ int ffs(int x)
 #include <asm-generic/bitops/hweight.h>
 
 #define ext2_set_bit_atomic(lock, nr, addr) \
-        test_and_set_bit((nr) ^ 0x18, (addr))
+        test_and_set_bit((nr), (addr))
 #define ext2_clear_bit_atomic(lock, nr, addr) \
-        test_and_clear_bit((nr) ^ 0x18, (addr))
+        test_and_clear_bit((nr), (addr))
 
 #include <asm-generic/bitops/ext2-non-atomic.h>
 #include <asm-generic/bitops/minix-le.h>
diff --git a/arch/mn10300/include/asm/signal.h b/arch/mn10300/include/asm/signal.h
index 7e891fce2370..1865d72a86ff 100644
--- a/arch/mn10300/include/asm/signal.h
+++ b/arch/mn10300/include/asm/signal.h
@@ -78,7 +78,7 @@ typedef unsigned long sigset_t;
 
 /* These should not be considered constants from userland.  */
 #define SIGRTMIN        32
-#define SIGRTMAX        (_NSIG-1)
+#define SIGRTMAX        _NSIG
 
 /*
  * SA_FLAGS values:
diff --git a/arch/mn10300/kernel/module.c b/arch/mn10300/kernel/module.c
index 6aea7fd76993..196a111e2e29 100644
--- a/arch/mn10300/kernel/module.c
+++ b/arch/mn10300/kernel/module.c
@@ -206,7 +206,7 @@ int module_finalize(const Elf_Ehdr *hdr,
                     const Elf_Shdr *sechdrs,
                     struct module *me)
 {
-        return module_bug_finalize(hdr, sechdrs, me);
+        return 0;
 }
 
 /*
@@ -214,5 +214,4 @@ int module_finalize(const Elf_Ehdr *hdr,
  */
 void module_arch_cleanup(struct module *mod)
 {
-        module_bug_cleanup(mod);
 }
diff --git a/arch/mn10300/kernel/signal.c b/arch/mn10300/kernel/signal.c
index 717db14c2cc3..d4de05ab7864 100644
--- a/arch/mn10300/kernel/signal.c
+++ b/arch/mn10300/kernel/signal.c
@@ -65,10 +65,10 @@ asmlinkage long sys_sigaction(int sig,
                 old_sigset_t mask;
                 if (verify_area(VERIFY_READ, act, sizeof(*act)) ||
                     __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
-                    __get_user(new_ka.sa.sa_restorer, &act->sa_restorer))
+                    __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) ||
+                    __get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
+                    __get_user(mask, &act->sa_mask))
                         return -EFAULT;
-                __get_user(new_ka.sa.sa_flags, &act->sa_flags);
-                __get_user(mask, &act->sa_mask);
                 siginitset(&new_ka.sa.sa_mask, mask);
         }
 
@@ -77,10 +77,10 @@ asmlinkage long sys_sigaction(int sig,
         if (!ret && oact) {
                 if (verify_area(VERIFY_WRITE, oact, sizeof(*oact)) ||
                     __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
-                    __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer))
+                    __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) ||
+                    __put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
+                    __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
                         return -EFAULT;
-                __put_user(old_ka.sa.sa_flags, &oact->sa_flags);
-                __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
         }
 
         return ret;
@@ -102,6 +102,9 @@ static int restore_sigcontext(struct pt_regs *regs,
 {
         unsigned int err = 0;
 
+        /* Always make any pending restarted system calls return -EINTR */
+        current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
         if (is_using_fpu(current))
                 fpu_kill_state(current);
 
@@ -330,8 +333,6 @@ static int setup_frame(int sig, struct k_sigaction *ka, sigset_t *set,
         regs->d0 = sig;
         regs->d1 = (unsigned long) &frame->sc;
 
-        set_fs(USER_DS);
-
         /* the tracer may want to single-step inside the handler */
         if (test_thread_flag(TIF_SINGLESTEP))
                 ptrace_notify(SIGTRAP);
@@ -345,7 +346,7 @@ static int setup_frame(int sig, struct k_sigaction *ka, sigset_t *set,
         return 0;
 
 give_sigsegv:
-        force_sig(SIGSEGV, current);
+        force_sigsegv(sig, current);
         return -EFAULT;
 }
 
@@ -413,8 +414,6 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         regs->d0 = sig;
         regs->d1 = (long) &frame->info;
 
-        set_fs(USER_DS);
-
         /* the tracer may want to single-step inside the handler */
         if (test_thread_flag(TIF_SINGLESTEP))
                 ptrace_notify(SIGTRAP);
@@ -428,10 +427,16 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         return 0;
 
 give_sigsegv:
-        force_sig(SIGSEGV, current);
+        force_sigsegv(sig, current);
         return -EFAULT;
 }
 
+static inline void stepback(struct pt_regs *regs)
+{
+        regs->pc -= 2;
+        regs->orig_d0 = -1;
+}
+
 /*
  * handle the actual delivery of a signal to userspace
  */
@@ -459,7 +464,7 @@ static int handle_signal(int sig,
                         /* fallthrough */
                 case -ERESTARTNOINTR:
                         regs->d0 = regs->orig_d0;
-                        regs->pc -= 2;
+                        stepback(regs);
                 }
         }
 
@@ -527,12 +532,12 @@ static void do_signal(struct pt_regs *regs)
                 case -ERESTARTSYS:
                 case -ERESTARTNOINTR:
                         regs->d0 = regs->orig_d0;
-                        regs->pc -= 2;
+                        stepback(regs);
                         break;
 
                 case -ERESTART_RESTARTBLOCK:
                         regs->d0 = __NR_restart_syscall;
-                        regs->pc -= 2;
+                        stepback(regs);
                         break;
                 }
         }
diff --git a/arch/mn10300/mm/Makefile b/arch/mn10300/mm/Makefile
index 28b9d983db0c..1557277fbc5c 100644
--- a/arch/mn10300/mm/Makefile
+++ b/arch/mn10300/mm/Makefile
@@ -2,13 +2,11 @@
 # Makefile for the MN10300-specific memory management code
 #
 
+cacheflush-y    := cache.o cache-mn10300.o
+cacheflush-$(CONFIG_MN10300_CACHE_WBACK) += cache-flush-mn10300.o
+
+cacheflush-$(CONFIG_MN10300_CACHE_DISABLED) := cache-disabled.o
+
 obj-y := \
         init.o fault.o pgtable.o extable.o tlb-mn10300.o mmu-context.o \
-        misalignment.o dma-alloc.o
-
-ifneq ($(CONFIG_MN10300_CACHE_DISABLED),y)
-obj-y   += cache.o cache-mn10300.o
-ifeq ($(CONFIG_MN10300_CACHE_WBACK),y)
-obj-y   += cache-flush-mn10300.o
-endif
-endif
+        misalignment.o dma-alloc.o $(cacheflush-y)
diff --git a/arch/mn10300/mm/cache-disabled.c b/arch/mn10300/mm/cache-disabled.c
new file mode 100644
index 000000000000..f669ea42aba6
--- /dev/null
+++ b/arch/mn10300/mm/cache-disabled.c
@@ -0,0 +1,21 @@
+/* Handle the cache being disabled
+ *
+ * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/mm.h>
+
+/*
+ * allow userspace to flush the instruction cache
+ */
+asmlinkage long sys_cacheflush(unsigned long start, unsigned long end)
+{
+        if (end < start)
+                return -EINVAL;
+        return 0;
+}
diff --git a/arch/mn10300/mm/cache.c b/arch/mn10300/mm/cache.c
index 1b76719ec1c3..9261217e8d2c 100644
--- a/arch/mn10300/mm/cache.c
+++ b/arch/mn10300/mm/cache.c
@@ -54,13 +54,30 @@ EXPORT_SYMBOL(flush_icache_page);
 void flush_icache_range(unsigned long start, unsigned long end)
 {
 #ifdef CONFIG_MN10300_CACHE_WBACK
-        unsigned long addr, size, off;
+        unsigned long addr, size, base, off;
         struct page *page;
         pgd_t *pgd;
         pud_t *pud;
         pmd_t *pmd;
         pte_t *ppte, pte;
 
+        if (end > 0x80000000UL) {
+                /* addresses above 0xa0000000 do not go through the cache */
+                if (end > 0xa0000000UL) {
+                        end = 0xa0000000UL;
+                        if (start >= end)
+                                return;
+                }
+
+                /* kernel addresses between 0x80000000 and 0x9fffffff do not
+                 * require page tables, so we just map such addresses directly */
+                base = (start >= 0x80000000UL) ? start : 0x80000000UL;
+                mn10300_dcache_flush_range(base, end);
+                if (base == start)
+                        goto invalidate;
+                end = base;
+        }
+
         for (; start < end; start += size) {
                 /* work out how much of the page to flush */
                 off = start & (PAGE_SIZE - 1);
@@ -104,6 +121,7 @@ void flush_icache_range(unsigned long start, unsigned long end)
         }
 #endif
 
+invalidate:
         mn10300_icache_inv();
 }
 EXPORT_SYMBOL(flush_icache_range);
diff --git a/arch/parisc/kernel/module.c b/arch/parisc/kernel/module.c
index 159a2b81e90c..6e81bb596e5b 100644
--- a/arch/parisc/kernel/module.c
+++ b/arch/parisc/kernel/module.c
@@ -941,11 +941,10 @@ int module_finalize(const Elf_Ehdr *hdr,
         nsyms = newptr - (Elf_Sym *)symhdr->sh_addr;
         DEBUGP("NEW num_symtab %lu\n", nsyms);
         symhdr->sh_size = nsyms * sizeof(Elf_Sym);
-        return module_bug_finalize(hdr, sechdrs, me);
+        return 0;
 }
 
 void module_arch_cleanup(struct module *mod)
 {
         deregister_unwind_table(mod);
-        module_bug_cleanup(mod);
 }
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
index 477c663e0140..49cee9df225b 100644
--- a/arch/powerpc/kernel/module.c
+++ b/arch/powerpc/kernel/module.c
@@ -63,11 +63,6 @@ int module_finalize(const Elf_Ehdr *hdr,
                 const Elf_Shdr *sechdrs, struct module *me)
 {
         const Elf_Shdr *sect;
-        int err;
-
-        err = module_bug_finalize(hdr, sechdrs, me);
-        if (err)
-                return err;
 
         /* Apply feature fixups */
         sect = find_section(hdr, sechdrs, "__ftr_fixup");
@@ -101,5 +96,4 @@ int module_finalize(const Elf_Ehdr *hdr,
 
 void module_arch_cleanup(struct module *mod)
 {
-        module_bug_cleanup(mod);
 }
diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c
index 7109f5b1baa8..2300426e531a 100644
--- a/arch/powerpc/kernel/signal.c
+++ b/arch/powerpc/kernel/signal.c
@@ -138,6 +138,7 @@ static int do_signal_pending(sigset_t *oldset, struct pt_regs *regs)
                         ti->local_flags &= ~_TLF_RESTORE_SIGMASK;
                         sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
                 }
+                regs->trap = 0;
                 return 0;               /* no signals delivered */
         }
 
@@ -164,6 +165,7 @@ static int do_signal_pending(sigset_t *oldset, struct pt_regs *regs)
                 ret = handle_rt_signal64(signr, &ka, &info, oldset, regs);
         }
 
+        regs->trap = 0;
         if (ret) {
                 spin_lock_irq(&current->sighand->siglock);
                 sigorsets(&current->blocked, &current->blocked,
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 266610119f66..b96a3a010c26 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -511,6 +511,7 @@ static long restore_user_regs(struct pt_regs *regs,
         if (!sig)
                 save_r2 = (unsigned int)regs->gpr[2];
         err = restore_general_regs(regs, sr);
+        regs->trap = 0;
         err |= __get_user(msr, &sr->mc_gregs[PT_MSR]);
         if (!sig)
                 regs->gpr[2] = (unsigned long) save_r2;
@@ -884,7 +885,6 @@ int handle_rt_signal32(unsigned long sig, struct k_sigaction *ka,
         regs->nip = (unsigned long) ka->sa.sa_handler;
         /* enter the signal handler in big-endian mode */
         regs->msr &= ~MSR_LE;
-        regs->trap = 0;
         return 1;
 
 badframe:
@@ -1228,7 +1228,6 @@ int handle_signal32(unsigned long sig, struct k_sigaction *ka,
         regs->nip = (unsigned long) ka->sa.sa_handler;
         /* enter the signal handler in big-endian mode */
         regs->msr &= ~MSR_LE;
-        regs->trap = 0;
 
         return 1;
 
diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c
index 2fe6fc64b614..27c4a4584f80 100644
--- a/arch/powerpc/kernel/signal_64.c
+++ b/arch/powerpc/kernel/signal_64.c
@@ -178,7 +178,7 @@ static long restore_sigcontext(struct pt_regs *regs, sigset_t *set, int sig,
         err |= __get_user(regs->xer, &sc->gp_regs[PT_XER]);
         err |= __get_user(regs->ccr, &sc->gp_regs[PT_CCR]);
         /* skip SOFTE */
-        err |= __get_user(regs->trap, &sc->gp_regs[PT_TRAP]);
+        regs->trap = 0;
         err |= __get_user(regs->dar, &sc->gp_regs[PT_DAR]);
         err |= __get_user(regs->dsisr, &sc->gp_regs[PT_DSISR]);
         err |= __get_user(regs->result, &sc->gp_regs[PT_RESULT]);
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
index 5b243bd3eb3b..3dc2a8d262b8 100644
--- a/arch/powerpc/platforms/512x/clock.c
+++ b/arch/powerpc/platforms/512x/clock.c
@@ -57,7 +57,7 @@ static struct clk *mpc5121_clk_get(struct device *dev, const char *id)
         int id_match = 0;
 
         if (dev == NULL || id == NULL)
-                return NULL;
+                return clk;
 
         mutex_lock(&clocks_mutex);
         list_for_each_entry(p, &clocks, node) {
diff --git a/arch/powerpc/platforms/52xx/efika.c b/arch/powerpc/platforms/52xx/efika.c
index 45c0cb9b67e6..18c104820198 100644
--- a/arch/powerpc/platforms/52xx/efika.c
+++ b/arch/powerpc/platforms/52xx/efika.c
@@ -99,7 +99,7 @@ static void __init efika_pcisetup(void)
         if (bus_range == NULL || len < 2 * sizeof(int)) {
                 printk(KERN_WARNING EFIKA_PLATFORM_NAME
                        ": Can't get bus-range for %s\n", pcictrl->full_name);
-                return;
+                goto out_put;
         }
 
         if (bus_range[1] == bus_range[0])
@@ -111,12 +111,12 @@ static void __init efika_pcisetup(void)
         printk(" controlled by %s\n", pcictrl->full_name);
         printk("\n");
 
-        hose = pcibios_alloc_controller(of_node_get(pcictrl));
+        hose = pcibios_alloc_controller(pcictrl);
         if (!hose) {
                 printk(KERN_WARNING EFIKA_PLATFORM_NAME
                        ": Can't allocate PCI controller structure for %s\n",
                        pcictrl->full_name);
-                return;
+                goto out_put;
         }
 
         hose->first_busno = bus_range[0];
@@ -124,6 +124,9 @@ static void __init efika_pcisetup(void)
         hose->ops = &rtas_pci_ops;
 
         pci_process_bridge_OF_ranges(hose, pcictrl, 0);
+        return;
+out_put:
+        of_node_put(pcictrl);
 }
 
 #else
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c
index 6e905314ad5d..41f3a7eda1de 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -325,12 +325,16 @@ int mpc5200_psc_ac97_gpio_reset(int psc_number)
         clrbits32(&simple_gpio->simple_dvo, sync | out);
         clrbits8(&wkup_gpio->wkup_dvo, reset);
 
-        /* wait at lease 1 us */
-        udelay(2);
+        /* wait for 1 us */
+        udelay(1);
 
         /* Deassert reset */
         setbits8(&wkup_gpio->wkup_dvo, reset);
 
+        /* wait at least 200ns */
+        /* 7 ~= (200ns * timebase) / ns2sec */
+        __delay(7);
+
         /* Restore pin-muxing */
         out_be32(&simple_gpio->port_config, mux);
 
diff --git a/arch/s390/kernel/module.c b/arch/s390/kernel/module.c
index 22cfd634c355..f7167ee4604c 100644
--- a/arch/s390/kernel/module.c
+++ b/arch/s390/kernel/module.c
@@ -407,10 +407,9 @@ int module_finalize(const Elf_Ehdr *hdr,
 {
         vfree(me->arch.syminfo);
         me->arch.syminfo = NULL;
-        return module_bug_finalize(hdr, sechdrs, me);
+        return 0;
 }
 
 void module_arch_cleanup(struct module *mod)
 {
-        module_bug_cleanup(mod);
 }
diff --git a/arch/sh/kernel/module.c b/arch/sh/kernel/module.c
index 43adddfe4c04..ae0be697a89e 100644
--- a/arch/sh/kernel/module.c
+++ b/arch/sh/kernel/module.c
@@ -149,13 +149,11 @@ int module_finalize(const Elf_Ehdr *hdr,
         int ret = 0;
 
         ret |= module_dwarf_finalize(hdr, sechdrs, me);
-        ret |= module_bug_finalize(hdr, sechdrs, me);
 
         return ret;
 }
 
 void module_arch_cleanup(struct module *mod)
 {
-        module_bug_cleanup(mod);
         module_dwarf_cleanup(mod);
 }
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index 357ced3c33ff..6318e622cfb0 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -1038,6 +1038,7 @@ static int __hw_perf_event_init(struct perf_event *event)
         if (atomic_read(&nmi_active) < 0)
                 return -ENODEV;
 
+        pmap = NULL;
         if (attr->type == PERF_TYPE_HARDWARE) {
                 if (attr->config >= sparc_pmu->max_events)
                         return -EINVAL;
@@ -1046,9 +1047,18 @@ static int __hw_perf_event_init(struct perf_event *event)
                 pmap = sparc_map_cache_event(attr->config);
                 if (IS_ERR(pmap))
                         return PTR_ERR(pmap);
-        } else
+        } else if (attr->type != PERF_TYPE_RAW)
                 return -EOPNOTSUPP;
 
+        if (pmap) {
+                hwc->event_base = perf_event_encode(pmap);
+        } else {
+                /* User gives us "(encoding << 16) | pic_mask" for
+                 * PERF_TYPE_RAW events.
+                 */
+                hwc->event_base = attr->config;
+        }
+
         /* We save the enable bits in the config_base.  */
         hwc->config_base = sparc_pmu->irq_bit;
         if (!attr->exclude_user)
@@ -1058,8 +1068,6 @@ static int __hw_perf_event_init(struct perf_event *event)
         if (!attr->exclude_hv)
                 hwc->config_base |= sparc_pmu->hv_bit;
 
-        hwc->event_base = perf_event_encode(pmap);
-
         n = 0;
         if (event->group_leader != event) {
                 n = collect_events(event->group_leader,
diff --git a/arch/sparc/kernel/signal32.c b/arch/sparc/kernel/signal32.c
index ea22cd373c64..75fad425e249 100644
--- a/arch/sparc/kernel/signal32.c
+++ b/arch/sparc/kernel/signal32.c
@@ -453,8 +453,66 @@ static int save_fpu_state32(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
         return err;
 }
 
-static void setup_frame32(struct k_sigaction *ka, struct pt_regs *regs,
-                          int signo, sigset_t *oldset)
+/* The I-cache flush instruction only works in the primary ASI, which
+ * right now is the nucleus, aka. kernel space.
+ *
+ * Therefore we have to kick the instructions out using the kernel
+ * side linear mapping of the physical address backing the user
+ * instructions.
+ */
+static void flush_signal_insns(unsigned long address)
+{
+        unsigned long pstate, paddr;
+        pte_t *ptep, pte;
+        pgd_t *pgdp;
+        pud_t *pudp;
+        pmd_t *pmdp;
+
+        /* Commit all stores of the instructions we are about to flush.  */
+        wmb();
+
+        /* Disable cross-call reception.  In this way even a very wide
+         * munmap() on another cpu can't tear down the page table
+         * hierarchy from underneath us, since that can't complete
+         * until the IPI tlb flush returns.
+         */
+
+        __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
+        __asm__ __volatile__("wrpr %0, %1, %%pstate"
+                                : : "r" (pstate), "i" (PSTATE_IE));
+
+        pgdp = pgd_offset(current->mm, address);
+        if (pgd_none(*pgdp))
+                goto out_irqs_on;
+        pudp = pud_offset(pgdp, address);
+        if (pud_none(*pudp))
+                goto out_irqs_on;
+        pmdp = pmd_offset(pudp, address);
+        if (pmd_none(*pmdp))
+                goto out_irqs_on;
+
+        ptep = pte_offset_map(pmdp, address);
+        pte = *ptep;
+        if (!pte_present(pte))
+                goto out_unmap;
+
+        paddr = (unsigned long) page_address(pte_page(pte));
+
+        __asm__ __volatile__("flush     %0 + %1"
+                             : /* no outputs */
+                             : "r" (paddr),
+                               "r" (address & (PAGE_SIZE - 1))
+                             : "memory");
+
+out_unmap:
+        pte_unmap(ptep);
+out_irqs_on:
+        __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
+
+}
+
+static int setup_frame32(struct k_sigaction *ka, struct pt_regs *regs,
+                         int signo, sigset_t *oldset)
 {
         struct signal_frame32 __user *sf;
         int sigframe_size;
@@ -547,13 +605,7 @@ static void setup_frame32(struct k_sigaction *ka, struct pt_regs *regs,
         if (ka->ka_restorer) {
                 regs->u_regs[UREG_I7] = (unsigned long)ka->ka_restorer;
         } else {
-                /* Flush instruction space. */
                 unsigned long address = ((unsigned long)&(sf->insns[0]));
-                pgd_t *pgdp = pgd_offset(current->mm, address);
-                pud_t *pudp = pud_offset(pgdp, address);
-                pmd_t *pmdp = pmd_offset(pudp, address);
-                pte_t *ptep;
-                pte_t pte;
 
                 regs->u_regs[UREG_I7] = (unsigned long) (&(sf->insns[0]) - 2);
         
@@ -562,34 +614,22 @@ static void setup_frame32(struct k_sigaction *ka, struct pt_regs *regs,
                 if (err)
                         goto sigsegv;
 
-                preempt_disable();
-                ptep = pte_offset_map(pmdp, address);
-                pte = *ptep;
-                if (pte_present(pte)) {
-                        unsigned long page = (unsigned long)
-                                page_address(pte_page(pte));
-
-                        wmb();
-                        __asm__ __volatile__("flush     %0 + %1"
-                                             : /* no outputs */
-                                             : "r" (page),
-                                               "r" (address & (PAGE_SIZE - 1))
-                                             : "memory");
-                }
-                pte_unmap(ptep);
-                preempt_enable();
+                flush_signal_insns(address);
         }
-        return;
+        return 0;
 
 sigill:
         do_exit(SIGILL);
+        return -EINVAL;
+
 sigsegv:
         force_sigsegv(signo, current);
+        return -EFAULT;
 }
 
-static void setup_rt_frame32(struct k_sigaction *ka, struct pt_regs *regs,
-                             unsigned long signr, sigset_t *oldset,
-                             siginfo_t *info)
+static int setup_rt_frame32(struct k_sigaction *ka, struct pt_regs *regs,
+                            unsigned long signr, sigset_t *oldset,
+                            siginfo_t *info)
 {
         struct rt_signal_frame32 __user *sf;
         int sigframe_size;
@@ -687,12 +727,7 @@ static void setup_rt_frame32(struct k_sigaction *ka, struct pt_regs *regs,
         if (ka->ka_restorer)
                 regs->u_regs[UREG_I7] = (unsigned long)ka->ka_restorer;
         else {
-                /* Flush instruction space. */
                 unsigned long address = ((unsigned long)&(sf->insns[0]));
-                pgd_t *pgdp = pgd_offset(current->mm, address);
-                pud_t *pudp = pud_offset(pgdp, address);
-                pmd_t *pmdp = pmd_offset(pudp, address);
-                pte_t *ptep;
 
                 regs->u_regs[UREG_I7] = (unsigned long) (&(sf->insns[0]) - 2);
         
@@ -704,38 +739,32 @@ static void setup_rt_frame32(struct k_sigaction *ka, struct pt_regs *regs,
                 if (err)
                         goto sigsegv;
 
-                preempt_disable();
-                ptep = pte_offset_map(pmdp, address);
-                if (pte_present(*ptep)) {
-                        unsigned long page = (unsigned long)
-                                page_address(pte_page(*ptep));
-
-                        wmb();
-                        __asm__ __volatile__("flush     %0 + %1"
-                                             : /* no outputs */
-                                             : "r" (page),
-                                               "r" (address & (PAGE_SIZE - 1))
-                                             : "memory");
-                }
-                pte_unmap(ptep);
-                preempt_enable();
+                flush_signal_insns(address);
         }
-        return;
+        return 0;
 
 sigill:
         do_exit(SIGILL);
+        return -EINVAL;
+
 sigsegv:
         force_sigsegv(signr, current);
+        return -EFAULT;
 }
 
-static inline void handle_signal32(unsigned long signr, struct k_sigaction *ka,
-                                   siginfo_t *info,
-                                   sigset_t *oldset, struct pt_regs *regs)
+static inline int handle_signal32(unsigned long signr, struct k_sigaction *ka,
+                                  siginfo_t *info,
+                                  sigset_t *oldset, struct pt_regs *regs)
 {
+        int err;
+
         if (ka->sa.sa_flags & SA_SIGINFO)
-                setup_rt_frame32(ka, regs, signr, oldset, info);
+                err = setup_rt_frame32(ka, regs, signr, oldset, info);
         else
-                setup_frame32(ka, regs, signr, oldset);
+                err = setup_frame32(ka, regs, signr, oldset);
+
+        if (err)
+                return err;
 
         spin_lock_irq(&current->sighand->siglock);
         sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
@@ -743,6 +772,10 @@ static inline void handle_signal32(unsigned long signr, struct k_sigaction *ka,
                 sigaddset(&current->blocked,signr);
         recalc_sigpending();
         spin_unlock_irq(&current->sighand->siglock);
+
+        tracehook_signal_handler(signr, info, ka, regs, 0);
+
+        return 0;
 }
 
 static inline void syscall_restart32(unsigned long orig_i0, struct pt_regs *regs,
@@ -789,16 +822,14 @@ void do_signal32(sigset_t *oldset, struct pt_regs * regs,
         if (signr > 0) {
                 if (restart_syscall)
                         syscall_restart32(orig_i0, regs, &ka.sa);
-                handle_signal32(signr, &ka, &info, oldset, regs);
-
-                /* A signal was successfully delivered; the saved
-                 * sigmask will have been stored in the signal frame,
-                 * and will be restored by sigreturn, so we can simply
-                 * clear the TS_RESTORE_SIGMASK flag.
-                 */
-                current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
-
-                tracehook_signal_handler(signr, &info, &ka, regs, 0);
+                if (handle_signal32(signr, &ka, &info, oldset, regs) == 0) {
+                        /* A signal was successfully delivered; the saved
+                         * sigmask will have been stored in the signal frame,
+                         * and will be restored by sigreturn, so we can simply
+                         * clear the TS_RESTORE_SIGMASK flag.
+                         */
+                        current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
+                }
                 return;
         }
         if (restart_syscall &&
@@ -809,12 +840,14 @@ void do_signal32(sigset_t *oldset, struct pt_regs * regs,
                 regs->u_regs[UREG_I0] = orig_i0;
                 regs->tpc -= 4;
                 regs->tnpc -= 4;
+                pt_regs_clear_syscall(regs);
         }
         if (restart_syscall &&
             regs->u_regs[UREG_I0] == ERESTART_RESTARTBLOCK) {
                 regs->u_regs[UREG_G1] = __NR_restart_syscall;
                 regs->tpc -= 4;
                 regs->tnpc -= 4;
+                pt_regs_clear_syscall(regs);
         }
 
         /* If there's no signal to deliver, we just put the saved sigmask
diff --git a/arch/sparc/kernel/signal_32.c b/arch/sparc/kernel/signal_32.c
index 9882df92ba0a..5e5c5fd03783 100644
--- a/arch/sparc/kernel/signal_32.c
+++ b/arch/sparc/kernel/signal_32.c
@@ -315,8 +315,8 @@ save_fpu_state(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
         return err;
 }
 
-static void setup_frame(struct k_sigaction *ka, struct pt_regs *regs,
-                        int signo, sigset_t *oldset)
+static int setup_frame(struct k_sigaction *ka, struct pt_regs *regs,
+                       int signo, sigset_t *oldset)
 {
         struct signal_frame __user *sf;
         int sigframe_size, err;
@@ -384,16 +384,19 @@ static void setup_frame(struct k_sigaction *ka, struct pt_regs *regs,
                 /* Flush instruction space. */
                 flush_sig_insns(current->mm, (unsigned long) &(sf->insns[0]));
         }
-        return;
+        return 0;
 
 sigill_and_return:
         do_exit(SIGILL);
+        return -EINVAL;
+
 sigsegv:
         force_sigsegv(signo, current);
+        return -EFAULT;
 }
 
-static void setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs,
-                           int signo, sigset_t *oldset, siginfo_t *info)
+static int setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs,
+                          int signo, sigset_t *oldset, siginfo_t *info)
 {
         struct rt_signal_frame __user *sf;
         int sigframe_size;
@@ -466,22 +469,30 @@ static void setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs,
                 /* Flush instruction space. */
                 flush_sig_insns(current->mm, (unsigned long) &(sf->insns[0]));
         }
-        return;
+        return 0;
 
 sigill:
         do_exit(SIGILL);
+        return -EINVAL;
+
 sigsegv:
         force_sigsegv(signo, current);
+        return -EFAULT;
 }
 
-static inline void
+static inline int
 handle_signal(unsigned long signr, struct k_sigaction *ka,
               siginfo_t *info, sigset_t *oldset, struct pt_regs *regs)
 {
+        int err;
+
         if (ka->sa.sa_flags & SA_SIGINFO)
-                setup_rt_frame(ka, regs, signr, oldset, info);
+                err = setup_rt_frame(ka, regs, signr, oldset, info);
         else
-                setup_frame(ka, regs, signr, oldset);
+                err = setup_frame(ka, regs, signr, oldset);
+
+        if (err)
+                return err;
 
         spin_lock_irq(&current->sighand->siglock);
         sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
@@ -489,6 +500,10 @@ handle_signal(unsigned long signr, struct k_sigaction *ka,
                 sigaddset(&current->blocked, signr);
         recalc_sigpending();
         spin_unlock_irq(&current->sighand->siglock);
+
+        tracehook_signal_handler(signr, info, ka, regs, 0);
+
+        return 0;
 }
 
 static inline void syscall_restart(unsigned long orig_i0, struct pt_regs *regs,
@@ -546,17 +561,15 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
         if (signr > 0) {
                 if (restart_syscall)
                         syscall_restart(orig_i0, regs, &ka.sa);
-                handle_signal(signr, &ka, &info, oldset, regs);
-
-                /* a signal was successfully delivered; the saved
-                 * sigmask will have been stored in the signal frame,
-                 * and will be restored by sigreturn, so we can simply
-                 * clear the TIF_RESTORE_SIGMASK flag.
-                 */
-                if (test_thread_flag(TIF_RESTORE_SIGMASK))
-                        clear_thread_flag(TIF_RESTORE_SIGMASK);
-
-                tracehook_signal_handler(signr, &info, &ka, regs, 0);
+                if (handle_signal(signr, &ka, &info, oldset, regs) == 0) {
+                        /* a signal was successfully delivered; the saved
+                         * sigmask will have been stored in the signal frame,
+                         * and will be restored by sigreturn, so we can simply
+                         * clear the TIF_RESTORE_SIGMASK flag.
+                         */
+                        if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                                clear_thread_flag(TIF_RESTORE_SIGMASK);
+                }
                 return;
         }
         if (restart_syscall &&
@@ -567,12 +580,14 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
                 regs->u_regs[UREG_I0] = orig_i0;
                 regs->pc -= 4;
                 regs->npc -= 4;
+                pt_regs_clear_syscall(regs);
         }
         if (restart_syscall &&
             regs->u_regs[UREG_I0] == ERESTART_RESTARTBLOCK) {
                 regs->u_regs[UREG_G1] = __NR_restart_syscall;
                 regs->pc -= 4;
                 regs->npc -= 4;
+                pt_regs_clear_syscall(regs);
         }
 
         /* if there's no signal to deliver, we just put the saved sigmask
diff --git a/arch/sparc/kernel/signal_64.c b/arch/sparc/kernel/signal_64.c
index 9fa48c30037e..006fe4515886 100644
--- a/arch/sparc/kernel/signal_64.c
+++ b/arch/sparc/kernel/signal_64.c
@@ -409,7 +409,7 @@ static inline void __user *get_sigframe(struct k_sigaction *ka, struct pt_regs *
         return (void __user *) sp;
 }
 
-static inline void
+static inline int
 setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs,
                int signo, sigset_t *oldset, siginfo_t *info)
 {
@@ -483,26 +483,37 @@ setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs,
         }
         /* 4. return to kernel instructions */
         regs->u_regs[UREG_I7] = (unsigned long)ka->ka_restorer;
-        return;
+        return 0;
 
 sigill:
         do_exit(SIGILL);
+        return -EINVAL;
+
 sigsegv:
         force_sigsegv(signo, current);
+        return -EFAULT;
 }
 
-static inline void handle_signal(unsigned long signr, struct k_sigaction *ka,
-                                 siginfo_t *info,
-                                 sigset_t *oldset, struct pt_regs *regs)
+static inline int handle_signal(unsigned long signr, struct k_sigaction *ka,
+                                siginfo_t *info,
+                                sigset_t *oldset, struct pt_regs *regs)
 {
-        setup_rt_frame(ka, regs, signr, oldset,
-                       (ka->sa.sa_flags & SA_SIGINFO) ? info : NULL);
+        int err;
+
+        err = setup_rt_frame(ka, regs, signr, oldset,
+                             (ka->sa.sa_flags & SA_SIGINFO) ? info : NULL);
+        if (err)
+                return err;
         spin_lock_irq(&current->sighand->siglock);
         sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
         if (!(ka->sa.sa_flags & SA_NOMASK))
                 sigaddset(&current->blocked,signr);
         recalc_sigpending();
         spin_unlock_irq(&current->sighand->siglock);
+
+        tracehook_signal_handler(signr, info, ka, regs, 0);
+
+        return 0;
 }
 
 static inline void syscall_restart(unsigned long orig_i0, struct pt_regs *regs,
@@ -571,16 +582,14 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
         if (signr > 0) {
                 if (restart_syscall)
                         syscall_restart(orig_i0, regs, &ka.sa);
-                handle_signal(signr, &ka, &info, oldset, regs);
-
-                /* A signal was successfully delivered; the saved
-                 * sigmask will have been stored in the signal frame,
-                 * and will be restored by sigreturn, so we can simply
-                 * clear the TS_RESTORE_SIGMASK flag.
-                 */
-                current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
-
-                tracehook_signal_handler(signr, &info, &ka, regs, 0);
+                if (handle_signal(signr, &ka, &info, oldset, regs) == 0) {
+                        /* A signal was successfully delivered; the saved
+                         * sigmask will have been stored in the signal frame,
+                         * and will be restored by sigreturn, so we can simply
+                         * clear the TS_RESTORE_SIGMASK flag.
+                         */
+                        current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
+                }
                 return;
         }
         if (restart_syscall &&
@@ -591,12 +600,14 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
                 regs->u_regs[UREG_I0] = orig_i0;
                 regs->tpc -= 4;
                 regs->tnpc -= 4;
+                pt_regs_clear_syscall(regs);
         }
         if (restart_syscall &&
             regs->u_regs[UREG_I0] == ERESTART_RESTARTBLOCK) {
                 regs->u_regs[UREG_G1] = __NR_restart_syscall;
                 regs->tpc -= 4;
                 regs->tnpc -= 4;
+                pt_regs_clear_syscall(regs);
         }
 
         /* If there's no signal to deliver, we just put the saved sigmask
diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S
index 84f296ca9e63..8f58bdff20d7 100644
--- a/arch/tile/kernel/intvec_32.S
+++ b/arch/tile/kernel/intvec_32.S
@@ -1506,13 +1506,6 @@ handle_ill:
         }
         STD_ENDPROC(handle_ill)
 
-        .pushsection .rodata, "a"
-        .align  8
-bpt_code:
-        bpt
-        ENDPROC(bpt_code)
-        .popsection
-
 /* Various stub interrupt handlers and syscall handlers */
 
 STD_ENTRY_LOCAL(_kernel_double_fault)
diff --git a/arch/um/drivers/net_kern.c b/arch/um/drivers/net_kern.c
index 2ab233ba32c1..47d0c37897d5 100644
--- a/arch/um/drivers/net_kern.c
+++ b/arch/um/drivers/net_kern.c
@@ -255,18 +255,6 @@ static void uml_net_tx_timeout(struct net_device *dev)
         netif_wake_queue(dev);
 }
 
-static int uml_net_set_mac(struct net_device *dev, void *addr)
-{
-        struct uml_net_private *lp = netdev_priv(dev);
-        struct sockaddr *hwaddr = addr;
-
-        spin_lock_irq(&lp->lock);
-        eth_mac_addr(dev, hwaddr->sa_data);
-        spin_unlock_irq(&lp->lock);
-
-        return 0;
-}
-
 static int uml_net_change_mtu(struct net_device *dev, int new_mtu)
 {
         dev->mtu = new_mtu;
@@ -373,7 +361,7 @@ static const struct net_device_ops uml_netdev_ops = {
         .ndo_start_xmit         = uml_net_start_xmit,
         .ndo_set_multicast_list = uml_net_set_multicast_list,
         .ndo_tx_timeout         = uml_net_tx_timeout,
-        .ndo_set_mac_address    = uml_net_set_mac,
+        .ndo_set_mac_address    = eth_mac_addr,
         .ndo_change_mtu         = uml_net_change_mtu,
         .ndo_validate_addr      = eth_validate_addr,
 };
@@ -472,7 +460,8 @@ static void eth_configure(int n, void *init, char *mac,
             ((*transport->user->init)(&lp->user, dev) != 0))
                 goto out_unregister;
 
-        eth_mac_addr(dev, device->mac);
+        /* don't use eth_mac_addr, it will not work here */
+        memcpy(dev->dev_addr, device->mac, ETH_ALEN);
         dev->mtu = transport->user->mtu;
         dev->netdev_ops = &uml_netdev_ops;
         dev->ethtool_ops = &uml_net_ethtool_ops;
diff --git a/arch/um/kernel/exec.c b/arch/um/kernel/exec.c
index cd145eda3579..49b5e1eb3262 100644
--- a/arch/um/kernel/exec.c
+++ b/arch/um/kernel/exec.c
@@ -62,7 +62,7 @@ static long execve1(const char *file,
         return error;
 }
 
-long um_execve(const char *file, char __user *__user *argv, char __user *__user *env)
+long um_execve(const char *file, const char __user *const __user *argv, const char __user *const __user *env)
 {
         long err;
 
@@ -72,8 +72,8 @@ long um_execve(const char *file, char __user *__user *argv, char __user *__user
         return err;
 }
 
-long sys_execve(const char __user *file, char __user *__user *argv,
-                char __user *__user *env)
+long sys_execve(const char __user *file, const char __user *const __user *argv,
+                const char __user *const __user *env)
 {
         long error;
         char *filename;
diff --git a/arch/um/kernel/internal.h b/arch/um/kernel/internal.h
index 1303a105fe91..5bf97db24a04 100644
--- a/arch/um/kernel/internal.h
+++ b/arch/um/kernel/internal.h
@@ -1 +1 @@
-extern long um_execve(const char *file, char __user *__user *argv, char __user *__user *env);
+extern long um_execve(const char *file, const char __user *const __user *argv, const char __user *const __user *env);
diff --git a/arch/um/kernel/syscall.c b/arch/um/kernel/syscall.c
index 5ddb246626db..f958cb876ee3 100644
--- a/arch/um/kernel/syscall.c
+++ b/arch/um/kernel/syscall.c
@@ -60,8 +60,8 @@ int kernel_execve(const char *filename,
 
         fs = get_fs();
         set_fs(KERNEL_DS);
-        ret = um_execve(filename, (char __user *__user *)argv,
-                        (char __user *__user *) envp);
+        ret = um_execve(filename, (const char __user *const __user *)argv,
+                        (const char __user *const __user *) envp);
         set_fs(fs);
 
         return ret;
diff --git a/arch/x86/boot/early_serial_console.c b/arch/x86/boot/early_serial_console.c
index 030f4b93e255..5df2869c874b 100644
--- a/arch/x86/boot/early_serial_console.c
+++ b/arch/x86/boot/early_serial_console.c
@@ -58,7 +58,19 @@ static void parse_earlyprintk(void)
                 if (arg[pos] == ',')
                         pos++;
 
-                if (!strncmp(arg, "ttyS", 4)) {
+                /*
+                 * make sure we have
+                 *      "serial,0x3f8,115200"
+                 *      "serial,ttyS0,115200"
+                 *      "ttyS0,115200"
+                 */
+                if (pos == 7 && !strncmp(arg + pos, "0x", 2)) {
+                        port = simple_strtoull(arg + pos, &e, 16);
+                        if (port == 0 || arg + pos == e)
+                                port = DEFAULT_SERIAL_PORT;
+                        else
+                                pos = e - arg;
+                } else if (!strncmp(arg + pos, "ttyS", 4)) {
                         static const int bases[] = { 0x3f8, 0x2f8 };
                         int idx = 0;
 
diff --git a/arch/x86/include/asm/amd_iommu_proto.h b/arch/x86/include/asm/amd_iommu_proto.h
index d2544f1d705d..cb030374b90a 100644
--- a/arch/x86/include/asm/amd_iommu_proto.h
+++ b/arch/x86/include/asm/amd_iommu_proto.h
@@ -38,4 +38,10 @@ static inline void amd_iommu_stats_init(void) { }
 
 #endif /* !CONFIG_AMD_IOMMU_STATS */
 
+static inline bool is_rd890_iommu(struct pci_dev *pdev)
+{
+        return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
+               (pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
+}
+
 #endif /* _ASM_X86_AMD_IOMMU_PROTO_H  */
diff --git a/arch/x86/include/asm/amd_iommu_types.h b/arch/x86/include/asm/amd_iommu_types.h
index 7014e88bc779..08616180deaf 100644
--- a/arch/x86/include/asm/amd_iommu_types.h
+++ b/arch/x86/include/asm/amd_iommu_types.h
@@ -368,6 +368,9 @@ struct amd_iommu {
         /* capabilities of that IOMMU read from ACPI */
         u32 cap;
 
+        /* flags read from acpi table */
+        u8 acpi_flags;
+
         /*
          * Capability pointer. There could be more than one IOMMU per PCI
          * device function if there are more than one AMD IOMMU capability
@@ -411,6 +414,15 @@ struct amd_iommu {
 
         /* default dma_ops domain for that IOMMU */
         struct dma_ops_domain *default_dom;
+
+        /*
+         * This array is required to work around a potential BIOS bug.
+         * The BIOS may miss to restore parts of the PCI configuration
+         * space when the system resumes from S3. The result is that the
+         * IOMMU does not execute commands anymore which leads to system
+         * failure.
+         */
+        u32 cache_cfg[4];
 };
 
 /*
diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h
index 545776efeb16..bafd80defa43 100644
--- a/arch/x86/include/asm/bitops.h
+++ b/arch/x86/include/asm/bitops.h
@@ -309,7 +309,7 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
 static __always_inline int constant_test_bit(unsigned int nr, const volatile unsigned long *addr)
 {
         return ((1UL << (nr % BITS_PER_LONG)) &
-                (((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0;
+                (addr[nr / BITS_PER_LONG])) != 0;
 }
 
 static inline int variable_test_bit(int nr, volatile const unsigned long *addr)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index c6fbb7b430d1..3f76523589af 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -168,6 +168,7 @@
 #define X86_FEATURE_XSAVEOPT    (7*32+ 4) /* Optimized Xsave */
 #define X86_FEATURE_PLN         (7*32+ 5) /* Intel Power Limit Notification */
 #define X86_FEATURE_PTS         (7*32+ 6) /* Intel Package Thermal Status */
+#define X86_FEATURE_DTS         (7*32+ 7) /* Digital Thermal Sensor */
 
 /* Virtualization flags: Linux defined, word 8 */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/include/asm/hw_breakpoint.h b/arch/x86/include/asm/hw_breakpoint.h
index 528a11e8d3e3..824ca07860d0 100644
--- a/arch/x86/include/asm/hw_breakpoint.h
+++ b/arch/x86/include/asm/hw_breakpoint.h
@@ -20,7 +20,7 @@ struct arch_hw_breakpoint {
 #include <linux/list.h>
 
 /* Available HW breakpoint length encodings */
-#define X86_BREAKPOINT_LEN_X            0x00
+#define X86_BREAKPOINT_LEN_X            0x40
 #define X86_BREAKPOINT_LEN_1            0x40
 #define X86_BREAKPOINT_LEN_2            0x44
 #define X86_BREAKPOINT_LEN_4            0x4c
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 0925676266bd..fedf32a8c3ec 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -11,6 +11,8 @@ ifdef CONFIG_FUNCTION_TRACER
 CFLAGS_REMOVE_tsc.o = -pg
 CFLAGS_REMOVE_rtc.o = -pg
 CFLAGS_REMOVE_paravirt-spinlocks.o = -pg
+CFLAGS_REMOVE_pvclock.o = -pg
+CFLAGS_REMOVE_kvmclock.o = -pg
 CFLAGS_REMOVE_ftrace.o = -pg
 CFLAGS_REMOVE_early_printk.o = -pg
 endif
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index fb7a5f052e2b..fb16f17e59be 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -61,7 +61,7 @@ struct cstate_entry {
                 unsigned int ecx;
         } states[ACPI_PROCESSOR_MAX_POWER];
 };
-static struct cstate_entry *cpu_cstate_entry;   /* per CPU ptr */
+static struct cstate_entry __percpu *cpu_cstate_entry;  /* per CPU ptr */
 
 static short mwait_supported[ACPI_PROCESSOR_MAX_POWER];
 
diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c
index fa044e1e30a2..679b6450382b 100644
--- a/arch/x86/kernel/amd_iommu.c
+++ b/arch/x86/kernel/amd_iommu.c
@@ -1953,6 +1953,7 @@ static void __unmap_single(struct dma_ops_domain *dma_dom,
                            size_t size,
                            int dir)
 {
+        dma_addr_t flush_addr;
         dma_addr_t i, start;
         unsigned int pages;
 
@@ -1960,6 +1961,7 @@ static void __unmap_single(struct dma_ops_domain *dma_dom,
             (dma_addr + size > dma_dom->aperture_size))
                 return;
 
+        flush_addr = dma_addr;
         pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
         dma_addr &= PAGE_MASK;
         start = dma_addr;
@@ -1974,7 +1976,7 @@ static void __unmap_single(struct dma_ops_domain *dma_dom,
         dma_ops_free_addresses(dma_dom, dma_addr, pages);
 
         if (amd_iommu_unmap_flush || dma_dom->need_flush) {
-                iommu_flush_pages(&dma_dom->domain, dma_addr, size);
+                iommu_flush_pages(&dma_dom->domain, flush_addr, size);
                 dma_dom->need_flush = false;
         }
 }
diff --git a/arch/x86/kernel/amd_iommu_init.c b/arch/x86/kernel/amd_iommu_init.c
index 3cc63e2b8dd4..5a170cbbbed8 100644
--- a/arch/x86/kernel/amd_iommu_init.c
+++ b/arch/x86/kernel/amd_iommu_init.c
@@ -632,6 +632,13 @@ static void __init init_iommu_from_pci(struct amd_iommu *iommu)
         iommu->last_device = calc_devid(MMIO_GET_BUS(range),
                                         MMIO_GET_LD(range));
         iommu->evt_msi_num = MMIO_MSI_NUM(misc);
+
+        if (is_rd890_iommu(iommu->dev)) {
+                pci_read_config_dword(iommu->dev, 0xf0, &iommu->cache_cfg[0]);
+                pci_read_config_dword(iommu->dev, 0xf4, &iommu->cache_cfg[1]);
+                pci_read_config_dword(iommu->dev, 0xf8, &iommu->cache_cfg[2]);
+                pci_read_config_dword(iommu->dev, 0xfc, &iommu->cache_cfg[3]);
+        }
 }
 
 /*
@@ -649,29 +656,9 @@ static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
         struct ivhd_entry *e;
 
         /*
-         * First set the recommended feature enable bits from ACPI
-         * into the IOMMU control registers
+         * First save the recommended feature enable bits from ACPI
          */
-        h->flags & IVHD_FLAG_HT_TUN_EN_MASK ?
-                iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
-                iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
-
-        h->flags & IVHD_FLAG_PASSPW_EN_MASK ?
-                iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
-                iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
-
-        h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
-                iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
-                iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
-
-        h->flags & IVHD_FLAG_ISOC_EN_MASK ?
-                iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
-                iommu_feature_disable(iommu, CONTROL_ISOC_EN);
-
-        /*
-         * make IOMMU memory accesses cache coherent
-         */
-        iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
+        iommu->acpi_flags = h->flags;
 
         /*
          * Done. Now parse the device entries
@@ -1116,6 +1103,40 @@ static void init_device_table(void)
         }
 }
 
+static void iommu_init_flags(struct amd_iommu *iommu)
+{
+        iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
+                iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
+                iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
+
+        iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
+                iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
+                iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
+
+        iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
+                iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
+                iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
+
+        iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
+                iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
+                iommu_feature_disable(iommu, CONTROL_ISOC_EN);
+
+        /*
+         * make IOMMU memory accesses cache coherent
+         */
+        iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
+}
+
+static void iommu_apply_quirks(struct amd_iommu *iommu)
+{
+        if (is_rd890_iommu(iommu->dev)) {
+                pci_write_config_dword(iommu->dev, 0xf0, iommu->cache_cfg[0]);
+                pci_write_config_dword(iommu->dev, 0xf4, iommu->cache_cfg[1]);
+                pci_write_config_dword(iommu->dev, 0xf8, iommu->cache_cfg[2]);
+                pci_write_config_dword(iommu->dev, 0xfc, iommu->cache_cfg[3]);
+        }
+}
+
 /*
  * This function finally enables all IOMMUs found in the system after
  * they have been initialized
@@ -1126,6 +1147,8 @@ static void enable_iommus(void)
 
         for_each_iommu(iommu) {
                 iommu_disable(iommu);
+                iommu_apply_quirks(iommu);
+                iommu_init_flags(iommu);
                 iommu_set_device_table(iommu);
                 iommu_enable_command_buffer(iommu);
                 iommu_enable_event_buffer(iommu);
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index f1efebaf5510..5c5b8f3dddb5 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -306,14 +306,19 @@ void arch_init_copy_chip_data(struct irq_desc *old_desc,
 
         old_cfg = old_desc->chip_data;
 
-        memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
+        cfg->vector = old_cfg->vector;
+        cfg->move_in_progress = old_cfg->move_in_progress;
+        cpumask_copy(cfg->domain, old_cfg->domain);
+        cpumask_copy(cfg->old_domain, old_cfg->old_domain);
 
         init_copy_irq_2_pin(old_cfg, cfg, node);
 }
 
-static void free_irq_cfg(struct irq_cfg *old_cfg)
+static void free_irq_cfg(struct irq_cfg *cfg)
 {
-        kfree(old_cfg);
+        free_cpumask_var(cfg->domain);
+        free_cpumask_var(cfg->old_domain);
+        kfree(cfg);
 }
 
 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 490dac63c2d2..f2f9ac7da25c 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -545,7 +545,7 @@ void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
         }
 }
 
-static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
+void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 {
         u32 tfms, xlvl;
         u32 ebx;
diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h
index 3624e8a0f71b..f668bb1f7d43 100644
--- a/arch/x86/kernel/cpu/cpu.h
+++ b/arch/x86/kernel/cpu/cpu.h
@@ -33,5 +33,6 @@ extern const struct cpu_dev *const __x86_cpu_dev_start[],
                             *const __x86_cpu_dev_end[];
 
 extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);
+extern void get_cpu_cap(struct cpuinfo_x86 *c);
 
 #endif
diff --git a/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c
index 994230d4dc4e..4f6f679f2799 100644
--- a/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c
+++ b/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c
@@ -368,16 +368,22 @@ static int __init pcc_cpufreq_do_osc(acpi_handle *handle)
                 return -ENODEV;
 
         out_obj = output.pointer;
-        if (out_obj->type != ACPI_TYPE_BUFFER)
-                return -ENODEV;
+        if (out_obj->type != ACPI_TYPE_BUFFER) {
+                ret = -ENODEV;
+                goto out_free;
+        }
 
         errors = *((u32 *)out_obj->buffer.pointer) & ~(1 << 0);
-        if (errors)
-                return -ENODEV;
+        if (errors) {
+                ret = -ENODEV;
+                goto out_free;
+        }
 
         supported = *((u32 *)(out_obj->buffer.pointer + 4));
-        if (!(supported & 0x1))
-                return -ENODEV;
+        if (!(supported & 0x1)) {
+                ret = -ENODEV;
+                goto out_free;
+        }
 
 out_free:
         kfree(output.pointer);
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 85f69cdeae10..b4389441efbb 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -39,6 +39,7 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
                         misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
                         wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
                         c->cpuid_level = cpuid_eax(0);
+                        get_cpu_cap(c);
                 }
         }
 
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 3efdf2870a35..03a5b0385ad6 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -102,6 +102,7 @@ struct cpu_hw_events {
          */
         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
+        unsigned long           running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
         int                     enabled;
 
         int                     n_events;
@@ -1010,6 +1011,7 @@ static int x86_pmu_start(struct perf_event *event)
         x86_perf_event_set_period(event);
         cpuc->events[idx] = event;
         __set_bit(idx, cpuc->active_mask);
+        __set_bit(idx, cpuc->running);
         x86_pmu.enable(event);
         perf_event_update_userpage(event);
 
@@ -1141,8 +1143,16 @@ static int x86_pmu_handle_irq(struct pt_regs *regs)
         cpuc = &__get_cpu_var(cpu_hw_events);
 
         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
-                if (!test_bit(idx, cpuc->active_mask))
+                if (!test_bit(idx, cpuc->active_mask)) {
+                        /*
+                         * Though we deactivated the counter some cpus
+                         * might still deliver spurious interrupts still
+                         * in flight. Catch them:
+                         */
+                        if (__test_and_clear_bit(idx, cpuc->running))
+                                handled++;
                         continue;
+                }
 
                 event = cpuc->events[idx];
                 hwc = &event->hw;
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index b560db3305be..249015173992 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -660,8 +660,12 @@ static int p4_pmu_handle_irq(struct pt_regs *regs)
         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
                 int overflow;
 
-                if (!test_bit(idx, cpuc->active_mask))
+                if (!test_bit(idx, cpuc->active_mask)) {
+                        /* catch in-flight IRQs */
+                        if (__test_and_clear_bit(idx, cpuc->running))
+                                handled++;
                         continue;
+                }
 
                 event = cpuc->events[idx];
                 hwc = &event->hw;
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 34b4dad6f0b8..d49079515122 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -31,6 +31,7 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
         const struct cpuid_bit *cb;
 
         static const struct cpuid_bit __cpuinitconst cpuid_bits[] = {
+                { X86_FEATURE_DTS,              CR_EAX, 0, 0x00000006, 0 },
                 { X86_FEATURE_IDA,              CR_EAX, 1, 0x00000006, 0 },
                 { X86_FEATURE_ARAT,             CR_EAX, 2, 0x00000006, 0 },
                 { X86_FEATURE_PLN,              CR_EAX, 4, 0x00000006, 0 },
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 410fdb3f1939..7494999141b3 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -506,7 +506,7 @@ static int hpet_assign_irq(struct hpet_dev *dev)
 {
         unsigned int irq;
 
-        irq = create_irq();
+        irq = create_irq_nr(0, -1);
         if (!irq)
                 return -EINVAL;
 
diff --git a/arch/x86/kernel/hw_breakpoint.c b/arch/x86/kernel/hw_breakpoint.c
index a474ec37c32f..ff15c9dcc25d 100644
--- a/arch/x86/kernel/hw_breakpoint.c
+++ b/arch/x86/kernel/hw_breakpoint.c
@@ -206,11 +206,27 @@ int arch_check_bp_in_kernelspace(struct perf_event *bp)
 int arch_bp_generic_fields(int x86_len, int x86_type,
                            int *gen_len, int *gen_type)
 {
-        /* Len */
-        switch (x86_len) {
-        case X86_BREAKPOINT_LEN_X:
+        /* Type */
+        switch (x86_type) {
+        case X86_BREAKPOINT_EXECUTE:
+                if (x86_len != X86_BREAKPOINT_LEN_X)
+                        return -EINVAL;
+
+                *gen_type = HW_BREAKPOINT_X;
                 *gen_len = sizeof(long);
+                return 0;
+        case X86_BREAKPOINT_WRITE:
+                *gen_type = HW_BREAKPOINT_W;
                 break;
+        case X86_BREAKPOINT_RW:
+                *gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* Len */
+        switch (x86_len) {
         case X86_BREAKPOINT_LEN_1:
                 *gen_len = HW_BREAKPOINT_LEN_1;
                 break;
@@ -229,21 +245,6 @@ int arch_bp_generic_fields(int x86_len, int x86_type,
                 return -EINVAL;
         }
 
-        /* Type */
-        switch (x86_type) {
-        case X86_BREAKPOINT_EXECUTE:
-                *gen_type = HW_BREAKPOINT_X;
-                break;
-        case X86_BREAKPOINT_WRITE:
-                *gen_type = HW_BREAKPOINT_W;
-                break;
-        case X86_BREAKPOINT_RW:
-                *gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R;
-                break;
-        default:
-                return -EINVAL;
-        }
-
         return 0;
 }
 
@@ -316,9 +317,6 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
         ret = -EINVAL;
 
         switch (info->len) {
-        case X86_BREAKPOINT_LEN_X:
-                align = sizeof(long) -1;
-                break;
         case X86_BREAKPOINT_LEN_1:
                 align = 0;
                 break;
diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c
index e0bc186d7501..1c355c550960 100644
--- a/arch/x86/kernel/module.c
+++ b/arch/x86/kernel/module.c
@@ -239,11 +239,10 @@ int module_finalize(const Elf_Ehdr *hdr,
                 apply_paravirt(pseg, pseg + para->sh_size);
         }
 
-        return module_bug_finalize(hdr, sechdrs, me);
+        return 0;
 }
 
 void module_arch_cleanup(struct module *mod)
 {
         alternatives_smp_module_del(mod);
-        module_bug_cleanup(mod);
 }
diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c
index 9257510b4836..9d5f55848455 100644
--- a/arch/x86/lguest/boot.c
+++ b/arch/x86/lguest/boot.c
@@ -324,9 +324,8 @@ static void lguest_load_gdt(const struct desc_ptr *desc)
 }
 
 /*
- * For a single GDT entry which changes, we do the lazy thing: alter our GDT,
- * then tell the Host to reload the entire thing.  This operation is so rare
- * that this naive implementation is reasonable.
+ * For a single GDT entry which changes, we simply change our copy and
+ * then tell the host about it.
  */
 static void lguest_write_gdt_entry(struct desc_struct *dt, int entrynum,
                                    const void *desc, int type)
@@ -338,9 +337,13 @@ static void lguest_write_gdt_entry(struct desc_struct *dt, int entrynum,
 }
 
 /*
- * OK, I lied.  There are three "thread local storage" GDT entries which change
+ * There are three "thread local storage" GDT entries which change
  * on every context switch (these three entries are how glibc implements
- * __thread variables).  So we have a hypercall specifically for this case.
+ * __thread variables).  As an optimization, we have a hypercall
+ * specifically for this case.
+ *
+ * Wouldn't it be nicer to have a general LOAD_GDT_ENTRIES hypercall
+ * which took a range of entries?
  */
 static void lguest_load_tls(struct thread_struct *t, unsigned int cpu)
 {
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index cfe4faabb0f6..f1575c9a2572 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -671,7 +671,10 @@ static int __init ppro_init(char **cpu_type)
         case 14:
                 *cpu_type = "i386/core";
                 break;
-        case 15: case 23:
+        case 0x0f:
+        case 0x16:
+        case 0x17:
+        case 0x1d:
                 *cpu_type = "i386/core_2";
                 break;
         case 0x1a:
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index 1a5353a753fc..b2bb5aa3b054 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -489,8 +489,9 @@ static void xen_hvm_setup_cpu_clockevents(void)
 __init void xen_hvm_init_time_ops(void)
 {
         /* vector callback is needed otherwise we cannot receive interrupts
-         * on cpu > 0 */
-        if (!xen_have_vector_callback && num_present_cpus() > 1)
+         * on cpu > 0 and at this point we don't know how many cpus are
+         * available */
+        if (!xen_have_vector_callback)
                 return;
         if (!xen_feature(XENFEAT_hvm_safe_pvclock)) {
                 printk(KERN_INFO "Xen doesn't support pvclock on HVM,"