550 files changed, 11957 insertions, 10224 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3146ed3f6eca..9277237810e9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -29,6 +29,7 @@ config ARM
         select HAVE_GENERIC_HARDIRQS
         select HAVE_SPARSE_IRQ
         select GENERIC_IRQ_SHOW
+        select CPU_PM if (SUSPEND || CPU_IDLE)
         help
           The ARM series is a line of low-power-consumption RISC chip designs
           licensed by ARM Ltd and targeted at embedded applications and
@@ -830,6 +831,7 @@ config ARCH_U300
         select HAVE_SCHED_CLOCK
         select HAVE_TCM
         select ARM_AMBA
+        select ARM_PATCH_PHYS_VIRT
         select ARM_VIC
         select GENERIC_CLOCKEVENTS
         select CLKDEV_LOOKUP
@@ -1807,6 +1809,38 @@ config ZBOOT_ROM_SH_MOBILE_SDHI
 
 endchoice
 
+config ARM_APPENDED_DTB
+        bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
+        depends on OF && !ZBOOT_ROM && EXPERIMENTAL
+        help
+          With this option, the boot code will look for a device tree binary
+          (DTB) appended to zImage
+          (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
+
+          This is meant as a backward compatibility convenience for those
+          systems with a bootloader that can't be upgraded to accommodate
+          the documented boot protocol using a device tree.
+
+          Beware that there is very little in terms of protection against
+          this option being confused by leftover garbage in memory that might
+          look like a DTB header after a reboot if no actual DTB is appended
+          to zImage.  Do not leave this option active in a production kernel
+          if you don't intend to always append a DTB.  Proper passing of the
+          location into r2 of a bootloader provided DTB is always preferable
+          to this option.
+
+config ARM_ATAG_DTB_COMPAT
+        bool "Supplement the appended DTB with traditional ATAG information"
+        depends on ARM_APPENDED_DTB
+        help
+          Some old bootloaders can't be updated to a DTB capable one, yet
+          they provide ATAGs with memory configuration, the ramdisk address,
+          the kernel cmdline string, etc.  Such information is dynamically
+          provided by the bootloader and can't always be stored in a static
+          DTB.  To allow a device tree enabled kernel to be used with such
+          bootloaders, this option allows zImage to extract the information
+          from the ATAG list and store it at run time into the appended DTB.
+
 config CMDLINE
         string "Default kernel command string"
         default ""
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 81cbe40c159c..be3a0f78d915 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -129,4 +129,10 @@ config DEBUG_S3C_UART
           The uncompressor code port configuration is now handled
           by CONFIG_S3C_LOWLEVEL_UART_PORT.
 
+config ARM_KPROBES_TEST
+        tristate "Kprobes test module"
+        depends on KPROBES && MODULES
+        help
+          Perform tests of kprobes API and instruction set simulation.
+
 endmenu
diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore
index c6028967d336..e0936a148516 100644
--- a/arch/arm/boot/compressed/.gitignore
+++ b/arch/arm/boot/compressed/.gitignore
@@ -5,3 +5,12 @@ piggy.lzo
 piggy.lzma
 vmlinux
 vmlinux.lds
+
+# borrowed libfdt files
+fdt.c
+fdt.h
+fdt_ro.c
+fdt_rw.c
+fdt_wip.c
+libfdt.h
+libfdt_internal.h
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 0c74a6fab952..e4f32a8e002a 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -26,6 +26,10 @@ HEAD	= head.o
 OBJS    += misc.o decompress.o
 FONTC   = $(srctree)/drivers/video/console/font_acorn_8x8.c
 
+# string library code (-Os is enforced to keep it much smaller)
+OBJS            += string.o
+CFLAGS_string.o := -Os
+
 #
 # Architecture dependencies
 #
@@ -89,21 +93,41 @@ suffix_$(CONFIG_KERNEL_GZIP) = gzip
 suffix_$(CONFIG_KERNEL_LZO)  = lzo
 suffix_$(CONFIG_KERNEL_LZMA) = lzma
 
+# Borrowed libfdt files for the ATAG compatibility mode
+
+libfdt          := fdt_rw.c fdt_ro.c fdt_wip.c fdt.c
+libfdt_hdrs     := fdt.h libfdt.h libfdt_internal.h
+
+libfdt_objs     := $(addsuffix .o, $(basename $(libfdt)))
+
+$(addprefix $(obj)/,$(libfdt) $(libfdt_hdrs)): $(obj)/%: $(srctree)/scripts/dtc/libfdt/%
+        $(call cmd,shipped)
+
+$(addprefix $(obj)/,$(libfdt_objs) atags_to_fdt.o): \
+        $(addprefix $(obj)/,$(libfdt_hdrs))
+
+ifeq ($(CONFIG_ARM_ATAG_DTB_COMPAT),y)
+OBJS    += $(libfdt_objs) atags_to_fdt.o
+endif
+
 targets       := vmlinux vmlinux.lds \
                  piggy.$(suffix_y) piggy.$(suffix_y).o \
-                 font.o font.c head.o misc.o $(OBJS)
+                 lib1funcs.o lib1funcs.S font.o font.c head.o misc.o $(OBJS)
 
 # Make sure files are removed during clean
-extra-y       += piggy.gzip piggy.lzo piggy.lzma lib1funcs.S
+extra-y       += piggy.gzip piggy.lzo piggy.lzma lib1funcs.S $(libfdt) $(libfdt_hdrs)
 
 ifeq ($(CONFIG_FUNCTION_TRACER),y)
 ORIG_CFLAGS := $(KBUILD_CFLAGS)
 KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
 endif
 
-ccflags-y := -fpic -fno-builtin
+ccflags-y := -fpic -fno-builtin -I$(obj)
 asflags-y := -Wa,-march=all
 
+# Supply kernel BSS size to the decompressor via a linker symbol.
+KBSS_SZ = $(shell size $(obj)/../../../../vmlinux | awk 'END{print $$3}')
+LDFLAGS_vmlinux = --defsym _kernel_bss_size=$(KBSS_SZ)
 # Supply ZRELADDR to the decompressor via a linker symbol.
 ifneq ($(CONFIG_AUTO_ZRELADDR),y)
 LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR)
@@ -123,7 +147,7 @@ LDFLAGS_vmlinux += -T
 # For __aeabi_uidivmod
 lib1funcs = $(obj)/lib1funcs.o
 
-$(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE
+$(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S
         $(call cmd,shipped)
 
 # We need to prevent any GOTOFF relocs being used with references
diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c
new file mode 100644
index 000000000000..6ce11c481178
--- /dev/null
+++ b/arch/arm/boot/compressed/atags_to_fdt.c
@@ -0,0 +1,97 @@
+#include <asm/setup.h>
+#include <libfdt.h>
+
+static int node_offset(void *fdt, const char *node_path)
+{
+        int offset = fdt_path_offset(fdt, node_path);
+        if (offset == -FDT_ERR_NOTFOUND)
+                offset = fdt_add_subnode(fdt, 0, node_path);
+        return offset;
+}
+
+static int setprop(void *fdt, const char *node_path, const char *property,
+                   uint32_t *val_array, int size)
+{
+        int offset = node_offset(fdt, node_path);
+        if (offset < 0)
+                return offset;
+        return fdt_setprop(fdt, offset, property, val_array, size);
+}
+
+static int setprop_string(void *fdt, const char *node_path,
+                          const char *property, const char *string)
+{
+        int offset = node_offset(fdt, node_path);
+        if (offset < 0)
+                return offset;
+        return fdt_setprop_string(fdt, offset, property, string);
+}
+
+static int setprop_cell(void *fdt, const char *node_path,
+                        const char *property, uint32_t val)
+{
+        int offset = node_offset(fdt, node_path);
+        if (offset < 0)
+                return offset;
+        return fdt_setprop_cell(fdt, offset, property, val);
+}
+
+/*
+ * Convert and fold provided ATAGs into the provided FDT.
+ *
+ * REturn values:
+ *    = 0 -> pretend success
+ *    = 1 -> bad ATAG (may retry with another possible ATAG pointer)
+ *    < 0 -> error from libfdt
+ */
+int atags_to_fdt(void *atag_list, void *fdt, int total_space)
+{
+        struct tag *atag = atag_list;
+        uint32_t mem_reg_property[2 * NR_BANKS];
+        int memcount = 0;
+        int ret;
+
+        /* make sure we've got an aligned pointer */
+        if ((u32)atag_list & 0x3)
+                return 1;
+
+        /* if we get a DTB here we're done already */
+        if (*(u32 *)atag_list == fdt32_to_cpu(FDT_MAGIC))
+               return 0;
+
+        /* validate the ATAG */
+        if (atag->hdr.tag != ATAG_CORE ||
+            (atag->hdr.size != tag_size(tag_core) &&
+             atag->hdr.size != 2))
+                return 1;
+
+        /* let's give it all the room it could need */
+        ret = fdt_open_into(fdt, fdt, total_space);
+        if (ret < 0)
+                return ret;
+
+        for_each_tag(atag, atag_list) {
+                if (atag->hdr.tag == ATAG_CMDLINE) {
+                        setprop_string(fdt, "/chosen", "bootargs",
+                                        atag->u.cmdline.cmdline);
+                } else if (atag->hdr.tag == ATAG_MEM) {
+                        if (memcount >= sizeof(mem_reg_property)/4)
+                                continue;
+                        mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.start);
+                        mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.size);
+                } else if (atag->hdr.tag == ATAG_INITRD2) {
+                        uint32_t initrd_start, initrd_size;
+                        initrd_start = atag->u.initrd.start;
+                        initrd_size = atag->u.initrd.size;
+                        setprop_cell(fdt, "/chosen", "linux,initrd-start",
+                                        initrd_start);
+                        setprop_cell(fdt, "/chosen", "linux,initrd-end",
+                                        initrd_start + initrd_size);
+                }
+        }
+
+        if (memcount)
+                setprop(fdt, "/memory", "reg", mem_reg_property, 4*memcount);
+
+        return fdt_pack(fdt);
+}
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index e95a5989602a..9f5ac11ccd8e 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -216,6 +216,103 @@ restart:	adr	r0, LC0
                 mov     r10, r6
 #endif
 
+                mov     r5, #0                  @ init dtb size to 0
+#ifdef CONFIG_ARM_APPENDED_DTB
+/*
+ *   r0  = delta
+ *   r2  = BSS start
+ *   r3  = BSS end
+ *   r4  = final kernel address
+ *   r5  = appended dtb size (still unknown)
+ *   r6  = _edata
+ *   r7  = architecture ID
+ *   r8  = atags/device tree pointer
+ *   r9  = size of decompressed image
+ *   r10 = end of this image, including  bss/stack/malloc space if non XIP
+ *   r11 = GOT start
+ *   r12 = GOT end
+ *   sp  = stack pointer
+ *
+ * if there are device trees (dtb) appended to zImage, advance r10 so that the
+ * dtb data will get relocated along with the kernel if necessary.
+ */
+
+                ldr     lr, [r6, #0]
+#ifndef __ARMEB__
+                ldr     r1, =0xedfe0dd0         @ sig is 0xd00dfeed big endian
+#else
+                ldr     r1, =0xd00dfeed
+#endif
+                cmp     lr, r1
+                bne     dtb_check_done          @ not found
+
+#ifdef CONFIG_ARM_ATAG_DTB_COMPAT
+                /*
+                 * OK... Let's do some funky business here.
+                 * If we do have a DTB appended to zImage, and we do have
+                 * an ATAG list around, we want the later to be translated
+                 * and folded into the former here.  To be on the safe side,
+                 * let's temporarily move  the stack away into the malloc
+                 * area.  No GOT fixup has occurred yet, but none of the
+                 * code we're about to call uses any global variable.
+                */
+                add     sp, sp, #0x10000
+                stmfd   sp!, {r0-r3, ip, lr}
+                mov     r0, r8
+                mov     r1, r6
+                sub     r2, sp, r6
+                bl      atags_to_fdt
+
+                /*
+                 * If returned value is 1, there is no ATAG at the location
+                 * pointed by r8.  Try the typical 0x100 offset from start
+                 * of RAM and hope for the best.
+                 */
+                cmp     r0, #1
+                sub     r0, r4, #(TEXT_OFFSET - 0x100)
+                mov     r1, r6
+                sub     r2, sp, r6
+                blne    atags_to_fdt
+
+                ldmfd   sp!, {r0-r3, ip, lr}
+                sub     sp, sp, #0x10000
+#endif
+
+                mov     r8, r6                  @ use the appended device tree
+
+                /*
+                 * Make sure that the DTB doesn't end up in the final
+                 * kernel's .bss area. To do so, we adjust the decompressed
+                 * kernel size to compensate if that .bss size is larger
+                 * than the relocated code.
+                 */
+                ldr     r5, =_kernel_bss_size
+                adr     r1, wont_overwrite
+                sub     r1, r6, r1
+                subs    r1, r5, r1
+                addhi   r9, r9, r1
+
+                /* Get the dtb's size */
+                ldr     r5, [r6, #4]
+#ifndef __ARMEB__
+                /* convert r5 (dtb size) to little endian */
+                eor     r1, r5, r5, ror #16
+                bic     r1, r1, #0x00ff0000
+                mov     r5, r5, ror #8
+                eor     r5, r5, r1, lsr #8
+#endif
+
+                /* preserve 64-bit alignment */
+                add     r5, r5, #7
+                bic     r5, r5, #7
+
+                /* relocate some pointers past the appended dtb */
+                add     r6, r6, r5
+                add     r10, r10, r5
+                add     sp, sp, r5
+dtb_check_done:
+#endif
+
 /*
  * Check to see if we will overwrite ourselves.
  *   r4  = final kernel address
@@ -223,15 +320,14 @@ restart:	adr	r0, LC0
  *   r10 = end of this image, including  bss/stack/malloc space if non XIP
  * We basically want:
  *   r4 - 16k page directory >= r10 -> OK
- *   r4 + image length <= current position (pc) -> OK
+ *   r4 + image length <= address of wont_overwrite -> OK
  */
                 add     r10, r10, #16384
                 cmp     r4, r10
                 bhs     wont_overwrite
                 add     r10, r4, r9
-   ARM(         cmp     r10, pc         )
- THUMB(         mov     lr, pc          )
- THUMB(         cmp     r10, lr         )
+                adr     r9, wont_overwrite
+                cmp     r10, r9
                 bls     wont_overwrite
 
 /*
@@ -285,14 +381,16 @@ wont_overwrite:
  *   r2  = BSS start
  *   r3  = BSS end
  *   r4  = kernel execution address
+ *   r5  = appended dtb size (0 if not present)
  *   r7  = architecture ID
  *   r8  = atags pointer
  *   r11 = GOT start
  *   r12 = GOT end
  *   sp  = stack pointer
  */
-                teq     r0, #0
+                orrs    r1, r0, r5
                 beq     not_relocated
+
                 add     r11, r11, r0
                 add     r12, r12, r0
 
@@ -307,12 +405,21 @@ wont_overwrite:
 
                 /*
                  * Relocate all entries in the GOT table.
+                 * Bump bss entries to _edata + dtb size
                  */
 1:              ldr     r1, [r11, #0]           @ relocate entries in the GOT
-                add     r1, r1, r0              @ table.  This fixes up the
-                str     r1, [r11], #4           @ C references.
+                add     r1, r1, r0              @ This fixes up C references
+                cmp     r1, r2                  @ if entry >= bss_start &&
+                cmphs   r3, r1                  @       bss_end > entry
+                addhi   r1, r1, r5              @    entry += dtb size
+                str     r1, [r11], #4           @ next entry
                 cmp     r11, r12
                 blo     1b
+
+                /* bump our bss pointers too */
+                add     r2, r2, r5
+                add     r3, r3, r5
+
 #else
 
                 /*
diff --git a/arch/arm/boot/compressed/libfdt_env.h b/arch/arm/boot/compressed/libfdt_env.h
new file mode 100644
index 000000000000..1f4e71876b00
--- /dev/null
+++ b/arch/arm/boot/compressed/libfdt_env.h
@@ -0,0 +1,15 @@
+#ifndef _ARM_LIBFDT_ENV_H
+#define _ARM_LIBFDT_ENV_H
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <asm/byteorder.h>
+
+#define fdt16_to_cpu(x)         be16_to_cpu(x)
+#define cpu_to_fdt16(x)         cpu_to_be16(x)
+#define fdt32_to_cpu(x)         be32_to_cpu(x)
+#define cpu_to_fdt32(x)         cpu_to_be32(x)
+#define fdt64_to_cpu(x)         be64_to_cpu(x)
+#define cpu_to_fdt64(x)         cpu_to_be64(x)
+
+#endif
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 832d37236c59..8e2a8fca5ed2 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -18,14 +18,9 @@
 
 unsigned int __machine_arch_type;
 
-#define _LINUX_STRING_H_
-
 #include <linux/compiler.h>     /* for inline */
-#include <linux/types.h>        /* for size_t */
-#include <linux/stddef.h>       /* for NULL */
+#include <linux/types.h>
 #include <linux/linkage.h>
-#include <asm/string.h>
-
 
 static void putstr(const char *ptr);
 extern void error(char *x);
@@ -101,41 +96,6 @@ static void putstr(const char *ptr)
         flush();
 }
 
-
-void *memcpy(void *__dest, __const void *__src, size_t __n)
-{
-        int i = 0;
-        unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src;
-
-        for (i = __n >> 3; i > 0; i--) {
-                *d++ = *s++;
-                *d++ = *s++;
-                *d++ = *s++;
-                *d++ = *s++;
-                *d++ = *s++;
-                *d++ = *s++;
-                *d++ = *s++;
-                *d++ = *s++;
-        }
-
-        if (__n & 1 << 2) {
-                *d++ = *s++;
-                *d++ = *s++;
-                *d++ = *s++;
-                *d++ = *s++;
-        }
-
-        if (__n & 1 << 1) {
-                *d++ = *s++;
-                *d++ = *s++;
-        }
-
-        if (__n & 1)
-                *d++ = *s++;
-
-        return __dest;
-}
-
 /*
  * gzip declarations
  */
diff --git a/arch/arm/boot/compressed/string.c b/arch/arm/boot/compressed/string.c
new file mode 100644
index 000000000000..36e53ef9200f
--- /dev/null
+++ b/arch/arm/boot/compressed/string.c
@@ -0,0 +1,127 @@
+/*
+ * arch/arm/boot/compressed/string.c
+ *
+ * Small subset of simple string routines
+ */
+
+#include <linux/string.h>
+
+void *memcpy(void *__dest, __const void *__src, size_t __n)
+{
+        int i = 0;
+        unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src;
+
+        for (i = __n >> 3; i > 0; i--) {
+                *d++ = *s++;
+                *d++ = *s++;
+                *d++ = *s++;
+                *d++ = *s++;
+                *d++ = *s++;
+                *d++ = *s++;
+                *d++ = *s++;
+                *d++ = *s++;
+        }
+
+        if (__n & 1 << 2) {
+                *d++ = *s++;
+                *d++ = *s++;
+                *d++ = *s++;
+                *d++ = *s++;
+        }
+
+        if (__n & 1 << 1) {
+                *d++ = *s++;
+                *d++ = *s++;
+        }
+
+        if (__n & 1)
+                *d++ = *s++;
+
+        return __dest;
+}
+
+void *memmove(void *__dest, __const void *__src, size_t count)
+{
+        unsigned char *d = __dest;
+        const unsigned char *s = __src;
+
+        if (__dest == __src)
+                return __dest;
+
+        if (__dest < __src)
+                return memcpy(__dest, __src, count);
+
+        while (count--)
+                d[count] = s[count];
+        return __dest;
+}
+
+size_t strlen(const char *s)
+{
+        const char *sc = s;
+
+        while (*sc != '\0')
+                sc++;
+        return sc - s;
+}
+
+int memcmp(const void *cs, const void *ct, size_t count)
+{
+        const unsigned char *su1 = cs, *su2 = ct, *end = su1 + count;
+        int res = 0;
+
+        while (su1 < end) {
+                res = *su1++ - *su2++;
+                if (res)
+                        break;
+        }
+        return res;
+}
+
+int strcmp(const char *cs, const char *ct)
+{
+        unsigned char c1, c2;
+        int res = 0;
+
+        do {
+                c1 = *cs++;
+                c2 = *ct++;
+                res = c1 - c2;
+                if (res)
+                        break;
+        } while (c1);
+        return res;
+}
+
+void *memchr(const void *s, int c, size_t count)
+{
+        const unsigned char *p = s;
+
+        while (count--)
+                if ((unsigned char)c == *p++)
+                        return (void *)(p - 1);
+        return NULL;
+}
+
+char *strchr(const char *s, int c)
+{
+        while (*s != (char)c)
+                if (*s++ == '\0')
+                        return NULL;
+        return (char *)s;
+}
+
+#undef memset
+
+void *memset(void *s, int c, size_t count)
+{
+        char *xs = s;
+        while (count--)
+                *xs++ = c;
+        return s;
+}
+
+void __memzero(void *s, size_t count)
+{
+        memset(s, 0, count);
+}
diff --git a/arch/arm/boot/compressed/vmlinux.lds.in b/arch/arm/boot/compressed/vmlinux.lds.in
index 4e728834a1b9..4919f2ac8b89 100644
--- a/arch/arm/boot/compressed/vmlinux.lds.in
+++ b/arch/arm/boot/compressed/vmlinux.lds.in
@@ -51,6 +51,10 @@ SECTIONS
   _got_start = .;
   .got                  : { *(.got) }
   _got_end = .;
+
+  /* ensure the zImage file size is always a multiple of 64 bits */
+  /* (without a dummy byte, ld just ignores the empty section) */
+  .pad                  : { BYTE(0); . = ALIGN(8); }
   _edata = .;
 
   . = BSS_START;
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 3227ca952a12..734db99eaee7 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -26,6 +26,7 @@
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/smp.h>
+#include <linux/cpu_pm.h>
 #include <linux/cpumask.h>
 #include <linux/io.h>
 
@@ -276,6 +277,8 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
         if (gic_irqs > 1020)
                 gic_irqs = 1020;
 
+        gic->gic_irqs = gic_irqs;
+
         /*
          * Set all global interrupts to be level triggered, active low.
          */
@@ -343,6 +346,189 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
         writel_relaxed(1, base + GIC_CPU_CTRL);
 }
 
+#ifdef CONFIG_CPU_PM
+/*
+ * Saves the GIC distributor registers during suspend or idle.  Must be called
+ * with interrupts disabled but before powering down the GIC.  After calling
+ * this function, no interrupts will be delivered by the GIC, and another
+ * platform-specific wakeup source must be enabled.
+ */
+static void gic_dist_save(unsigned int gic_nr)
+{
+        unsigned int gic_irqs;
+        void __iomem *dist_base;
+        int i;
+
+        if (gic_nr >= MAX_GIC_NR)
+                BUG();
+
+        gic_irqs = gic_data[gic_nr].gic_irqs;
+        dist_base = gic_data[gic_nr].dist_base;
+
+        if (!dist_base)
+                return;
+
+        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
+                gic_data[gic_nr].saved_spi_conf[i] =
+                        readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
+
+        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+                gic_data[gic_nr].saved_spi_target[i] =
+                        readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
+
+        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
+                gic_data[gic_nr].saved_spi_enable[i] =
+                        readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
+}
+
+/*
+ * Restores the GIC distributor registers during resume or when coming out of
+ * idle.  Must be called before enabling interrupts.  If a level interrupt
+ * that occured while the GIC was suspended is still present, it will be
+ * handled normally, but any edge interrupts that occured will not be seen by
+ * the GIC and need to be handled by the platform-specific wakeup source.
+ */
+static void gic_dist_restore(unsigned int gic_nr)
+{
+        unsigned int gic_irqs;
+        unsigned int i;
+        void __iomem *dist_base;
+
+        if (gic_nr >= MAX_GIC_NR)
+                BUG();
+
+        gic_irqs = gic_data[gic_nr].gic_irqs;
+        dist_base = gic_data[gic_nr].dist_base;
+
+        if (!dist_base)
+                return;
+
+        writel_relaxed(0, dist_base + GIC_DIST_CTRL);
+
+        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
+                writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
+                        dist_base + GIC_DIST_CONFIG + i * 4);
+
+        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+                writel_relaxed(0xa0a0a0a0,
+                        dist_base + GIC_DIST_PRI + i * 4);
+
+        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+                writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
+                        dist_base + GIC_DIST_TARGET + i * 4);
+
+        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
+                writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
+                        dist_base + GIC_DIST_ENABLE_SET + i * 4);
+
+        writel_relaxed(1, dist_base + GIC_DIST_CTRL);
+}
+
+static void gic_cpu_save(unsigned int gic_nr)
+{
+        int i;
+        u32 *ptr;
+        void __iomem *dist_base;
+        void __iomem *cpu_base;
+
+        if (gic_nr >= MAX_GIC_NR)
+                BUG();
+
+        dist_base = gic_data[gic_nr].dist_base;
+        cpu_base = gic_data[gic_nr].cpu_base;
+
+        if (!dist_base || !cpu_base)
+                return;
+
+        ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
+        for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
+                ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
+
+        ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
+        for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
+                ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
+
+}
+
+static void gic_cpu_restore(unsigned int gic_nr)
+{
+        int i;
+        u32 *ptr;
+        void __iomem *dist_base;
+        void __iomem *cpu_base;
+
+        if (gic_nr >= MAX_GIC_NR)
+                BUG();
+
+        dist_base = gic_data[gic_nr].dist_base;
+        cpu_base = gic_data[gic_nr].cpu_base;
+
+        if (!dist_base || !cpu_base)
+                return;
+
+        ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
+        for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
+                writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
+
+        ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
+        for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
+                writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
+
+        for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
+                writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
+
+        writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
+        writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
+}
+
+static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
+{
+        int i;
+
+        for (i = 0; i < MAX_GIC_NR; i++) {
+                switch (cmd) {
+                case CPU_PM_ENTER:
+                        gic_cpu_save(i);
+                        break;
+                case CPU_PM_ENTER_FAILED:
+                case CPU_PM_EXIT:
+                        gic_cpu_restore(i);
+                        break;
+                case CPU_CLUSTER_PM_ENTER:
+                        gic_dist_save(i);
+                        break;
+                case CPU_CLUSTER_PM_ENTER_FAILED:
+                case CPU_CLUSTER_PM_EXIT:
+                        gic_dist_restore(i);
+                        break;
+                }
+        }
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block gic_notifier_block = {
+        .notifier_call = gic_notifier,
+};
+
+static void __init gic_pm_init(struct gic_chip_data *gic)
+{
+        gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
+                sizeof(u32));
+        BUG_ON(!gic->saved_ppi_enable);
+
+        gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
+                sizeof(u32));
+        BUG_ON(!gic->saved_ppi_conf);
+
+        cpu_pm_register_notifier(&gic_notifier_block);
+}
+#else
+static void __init gic_pm_init(struct gic_chip_data *gic)
+{
+}
+#endif
+
 void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
         void __iomem *dist_base, void __iomem *cpu_base)
 {
@@ -358,8 +544,10 @@ void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
         if (gic_nr == 0)
                 gic_cpu_base_addr = cpu_base;
 
+        gic_chip.flags |= gic_arch_extn.flags;
         gic_dist_init(gic, irq_start);
         gic_cpu_init(gic);
+        gic_pm_init(gic);
 }
 
 void __cpuinit gic_secondary_init(unsigned int gic_nr)
diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h
index 9f390ce335cb..b5c9f5b1f6a3 100644
--- a/arch/arm/include/asm/device.h
+++ b/arch/arm/include/asm/device.h
@@ -12,7 +12,12 @@ struct dev_archdata {
 #endif
 };
 
+struct omap_device;
+
 struct pdev_archdata {
+#ifdef CONFIG_ARCH_OMAP
+        struct omap_device *od;
+#endif
 };
 
 #endif
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 7a21d0bf7134..7f27fab9d404 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -205,6 +205,13 @@ extern void *dma_alloc_writecombine(struct device *, size_t, dma_addr_t *,
 int dma_mmap_writecombine(struct device *, struct vm_area_struct *,
                 void *, dma_addr_t, size_t);
 
+/*
+ * This can be called during boot to increase the size of the consistent
+ * DMA region above it's default value of 2MB. It must be called before the
+ * memory allocator is initialised, i.e. before any core_initcall.
+ */
+extern void __init init_consistent_dma_size(unsigned long size);
+
 
 #ifdef CONFIG_DMABOUNCE
 /*
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 435d3f86c708..c5627057b1c7 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -46,6 +46,14 @@ struct gic_chip_data {
         unsigned int irq_offset;
         void __iomem *dist_base;
         void __iomem *cpu_base;
+#ifdef CONFIG_CPU_PM
+        u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
+        u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
+        u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
+        u32 __percpu *saved_ppi_enable;
+        u32 __percpu *saved_ppi_conf;
+#endif
+        unsigned int gic_irqs;
 };
 #endif
 
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
index f389b2704d82..c190bc992f0e 100644
--- a/arch/arm/include/asm/hw_breakpoint.h
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -50,6 +50,7 @@ static inline void decode_ctrl_reg(u32 reg,
 #define ARM_DEBUG_ARCH_V6_1     2
 #define ARM_DEBUG_ARCH_V7_ECP14 3
 #define ARM_DEBUG_ARCH_V7_MM    4
+#define ARM_DEBUG_ARCH_V7_1     5
 
 /* Breakpoint */
 #define ARM_BREAKPOINT_EXECUTE  0
@@ -57,6 +58,7 @@ static inline void decode_ctrl_reg(u32 reg,
 /* Watchpoints */
 #define ARM_BREAKPOINT_LOAD     1
 #define ARM_BREAKPOINT_STORE    2
+#define ARM_FSR_ACCESS_MASK     (1 << 11)
 
 /* Privilege Levels */
 #define ARM_BREAKPOINT_PRIV     1
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 217aa1911dd7..727da118bcc1 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -17,7 +17,7 @@ struct sys_timer;
 struct machine_desc {
         unsigned int            nr;             /* architecture number  */
         const char              *name;          /* architecture name    */
-        unsigned long           boot_params;    /* tagged list          */
+        unsigned long           atag_offset;    /* tagged list (relative) */
         const char              **dt_compat;    /* array of device tree
                                                  * 'compatible' strings */
 
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index d2fedb5aeb1f..b36f3654bf54 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -29,6 +29,7 @@ struct map_desc {
 #define MT_MEMORY_NONCACHED     11
 #define MT_MEMORY_DTCM          12
 #define MT_MEMORY_ITCM          13
+#define MT_MEMORY_SO            14
 
 #ifdef CONFIG_MMU
 extern void iotable_init(struct map_desc *, int);
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index b8de516e600e..652fccca4952 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -77,16 +77,7 @@
  */
 #define IOREMAP_MAX_ORDER       24
 
-/*
- * Size of DMA-consistent memory region.  Must be multiple of 2M,
- * between 2MB and 14MB inclusive.
- */
-#ifndef CONSISTENT_DMA_SIZE
-#define CONSISTENT_DMA_SIZE     SZ_2M
-#endif
-
 #define CONSISTENT_END          (0xffe00000UL)
-#define CONSISTENT_BASE         (CONSISTENT_END - CONSISTENT_DMA_SIZE)
 
 #else /* CONFIG_MMU */
 
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 5750704e0271..f1956b27ae5a 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -232,6 +232,9 @@ extern pgprot_t		pgprot_kernel;
 #define pgprot_writecombine(prot) \
         __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
 
+#define pgprot_stronglyordered(prot) \
+        __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
+
 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 #define pgprot_dmacoherent(prot) \
         __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index b7e82c4aced6..71d99b83cdb9 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -13,7 +13,12 @@
 #define __ARM_PMU_H__
 
 #include <linux/interrupt.h>
+#include <linux/perf_event.h>
 
+/*
+ * Types of PMUs that can be accessed directly and require mutual
+ * exclusion between profiling tools.
+ */
 enum arm_pmu_type {
         ARM_PMU_DEVICE_CPU      = 0,
         ARM_NUM_PMU_DEVICES,
@@ -37,21 +42,17 @@ struct arm_pmu_platdata {
  * reserve_pmu() - reserve the hardware performance counters
  *
  * Reserve the hardware performance counters in the system for exclusive use.
- * The platform_device for the system is returned on success, ERR_PTR()
- * encoded error on failure.
+ * Returns 0 on success or -EBUSY if the lock is already held.
  */
-extern struct platform_device *
+extern int
 reserve_pmu(enum arm_pmu_type type);
 
 /**
  * release_pmu() - Relinquish control of the performance counters
  *
  * Release the performance counters and allow someone else to use them.
- * Callers must have disabled the counters and released IRQs before calling
- * this. The platform_device returned from reserve_pmu() must be passed as
- * a cookie.
  */
-extern int
+extern void
 release_pmu(enum arm_pmu_type type);
 
 /**
@@ -68,24 +69,78 @@ init_pmu(enum arm_pmu_type type);
 
 #include <linux/err.h>
 
-static inline struct platform_device *
-reserve_pmu(enum arm_pmu_type type)
-{
-        return ERR_PTR(-ENODEV);
-}
-
 static inline int
-release_pmu(enum arm_pmu_type type)
+reserve_pmu(enum arm_pmu_type type)
 {
         return -ENODEV;
 }
 
-static inline int
-init_pmu(enum arm_pmu_type type)
-{
-        return -ENODEV;
-}
+static inline void
+release_pmu(enum arm_pmu_type type)     { }
 
 #endif /* CONFIG_CPU_HAS_PMU */
 
+#ifdef CONFIG_HW_PERF_EVENTS
+
+/* The events for a given PMU register set. */
+struct pmu_hw_events {
+        /*
+         * The events that are active on the PMU for the given index.
+         */
+        struct perf_event       **events;
+
+        /*
+         * A 1 bit for an index indicates that the counter is being used for
+         * an event. A 0 means that the counter can be used.
+         */
+        unsigned long           *used_mask;
+
+        /*
+         * Hardware lock to serialize accesses to PMU registers. Needed for the
+         * read/modify/write sequences.
+         */
+        raw_spinlock_t          pmu_lock;
+};
+
+struct arm_pmu {
+        struct pmu      pmu;
+        enum arm_perf_pmu_ids id;
+        enum arm_pmu_type type;
+        cpumask_t       active_irqs;
+        const char      *name;
+        irqreturn_t     (*handle_irq)(int irq_num, void *dev);
+        void            (*enable)(struct hw_perf_event *evt, int idx);
+        void            (*disable)(struct hw_perf_event *evt, int idx);
+        int             (*get_event_idx)(struct pmu_hw_events *hw_events,
+                                         struct hw_perf_event *hwc);
+        int             (*set_event_filter)(struct hw_perf_event *evt,
+                                            struct perf_event_attr *attr);
+        u32             (*read_counter)(int idx);
+        void            (*write_counter)(int idx, u32 val);
+        void            (*start)(void);
+        void            (*stop)(void);
+        void            (*reset)(void *);
+        int             (*map_event)(struct perf_event *event);
+        int             num_events;
+        atomic_t        active_events;
+        struct mutex    reserve_mutex;
+        u64             max_period;
+        struct platform_device  *plat_device;
+        struct pmu_hw_events    *(*get_hw_events)(void);
+};
+
+#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
+
+int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
+
+u64 armpmu_event_update(struct perf_event *event,
+                        struct hw_perf_event *hwc,
+                        int idx, int overflow);
+
+int armpmu_event_set_period(struct perf_event *event,
+                            struct hw_perf_event *hwc,
+                            int idx);
+
+#endif /* CONFIG_HW_PERF_EVENTS */
+
 #endif /* __ARM_PMU_H__ */
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index 633d1cb84d87..9e92cb205e65 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -81,6 +81,10 @@ extern void cpu_dcache_clean_area(void *, int);
 extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
 extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext);
 extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
+
+/* These three are private to arch/arm/kernel/suspend.c */
+extern void cpu_do_suspend(void *);
+extern void cpu_do_resume(void *);
 #else
 #define cpu_proc_init                   processor._proc_init
 #define cpu_proc_fin                    processor._proc_fin
@@ -89,6 +93,10 @@ extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
 #define cpu_dcache_clean_area           processor.dcache_clean_area
 #define cpu_set_pte_ext                 processor.set_pte_ext
 #define cpu_do_switch_mm                processor.switch_mm
+
+/* These three are private to arch/arm/kernel/suspend.c */
+#define cpu_do_suspend                  processor.do_suspend
+#define cpu_do_resume                   processor.do_resume
 #endif
 
 extern void cpu_resume(void);
diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h
index b0e4e1a02318..1c0a551ae375 100644
--- a/arch/arm/include/asm/suspend.h
+++ b/arch/arm/include/asm/suspend.h
@@ -1,22 +1,7 @@
 #ifndef __ASM_ARM_SUSPEND_H
 #define __ASM_ARM_SUSPEND_H
 
-#include <asm/memory.h>
-#include <asm/tlbflush.h>
-
 extern void cpu_resume(void);
-
-/*
- * Hide the first two arguments to __cpu_suspend - these are an implementation
- * detail which platform code shouldn't have to know about.
- */
-static inline int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
-{
-        extern int __cpu_suspend(int, long, unsigned long,
-                                 int (*)(unsigned long));
-        int ret = __cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);
-        flush_tlb_all();
-        return ret;
-}
+extern int cpu_suspend(unsigned long, int (*)(unsigned long));
 
 #endif
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index f7887dc53c1f..8fa83f54c967 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -29,7 +29,7 @@ obj-$(CONFIG_MODULES)		+= armksyms.o module.o
 obj-$(CONFIG_ARTHUR)            += arthur.o
 obj-$(CONFIG_ISA_DMA)           += dma-isa.o
 obj-$(CONFIG_PCI)               += bios32.o isa.o
-obj-$(CONFIG_PM_SLEEP)          += sleep.o
+obj-$(CONFIG_PM_SLEEP)          += sleep.o suspend.o
 obj-$(CONFIG_HAVE_SCHED_CLOCK)  += sched_clock.o
 obj-$(CONFIG_SMP)               += smp.o smp_tlb.o
 obj-$(CONFIG_HAVE_ARM_SCU)      += smp_scu.o
@@ -43,6 +43,13 @@ obj-$(CONFIG_KPROBES)		+= kprobes-thumb.o
 else
 obj-$(CONFIG_KPROBES)           += kprobes-arm.o
 endif
+obj-$(CONFIG_ARM_KPROBES_TEST)  += test-kprobes.o
+test-kprobes-objs               := kprobes-test.o
+ifdef CONFIG_THUMB2_KERNEL
+test-kprobes-objs               += kprobes-test-thumb.o
+else
+test-kprobes-objs               += kprobes-test-arm.o
+endif
 obj-$(CONFIG_ATAGS_PROC)        += atags.o
 obj-$(CONFIG_OABI_COMPAT)       += sys_oabi-compat.o
 obj-$(CONFIG_ARM_THUMBEE)       += thumbee.o
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index a927ca1f5566..5a46225f007e 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -45,7 +45,6 @@ static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
 
 /* Number of BRP/WRP registers on this CPU. */
 static int core_num_brps;
-static int core_num_reserved_brps;
 static int core_num_wrps;
 
 /* Debug architecture version. */
@@ -137,10 +136,11 @@ static u8 get_debug_arch(void)
         u32 didr;
 
         /* Do we implement the extended CPUID interface? */
-        if (WARN_ONCE((((read_cpuid_id() >> 16) & 0xf) != 0xf),
-            "CPUID feature registers not supported. "
-            "Assuming v6 debug is present.\n"))
+        if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
+                pr_warning("CPUID feature registers not supported. "
+                           "Assuming v6 debug is present.\n");
                 return ARM_DEBUG_ARCH_V6;
+        }
 
         ARM_DBG_READ(c0, 0, didr);
         return (didr >> 16) & 0xf;
@@ -154,10 +154,21 @@ u8 arch_get_debug_arch(void)
 static int debug_arch_supported(void)
 {
         u8 arch = get_debug_arch();
-        return arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14;
+
+        /* We don't support the memory-mapped interface. */
+        return (arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14) ||
+                arch >= ARM_DEBUG_ARCH_V7_1;
+}
+
+/* Determine number of WRP registers available. */
+static int get_num_wrp_resources(void)
+{
+        u32 didr;
+        ARM_DBG_READ(c0, 0, didr);
+        return ((didr >> 28) & 0xf) + 1;
 }
 
-/* Determine number of BRP register available. */
+/* Determine number of BRP registers available. */
 static int get_num_brp_resources(void)
 {
         u32 didr;
@@ -176,9 +187,10 @@ static int core_has_mismatch_brps(void)
 static int get_num_wrps(void)
 {
         /*
-         * FIXME: When a watchpoint fires, the only way to work out which
-         * watchpoint it was is by disassembling the faulting instruction
-         * and working out the address of the memory access.
+         * On debug architectures prior to 7.1, when a watchpoint fires, the
+         * only way to work out which watchpoint it was is by disassembling
+         * the faulting instruction and working out the address of the memory
+         * access.
          *
          * Furthermore, we can only do this if the watchpoint was precise
          * since imprecise watchpoints prevent us from calculating register
@@ -192,36 +204,17 @@ static int get_num_wrps(void)
          * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows
          * that it is set on some implementations].
          */
+        if (get_debug_arch() < ARM_DEBUG_ARCH_V7_1)
+                return 1;
 
-#if 0
-        int wrps;
-        u32 didr;
-        ARM_DBG_READ(c0, 0, didr);
-        wrps = ((didr >> 28) & 0xf) + 1;
-#endif
-        int wrps = 1;
-
-        if (core_has_mismatch_brps() && wrps >= get_num_brp_resources())
-                wrps = get_num_brp_resources() - 1;
-
-        return wrps;
-}
-
-/* We reserve one breakpoint for each watchpoint. */
-static int get_num_reserved_brps(void)
-{
-        if (core_has_mismatch_brps())
-                return get_num_wrps();
-        return 0;
+        return get_num_wrp_resources();
 }
 
 /* Determine number of usable BRPs available. */
 static int get_num_brps(void)
 {
         int brps = get_num_brp_resources();
-        if (core_has_mismatch_brps())
-                brps -= get_num_reserved_brps();
-        return brps;
+        return core_has_mismatch_brps() ? brps - 1 : brps;
 }
 
 /*
@@ -239,7 +232,7 @@ static int enable_monitor_mode(void)
 
         /* Ensure that halting mode is disabled. */
         if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN,
-                        "halting debug mode enabled. Unable to access hardware resources.\n")) {
+                "halting debug mode enabled. Unable to access hardware resources.\n")) {
                 ret = -EPERM;
                 goto out;
         }
@@ -255,6 +248,7 @@ static int enable_monitor_mode(void)
                 ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN));
                 break;
         case ARM_DEBUG_ARCH_V7_ECP14:
+        case ARM_DEBUG_ARCH_V7_1:
                 ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN));
                 break;
         default:
@@ -346,24 +340,10 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
                 val_base = ARM_BASE_BVR;
                 slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
                 max_slots = core_num_brps;
-                if (info->step_ctrl.enabled) {
-                        /* Override the breakpoint data with the step data. */
-                        addr = info->trigger & ~0x3;
-                        ctrl = encode_ctrl_reg(info->step_ctrl);
-                }
         } else {
                 /* Watchpoint */
-                if (info->step_ctrl.enabled) {
-                        /* Install into the reserved breakpoint region. */
-                        ctrl_base = ARM_BASE_BCR + core_num_brps;
-                        val_base = ARM_BASE_BVR + core_num_brps;
-                        /* Override the watchpoint data with the step data. */
-                        addr = info->trigger & ~0x3;
-                        ctrl = encode_ctrl_reg(info->step_ctrl);
-                } else {
-                        ctrl_base = ARM_BASE_WCR;
-                        val_base = ARM_BASE_WVR;
-                }
+                ctrl_base = ARM_BASE_WCR;
+                val_base = ARM_BASE_WVR;
                 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
                 max_slots = core_num_wrps;
         }
@@ -382,6 +362,17 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
                 goto out;
         }
 
+        /* Override the breakpoint data with the step data. */
+        if (info->step_ctrl.enabled) {
+                addr = info->trigger & ~0x3;
+                ctrl = encode_ctrl_reg(info->step_ctrl);
+                if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE) {
+                        i = 0;
+                        ctrl_base = ARM_BASE_BCR + core_num_brps;
+                        val_base = ARM_BASE_BVR + core_num_brps;
+                }
+        }
+
         /* Setup the address register. */
         write_wb_reg(val_base + i, addr);
 
@@ -405,10 +396,7 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
                 max_slots = core_num_brps;
         } else {
                 /* Watchpoint */
-                if (info->step_ctrl.enabled)
-                        base = ARM_BASE_BCR + core_num_brps;
-                else
-                        base = ARM_BASE_WCR;
+                base = ARM_BASE_WCR;
                 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
                 max_slots = core_num_wrps;
         }
@@ -426,6 +414,13 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
         if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n"))
                 return;
 
+        /* Ensure that we disable the mismatch breakpoint. */
+        if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE &&
+            info->step_ctrl.enabled) {
+                i = 0;
+                base = ARM_BASE_BCR + core_num_brps;
+        }
+
         /* Reset the control register. */
         write_wb_reg(base + i, 0);
 }
@@ -632,10 +627,9 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
          * we can use the mismatch feature as a poor-man's hardware
          * single-step, but this only works for per-task breakpoints.
          */
-        if (WARN_ONCE(!bp->overflow_handler &&
-                (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_brps()
-                 || !bp->hw.bp_target),
-                        "overflow handler required but none found\n")) {
+        if (!bp->overflow_handler && (arch_check_bp_in_kernelspace(bp) ||
+            !core_has_mismatch_brps() || !bp->hw.bp_target)) {
+                pr_warning("overflow handler required but none found\n");
                 ret = -EINVAL;
         }
 out:
@@ -666,34 +660,62 @@ static void disable_single_step(struct perf_event *bp)
         arch_install_hw_breakpoint(bp);
 }
 
-static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs)
+static void watchpoint_handler(unsigned long addr, unsigned int fsr,
+                               struct pt_regs *regs)
 {
-        int i;
+        int i, access;
+        u32 val, ctrl_reg, alignment_mask;
         struct perf_event *wp, **slots;
         struct arch_hw_breakpoint *info;
+        struct arch_hw_breakpoint_ctrl ctrl;
 
         slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
 
-        /* Without a disassembler, we can only handle 1 watchpoint. */
-        BUG_ON(core_num_wrps > 1);
-
         for (i = 0; i < core_num_wrps; ++i) {
                 rcu_read_lock();
 
                 wp = slots[i];
 
-                if (wp == NULL) {
-                        rcu_read_unlock();
-                        continue;
-                }
+                if (wp == NULL)
+                        goto unlock;
 
+                info = counter_arch_bp(wp);
                 /*
-                 * The DFAR is an unknown value. Since we only allow a
-                 * single watchpoint, we can set the trigger to the lowest
-                 * possible faulting address.
+                 * The DFAR is an unknown value on debug architectures prior
+                 * to 7.1. Since we only allow a single watchpoint on these
+                 * older CPUs, we can set the trigger to the lowest possible
+                 * faulting address.
                  */
-                info = counter_arch_bp(wp);
-                info->trigger = wp->attr.bp_addr;
+                if (debug_arch < ARM_DEBUG_ARCH_V7_1) {
+                        BUG_ON(i > 0);
+                        info->trigger = wp->attr.bp_addr;
+                } else {
+                        if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
+                                alignment_mask = 0x7;
+                        else
+                                alignment_mask = 0x3;
+
+                        /* Check if the watchpoint value matches. */
+                        val = read_wb_reg(ARM_BASE_WVR + i);
+                        if (val != (addr & ~alignment_mask))
+                                goto unlock;
+
+                        /* Possible match, check the byte address select. */
+                        ctrl_reg = read_wb_reg(ARM_BASE_WCR + i);
+                        decode_ctrl_reg(ctrl_reg, &ctrl);
+                        if (!((1 << (addr & alignment_mask)) & ctrl.len))
+                                goto unlock;
+
+                        /* Check that the access type matches. */
+                        access = (fsr & ARM_FSR_ACCESS_MASK) ? HW_BREAKPOINT_W :
+                                 HW_BREAKPOINT_R;
+                        if (!(access & hw_breakpoint_type(wp)))
+                                goto unlock;
+
+                        /* We have a winner. */
+                        info->trigger = addr;
+                }
+
                 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
                 perf_bp_event(wp, regs);
 
@@ -705,6 +727,7 @@ static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs)
                 if (!wp->overflow_handler)
                         enable_single_step(wp, instruction_pointer(regs));
 
+unlock:
                 rcu_read_unlock();
         }
 }
@@ -717,7 +740,7 @@ static void watchpoint_single_step_handler(unsigned long pc)
 
         slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
 
-        for (i = 0; i < core_num_reserved_brps; ++i) {
+        for (i = 0; i < core_num_wrps; ++i) {
                 rcu_read_lock();
 
                 wp = slots[i];
@@ -820,7 +843,7 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
         case ARM_ENTRY_ASYNC_WATCHPOINT:
                 WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
         case ARM_ENTRY_SYNC_WATCHPOINT:
-                watchpoint_handler(addr, regs);
+                watchpoint_handler(addr, fsr, regs);
                 break;
         default:
                 ret = 1; /* Unhandled fault. */
@@ -834,11 +857,31 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
 /*
  * One-time initialisation.
  */
-static void reset_ctrl_regs(void *info)
+static cpumask_t debug_err_mask;
+
+static int debug_reg_trap(struct pt_regs *regs, unsigned int instr)
 {
-        int i, cpu = smp_processor_id();
+        int cpu = smp_processor_id();
+
+        pr_warning("Debug register access (0x%x) caused undefined instruction on CPU %d\n",
+                   instr, cpu);
+
+        /* Set the error flag for this CPU and skip the faulting instruction. */
+        cpumask_set_cpu(cpu, &debug_err_mask);
+        instruction_pointer(regs) += 4;
+        return 0;
+}
+
+static struct undef_hook debug_reg_hook = {
+        .instr_mask     = 0x0fe80f10,
+        .instr_val      = 0x0e000e10,
+        .fn             = debug_reg_trap,
+};
+
+static void reset_ctrl_regs(void *unused)
+{
+        int i, raw_num_brps, err = 0, cpu = smp_processor_id();
         u32 dbg_power;
-        cpumask_t *cpumask = info;
 
         /*
          * v7 debug contains save and restore registers so that debug state
@@ -848,38 +891,52 @@ static void reset_ctrl_regs(void *info)
          * Access Register to avoid taking undefined instruction exceptions
          * later on.
          */
-        if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) {
+        switch (debug_arch) {
+        case ARM_DEBUG_ARCH_V7_ECP14:
                 /*
                  * Ensure sticky power-down is clear (i.e. debug logic is
                  * powered up).
                  */
                 asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power));
-                if ((dbg_power & 0x1) == 0) {
-                        pr_warning("CPU %d debug is powered down!\n", cpu);
-                        cpumask_or(cpumask, cpumask, cpumask_of(cpu));
-                        return;
-                }
-
+                if ((dbg_power & 0x1) == 0)
+                        err = -EPERM;
+                break;
+        case ARM_DEBUG_ARCH_V7_1:
                 /*
-                 * Unconditionally clear the lock by writing a value
-                 * other than 0xC5ACCE55 to the access register.
+                 * Ensure the OS double lock is clear.
                  */
-                asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0));
-                isb();
+                asm volatile("mrc p14, 0, %0, c1, c3, 4" : "=r" (dbg_power));
+                if ((dbg_power & 0x1) == 1)
+                        err = -EPERM;
+                break;
+        }
 
-                /*
-                 * Clear any configured vector-catch events before
-                 * enabling monitor mode.
-                 */
-                asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0));
-                isb();
+        if (err) {
+                pr_warning("CPU %d debug is powered down!\n", cpu);
+                cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
+                return;
         }
 
+        /*
+         * Unconditionally clear the lock by writing a value
+         * other than 0xC5ACCE55 to the access register.
+         */
+        asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0));
+        isb();
+
+        /*
+         * Clear any configured vector-catch events before
+         * enabling monitor mode.
+         */
+        asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0));
+        isb();
+
         if (enable_monitor_mode())
                 return;
 
         /* We must also reset any reserved registers. */
-        for (i = 0; i < core_num_brps + core_num_reserved_brps; ++i) {
+        raw_num_brps = get_num_brp_resources();
+        for (i = 0; i < raw_num_brps; ++i) {
                 write_wb_reg(ARM_BASE_BCR + i, 0UL);
                 write_wb_reg(ARM_BASE_BVR + i, 0UL);
         }
@@ -895,6 +952,7 @@ static int __cpuinit dbg_reset_notify(struct notifier_block *self,
 {
         if (action == CPU_ONLINE)
                 smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1);
+
         return NOTIFY_OK;
 }
 
@@ -905,7 +963,6 @@ static struct notifier_block __cpuinitdata dbg_reset_nb = {
 static int __init arch_hw_breakpoint_init(void)
 {
         u32 dscr;
-        cpumask_t cpumask = { CPU_BITS_NONE };
 
         debug_arch = get_debug_arch();
 
@@ -916,28 +973,31 @@ static int __init arch_hw_breakpoint_init(void)
 
         /* Determine how many BRPs/WRPs are available. */
         core_num_brps = get_num_brps();
-        core_num_reserved_brps = get_num_reserved_brps();
         core_num_wrps = get_num_wrps();
 
-        pr_info("found %d breakpoint and %d watchpoint registers.\n",
-                core_num_brps + core_num_reserved_brps, core_num_wrps);
-
-        if (core_num_reserved_brps)
-                pr_info("%d breakpoint(s) reserved for watchpoint "
-                                "single-step.\n", core_num_reserved_brps);
+        /*
+         * We need to tread carefully here because DBGSWENABLE may be
+         * driven low on this core and there isn't an architected way to
+         * determine that.
+         */
+        register_undef_hook(&debug_reg_hook);
 
         /*
          * Reset the breakpoint resources. We assume that a halting
          * debugger will leave the world in a nice state for us.
          */
-        on_each_cpu(reset_ctrl_regs, &cpumask, 1);
-        if (!cpumask_empty(&cpumask)) {
+        on_each_cpu(reset_ctrl_regs, NULL, 1);
+        unregister_undef_hook(&debug_reg_hook);
+        if (!cpumask_empty(&debug_err_mask)) {
                 core_num_brps = 0;
-                core_num_reserved_brps = 0;
                 core_num_wrps = 0;
                 return 0;
         }
 
+        pr_info("found %d " "%s" "breakpoint and %d watchpoint registers.\n",
+                core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " :
+                "", core_num_wrps);
+
         ARM_DBG_READ(c1, 0, dscr);
         if (dscr & ARM_DSCR_HDBGEN) {
                 max_watchpoint_len = 4;
diff --git a/arch/arm/kernel/kprobes-arm.c b/arch/arm/kernel/kprobes-arm.c
index 79203ee1d039..9fe8910308af 100644
--- a/arch/arm/kernel/kprobes-arm.c
+++ b/arch/arm/kernel/kprobes-arm.c
@@ -60,6 +60,7 @@
 
 #include <linux/kernel.h>
 #include <linux/kprobes.h>
+#include <linux/module.h>
 
 #include "kprobes.h"
 
@@ -971,6 +972,9 @@ const union decode_item kprobe_decode_arm_table[] = {
 
         DECODE_END
 };
+#ifdef CONFIG_ARM_KPROBES_TEST_MODULE
+EXPORT_SYMBOL_GPL(kprobe_decode_arm_table);
+#endif
 
 static void __kprobes arm_singlestep(struct kprobe *p, struct pt_regs *regs)
 {
diff --git a/arch/arm/kernel/kprobes-test-arm.c b/arch/arm/kernel/kprobes-test-arm.c
new file mode 100644
index 000000000000..fc82de8bdcce
--- /dev/null
+++ b/arch/arm/kernel/kprobes-test-arm.c
@@ -0,0 +1,1323 @@
+/*
+ * arch/arm/kernel/kprobes-test-arm.c
+ *
+ * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include "kprobes-test.h"
+
+
+#define TEST_ISA "32"
+
+#define TEST_ARM_TO_THUMB_INTERWORK_R(code1, reg, val, code2)   \
+        TESTCASE_START(code1 #reg code2)                        \
+        TEST_ARG_REG(reg, val)                                  \
+        TEST_ARG_REG(14, 99f)                                   \
+        TEST_ARG_END("")                                        \
+        "50:    nop                     \n\t"                   \
+        "1:     "code1 #reg code2"      \n\t"                   \
+        "       bx      lr              \n\t"                   \
+        ".thumb                         \n\t"                   \
+        "3:     adr     lr, 2f          \n\t"                   \
+        "       bx      lr              \n\t"                   \
+        ".arm                           \n\t"                   \
+        "2:     nop                     \n\t"                   \
+        TESTCASE_END
+
+#define TEST_ARM_TO_THUMB_INTERWORK_P(code1, reg, val, code2)   \
+        TESTCASE_START(code1 #reg code2)                        \
+        TEST_ARG_PTR(reg, val)                                  \
+        TEST_ARG_REG(14, 99f)                                   \
+        TEST_ARG_MEM(15, 3f+1)                                  \
+        TEST_ARG_END("")                                        \
+        "50:    nop                     \n\t"                   \
+        "1:     "code1 #reg code2"      \n\t"                   \
+        "       bx      lr              \n\t"                   \
+        ".thumb                         \n\t"                   \
+        "3:     adr     lr, 2f          \n\t"                   \
+        "       bx      lr              \n\t"                   \
+        ".arm                           \n\t"                   \
+        "2:     nop                     \n\t"                   \
+        TESTCASE_END
+
+
+void kprobe_arm_test_cases(void)
+{
+        kprobe_test_flags = 0;
+
+        TEST_GROUP("Data-processing (register), (register-shifted register), (immediate)")
+
+#define _DATA_PROCESSING_DNM(op,s,val)                                          \
+        TEST_RR(  op "eq" s "   r0,  r",1, VAL1,", r",2, val, "")               \
+        TEST_RR(  op "ne" s "   r1,  r",1, VAL1,", r",2, val, ", lsl #3")       \
+        TEST_RR(  op "cs" s "   r2,  r",3, VAL1,", r",2, val, ", lsr #4")       \
+        TEST_RR(  op "cc" s "   r3,  r",3, VAL1,", r",2, val, ", asr #5")       \
+        TEST_RR(  op "mi" s "   r4,  r",5, VAL1,", r",2, N(val),", asr #6")     \
+        TEST_RR(  op "pl" s "   r5,  r",5, VAL1,", r",2, val, ", ror #7")       \
+        TEST_RR(  op "vs" s "   r6,  r",7, VAL1,", r",2, val, ", rrx")          \
+        TEST_R(   op "vc" s "   r6,  r",7, VAL1,", pc, lsl #3")                 \
+        TEST_R(   op "vc" s "   r6,  r",7, VAL1,", sp, lsr #4")                 \
+        TEST_R(   op "vc" s "   r6,  pc, r",7, VAL1,", asr #5")                 \
+        TEST_R(   op "vc" s "   r6,  sp, r",7, VAL1,", ror #6")                 \
+        TEST_RRR( op "hi" s "   r8,  r",9, VAL1,", r",14,val, ", lsl r",0, 3,"")\
+        TEST_RRR( op "ls" s "   r9,  r",9, VAL1,", r",14,val, ", lsr r",7, 4,"")\
+        TEST_RRR( op "ge" s "   r10, r",11,VAL1,", r",14,val, ", asr r",7, 5,"")\
+        TEST_RRR( op "lt" s "   r11, r",11,VAL1,", r",14,N(val),", asr r",7, 6,"")\
+        TEST_RR(  op "gt" s "   r12, r13"       ", r",14,val, ", ror r",14,7,"")\
+        TEST_RR(  op "le" s "   r14, r",0, val, ", r13"       ", lsl r",14,8,"")\
+        TEST_RR(  op s "        r12, pc"        ", r",14,val, ", ror r",14,7,"")\
+        TEST_RR(  op s "        r14, r",0, val, ", pc"        ", lsl r",14,8,"")\
+        TEST_R(   op "eq" s "   r0,  r",11,VAL1,", #0xf5")                      \
+        TEST_R(   op "ne" s "   r11, r",0, VAL1,", #0xf5000000")                \
+        TEST_R(   op s "        r7,  r",8, VAL2,", #0x000af000")                \
+        TEST(     op s "        r4,  pc"        ", #0x00005a00")
+
+#define DATA_PROCESSING_DNM(op,val)             \
+        _DATA_PROCESSING_DNM(op,"",val)         \
+        _DATA_PROCESSING_DNM(op,"s",val)
+
+#define DATA_PROCESSING_NM(op,val)                                              \
+        TEST_RR(  op "ne        r",1, VAL1,", r",2, val, "")                    \
+        TEST_RR(  op "eq        r",1, VAL1,", r",2, val, ", lsl #3")            \
+        TEST_RR(  op "cc        r",3, VAL1,", r",2, val, ", lsr #4")            \
+        TEST_RR(  op "cs        r",3, VAL1,", r",2, val, ", asr #5")            \
+        TEST_RR(  op "pl        r",5, VAL1,", r",2, N(val),", asr #6")          \
+        TEST_RR(  op "mi        r",5, VAL1,", r",2, val, ", ror #7")            \
+        TEST_RR(  op "vc        r",7, VAL1,", r",2, val, ", rrx")               \
+        TEST_R (  op "vs        r",7, VAL1,", pc, lsl #3")                      \
+        TEST_R (  op "vs        r",7, VAL1,", sp, lsr #4")                      \
+        TEST_R(   op "vs        pc, r",7, VAL1,", asr #5")                      \
+        TEST_R(   op "vs        sp, r",7, VAL1,", ror #6")                      \
+        TEST_RRR( op "ls        r",9, VAL1,", r",14,val, ", lsl r",0, 3,"")     \
+        TEST_RRR( op "hi        r",9, VAL1,", r",14,val, ", lsr r",7, 4,"")     \
+        TEST_RRR( op "lt        r",11,VAL1,", r",14,val, ", asr r",7, 5,"")     \
+        TEST_RRR( op "ge        r",11,VAL1,", r",14,N(val),", asr r",7, 6,"")   \
+        TEST_RR(  op "le        r13"       ", r",14,val, ", ror r",14,7,"")     \
+        TEST_RR(  op "gt        r",0, val, ", r13"       ", lsl r",14,8,"")     \
+        TEST_RR(  op "  pc"        ", r",14,val, ", ror r",14,7,"")             \
+        TEST_RR(  op "  r",0, val, ", pc"        ", lsl r",14,8,"")             \
+        TEST_R(   op "eq        r",11,VAL1,", #0xf5")                           \
+        TEST_R(   op "ne        r",0, VAL1,", #0xf5000000")                     \
+        TEST_R(   op "  r",8, VAL2,", #0x000af000")
+
+#define _DATA_PROCESSING_DM(op,s,val)                                   \
+        TEST_R(   op "eq" s "   r0,  r",1, val, "")                     \
+        TEST_R(   op "ne" s "   r1,  r",1, val, ", lsl #3")             \
+        TEST_R(   op "cs" s "   r2,  r",3, val, ", lsr #4")             \
+        TEST_R(   op "cc" s "   r3,  r",3, val, ", asr #5")             \
+        TEST_R(   op "mi" s "   r4,  r",5, N(val),", asr #6")           \
+        TEST_R(   op "pl" s "   r5,  r",5, val, ", ror #7")             \
+        TEST_R(   op "vs" s "   r6,  r",10,val, ", rrx")                \
+        TEST(     op "vs" s "   r7,  pc, lsl #3")                       \
+        TEST(     op "vs" s "   r7,  sp, lsr #4")                       \
+        TEST_RR(  op "vc" s "   r8,  r",7, val, ", lsl r",0, 3,"")      \
+        TEST_RR(  op "hi" s "   r9,  r",9, val, ", lsr r",7, 4,"")      \
+        TEST_RR(  op "ls" s "   r10, r",9, val, ", asr r",7, 5,"")      \
+        TEST_RR(  op "ge" s "   r11, r",11,N(val),", asr r",7, 6,"")    \
+        TEST_RR(  op "lt" s "   r12, r",11,val, ", ror r",14,7,"")      \
+        TEST_R(   op "gt" s "   r14, r13"       ", lsl r",14,8,"")      \
+        TEST_R(   op "le" s "   r14, pc"        ", lsl r",14,8,"")      \
+        TEST(     op "eq" s "   r0,  #0xf5")                            \
+        TEST(     op "ne" s "   r11, #0xf5000000")                      \
+        TEST(     op s "        r7,  #0x000af000")                      \
+        TEST(     op s "        r4,  #0x00005a00")
+
+#define DATA_PROCESSING_DM(op,val)              \
+        _DATA_PROCESSING_DM(op,"",val)          \
+        _DATA_PROCESSING_DM(op,"s",val)
+
+        DATA_PROCESSING_DNM("and",0xf00f00ff)
+        DATA_PROCESSING_DNM("eor",0xf00f00ff)
+        DATA_PROCESSING_DNM("sub",VAL2)
+        DATA_PROCESSING_DNM("rsb",VAL2)
+        DATA_PROCESSING_DNM("add",VAL2)
+        DATA_PROCESSING_DNM("adc",VAL2)
+        DATA_PROCESSING_DNM("sbc",VAL2)
+        DATA_PROCESSING_DNM("rsc",VAL2)
+        DATA_PROCESSING_NM("tst",0xf00f00ff)
+        DATA_PROCESSING_NM("teq",0xf00f00ff)
+        DATA_PROCESSING_NM("cmp",VAL2)
+        DATA_PROCESSING_NM("cmn",VAL2)
+        DATA_PROCESSING_DNM("orr",0xf00f00ff)
+        DATA_PROCESSING_DM("mov",VAL2)
+        DATA_PROCESSING_DNM("bic",0xf00f00ff)
+        DATA_PROCESSING_DM("mvn",VAL2)
+
+        TEST("mov       ip, sp") /* This has special case emulation code */
+
+        TEST_SUPPORTED("mov     pc, #0x1000");
+        TEST_SUPPORTED("mov     sp, #0x1000");
+        TEST_SUPPORTED("cmp     pc, #0x1000");
+        TEST_SUPPORTED("cmp     sp, #0x1000");
+
+        /* Data-processing with PC as shift*/
+        TEST_UNSUPPORTED(".word 0xe15c0f1e      @ cmp   r12, r14, asl pc")
+        TEST_UNSUPPORTED(".word 0xe1a0cf1e      @ mov   r12, r14, asl pc")
+        TEST_UNSUPPORTED(".word 0xe08caf1e      @ add   r10, r12, r14, asl pc")
+
+        /* Data-processing with PC as shift*/
+        TEST_UNSUPPORTED("movs  pc, r1")
+        TEST_UNSUPPORTED("movs  pc, r1, lsl r2")
+        TEST_UNSUPPORTED("movs  pc, #0x10000")
+        TEST_UNSUPPORTED("adds  pc, lr, r1")
+        TEST_UNSUPPORTED("adds  pc, lr, r1, lsl r2")
+        TEST_UNSUPPORTED("adds  pc, lr, #4")
+
+        /* Data-processing with SP as target */
+        TEST("add       sp, sp, #16")
+        TEST("sub       sp, sp, #8")
+        TEST("bic       sp, sp, #0x20")
+        TEST("orr       sp, sp, #0x20")
+        TEST_PR( "add   sp, r",10,0,", r",11,4,"")
+        TEST_PRR("add   sp, r",10,0,", r",11,4,", asl r",12,1,"")
+        TEST_P(  "mov   sp, r",10,0,"")
+        TEST_PR( "mov   sp, r",10,0,", asl r",12,0,"")
+
+        /* Data-processing with PC as target */
+        TEST_BF(   "add pc, pc, #2f-1b-8")
+        TEST_BF_R ("add pc, pc, r",14,2f-1f-8,"")
+        TEST_BF_R ("add pc, r",14,2f-1f-8,", pc")
+        TEST_BF_R ("mov pc, r",0,2f,"")
+        TEST_BF_RR("mov pc, r",0,2f,", asl r",1,0,"")
+        TEST_BB(   "sub pc, pc, #1b-2b+8")
+#if __LINUX_ARM_ARCH__ >= 6
+        TEST_BB(   "sub pc, pc, #1b-2b+8-2") /* UNPREDICTABLE before ARMv6 */
+#endif
+        TEST_BB_R( "sub pc, pc, r",14, 1f-2f+8,"")
+        TEST_BB_R( "rsb pc, r",14,1f-2f+8,", pc")
+        TEST_RR(   "add pc, pc, r",10,-2,", asl r",11,1,"")
+#ifdef CONFIG_THUMB2_KERNEL
+        TEST_ARM_TO_THUMB_INTERWORK_R("add      pc, pc, r",0,3f-1f-8+1,"")
+        TEST_ARM_TO_THUMB_INTERWORK_R("sub      pc, r",0,3f+8+1,", #8")
+#endif
+        TEST_GROUP("Miscellaneous instructions")
+
+        TEST("mrs       r0, cpsr")
+        TEST("mrspl     r7, cpsr")
+        TEST("mrs       r14, cpsr")
+        TEST_UNSUPPORTED(".word 0xe10ff000      @ mrs r15, cpsr")
+        TEST_UNSUPPORTED("mrs   r0, spsr")
+        TEST_UNSUPPORTED("mrs   lr, spsr")
+
+        TEST_UNSUPPORTED("msr   cpsr, r0")
+        TEST_UNSUPPORTED("msr   cpsr_f, lr")
+        TEST_UNSUPPORTED("msr   spsr, r0")
+
+        TEST_BF_R("bx   r",0,2f,"")
+        TEST_BB_R("bx   r",7,2f,"")
+        TEST_BF_R("bxeq r",14,2f,"")
+
+        TEST_R("clz     r0, r",0, 0x0,"")
+        TEST_R("clzeq   r7, r",14,0x1,"")
+        TEST_R("clz     lr, r",7, 0xffffffff,"")
+        TEST(  "clz     r4, sp")
+        TEST_UNSUPPORTED(".word 0x016fff10      @ clz pc, r0")
+        TEST_UNSUPPORTED(".word 0x016f0f1f      @ clz r0, pc")
+
+#if __LINUX_ARM_ARCH__ >= 6
+        TEST_UNSUPPORTED("bxj   r0")
+#endif
+
+        TEST_BF_R("blx  r",0,2f,"")
+        TEST_BB_R("blx  r",7,2f,"")
+        TEST_BF_R("blxeq        r",14,2f,"")
+        TEST_UNSUPPORTED(".word 0x0120003f      @ blx pc")
+
+        TEST_RR(   "qadd        r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(   "qaddvs      lr, r",9, VAL2,", r",8, VAL1,"")
+        TEST_R(    "qadd        lr, r",9, VAL2,", r13")
+        TEST_RR(   "qsub        r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(   "qsubvs      lr, r",9, VAL2,", r",8, VAL1,"")
+        TEST_R(    "qsub        lr, r",9, VAL2,", r13")
+        TEST_RR(   "qdadd       r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(   "qdaddvs     lr, r",9, VAL2,", r",8, VAL1,"")
+        TEST_R(    "qdadd       lr, r",9, VAL2,", r13")
+        TEST_RR(   "qdsub       r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(   "qdsubvs     lr, r",9, VAL2,", r",8, VAL1,"")
+        TEST_R(    "qdsub       lr, r",9, VAL2,", r13")
+        TEST_UNSUPPORTED(".word 0xe101f050      @ qadd pc, r0, r1")
+        TEST_UNSUPPORTED(".word 0xe121f050      @ qsub pc, r0, r1")
+        TEST_UNSUPPORTED(".word 0xe141f050      @ qdadd pc, r0, r1")
+        TEST_UNSUPPORTED(".word 0xe161f050      @ qdsub pc, r0, r1")
+        TEST_UNSUPPORTED(".word 0xe16f2050      @ qdsub r2, r0, pc")
+        TEST_UNSUPPORTED(".word 0xe161205f      @ qdsub r2, pc, r1")
+
+        TEST_UNSUPPORTED("bkpt  0xffff")
+        TEST_UNSUPPORTED("bkpt  0x0000")
+
+        TEST_UNSUPPORTED(".word 0xe1600070 @ smc #0")
+
+        TEST_GROUP("Halfword multiply and multiply-accumulate")
+
+        TEST_RRR(    "smlabb    r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(    "smlabbge  r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+        TEST_RR(     "smlabb    lr, r",1, VAL2,", r",2, VAL3,", r13")
+        TEST_UNSUPPORTED(".word 0xe10f3281 @ smlabb pc, r1, r2, r3")
+        TEST_RRR(    "smlatb    r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(    "smlatbge  r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+        TEST_RR(     "smlatb    lr, r",1, VAL2,", r",2, VAL3,", r13")
+        TEST_UNSUPPORTED(".word 0xe10f32a1 @ smlatb pc, r1, r2, r3")
+        TEST_RRR(    "smlabt    r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(    "smlabtge  r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+        TEST_RR(     "smlabt    lr, r",1, VAL2,", r",2, VAL3,", r13")
+        TEST_UNSUPPORTED(".word 0xe10f32c1 @ smlabt pc, r1, r2, r3")
+        TEST_RRR(    "smlatt    r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(    "smlattge  r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+        TEST_RR(     "smlatt    lr, r",1, VAL2,", r",2, VAL3,", r13")
+        TEST_UNSUPPORTED(".word 0xe10f32e1 @ smlatt pc, r1, r2, r3")
+
+        TEST_RRR(    "smlawb    r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(    "smlawbge  r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+        TEST_RR(     "smlawb    lr, r",1, VAL2,", r",2, VAL3,", r13")
+        TEST_UNSUPPORTED(".word 0xe12f3281 @ smlawb pc, r1, r2, r3")
+        TEST_RRR(    "smlawt    r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(    "smlawtge  r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+        TEST_RR(     "smlawt    lr, r",1, VAL2,", r",2, VAL3,", r13")
+        TEST_UNSUPPORTED(".word 0xe12f32c1 @ smlawt pc, r1, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe12032cf @ smlawt r0, pc, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe1203fc1 @ smlawt r0, r1, pc, r3")
+        TEST_UNSUPPORTED(".word 0xe120f2c1 @ smlawt r0, r1, r2, pc")
+
+        TEST_RR(    "smulwb     r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(    "smulwbge   r7, r",8, VAL3,", r",9, VAL1,"")
+        TEST_R(     "smulwb     lr, r",1, VAL2,", r13")
+        TEST_UNSUPPORTED(".word 0xe12f02a1 @ smulwb pc, r1, r2")
+        TEST_RR(    "smulwt     r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(    "smulwtge   r7, r",8, VAL3,", r",9, VAL1,"")
+        TEST_R(     "smulwt     lr, r",1, VAL2,", r13")
+        TEST_UNSUPPORTED(".word 0xe12f02e1 @ smulwt pc, r1, r2")
+
+        TEST_RRRR(  "smlalbb    r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
+        TEST_RRRR(  "smlalbble  r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
+        TEST_RRR(   "smlalbb    r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
+        TEST_UNSUPPORTED(".word 0xe14f1382 @ smlalbb pc, r1, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe141f382 @ smlalbb r1, pc, r2, r3")
+        TEST_RRRR(  "smlaltb    r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
+        TEST_RRRR(  "smlaltble  r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
+        TEST_RRR(   "smlaltb    r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
+        TEST_UNSUPPORTED(".word 0xe14f13a2 @ smlaltb pc, r1, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe141f3a2 @ smlaltb r1, pc, r2, r3")
+        TEST_RRRR(  "smlalbt    r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
+        TEST_RRRR(  "smlalbtle  r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
+        TEST_RRR(   "smlalbt    r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
+        TEST_UNSUPPORTED(".word 0xe14f13c2 @ smlalbt pc, r1, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe141f3c2 @ smlalbt r1, pc, r2, r3")
+        TEST_RRRR(  "smlaltt    r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
+        TEST_RRRR(  "smlalttle  r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
+        TEST_RRR(   "smlaltt    r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
+        TEST_UNSUPPORTED(".word 0xe14f13e2 @ smlalbb pc, r1, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe140f3e2 @ smlalbb r0, pc, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe14013ef @ smlalbb r0, r1, pc, r3")
+        TEST_UNSUPPORTED(".word 0xe1401fe2 @ smlalbb r0, r1, r2, pc")
+
+        TEST_RR(    "smulbb     r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(    "smulbbge   r7, r",8, VAL3,", r",9, VAL1,"")
+        TEST_R(     "smulbb     lr, r",1, VAL2,", r13")
+        TEST_UNSUPPORTED(".word 0xe16f0281 @ smulbb pc, r1, r2")
+        TEST_RR(    "smultb     r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(    "smultbge   r7, r",8, VAL3,", r",9, VAL1,"")
+        TEST_R(     "smultb     lr, r",1, VAL2,", r13")
+        TEST_UNSUPPORTED(".word 0xe16f02a1 @ smultb pc, r1, r2")
+        TEST_RR(    "smulbt     r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(    "smulbtge   r7, r",8, VAL3,", r",9, VAL1,"")
+        TEST_R(     "smulbt     lr, r",1, VAL2,", r13")
+        TEST_UNSUPPORTED(".word 0xe16f02c1 @ smultb pc, r1, r2")
+        TEST_RR(    "smultt     r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(    "smulttge   r7, r",8, VAL3,", r",9, VAL1,"")
+        TEST_R(     "smultt     lr, r",1, VAL2,", r13")
+        TEST_UNSUPPORTED(".word 0xe16f02e1 @ smultt pc, r1, r2")
+        TEST_UNSUPPORTED(".word 0xe16002ef @ smultt r0, pc, r2")
+        TEST_UNSUPPORTED(".word 0xe1600fe1 @ smultt r0, r1, pc")
+
+        TEST_GROUP("Multiply and multiply-accumulate")
+
+        TEST_RR(    "mul        r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(    "mulls      r7, r",8, VAL2,", r",9, VAL2,"")
+        TEST_R(     "mul        lr, r",4, VAL3,", r13")
+        TEST_UNSUPPORTED(".word 0xe00f0291 @ mul pc, r1, r2")
+        TEST_UNSUPPORTED(".word 0xe000029f @ mul r0, pc, r2")
+        TEST_UNSUPPORTED(".word 0xe0000f91 @ mul r0, r1, pc")
+        TEST_RR(    "muls       r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(    "mullss     r7, r",8, VAL2,", r",9, VAL2,"")
+        TEST_R(     "muls       lr, r",4, VAL3,", r13")
+        TEST_UNSUPPORTED(".word 0xe01f0291 @ muls pc, r1, r2")
+
+        TEST_RRR(    "mla       r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(    "mlahi     r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+        TEST_RR(     "mla       lr, r",1, VAL2,", r",2, VAL3,", r13")
+        TEST_UNSUPPORTED(".word 0xe02f3291 @ mla pc, r1, r2, r3")
+        TEST_RRR(    "mlas      r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(    "mlahis    r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+        TEST_RR(     "mlas      lr, r",1, VAL2,", r",2, VAL3,", r13")
+        TEST_UNSUPPORTED(".word 0xe03f3291 @ mlas pc, r1, r2, r3")
+
+#if __LINUX_ARM_ARCH__ >= 6
+        TEST_RR(  "umaal        r0, r1, r",2, VAL1,", r",3, VAL2,"")
+        TEST_RR(  "umaalls      r7, r8, r",9, VAL2,", r",10, VAL1,"")
+        TEST_R(   "umaal        lr, r12, r",11,VAL3,", r13")
+        TEST_UNSUPPORTED(".word 0xe041f392 @ umaal pc, r1, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe04f0392 @ umaal r0, pc, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe0500090 @ undef")
+        TEST_UNSUPPORTED(".word 0xe05fff9f @ undef")
+
+        TEST_RRR(  "mls         r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(  "mlshi       r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+        TEST_RR(   "mls         lr, r",1, VAL2,", r",2, VAL3,", r13")
+        TEST_UNSUPPORTED(".word 0xe06f3291 @ mls pc, r1, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe060329f @ mls r0, pc, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe0603f91 @ mls r0, r1, pc, r3")
+        TEST_UNSUPPORTED(".word 0xe060f291 @ mls r0, r1, r2, pc")
+#endif
+
+        TEST_UNSUPPORTED(".word 0xe0700090 @ undef")
+        TEST_UNSUPPORTED(".word 0xe07fff9f @ undef")
+
+        TEST_RR(  "umull        r0, r1, r",2, VAL1,", r",3, VAL2,"")
+        TEST_RR(  "umullls      r7, r8, r",9, VAL2,", r",10, VAL1,"")
+        TEST_R(   "umull        lr, r12, r",11,VAL3,", r13")
+        TEST_UNSUPPORTED(".word 0xe081f392 @ umull pc, r1, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe08f1392 @ umull r1, pc, r2, r3")
+        TEST_RR(  "umulls       r0, r1, r",2, VAL1,", r",3, VAL2,"")
+        TEST_RR(  "umulllss     r7, r8, r",9, VAL2,", r",10, VAL1,"")
+        TEST_R(   "umulls       lr, r12, r",11,VAL3,", r13")
+        TEST_UNSUPPORTED(".word 0xe091f392 @ umulls pc, r1, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe09f1392 @ umulls r1, pc, r2, r3")
+
+        TEST_RRRR(  "umlal      r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
+        TEST_RRRR(  "umlalle    r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
+        TEST_RRR(   "umlal      r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
+        TEST_UNSUPPORTED(".word 0xe0af1392 @ umlal pc, r1, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe0a1f392 @ umlal r1, pc, r2, r3")
+        TEST_RRRR(  "umlals     r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
+        TEST_RRRR(  "umlalles   r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
+        TEST_RRR(   "umlals     r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
+        TEST_UNSUPPORTED(".word 0xe0bf1392 @ umlals pc, r1, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe0b1f392 @ umlals r1, pc, r2, r3")
+
+        TEST_RR(  "smull        r0, r1, r",2, VAL1,", r",3, VAL2,"")
+        TEST_RR(  "smullls      r7, r8, r",9, VAL2,", r",10, VAL1,"")
+        TEST_R(   "smull        lr, r12, r",11,VAL3,", r13")
+        TEST_UNSUPPORTED(".word 0xe0c1f392 @ smull pc, r1, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe0cf1392 @ smull r1, pc, r2, r3")
+        TEST_RR(  "smulls       r0, r1, r",2, VAL1,", r",3, VAL2,"")
+        TEST_RR(  "smulllss     r7, r8, r",9, VAL2,", r",10, VAL1,"")
+        TEST_R(   "smulls       lr, r12, r",11,VAL3,", r13")
+        TEST_UNSUPPORTED(".word 0xe0d1f392 @ smulls pc, r1, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe0df1392 @ smulls r1, pc, r2, r3")
+
+        TEST_RRRR(  "smlal      r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
+        TEST_RRRR(  "smlalle    r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
+        TEST_RRR(   "smlal      r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
+        TEST_UNSUPPORTED(".word 0xe0ef1392 @ smlal pc, r1, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe0e1f392 @ smlal r1, pc, r2, r3")
+        TEST_RRRR(  "smlals     r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
+        TEST_RRRR(  "smlalles   r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
+        TEST_RRR(   "smlals     r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
+        TEST_UNSUPPORTED(".word 0xe0ff1392 @ smlals pc, r1, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe0f0f392 @ smlals r0, pc, r2, r3")
+        TEST_UNSUPPORTED(".word 0xe0f0139f @ smlals r0, r1, pc, r3")
+        TEST_UNSUPPORTED(".word 0xe0f01f92 @ smlals r0, r1, r2, pc")
+
+        TEST_GROUP("Synchronization primitives")
+
+        /*
+         * Use hard coded constants for SWP instructions to avoid warnings
+         * about deprecated instructions.
+         */
+        TEST_RP( ".word 0xe108e097 @ swp        lr, r",7,VAL2,", [r",8,0,"]")
+        TEST_R(  ".word 0x610d0091 @ swpvs      r0, r",1,VAL1,", [sp]")
+        TEST_RP( ".word 0xe10cd09e @ swp        sp, r",14,VAL2,", [r",12,13*4,"]")
+        TEST_UNSUPPORTED(".word 0xe102f091 @ swp pc, r1, [r2]")
+        TEST_UNSUPPORTED(".word 0xe102009f @ swp r0, pc, [r2]")
+        TEST_UNSUPPORTED(".word 0xe10f0091 @ swp r0, r1, [pc]")
+        TEST_RP( ".word 0xe148e097 @ swpb       lr, r",7,VAL2,", [r",8,0,"]")
+        TEST_R(  ".word 0x614d0091 @ swpvsb     r0, r",1,VAL1,", [sp]")
+        TEST_UNSUPPORTED(".word 0xe142f091 @ swpb pc, r1, [r2]")
+
+        TEST_UNSUPPORTED(".word 0xe1100090") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe1200090") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe1300090") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe1500090") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe1600090") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe1700090") /* Unallocated space */
+#if __LINUX_ARM_ARCH__ >= 6
+        TEST_UNSUPPORTED("ldrex r2, [sp]")
+        TEST_UNSUPPORTED("strexd        r0, r2, r3, [sp]")
+        TEST_UNSUPPORTED("ldrexd        r2, r3, [sp]")
+        TEST_UNSUPPORTED("strexb        r0, r2, [sp]")
+        TEST_UNSUPPORTED("ldrexb        r2, [sp]")
+        TEST_UNSUPPORTED("strexh        r0, r2, [sp]")
+        TEST_UNSUPPORTED("ldrexh        r2, [sp]")
+#endif
+        TEST_GROUP("Extra load/store instructions")
+
+        TEST_RPR(  "strh        r",0, VAL1,", [r",1, 48,", -r",2, 24,"]")
+        TEST_RPR(  "streqh      r",14,VAL2,", [r",13,0, ", r",12, 48,"]")
+        TEST_RPR(  "strh        r",1, VAL1,", [r",2, 24,", r",3,  48,"]!")
+        TEST_RPR(  "strneh      r",12,VAL2,", [r",11,48,", -r",10,24,"]!")
+        TEST_RPR(  "strh        r",2, VAL1,", [r",3, 24,"], r",4, 48,"")
+        TEST_RPR(  "strh        r",10,VAL2,", [r",9, 48,"], -r",11,24,"")
+        TEST_UNSUPPORTED(".word 0xe1afc0ba      @ strh r12, [pc, r10]!")
+        TEST_UNSUPPORTED(".word 0xe089f0bb      @ strh pc, [r9], r11")
+        TEST_UNSUPPORTED(".word 0xe089a0bf      @ strh r10, [r9], pc")
+
+        TEST_PR(   "ldrh        r0, [r",0,  48,", -r",2, 24,"]")
+        TEST_PR(   "ldrcsh      r14, [r",13,0, ", r",12, 48,"]")
+        TEST_PR(   "ldrh        r1, [r",2,  24,", r",3,  48,"]!")
+        TEST_PR(   "ldrcch      r12, [r",11,48,", -r",10,24,"]!")
+        TEST_PR(   "ldrh        r2, [r",3,  24,"], r",4, 48,"")
+        TEST_PR(   "ldrh        r10, [r",9, 48,"], -r",11,24,"")
+        TEST_UNSUPPORTED(".word 0xe1bfc0ba      @ ldrh r12, [pc, r10]!")
+        TEST_UNSUPPORTED(".word 0xe099f0bb      @ ldrh pc, [r9], r11")
+        TEST_UNSUPPORTED(".word 0xe099a0bf      @ ldrh r10, [r9], pc")
+
+        TEST_RP(   "strh        r",0, VAL1,", [r",1, 24,", #-2]")
+        TEST_RP(   "strmih      r",14,VAL2,", [r",13,0, ", #2]")
+        TEST_RP(   "strh        r",1, VAL1,", [r",2, 24,", #4]!")
+        TEST_RP(   "strplh      r",12,VAL2,", [r",11,24,", #-4]!")
+        TEST_RP(   "strh        r",2, VAL1,", [r",3, 24,"], #48")
+        TEST_RP(   "strh        r",10,VAL2,", [r",9, 64,"], #-48")
+        TEST_UNSUPPORTED(".word 0xe1efc3b0      @ strh r12, [pc, #48]!")
+        TEST_UNSUPPORTED(".word 0xe0c9f3b0      @ strh pc, [r9], #48")
+
+        TEST_P(    "ldrh        r0, [r",0,  24,", #-2]")
+        TEST_P(    "ldrvsh      r14, [r",13,0, ", #2]")
+        TEST_P(    "ldrh        r1, [r",2,  24,", #4]!")
+        TEST_P(    "ldrvch      r12, [r",11,24,", #-4]!")
+        TEST_P(    "ldrh        r2, [r",3,  24,"], #48")
+        TEST_P(    "ldrh        r10, [r",9, 64,"], #-48")
+        TEST(      "ldrh        r0, [pc, #0]")
+        TEST_UNSUPPORTED(".word 0xe1ffc3b0      @ ldrh r12, [pc, #48]!")
+        TEST_UNSUPPORTED(".word 0xe0d9f3b0      @ ldrh pc, [r9], #48")
+
+        TEST_PR(   "ldrsb       r0, [r",0,  48,", -r",2, 24,"]")
+        TEST_PR(   "ldrhisb     r14, [r",13,0,", r",12,  48,"]")
+        TEST_PR(   "ldrsb       r1, [r",2,  24,", r",3,  48,"]!")
+        TEST_PR(   "ldrlssb     r12, [r",11,48,", -r",10,24,"]!")
+        TEST_PR(   "ldrsb       r2, [r",3,  24,"], r",4, 48,"")
+        TEST_PR(   "ldrsb       r10, [r",9, 48,"], -r",11,24,"")
+        TEST_UNSUPPORTED(".word 0xe1bfc0da      @ ldrsb r12, [pc, r10]!")
+        TEST_UNSUPPORTED(".word 0xe099f0db      @ ldrsb pc, [r9], r11")
+
+        TEST_P(    "ldrsb       r0, [r",0,  24,", #-1]")
+        TEST_P(    "ldrgesb     r14, [r",13,0, ", #1]")
+        TEST_P(    "ldrsb       r1, [r",2,  24,", #4]!")
+        TEST_P(    "ldrltsb     r12, [r",11,24,", #-4]!")
+        TEST_P(    "ldrsb       r2, [r",3,  24,"], #48")
+        TEST_P(    "ldrsb       r10, [r",9, 64,"], #-48")
+        TEST(      "ldrsb       r0, [pc, #0]")
+        TEST_UNSUPPORTED(".word 0xe1ffc3d0      @ ldrsb r12, [pc, #48]!")
+        TEST_UNSUPPORTED(".word 0xe0d9f3d0      @ ldrsb pc, [r9], #48")
+
+        TEST_PR(   "ldrsh       r0, [r",0,  48,", -r",2, 24,"]")
+        TEST_PR(   "ldrgtsh     r14, [r",13,0, ", r",12, 48,"]")
+        TEST_PR(   "ldrsh       r1, [r",2,  24,", r",3,  48,"]!")
+        TEST_PR(   "ldrlesh     r12, [r",11,48,", -r",10,24,"]!")
+        TEST_PR(   "ldrsh       r2, [r",3,  24,"], r",4, 48,"")
+        TEST_PR(   "ldrsh       r10, [r",9, 48,"], -r",11,24,"")
+        TEST_UNSUPPORTED(".word 0xe1bfc0fa      @ ldrsh r12, [pc, r10]!")
+        TEST_UNSUPPORTED(".word 0xe099f0fb      @ ldrsh pc, [r9], r11")
+
+        TEST_P(    "ldrsh       r0, [r",0,  24,", #-1]")
+        TEST_P(    "ldreqsh     r14, [r",13,0 ,", #1]")
+        TEST_P(    "ldrsh       r1, [r",2,  24,", #4]!")
+        TEST_P(    "ldrnesh     r12, [r",11,24,", #-4]!")
+        TEST_P(    "ldrsh       r2, [r",3,  24,"], #48")
+        TEST_P(    "ldrsh       r10, [r",9, 64,"], #-48")
+        TEST(      "ldrsh       r0, [pc, #0]")
+        TEST_UNSUPPORTED(".word 0xe1ffc3f0      @ ldrsh r12, [pc, #48]!")
+        TEST_UNSUPPORTED(".word 0xe0d9f3f0      @ ldrsh pc, [r9], #48")
+
+#if __LINUX_ARM_ARCH__ >= 7
+        TEST_UNSUPPORTED("strht r1, [r2], r3")
+        TEST_UNSUPPORTED("ldrht r1, [r2], r3")
+        TEST_UNSUPPORTED("strht r1, [r2], #48")
+        TEST_UNSUPPORTED("ldrht r1, [r2], #48")
+        TEST_UNSUPPORTED("ldrsbt        r1, [r2], r3")
+        TEST_UNSUPPORTED("ldrsbt        r1, [r2], #48")
+        TEST_UNSUPPORTED("ldrsht        r1, [r2], r3")
+        TEST_UNSUPPORTED("ldrsht        r1, [r2], #48")
+#endif
+
+        TEST_RPR(  "strd        r",0, VAL1,", [r",1, 48,", -r",2,24,"]")
+        TEST_RPR(  "strccd      r",8, VAL2,", [r",13,0, ", r",12,48,"]")
+        TEST_RPR(  "strd        r",4, VAL1,", [r",2, 24,", r",3, 48,"]!")
+        TEST_RPR(  "strcsd      r",12,VAL2,", [r",11,48,", -r",10,24,"]!")
+        TEST_RPR(  "strd        r",2, VAL1,", [r",3, 24,"], r",4,48,"")
+        TEST_RPR(  "strd        r",10,VAL2,", [r",9, 48,"], -r",7,24,"")
+        TEST_UNSUPPORTED(".word 0xe1afc0fa      @ strd r12, [pc, r10]!")
+
+        TEST_PR(   "ldrd        r0, [r",0, 48,", -r",2,24,"]")
+        TEST_PR(   "ldrmid      r8, [r",13,0, ", r",12,48,"]")
+        TEST_PR(   "ldrd        r4, [r",2, 24,", r",3, 48,"]!")
+        TEST_PR(   "ldrpld      r6, [r",11,48,", -r",10,24,"]!")
+        TEST_PR(   "ldrd        r2, [r",5, 24,"], r",4,48,"")
+        TEST_PR(   "ldrd        r10, [r",9,48,"], -r",7,24,"")
+        TEST_UNSUPPORTED(".word 0xe1afc0da      @ ldrd r12, [pc, r10]!")
+        TEST_UNSUPPORTED(".word 0xe089f0db      @ ldrd pc, [r9], r11")
+        TEST_UNSUPPORTED(".word 0xe089e0db      @ ldrd lr, [r9], r11")
+        TEST_UNSUPPORTED(".word 0xe089c0df      @ ldrd r12, [r9], pc")
+
+        TEST_RP(   "strd        r",0, VAL1,", [r",1, 24,", #-8]")
+        TEST_RP(   "strvsd      r",8, VAL2,", [r",13,0, ", #8]")
+        TEST_RP(   "strd        r",4, VAL1,", [r",2, 24,", #16]!")
+        TEST_RP(   "strvcd      r",12,VAL2,", [r",11,24,", #-16]!")
+        TEST_RP(   "strd        r",2, VAL1,", [r",4, 24,"], #48")
+        TEST_RP(   "strd        r",10,VAL2,", [r",9, 64,"], #-48")
+        TEST_UNSUPPORTED(".word 0xe1efc3f0      @ strd r12, [pc, #48]!")
+
+        TEST_P(    "ldrd        r0, [r",0, 24,", #-8]")
+        TEST_P(    "ldrhid      r8, [r",13,0, ", #8]")
+        TEST_P(    "ldrd        r4, [r",2, 24,", #16]!")
+        TEST_P(    "ldrlsd      r6, [r",11,24,", #-16]!")
+        TEST_P(    "ldrd        r2, [r",5, 24,"], #48")
+        TEST_P(    "ldrd        r10, [r",9,6,"], #-48")
+        TEST_UNSUPPORTED(".word 0xe1efc3d0      @ ldrd r12, [pc, #48]!")
+        TEST_UNSUPPORTED(".word 0xe0c9f3d0      @ ldrd pc, [r9], #48")
+        TEST_UNSUPPORTED(".word 0xe0c9e3d0      @ ldrd lr, [r9], #48")
+
+        TEST_GROUP("Miscellaneous")
+
+#if __LINUX_ARM_ARCH__ >= 7
+        TEST("movw      r0, #0")
+        TEST("movw      r0, #0xffff")
+        TEST("movw      lr, #0xffff")
+        TEST_UNSUPPORTED(".word 0xe300f000      @ movw pc, #0")
+        TEST_R("movt    r",0, VAL1,", #0")
+        TEST_R("movt    r",0, VAL2,", #0xffff")
+        TEST_R("movt    r",14,VAL1,", #0xffff")
+        TEST_UNSUPPORTED(".word 0xe340f000      @ movt pc, #0")
+#endif
+
+        TEST_UNSUPPORTED("msr   cpsr, 0x13")
+        TEST_UNSUPPORTED("msr   cpsr_f, 0xf0000000")
+        TEST_UNSUPPORTED("msr   spsr, 0x13")
+
+#if __LINUX_ARM_ARCH__ >= 7
+        TEST_SUPPORTED("yield")
+        TEST("sev")
+        TEST("nop")
+        TEST("wfi")
+        TEST_SUPPORTED("wfe")
+        TEST_UNSUPPORTED("dbg #0")
+#endif
+
+        TEST_GROUP("Load/store word and unsigned byte")
+
+#define LOAD_STORE(byte)                                                        \
+        TEST_RP( "str"byte"     r",0, VAL1,", [r",1, 24,", #-2]")               \
+        TEST_RP( "str"byte"     r",14,VAL2,", [r",13,0, ", #2]")                \
+        TEST_RP( "str"byte"     r",1, VAL1,", [r",2, 24,", #4]!")               \
+        TEST_RP( "str"byte"     r",12,VAL2,", [r",11,24,", #-4]!")              \
+        TEST_RP( "str"byte"     r",2, VAL1,", [r",3, 24,"], #48")               \
+        TEST_RP( "str"byte"     r",10,VAL2,", [r",9, 64,"], #-48")              \
+        TEST_RPR("str"byte"     r",0, VAL1,", [r",1, 48,", -r",2, 24,"]")       \
+        TEST_RPR("str"byte"     r",14,VAL2,", [r",13,0, ", r",12, 48,"]")       \
+        TEST_RPR("str"byte"     r",1, VAL1,", [r",2, 24,", r",3,  48,"]!")      \
+        TEST_RPR("str"byte"     r",12,VAL2,", [r",11,48,", -r",10,24,"]!")      \
+        TEST_RPR("str"byte"     r",2, VAL1,", [r",3, 24,"], r",4, 48,"")        \
+        TEST_RPR("str"byte"     r",10,VAL2,", [r",9, 48,"], -r",11,24,"")       \
+        TEST_RPR("str"byte"     r",0, VAL1,", [r",1, 24,", r",2,  32,", asl #1]")\
+        TEST_RPR("str"byte"     r",14,VAL2,", [r",13,0, ", r",12, 32,", lsr #2]")\
+        TEST_RPR("str"byte"     r",1, VAL1,", [r",2, 24,", r",3,  32,", asr #3]!")\
+        TEST_RPR("str"byte"     r",12,VAL2,", [r",11,24,", r",10, 4,", ror #31]!")\
+        TEST_P(  "ldr"byte"     r0, [r",0,  24,", #-2]")                        \
+        TEST_P(  "ldr"byte"     r14, [r",13,0, ", #2]")                         \
+        TEST_P(  "ldr"byte"     r1, [r",2,  24,", #4]!")                        \
+        TEST_P(  "ldr"byte"     r12, [r",11,24,", #-4]!")                       \
+        TEST_P(  "ldr"byte"     r2, [r",3,  24,"], #48")                        \
+        TEST_P(  "ldr"byte"     r10, [r",9, 64,"], #-48")                       \
+        TEST_PR( "ldr"byte"     r0, [r",0,  48,", -r",2, 24,"]")                \
+        TEST_PR( "ldr"byte"     r14, [r",13,0, ", r",12, 48,"]")                \
+        TEST_PR( "ldr"byte"     r1, [r",2,  24,", r",3, 48,"]!")                \
+        TEST_PR( "ldr"byte"     r12, [r",11,48,", -r",10,24,"]!")               \
+        TEST_PR( "ldr"byte"     r2, [r",3,  24,"], r",4, 48,"")                 \
+        TEST_PR( "ldr"byte"     r10, [r",9, 48,"], -r",11,24,"")                \
+        TEST_PR( "ldr"byte"     r0, [r",0,  24,", r",2,  32,", asl #1]")        \
+        TEST_PR( "ldr"byte"     r14, [r",13,0, ", r",12, 32,", lsr #2]")        \
+        TEST_PR( "ldr"byte"     r1, [r",2,  24,", r",3,  32,", asr #3]!")       \
+        TEST_PR( "ldr"byte"     r12, [r",11,24,", r",10, 4,", ror #31]!")       \
+        TEST(    "ldr"byte"     r0, [pc, #0]")                                  \
+        TEST_R(  "ldr"byte"     r12, [pc, r",14,0,"]")
+
+        LOAD_STORE("")
+        TEST_P(   "str  pc, [r",0,0,", #15*4]")
+        TEST_R(   "str  pc, [sp, r",2,15*4,"]")
+        TEST_BF(  "ldr  pc, [sp, #15*4]")
+        TEST_BF_R("ldr  pc, [sp, r",2,15*4,"]")
+
+        TEST_P(   "str  sp, [r",0,0,", #13*4]")
+        TEST_R(   "str  sp, [sp, r",2,13*4,"]")
+        TEST_BF(  "ldr  sp, [sp, #13*4]")
+        TEST_BF_R("ldr  sp, [sp, r",2,13*4,"]")
+
+#ifdef CONFIG_THUMB2_KERNEL
+        TEST_ARM_TO_THUMB_INTERWORK_P("ldr      pc, [r",0,0,", #15*4]")
+#endif
+        TEST_UNSUPPORTED(".word 0xe5af6008      @ str r6, [pc, #8]!")
+        TEST_UNSUPPORTED(".word 0xe7af6008      @ str r6, [pc, r8]!")
+        TEST_UNSUPPORTED(".word 0xe5bf6008      @ ldr r6, [pc, #8]!")
+        TEST_UNSUPPORTED(".word 0xe7bf6008      @ ldr r6, [pc, r8]!")
+        TEST_UNSUPPORTED(".word 0xe788600f      @ str r6, [r8, pc]")
+        TEST_UNSUPPORTED(".word 0xe798600f      @ ldr r6, [r8, pc]")
+
+        LOAD_STORE("b")
+        TEST_UNSUPPORTED(".word 0xe5f7f008      @ ldrb pc, [r7, #8]!")
+        TEST_UNSUPPORTED(".word 0xe7f7f008      @ ldrb pc, [r7, r8]!")
+        TEST_UNSUPPORTED(".word 0xe5ef6008      @ strb r6, [pc, #8]!")
+        TEST_UNSUPPORTED(".word 0xe7ef6008      @ strb r6, [pc, r3]!")
+        TEST_UNSUPPORTED(".word 0xe5ff6008      @ ldrb r6, [pc, #8]!")
+        TEST_UNSUPPORTED(".word 0xe7ff6008      @ ldrb r6, [pc, r3]!")
+
+        TEST_UNSUPPORTED("ldrt  r0, [r1], #4")
+        TEST_UNSUPPORTED("ldrt  r1, [r2], r3")
+        TEST_UNSUPPORTED("strt  r2, [r3], #4")
+        TEST_UNSUPPORTED("strt  r3, [r4], r5")
+        TEST_UNSUPPORTED("ldrbt r4, [r5], #4")
+        TEST_UNSUPPORTED("ldrbt r5, [r6], r7")
+        TEST_UNSUPPORTED("strbt r6, [r7], #4")
+        TEST_UNSUPPORTED("strbt r7, [r8], r9")
+
+#if __LINUX_ARM_ARCH__ >= 7
+        TEST_GROUP("Parallel addition and subtraction, signed")
+
+        TEST_UNSUPPORTED(".word 0xe6000010") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe60fffff") /* Unallocated space */
+
+        TEST_RR(    "sadd16     r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "sadd16     r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe61cff1a      @ sadd16        pc, r12, r10")
+        TEST_RR(    "sasx       r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "sasx       r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe61cff3a      @ sasx  pc, r12, r10")
+        TEST_RR(    "ssax       r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "ssax       r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe61cff5a      @ ssax  pc, r12, r10")
+        TEST_RR(    "ssub16     r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "ssub16     r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe61cff7a      @ ssub16        pc, r12, r10")
+        TEST_RR(    "sadd8      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "sadd8      r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe61cff9a      @ sadd8 pc, r12, r10")
+        TEST_UNSUPPORTED(".word 0xe61000b0") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe61fffbf") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe61000d0") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe61fffdf") /* Unallocated space */
+        TEST_RR(    "ssub8      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "ssub8      r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe61cfffa      @ ssub8 pc, r12, r10")
+
+        TEST_RR(    "qadd16     r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "qadd16     r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe62cff1a      @ qadd16        pc, r12, r10")
+        TEST_RR(    "qasx       r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "qasx       r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe62cff3a      @ qasx  pc, r12, r10")
+        TEST_RR(    "qsax       r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "qsax       r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe62cff5a      @ qsax  pc, r12, r10")
+        TEST_RR(    "qsub16     r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "qsub16     r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe62cff7a      @ qsub16        pc, r12, r10")
+        TEST_RR(    "qadd8      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "qadd8      r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe62cff9a      @ qadd8 pc, r12, r10")
+        TEST_UNSUPPORTED(".word 0xe62000b0") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe62fffbf") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe62000d0") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe62fffdf") /* Unallocated space */
+        TEST_RR(    "qsub8      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "qsub8      r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe62cfffa      @ qsub8 pc, r12, r10")
+
+        TEST_RR(    "shadd16    r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "shadd16    r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe63cff1a      @ shadd16       pc, r12, r10")
+        TEST_RR(    "shasx      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "shasx      r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe63cff3a      @ shasx pc, r12, r10")
+        TEST_RR(    "shsax      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "shsax      r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe63cff5a      @ shsax pc, r12, r10")
+        TEST_RR(    "shsub16    r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "shsub16    r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe63cff7a      @ shsub16       pc, r12, r10")
+        TEST_RR(    "shadd8     r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "shadd8     r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe63cff9a      @ shadd8        pc, r12, r10")
+        TEST_UNSUPPORTED(".word 0xe63000b0") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe63fffbf") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe63000d0") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe63fffdf") /* Unallocated space */
+        TEST_RR(    "shsub8     r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "shsub8     r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe63cfffa      @ shsub8        pc, r12, r10")
+
+        TEST_GROUP("Parallel addition and subtraction, unsigned")
+
+        TEST_UNSUPPORTED(".word 0xe6400010") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe64fffff") /* Unallocated space */
+
+        TEST_RR(    "uadd16     r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uadd16     r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe65cff1a      @ uadd16        pc, r12, r10")
+        TEST_RR(    "uasx       r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uasx       r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe65cff3a      @ uasx  pc, r12, r10")
+        TEST_RR(    "usax       r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "usax       r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe65cff5a      @ usax  pc, r12, r10")
+        TEST_RR(    "usub16     r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "usub16     r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe65cff7a      @ usub16        pc, r12, r10")
+        TEST_RR(    "uadd8      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uadd8      r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe65cff9a      @ uadd8 pc, r12, r10")
+        TEST_UNSUPPORTED(".word 0xe65000b0") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe65fffbf") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe65000d0") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe65fffdf") /* Unallocated space */
+        TEST_RR(    "usub8      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "usub8      r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe65cfffa      @ usub8 pc, r12, r10")
+
+        TEST_RR(    "uqadd16    r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uqadd16    r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe66cff1a      @ uqadd16       pc, r12, r10")
+        TEST_RR(    "uqasx      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uqasx      r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe66cff3a      @ uqasx pc, r12, r10")
+        TEST_RR(    "uqsax      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uqsax      r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe66cff5a      @ uqsax pc, r12, r10")
+        TEST_RR(    "uqsub16    r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uqsub16    r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe66cff7a      @ uqsub16       pc, r12, r10")
+        TEST_RR(    "uqadd8     r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uqadd8     r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe66cff9a      @ uqadd8        pc, r12, r10")
+        TEST_UNSUPPORTED(".word 0xe66000b0") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe66fffbf") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe66000d0") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe66fffdf") /* Unallocated space */
+        TEST_RR(    "uqsub8     r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uqsub8     r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe66cfffa      @ uqsub8        pc, r12, r10")
+
+        TEST_RR(    "uhadd16    r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uhadd16    r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe67cff1a      @ uhadd16       pc, r12, r10")
+        TEST_RR(    "uhasx      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uhasx      r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe67cff3a      @ uhasx pc, r12, r10")
+        TEST_RR(    "uhsax      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uhsax      r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe67cff5a      @ uhsax pc, r12, r10")
+        TEST_RR(    "uhsub16    r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uhsub16    r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe67cff7a      @ uhsub16       pc, r12, r10")
+        TEST_RR(    "uhadd8     r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uhadd8     r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe67cff9a      @ uhadd8        pc, r12, r10")
+        TEST_UNSUPPORTED(".word 0xe67000b0") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe67fffbf") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe67000d0") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe67fffdf") /* Unallocated space */
+        TEST_RR(    "uhsub8     r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uhsub8     r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe67cfffa      @ uhsub8        pc, r12, r10")
+        TEST_UNSUPPORTED(".word 0xe67feffa      @ uhsub8        r14, pc, r10")
+        TEST_UNSUPPORTED(".word 0xe67cefff      @ uhsub8        r14, r12, pc")
+#endif /* __LINUX_ARM_ARCH__ >= 7 */
+
+#if __LINUX_ARM_ARCH__ >= 6
+        TEST_GROUP("Packing, unpacking, saturation, and reversal")
+
+        TEST_RR(    "pkhbt      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "pkhbt      r14,r",12, HH1,", r",10,HH2,", lsl #2")
+        TEST_UNSUPPORTED(".word 0xe68cf11a      @ pkhbt pc, r12, r10, lsl #2")
+        TEST_RR(    "pkhtb      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "pkhtb      r14,r",12, HH1,", r",10,HH2,", asr #2")
+        TEST_UNSUPPORTED(".word 0xe68cf15a      @ pkhtb pc, r12, r10, asr #2")
+        TEST_UNSUPPORTED(".word 0xe68fe15a      @ pkhtb r14, pc, r10, asr #2")
+        TEST_UNSUPPORTED(".word 0xe68ce15f      @ pkhtb r14, r12, pc, asr #2")
+        TEST_UNSUPPORTED(".word 0xe6900010") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe69fffdf") /* Unallocated space */
+
+        TEST_R(     "ssat       r0, #24, r",0,   VAL1,"")
+        TEST_R(     "ssat       r14, #24, r",12, VAL2,"")
+        TEST_R(     "ssat       r0, #24, r",0,   VAL1,", lsl #8")
+        TEST_R(     "ssat       r14, #24, r",12, VAL2,", asr #8")
+        TEST_UNSUPPORTED(".word 0xe6b7f01c      @ ssat  pc, #24, r12")
+
+        TEST_R(     "usat       r0, #24, r",0,   VAL1,"")
+        TEST_R(     "usat       r14, #24, r",12, VAL2,"")
+        TEST_R(     "usat       r0, #24, r",0,   VAL1,", lsl #8")
+        TEST_R(     "usat       r14, #24, r",12, VAL2,", asr #8")
+        TEST_UNSUPPORTED(".word 0xe6f7f01c      @ usat  pc, #24, r12")
+
+        TEST_RR(    "sxtab16    r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "sxtab16    r14,r",12, HH2,", r",10,HH1,", ror #8")
+        TEST_R(     "sxtb16     r8, r",7,  HH1,"")
+        TEST_UNSUPPORTED(".word 0xe68cf47a      @ sxtab16       pc,r12, r10, ror #8")
+
+        TEST_RR(    "sel        r0, r",0,  VAL1,", r",1, VAL2,"")
+        TEST_RR(    "sel        r14, r",12,VAL1,", r",10, VAL2,"")
+        TEST_UNSUPPORTED(".word 0xe68cffba      @ sel   pc, r12, r10")
+        TEST_UNSUPPORTED(".word 0xe68fefba      @ sel   r14, pc, r10")
+        TEST_UNSUPPORTED(".word 0xe68cefbf      @ sel   r14, r12, pc")
+
+        TEST_R(     "ssat16     r0, #12, r",0,   HH1,"")
+        TEST_R(     "ssat16     r14, #12, r",12, HH2,"")
+        TEST_UNSUPPORTED(".word 0xe6abff3c      @ ssat16        pc, #12, r12")
+
+        TEST_RR(    "sxtab      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "sxtab      r14,r",12, HH2,", r",10,HH1,", ror #8")
+        TEST_R(     "sxtb       r8, r",7,  HH1,"")
+        TEST_UNSUPPORTED(".word 0xe6acf47a      @ sxtab pc,r12, r10, ror #8")
+
+        TEST_R(     "rev        r0, r",0,   VAL1,"")
+        TEST_R(     "rev        r14, r",12, VAL2,"")
+        TEST_UNSUPPORTED(".word 0xe6bfff3c      @ rev   pc, r12")
+
+        TEST_RR(    "sxtah      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "sxtah      r14,r",12, HH2,", r",10,HH1,", ror #8")
+        TEST_R(     "sxth       r8, r",7,  HH1,"")
+        TEST_UNSUPPORTED(".word 0xe6bcf47a      @ sxtah pc,r12, r10, ror #8")
+
+        TEST_R(     "rev16      r0, r",0,   VAL1,"")
+        TEST_R(     "rev16      r14, r",12, VAL2,"")
+        TEST_UNSUPPORTED(".word 0xe6bfffbc      @ rev16 pc, r12")
+
+        TEST_RR(    "uxtab16    r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uxtab16    r14,r",12, HH2,", r",10,HH1,", ror #8")
+        TEST_R(     "uxtb16     r8, r",7,  HH1,"")
+        TEST_UNSUPPORTED(".word 0xe6ccf47a      @ uxtab16       pc,r12, r10, ror #8")
+
+        TEST_R(     "usat16     r0, #12, r",0,   HH1,"")
+        TEST_R(     "usat16     r14, #12, r",12, HH2,"")
+        TEST_UNSUPPORTED(".word 0xe6ecff3c      @ usat16        pc, #12, r12")
+        TEST_UNSUPPORTED(".word 0xe6ecef3f      @ usat16        r14, #12, pc")
+
+        TEST_RR(    "uxtab      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uxtab      r14,r",12, HH2,", r",10,HH1,", ror #8")
+        TEST_R(     "uxtb       r8, r",7,  HH1,"")
+        TEST_UNSUPPORTED(".word 0xe6ecf47a      @ uxtab pc,r12, r10, ror #8")
+
+#if __LINUX_ARM_ARCH__ >= 7
+        TEST_R(     "rbit       r0, r",0,   VAL1,"")
+        TEST_R(     "rbit       r14, r",12, VAL2,"")
+        TEST_UNSUPPORTED(".word 0xe6ffff3c      @ rbit  pc, r12")
+#endif
+
+        TEST_RR(    "uxtah      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uxtah      r14,r",12, HH2,", r",10,HH1,", ror #8")
+        TEST_R(     "uxth       r8, r",7,  HH1,"")
+        TEST_UNSUPPORTED(".word 0xe6fff077      @ uxth  pc, r7")
+        TEST_UNSUPPORTED(".word 0xe6ff807f      @ uxth  r8, pc")
+        TEST_UNSUPPORTED(".word 0xe6fcf47a      @ uxtah pc, r12, r10, ror #8")
+        TEST_UNSUPPORTED(".word 0xe6fce47f      @ uxtah r14, r12, pc, ror #8")
+
+        TEST_R(     "revsh      r0, r",0,   VAL1,"")
+        TEST_R(     "revsh      r14, r",12, VAL2,"")
+        TEST_UNSUPPORTED(".word 0xe6ffff3c      @ revsh pc, r12")
+        TEST_UNSUPPORTED(".word 0xe6ffef3f      @ revsh r14, pc")
+
+        TEST_UNSUPPORTED(".word 0xe6900070") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe69fff7f") /* Unallocated space */
+
+        TEST_UNSUPPORTED(".word 0xe6d00070") /* Unallocated space */
+        TEST_UNSUPPORTED(".word 0xe6dfff7f") /* Unallocated space */
+#endif /* __LINUX_ARM_ARCH__ >= 6 */
+
+#if __LINUX_ARM_ARCH__ >= 6
+        TEST_GROUP("Signed multiplies")
+
+        TEST_RRR(   "smlad      r0, r",0,  HH1,", r",1, HH2,", r",2, VAL1,"")
+        TEST_RRR(   "smlad      r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
+        TEST_UNSUPPORTED(".word 0xe70f8a1c      @ smlad pc, r12, r10, r8")
+        TEST_RRR(   "smladx     r0, r",0,  HH1,", r",1, HH2,", r",2, VAL1,"")
+        TEST_RRR(   "smladx     r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
+        TEST_UNSUPPORTED(".word 0xe70f8a3c      @ smladx        pc, r12, r10, r8")
+
+        TEST_RR(   "smuad       r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(   "smuad       r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe70ffa1c      @ smuad pc, r12, r10")
+        TEST_RR(   "smuadx      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(   "smuadx      r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe70ffa3c      @ smuadx        pc, r12, r10")
+
+        TEST_RRR(   "smlsd      r0, r",0,  HH1,", r",1, HH2,", r",2, VAL1,"")
+        TEST_RRR(   "smlsd      r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
+        TEST_UNSUPPORTED(".word 0xe70f8a5c      @ smlsd pc, r12, r10, r8")
+        TEST_RRR(   "smlsdx     r0, r",0,  HH1,", r",1, HH2,", r",2, VAL1,"")
+        TEST_RRR(   "smlsdx     r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
+        TEST_UNSUPPORTED(".word 0xe70f8a7c      @ smlsdx        pc, r12, r10, r8")
+
+        TEST_RR(   "smusd       r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(   "smusd       r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe70ffa5c      @ smusd pc, r12, r10")
+        TEST_RR(   "smusdx      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(   "smusdx      r14, r",12,HH2,", r",10,HH1,"")
+        TEST_UNSUPPORTED(".word 0xe70ffa7c      @ smusdx        pc, r12, r10")
+
+        TEST_RRRR( "smlald      r",0, VAL1,", r",1, VAL2, ", r",0, HH1,", r",1, HH2)
+        TEST_RRRR( "smlald      r",11,VAL2,", r",10,VAL1, ", r",9, HH2,", r",8, HH1)
+        TEST_UNSUPPORTED(".word 0xe74af819      @ smlald        pc, r10, r9, r8")
+        TEST_UNSUPPORTED(".word 0xe74fb819      @ smlald        r11, pc, r9, r8")
+        TEST_UNSUPPORTED(".word 0xe74ab81f      @ smlald        r11, r10, pc, r8")
+        TEST_UNSUPPORTED(".word 0xe74abf19      @ smlald        r11, r10, r9, pc")
+
+        TEST_RRRR( "smlaldx     r",0, VAL1,", r",1, VAL2, ", r",0, HH1,", r",1, HH2)
+        TEST_RRRR( "smlaldx     r",11,VAL2,", r",10,VAL1, ", r",9, HH2,", r",8, HH1)
+        TEST_UNSUPPORTED(".word 0xe74af839      @ smlaldx       pc, r10, r9, r8")
+        TEST_UNSUPPORTED(".word 0xe74fb839      @ smlaldx       r11, pc, r9, r8")
+
+        TEST_RRR(  "smmla       r0, r",0,  VAL1,", r",1, VAL2,", r",2, VAL1,"")
+        TEST_RRR(  "smmla       r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
+        TEST_UNSUPPORTED(".word 0xe75f8a1c      @ smmla pc, r12, r10, r8")
+        TEST_RRR(  "smmlar      r0, r",0,  VAL1,", r",1, VAL2,", r",2, VAL1,"")
+        TEST_RRR(  "smmlar      r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
+        TEST_UNSUPPORTED(".word 0xe75f8a3c      @ smmlar        pc, r12, r10, r8")
+
+        TEST_RR(   "smmul       r0, r",0,  VAL1,", r",1, VAL2,"")
+        TEST_RR(   "smmul       r14, r",12,VAL2,", r",10,VAL1,"")
+        TEST_UNSUPPORTED(".word 0xe75ffa1c      @ smmul pc, r12, r10")
+        TEST_RR(   "smmulr      r0, r",0,  VAL1,", r",1, VAL2,"")
+        TEST_RR(   "smmulr      r14, r",12,VAL2,", r",10,VAL1,"")
+        TEST_UNSUPPORTED(".word 0xe75ffa3c      @ smmulr        pc, r12, r10")
+
+        TEST_RRR(  "smmls       r0, r",0,  VAL1,", r",1, VAL2,", r",2, VAL1,"")
+        TEST_RRR(  "smmls       r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
+        TEST_UNSUPPORTED(".word 0xe75f8adc      @ smmls pc, r12, r10, r8")
+        TEST_RRR(  "smmlsr      r0, r",0,  VAL1,", r",1, VAL2,", r",2, VAL1,"")
+        TEST_RRR(  "smmlsr      r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
+        TEST_UNSUPPORTED(".word 0xe75f8afc      @ smmlsr        pc, r12, r10, r8")
+        TEST_UNSUPPORTED(".word 0xe75e8aff      @ smmlsr        r14, pc, r10, r8")
+        TEST_UNSUPPORTED(".word 0xe75e8ffc      @ smmlsr        r14, r12, pc, r8")
+        TEST_UNSUPPORTED(".word 0xe75efafc      @ smmlsr        r14, r12, r10, pc")
+
+        TEST_RR(   "usad8       r0, r",0,  VAL1,", r",1, VAL2,"")
+        TEST_RR(   "usad8       r14, r",12,VAL2,", r",10,VAL1,"")
+        TEST_UNSUPPORTED(".word 0xe75ffa1c      @ usad8 pc, r12, r10")
+        TEST_UNSUPPORTED(".word 0xe75efa1f      @ usad8 r14, pc, r10")
+        TEST_UNSUPPORTED(".word 0xe75eff1c      @ usad8 r14, r12, pc")
+
+        TEST_RRR(  "usada8      r0, r",0,  VAL1,", r",1, VAL2,", r",2, VAL3,"")
+        TEST_RRR(  "usada8      r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL3,"")
+        TEST_UNSUPPORTED(".word 0xe78f8a1c      @ usada8        pc, r12, r10, r8")
+        TEST_UNSUPPORTED(".word 0xe78e8a1f      @ usada8        r14, pc, r10, r8")
+        TEST_UNSUPPORTED(".word 0xe78e8f1c      @ usada8        r14, r12, pc, r8")
+#endif /* __LINUX_ARM_ARCH__ >= 6 */
+
+#if __LINUX_ARM_ARCH__ >= 7
+        TEST_GROUP("Bit Field")
+
+        TEST_R(     "sbfx       r0, r",0  , VAL1,", #0, #31")
+        TEST_R(     "sbfxeq     r14, r",12, VAL2,", #8, #16")
+        TEST_R(     "sbfx       r4, r",10,  VAL1,", #16, #15")
+        TEST_UNSUPPORTED(".word 0xe7aff45c      @ sbfx  pc, r12, #8, #16")
+
+        TEST_R(     "ubfx       r0, r",0  , VAL1,", #0, #31")
+        TEST_R(     "ubfxcs     r14, r",12, VAL2,", #8, #16")
+        TEST_R(     "ubfx       r4, r",10,  VAL1,", #16, #15")
+        TEST_UNSUPPORTED(".word 0xe7eff45c      @ ubfx  pc, r12, #8, #16")
+        TEST_UNSUPPORTED(".word 0xe7efc45f      @ ubfx  r12, pc, #8, #16")
+
+        TEST_R(     "bfc        r",0, VAL1,", #4, #20")
+        TEST_R(     "bfcvs      r",14,VAL2,", #4, #20")
+        TEST_R(     "bfc        r",7, VAL1,", #0, #31")
+        TEST_R(     "bfc        r",8, VAL2,", #0, #31")
+        TEST_UNSUPPORTED(".word 0xe7def01f      @ bfc   pc, #0, #31");
+
+        TEST_RR(    "bfi        r",0, VAL1,", r",0  , VAL2,", #0, #31")
+        TEST_RR(    "bfipl      r",12,VAL1,", r",14 , VAL2,", #4, #20")
+        TEST_UNSUPPORTED(".word 0xe7d7f21e      @ bfi   pc, r14, #4, #20")
+
+        TEST_UNSUPPORTED(".word 0x07f000f0")  /* Permanently UNDEFINED */
+        TEST_UNSUPPORTED(".word 0x07ffffff")  /* Permanently UNDEFINED */
+#endif /* __LINUX_ARM_ARCH__ >= 6 */
+
+        TEST_GROUP("Branch, branch with link, and block data transfer")
+
+        TEST_P(   "stmda        r",0, 16*4,", {r0}")
+        TEST_P(   "stmeqda      r",4, 16*4,", {r0-r15}")
+        TEST_P(   "stmneda      r",8, 16*4,"!, {r8-r15}")
+        TEST_P(   "stmda        r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
+        TEST_P(   "stmda        r",13,0,   "!, {pc}")
+
+        TEST_P(   "ldmda        r",0, 16*4,", {r0}")
+        TEST_BF_P("ldmcsda      r",4, 15*4,", {r0-r15}")
+        TEST_BF_P("ldmccda      r",7, 15*4,"!, {r8-r15}")
+        TEST_P(   "ldmda        r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
+        TEST_BF_P("ldmda        r",14,15*4,"!, {pc}")
+
+        TEST_P(   "stmia        r",0, 16*4,", {r0}")
+        TEST_P(   "stmmiia      r",4, 16*4,", {r0-r15}")
+        TEST_P(   "stmplia      r",8, 16*4,"!, {r8-r15}")
+        TEST_P(   "stmia        r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
+        TEST_P(   "stmia        r",14,0,   "!, {pc}")
+
+        TEST_P(   "ldmia        r",0, 16*4,", {r0}")
+        TEST_BF_P("ldmvsia      r",4, 0,   ", {r0-r15}")
+        TEST_BF_P("ldmvcia      r",7, 8*4, "!, {r8-r15}")
+        TEST_P(   "ldmia        r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
+        TEST_BF_P("ldmia        r",14,15*4,"!, {pc}")
+
+        TEST_P(   "stmdb        r",0, 16*4,", {r0}")
+        TEST_P(   "stmhidb      r",4, 16*4,", {r0-r15}")
+        TEST_P(   "stmlsdb      r",8, 16*4,"!, {r8-r15}")
+        TEST_P(   "stmdb        r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
+        TEST_P(   "stmdb        r",13,4,   "!, {pc}")
+
+        TEST_P(   "ldmdb        r",0, 16*4,", {r0}")
+        TEST_BF_P("ldmgedb      r",4, 16*4,", {r0-r15}")
+        TEST_BF_P("ldmltdb      r",7, 16*4,"!, {r8-r15}")
+        TEST_P(   "ldmdb        r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
+        TEST_BF_P("ldmdb        r",14,16*4,"!, {pc}")
+
+        TEST_P(   "stmib        r",0, 16*4,", {r0}")
+        TEST_P(   "stmgtib      r",4, 16*4,", {r0-r15}")
+        TEST_P(   "stmleib      r",8, 16*4,"!, {r8-r15}")
+        TEST_P(   "stmib        r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
+        TEST_P(   "stmib        r",13,-4,  "!, {pc}")
+
+        TEST_P(   "ldmib        r",0, 16*4,", {r0}")
+        TEST_BF_P("ldmeqib      r",4, -4,", {r0-r15}")
+        TEST_BF_P("ldmneib      r",7, 7*4,"!, {r8-r15}")
+        TEST_P(   "ldmib        r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
+        TEST_BF_P("ldmib        r",14,14*4,"!, {pc}")
+
+        TEST_P(   "stmdb        r",13,16*4,"!, {r3-r12,lr}")
+        TEST_P(   "stmeqdb      r",13,16*4,"!, {r3-r12}")
+        TEST_P(   "stmnedb      r",2, 16*4,", {r3-r12,lr}")
+        TEST_P(   "stmdb        r",13,16*4,"!, {r2-r12,lr}")
+        TEST_P(   "stmdb        r",0, 16*4,", {r0-r12}")
+        TEST_P(   "stmdb        r",0, 16*4,", {r0-r12,lr}")
+
+        TEST_BF_P("ldmia        r",13,5*4, "!, {r3-r12,pc}")
+        TEST_P(   "ldmccia      r",13,5*4, "!, {r3-r12}")
+        TEST_BF_P("ldmcsia      r",2, 5*4, "!, {r3-r12,pc}")
+        TEST_BF_P("ldmia        r",13,4*4, "!, {r2-r12,pc}")
+        TEST_P(   "ldmia        r",0, 16*4,", {r0-r12}")
+        TEST_P(   "ldmia        r",0, 16*4,", {r0-r12,lr}")
+
+#ifdef CONFIG_THUMB2_KERNEL
+        TEST_ARM_TO_THUMB_INTERWORK_P("ldmplia  r",0,15*4,", {pc}")
+        TEST_ARM_TO_THUMB_INTERWORK_P("ldmmiia  r",13,0,", {r0-r15}")
+#endif
+        TEST_BF("b      2f")
+        TEST_BF("bl     2f")
+        TEST_BB("b      2b")
+        TEST_BB("bl     2b")
+
+        TEST_BF("beq    2f")
+        TEST_BF("bleq   2f")
+        TEST_BB("bne    2b")
+        TEST_BB("blne   2b")
+
+        TEST_BF("bgt    2f")
+        TEST_BF("blgt   2f")
+        TEST_BB("blt    2b")
+        TEST_BB("bllt   2b")
+
+        TEST_GROUP("Supervisor Call, and coprocessor instructions")
+
+        /*
+         * We can't really test these by executing them, so all
+         * we can do is check that probes are, or are not allowed.
+         * At the moment none are allowed...
+         */
+#define TEST_COPROCESSOR(code) TEST_UNSUPPORTED(code)
+
+#define COPROCESSOR_INSTRUCTIONS_ST_LD(two,cc)                                  \
+        TEST_COPROCESSOR("stc"two"      0, cr0, [r13, #4]")                     \
+        TEST_COPROCESSOR("stc"two"      0, cr0, [r13, #-4]")                    \
+        TEST_COPROCESSOR("stc"two"      0, cr0, [r13, #4]!")                    \
+        TEST_COPROCESSOR("stc"two"      0, cr0, [r13, #-4]!")                   \
+        TEST_COPROCESSOR("stc"two"      0, cr0, [r13], #4")                     \
+        TEST_COPROCESSOR("stc"two"      0, cr0, [r13], #-4")                    \
+        TEST_COPROCESSOR("stc"two"      0, cr0, [r13], {1}")                    \
+        TEST_COPROCESSOR("stc"two"l     0, cr0, [r13, #4]")                     \
+        TEST_COPROCESSOR("stc"two"l     0, cr0, [r13, #-4]")                    \
+        TEST_COPROCESSOR("stc"two"l     0, cr0, [r13, #4]!")                    \
+        TEST_COPROCESSOR("stc"two"l     0, cr0, [r13, #-4]!")                   \
+        TEST_COPROCESSOR("stc"two"l     0, cr0, [r13], #4")                     \
+        TEST_COPROCESSOR("stc"two"l     0, cr0, [r13], #-4")                    \
+        TEST_COPROCESSOR("stc"two"l     0, cr0, [r13], {1}")                    \
+        TEST_COPROCESSOR("ldc"two"      0, cr0, [r13, #4]")                     \
+        TEST_COPROCESSOR("ldc"two"      0, cr0, [r13, #-4]")                    \
+        TEST_COPROCESSOR("ldc"two"      0, cr0, [r13, #4]!")                    \
+        TEST_COPROCESSOR("ldc"two"      0, cr0, [r13, #-4]!")                   \
+        TEST_COPROCESSOR("ldc"two"      0, cr0, [r13], #4")                     \
+        TEST_COPROCESSOR("ldc"two"      0, cr0, [r13], #-4")                    \
+        TEST_COPROCESSOR("ldc"two"      0, cr0, [r13], {1}")                    \
+        TEST_COPROCESSOR("ldc"two"l     0, cr0, [r13, #4]")                     \
+        TEST_COPROCESSOR("ldc"two"l     0, cr0, [r13, #-4]")                    \
+        TEST_COPROCESSOR("ldc"two"l     0, cr0, [r13, #4]!")                    \
+        TEST_COPROCESSOR("ldc"two"l     0, cr0, [r13, #-4]!")                   \
+        TEST_COPROCESSOR("ldc"two"l     0, cr0, [r13], #4")                     \
+        TEST_COPROCESSOR("ldc"two"l     0, cr0, [r13], #-4")                    \
+        TEST_COPROCESSOR("ldc"two"l     0, cr0, [r13], {1}")                    \
+                                                                                \
+        TEST_COPROCESSOR( "stc"two"     0, cr0, [r15, #4]")                     \
+        TEST_COPROCESSOR( "stc"two"     0, cr0, [r15, #-4]")                    \
+        TEST_UNSUPPORTED(".word 0x"cc"daf0001   @ stc"two"      0, cr0, [r15, #4]!")    \
+        TEST_UNSUPPORTED(".word 0x"cc"d2f0001   @ stc"two"      0, cr0, [r15, #-4]!")   \
+        TEST_UNSUPPORTED(".word 0x"cc"caf0001   @ stc"two"      0, cr0, [r15], #4")     \
+        TEST_UNSUPPORTED(".word 0x"cc"c2f0001   @ stc"two"      0, cr0, [r15], #-4")    \
+        TEST_COPROCESSOR( "stc"two"     0, cr0, [r15], {1}")                    \
+        TEST_COPROCESSOR( "stc"two"l    0, cr0, [r15, #4]")                     \
+        TEST_COPROCESSOR( "stc"two"l    0, cr0, [r15, #-4]")                    \
+        TEST_UNSUPPORTED(".word 0x"cc"def0001   @ stc"two"l     0, cr0, [r15, #4]!")    \
+        TEST_UNSUPPORTED(".word 0x"cc"d6f0001   @ stc"two"l     0, cr0, [r15, #-4]!")   \
+        TEST_UNSUPPORTED(".word 0x"cc"cef0001   @ stc"two"l     0, cr0, [r15], #4")     \
+        TEST_UNSUPPORTED(".word 0x"cc"c6f0001   @ stc"two"l     0, cr0, [r15], #-4")    \
+        TEST_COPROCESSOR( "stc"two"l    0, cr0, [r15], {1}")                    \
+        TEST_COPROCESSOR( "ldc"two"     0, cr0, [r15, #4]")                     \
+        TEST_COPROCESSOR( "ldc"two"     0, cr0, [r15, #-4]")                    \
+        TEST_UNSUPPORTED(".word 0x"cc"dbf0001   @ ldc"two"      0, cr0, [r15, #4]!")    \
+        TEST_UNSUPPORTED(".word 0x"cc"d3f0001   @ ldc"two"      0, cr0, [r15, #-4]!")   \
+        TEST_UNSUPPORTED(".word 0x"cc"cbf0001   @ ldc"two"      0, cr0, [r15], #4")     \
+        TEST_UNSUPPORTED(".word 0x"cc"c3f0001   @ ldc"two"      0, cr0, [r15], #-4")    \
+        TEST_COPROCESSOR( "ldc"two"     0, cr0, [r15], {1}")                    \
+        TEST_COPROCESSOR( "ldc"two"l    0, cr0, [r15, #4]")                     \
+        TEST_COPROCESSOR( "ldc"two"l    0, cr0, [r15, #-4]")                    \
+        TEST_UNSUPPORTED(".word 0x"cc"dff0001   @ ldc"two"l     0, cr0, [r15, #4]!")    \
+        TEST_UNSUPPORTED(".word 0x"cc"d7f0001   @ ldc"two"l     0, cr0, [r15, #-4]!")   \
+        TEST_UNSUPPORTED(".word 0x"cc"cff0001   @ ldc"two"l     0, cr0, [r15], #4")     \
+        TEST_UNSUPPORTED(".word 0x"cc"c7f0001   @ ldc"two"l     0, cr0, [r15], #-4")    \
+        TEST_COPROCESSOR( "ldc"two"l    0, cr0, [r15], {1}")
+
+#define COPROCESSOR_INSTRUCTIONS_MC_MR(two,cc)                                  \
+                                                                                \
+        TEST_COPROCESSOR( "mcrr"two"    0, 15, r0, r14, cr0")                   \
+        TEST_COPROCESSOR( "mcrr"two"    15, 0, r14, r0, cr15")                  \
+        TEST_UNSUPPORTED(".word 0x"cc"c4f00f0   @ mcrr"two"     0, 15, r0, r15, cr0")   \
+        TEST_UNSUPPORTED(".word 0x"cc"c40ff0f   @ mcrr"two"     15, 0, r15, r0, cr15")  \
+        TEST_COPROCESSOR( "mrrc"two"    0, 15, r0, r14, cr0")                   \
+        TEST_COPROCESSOR( "mrrc"two"    15, 0, r14, r0, cr15")                  \
+        TEST_UNSUPPORTED(".word 0x"cc"c5f00f0   @ mrrc"two"     0, 15, r0, r15, cr0")   \
+        TEST_UNSUPPORTED(".word 0x"cc"c50ff0f   @ mrrc"two"     15, 0, r15, r0, cr15")  \
+        TEST_COPROCESSOR( "cdp"two"     15, 15, cr15, cr15, cr15, 7")           \
+        TEST_COPROCESSOR( "cdp"two"     0, 0, cr0, cr0, cr0, 0")                \
+        TEST_COPROCESSOR( "mcr"two"     15, 7, r15, cr15, cr15, 7")             \
+        TEST_COPROCESSOR( "mcr"two"     0, 0, r0, cr0, cr0, 0")                 \
+        TEST_COPROCESSOR( "mrc"two"     15, 7, r15, cr15, cr15, 7")             \
+        TEST_COPROCESSOR( "mrc"two"     0, 0, r0, cr0, cr0, 0")
+
+        COPROCESSOR_INSTRUCTIONS_ST_LD("","e")
+        COPROCESSOR_INSTRUCTIONS_MC_MR("","e")
+        TEST_UNSUPPORTED("svc   0")
+        TEST_UNSUPPORTED("svc   0xffffff")
+
+        TEST_UNSUPPORTED("svc   0")
+
+        TEST_GROUP("Unconditional instruction")
+
+#if __LINUX_ARM_ARCH__ >= 6
+        TEST_UNSUPPORTED("srsda sp, 0x13")
+        TEST_UNSUPPORTED("srsdb sp, 0x13")
+        TEST_UNSUPPORTED("srsia sp, 0x13")
+        TEST_UNSUPPORTED("srsib sp, 0x13")
+        TEST_UNSUPPORTED("srsda sp!, 0x13")
+        TEST_UNSUPPORTED("srsdb sp!, 0x13")
+        TEST_UNSUPPORTED("srsia sp!, 0x13")
+        TEST_UNSUPPORTED("srsib sp!, 0x13")
+
+        TEST_UNSUPPORTED("rfeda sp")
+        TEST_UNSUPPORTED("rfedb sp")
+        TEST_UNSUPPORTED("rfeia sp")
+        TEST_UNSUPPORTED("rfeib sp")
+        TEST_UNSUPPORTED("rfeda sp!")
+        TEST_UNSUPPORTED("rfedb sp!")
+        TEST_UNSUPPORTED("rfeia sp!")
+        TEST_UNSUPPORTED("rfeib sp!")
+        TEST_UNSUPPORTED(".word 0xf81d0a00      @ rfeda pc")
+        TEST_UNSUPPORTED(".word 0xf91d0a00      @ rfedb pc")
+        TEST_UNSUPPORTED(".word 0xf89d0a00      @ rfeia pc")
+        TEST_UNSUPPORTED(".word 0xf99d0a00      @ rfeib pc")
+        TEST_UNSUPPORTED(".word 0xf83d0a00      @ rfeda pc!")
+        TEST_UNSUPPORTED(".word 0xf93d0a00      @ rfedb pc!")
+        TEST_UNSUPPORTED(".word 0xf8bd0a00      @ rfeia pc!")
+        TEST_UNSUPPORTED(".word 0xf9bd0a00      @ rfeib pc!")
+#endif /* __LINUX_ARM_ARCH__ >= 6 */
+
+#if __LINUX_ARM_ARCH__ >= 6
+        TEST_X( "blx    __dummy_thumb_subroutine_even",
+                ".thumb                         \n\t"
+                ".space 4                       \n\t"
+                ".type __dummy_thumb_subroutine_even, %%function \n\t"
+                "__dummy_thumb_subroutine_even: \n\t"
+                "mov    r0, pc                  \n\t"
+                "bx     lr                      \n\t"
+                ".arm                           \n\t"
+        )
+        TEST(   "blx    __dummy_thumb_subroutine_even")
+
+        TEST_X( "blx    __dummy_thumb_subroutine_odd",
+                ".thumb                         \n\t"
+                ".space 2                       \n\t"
+                ".type __dummy_thumb_subroutine_odd, %%function \n\t"
+                "__dummy_thumb_subroutine_odd:  \n\t"
+                "mov    r0, pc                  \n\t"
+                "bx     lr                      \n\t"
+                ".arm                           \n\t"
+        )
+        TEST(   "blx    __dummy_thumb_subroutine_odd")
+#endif /* __LINUX_ARM_ARCH__ >= 6 */
+
+        COPROCESSOR_INSTRUCTIONS_ST_LD("2","f")
+#if __LINUX_ARM_ARCH__ >= 6
+        COPROCESSOR_INSTRUCTIONS_MC_MR("2","f")
+#endif
+
+        TEST_GROUP("Miscellaneous instructions, memory hints, and Advanced SIMD instructions")
+
+#if __LINUX_ARM_ARCH__ >= 6
+        TEST_UNSUPPORTED("cps   0x13")
+        TEST_UNSUPPORTED("cpsie i")
+        TEST_UNSUPPORTED("cpsid i")
+        TEST_UNSUPPORTED("cpsie i,0x13")
+        TEST_UNSUPPORTED("cpsid i,0x13")
+        TEST_UNSUPPORTED("setend        le")
+        TEST_UNSUPPORTED("setend        be")
+#endif
+
+#if __LINUX_ARM_ARCH__ >= 7
+        TEST_P("pli     [r",0,0b,", #16]")
+        TEST(  "pli     [pc, #0]")
+        TEST_RR("pli    [r",12,0b,", r",0, 16,"]")
+        TEST_RR("pli    [r",0, 0b,", -r",12,16,", lsl #4]")
+#endif
+
+#if __LINUX_ARM_ARCH__ >= 5
+        TEST_P("pld     [r",0,32,", #-16]")
+        TEST(  "pld     [pc, #0]")
+        TEST_PR("pld    [r",7, 24, ", r",0, 16,"]")
+        TEST_PR("pld    [r",8, 24, ", -r",12,16,", lsl #4]")
+#endif
+
+#if __LINUX_ARM_ARCH__ >= 7
+        TEST_SUPPORTED(  ".word 0xf590f000      @ pldw [r0, #0]")
+        TEST_SUPPORTED(  ".word 0xf797f000      @ pldw  [r7, r0]")
+        TEST_SUPPORTED(  ".word 0xf798f18c      @ pldw  [r8, r12, lsl #3]");
+#endif
+
+#if __LINUX_ARM_ARCH__ >= 7
+        TEST_UNSUPPORTED("clrex")
+        TEST_UNSUPPORTED("dsb")
+        TEST_UNSUPPORTED("dmb")
+        TEST_UNSUPPORTED("isb")
+#endif
+
+        verbose("\n");
+}
+
diff --git a/arch/arm/kernel/kprobes-test-thumb.c b/arch/arm/kernel/kprobes-test-thumb.c
new file mode 100644
index 000000000000..5e726c31c45a
--- /dev/null
+++ b/arch/arm/kernel/kprobes-test-thumb.c
@@ -0,0 +1,1187 @@
+/*
+ * arch/arm/kernel/kprobes-test-thumb.c
+ *
+ * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include "kprobes-test.h"
+
+
+#define TEST_ISA "16"
+
+#define DONT_TEST_IN_ITBLOCK(tests)                     \
+        kprobe_test_flags |= TEST_FLAG_NO_ITBLOCK;      \
+        tests                                           \
+        kprobe_test_flags &= ~TEST_FLAG_NO_ITBLOCK;
+
+#define CONDITION_INSTRUCTIONS(cc_pos, tests)           \
+        kprobe_test_cc_position = cc_pos;               \
+        DONT_TEST_IN_ITBLOCK(tests)                     \
+        kprobe_test_cc_position = 0;
+
+#define TEST_ITBLOCK(code)                              \
+        kprobe_test_flags |= TEST_FLAG_FULL_ITBLOCK;    \
+        TESTCASE_START(code)                            \
+        TEST_ARG_END("")                                \
+        "50:    nop                     \n\t"           \
+        "1:     "code"                  \n\t"           \
+        "       mov r1, #0x11           \n\t"           \
+        "       mov r2, #0x22           \n\t"           \
+        "       mov r3, #0x33           \n\t"           \
+        "2:     nop                     \n\t"           \
+        TESTCASE_END                                    \
+        kprobe_test_flags &= ~TEST_FLAG_FULL_ITBLOCK;
+
+#define TEST_THUMB_TO_ARM_INTERWORK_P(code1, reg, val, code2)   \
+        TESTCASE_START(code1 #reg code2)                        \
+        TEST_ARG_PTR(reg, val)                                  \
+        TEST_ARG_REG(14, 99f+1)                                 \
+        TEST_ARG_MEM(15, 3f)                                    \
+        TEST_ARG_END("")                                        \
+        "       nop                     \n\t" /* To align 1f */ \
+        "50:    nop                     \n\t"                   \
+        "1:     "code1 #reg code2"      \n\t"                   \
+        "       bx      lr              \n\t"                   \
+        ".arm                           \n\t"                   \
+        "3:     adr     lr, 2f+1        \n\t"                   \
+        "       bx      lr              \n\t"                   \
+        ".thumb                         \n\t"                   \
+        "2:     nop                     \n\t"                   \
+        TESTCASE_END
+
+
+void kprobe_thumb16_test_cases(void)
+{
+        kprobe_test_flags = TEST_FLAG_NARROW_INSTR;
+
+        TEST_GROUP("Shift (immediate), add, subtract, move, and compare")
+
+        TEST_R(    "lsls        r7, r",0,VAL1,", #5")
+        TEST_R(    "lsls        r0, r",7,VAL2,", #11")
+        TEST_R(    "lsrs        r7, r",0,VAL1,", #5")
+        TEST_R(    "lsrs        r0, r",7,VAL2,", #11")
+        TEST_R(    "asrs        r7, r",0,VAL1,", #5")
+        TEST_R(    "asrs        r0, r",7,VAL2,", #11")
+        TEST_RR(   "adds        r2, r",0,VAL1,", r",7,VAL2,"")
+        TEST_RR(   "adds        r5, r",7,VAL2,", r",0,VAL2,"")
+        TEST_RR(   "subs        r2, r",0,VAL1,", r",7,VAL2,"")
+        TEST_RR(   "subs        r5, r",7,VAL2,", r",0,VAL2,"")
+        TEST_R(    "adds        r7, r",0,VAL1,", #5")
+        TEST_R(    "adds        r0, r",7,VAL2,", #2")
+        TEST_R(    "subs        r7, r",0,VAL1,", #5")
+        TEST_R(    "subs        r0, r",7,VAL2,", #2")
+        TEST(      "movs.n      r0, #0x5f")
+        TEST(      "movs.n      r7, #0xa0")
+        TEST_R(    "cmp.n       r",0,0x5e, ", #0x5f")
+        TEST_R(    "cmp.n       r",5,0x15f,", #0x5f")
+        TEST_R(    "cmp.n       r",7,0xa0, ", #0xa0")
+        TEST_R(    "adds.n      r",0,VAL1,", #0x5f")
+        TEST_R(    "adds.n      r",7,VAL2,", #0xa0")
+        TEST_R(    "subs.n      r",0,VAL1,", #0x5f")
+        TEST_R(    "subs.n      r",7,VAL2,", #0xa0")
+
+        TEST_GROUP("16-bit Thumb data-processing instructions")
+
+#define DATA_PROCESSING16(op,val)                       \
+        TEST_RR(   op"  r",0,VAL1,", r",7,val,"")       \
+        TEST_RR(   op"  r",7,VAL2,", r",0,val,"")
+
+        DATA_PROCESSING16("ands",0xf00f00ff)
+        DATA_PROCESSING16("eors",0xf00f00ff)
+        DATA_PROCESSING16("lsls",11)
+        DATA_PROCESSING16("lsrs",11)
+        DATA_PROCESSING16("asrs",11)
+        DATA_PROCESSING16("adcs",VAL2)
+        DATA_PROCESSING16("sbcs",VAL2)
+        DATA_PROCESSING16("rors",11)
+        DATA_PROCESSING16("tst",0xf00f00ff)
+        TEST_R("rsbs    r",0,VAL1,", #0")
+        TEST_R("rsbs    r",7,VAL2,", #0")
+        DATA_PROCESSING16("cmp",0xf00f00ff)
+        DATA_PROCESSING16("cmn",0xf00f00ff)
+        DATA_PROCESSING16("orrs",0xf00f00ff)
+        DATA_PROCESSING16("muls",VAL2)
+        DATA_PROCESSING16("bics",0xf00f00ff)
+        DATA_PROCESSING16("mvns",VAL2)
+
+        TEST_GROUP("Special data instructions and branch and exchange")
+
+        TEST_RR(  "add  r",0, VAL1,", r",7,VAL2,"")
+        TEST_RR(  "add  r",3, VAL2,", r",8,VAL3,"")
+        TEST_RR(  "add  r",8, VAL3,", r",0,VAL1,"")
+        TEST_R(   "add  sp"        ", r",8,-8,  "")
+        TEST_R(   "add  r",14,VAL1,", pc")
+        TEST_BF_R("add  pc"        ", r",0,2f-1f-8,"")
+        TEST_UNSUPPORTED(".short 0x44ff @ add pc, pc")
+
+        TEST_RR(  "cmp  r",3,VAL1,", r",8,VAL2,"")
+        TEST_RR(  "cmp  r",8,VAL2,", r",0,VAL1,"")
+        TEST_R(   "cmp  sp"       ", r",8,-8,  "")
+
+        TEST_R(   "mov  r0, r",7,VAL2,"")
+        TEST_R(   "mov  r3, r",8,VAL3,"")
+        TEST_R(   "mov  r8, r",0,VAL1,"")
+        TEST_P(   "mov  sp, r",8,-8,  "")
+        TEST(     "mov  lr, pc")
+        TEST_BF_R("mov  pc, r",0,2f,  "")
+
+        TEST_BF_R("bx   r",0, 2f+1,"")
+        TEST_BF_R("bx   r",14,2f+1,"")
+        TESTCASE_START("bx      pc")
+                TEST_ARG_REG(14, 99f+1)
+                TEST_ARG_END("")
+                "       nop                     \n\t" /* To align the bx pc*/
+                "50:    nop                     \n\t"
+                "1:     bx      pc              \n\t"
+                "       bx      lr              \n\t"
+                ".arm                           \n\t"
+                "       adr     lr, 2f+1        \n\t"
+                "       bx      lr              \n\t"
+                ".thumb                         \n\t"
+                "2:     nop                     \n\t"
+        TESTCASE_END
+
+        TEST_BF_R("blx  r",0, 2f+1,"")
+        TEST_BB_R("blx  r",14,2f+1,"")
+        TEST_UNSUPPORTED(".short 0x47f8 @ blx pc")
+
+        TEST_GROUP("Load from Literal Pool")
+
+        TEST_X( "ldr    r0, 3f",
+                ".align                                 \n\t"
+                "3:     .word   "__stringify(VAL1))
+        TEST_X( "ldr    r7, 3f",
+                ".space 128                             \n\t"
+                ".align                                 \n\t"
+                "3:     .word   "__stringify(VAL2))
+
+        TEST_GROUP("16-bit Thumb Load/store instructions")
+
+        TEST_RPR("str   r",0, VAL1,", [r",1, 24,", r",2,  48,"]")
+        TEST_RPR("str   r",7, VAL2,", [r",6, 24,", r",5,  48,"]")
+        TEST_RPR("strh  r",0, VAL1,", [r",1, 24,", r",2,  48,"]")
+        TEST_RPR("strh  r",7, VAL2,", [r",6, 24,", r",5,  48,"]")
+        TEST_RPR("strb  r",0, VAL1,", [r",1, 24,", r",2,  48,"]")
+        TEST_RPR("strb  r",7, VAL2,", [r",6, 24,", r",5,  48,"]")
+        TEST_PR( "ldrsb r0, [r",1, 24,", r",2,  48,"]")
+        TEST_PR( "ldrsb r7, [r",6, 24,", r",5,  50,"]")
+        TEST_PR( "ldr   r0, [r",1, 24,", r",2,  48,"]")
+        TEST_PR( "ldr   r7, [r",6, 24,", r",5,  48,"]")
+        TEST_PR( "ldrh  r0, [r",1, 24,", r",2,  48,"]")
+        TEST_PR( "ldrh  r7, [r",6, 24,", r",5,  50,"]")
+        TEST_PR( "ldrb  r0, [r",1, 24,", r",2,  48,"]")
+        TEST_PR( "ldrb  r7, [r",6, 24,", r",5,  50,"]")
+        TEST_PR( "ldrsh r0, [r",1, 24,", r",2,  48,"]")
+        TEST_PR( "ldrsh r7, [r",6, 24,", r",5,  50,"]")
+
+        TEST_RP("str    r",0, VAL1,", [r",1, 24,", #120]")
+        TEST_RP("str    r",7, VAL2,", [r",6, 24,", #120]")
+        TEST_P( "ldr    r0, [r",1, 24,", #120]")
+        TEST_P( "ldr    r7, [r",6, 24,", #120]")
+        TEST_RP("strb   r",0, VAL1,", [r",1, 24,", #30]")
+        TEST_RP("strb   r",7, VAL2,", [r",6, 24,", #30]")
+        TEST_P( "ldrb   r0, [r",1, 24,", #30]")
+        TEST_P( "ldrb   r7, [r",6, 24,", #30]")
+        TEST_RP("strh   r",0, VAL1,", [r",1, 24,", #60]")
+        TEST_RP("strh   r",7, VAL2,", [r",6, 24,", #60]")
+        TEST_P( "ldrh   r0, [r",1, 24,", #60]")
+        TEST_P( "ldrh   r7, [r",6, 24,", #60]")
+
+        TEST_R( "str    r",0, VAL1,", [sp, #0]")
+        TEST_R( "str    r",7, VAL2,", [sp, #160]")
+        TEST(   "ldr    r0, [sp, #0]")
+        TEST(   "ldr    r7, [sp, #160]")
+
+        TEST_RP("str    r",0, VAL1,", [r",0, 24,"]")
+        TEST_P( "ldr    r0, [r",0, 24,"]")
+
+        TEST_GROUP("Generate PC-/SP-relative address")
+
+        TEST("add       r0, pc, #4")
+        TEST("add       r7, pc, #1020")
+        TEST("add       r0, sp, #4")
+        TEST("add       r7, sp, #1020")
+
+        TEST_GROUP("Miscellaneous 16-bit instructions")
+
+        TEST_UNSUPPORTED( "cpsie        i")
+        TEST_UNSUPPORTED( "cpsid        i")
+        TEST_UNSUPPORTED( "setend       le")
+        TEST_UNSUPPORTED( "setend       be")
+
+        TEST("add       sp, #"__stringify(TEST_MEMORY_SIZE)) /* Assumes TEST_MEMORY_SIZE < 0x400 */
+        TEST("sub       sp, #0x7f*4")
+
+DONT_TEST_IN_ITBLOCK(
+        TEST_BF_R(  "cbnz       r",0,0, ", 2f")
+        TEST_BF_R(  "cbz        r",2,-1,", 2f")
+        TEST_BF_RX( "cbnz       r",4,1, ", 2f",0x20)
+        TEST_BF_RX( "cbz        r",7,0, ", 2f",0x40)
+)
+        TEST_R("sxth    r0, r",7, HH1,"")
+        TEST_R("sxth    r7, r",0, HH2,"")
+        TEST_R("sxtb    r0, r",7, HH1,"")
+        TEST_R("sxtb    r7, r",0, HH2,"")
+        TEST_R("uxth    r0, r",7, HH1,"")
+        TEST_R("uxth    r7, r",0, HH2,"")
+        TEST_R("uxtb    r0, r",7, HH1,"")
+        TEST_R("uxtb    r7, r",0, HH2,"")
+        TEST_R("rev     r0, r",7, VAL1,"")
+        TEST_R("rev     r7, r",0, VAL2,"")
+        TEST_R("rev16   r0, r",7, VAL1,"")
+        TEST_R("rev16   r7, r",0, VAL2,"")
+        TEST_UNSUPPORTED(".short 0xba80")
+        TEST_UNSUPPORTED(".short 0xbabf")
+        TEST_R("revsh   r0, r",7, VAL1,"")
+        TEST_R("revsh   r7, r",0, VAL2,"")
+
+#define TEST_POPPC(code, offset)        \
+        TESTCASE_START(code)            \
+        TEST_ARG_PTR(13, offset)        \
+        TEST_ARG_END("")                \
+        TEST_BRANCH_F(code,0)           \
+        TESTCASE_END
+
+        TEST("push      {r0}")
+        TEST("push      {r7}")
+        TEST("push      {r14}")
+        TEST("push      {r0-r7,r14}")
+        TEST("push      {r0,r2,r4,r6,r14}")
+        TEST("push      {r1,r3,r5,r7}")
+        TEST("pop       {r0}")
+        TEST("pop       {r7}")
+        TEST("pop       {r0,r2,r4,r6}")
+        TEST_POPPC("pop {pc}",15*4)
+        TEST_POPPC("pop {r0-r7,pc}",7*4)
+        TEST_POPPC("pop {r1,r3,r5,r7,pc}",11*4)
+        TEST_THUMB_TO_ARM_INTERWORK_P("pop      {pc}    @ ",13,15*4,"")
+        TEST_THUMB_TO_ARM_INTERWORK_P("pop      {r0-r7,pc}      @ ",13,7*4,"")
+
+        TEST_UNSUPPORTED("bkpt.n        0")
+        TEST_UNSUPPORTED("bkpt.n        255")
+
+        TEST_SUPPORTED("yield")
+        TEST("sev")
+        TEST("nop")
+        TEST("wfi")
+        TEST_SUPPORTED("wfe")
+        TEST_UNSUPPORTED(".short 0xbf50") /* Unassigned hints */
+        TEST_UNSUPPORTED(".short 0xbff0") /* Unassigned hints */
+
+#define TEST_IT(code, code2)                    \
+        TESTCASE_START(code)                    \
+        TEST_ARG_END("")                        \
+        "50:    nop                     \n\t"   \
+        "1:     "code"                  \n\t"   \
+        "       "code2"                 \n\t"   \
+        "2:     nop                     \n\t"   \
+        TESTCASE_END
+
+DONT_TEST_IN_ITBLOCK(
+        TEST_IT("it     eq","moveq r0,#0")
+        TEST_IT("it     vc","movvc r0,#0")
+        TEST_IT("it     le","movle r0,#0")
+        TEST_IT("ite    eq","moveq r0,#0\n\t  movne r1,#1")
+        TEST_IT("itet   vc","movvc r0,#0\n\t  movvs r1,#1\n\t  movvc r2,#2")
+        TEST_IT("itete  le","movle r0,#0\n\t  movgt r1,#1\n\t  movle r2,#2\n\t  movgt r3,#3")
+        TEST_IT("itttt  le","movle r0,#0\n\t  movle r1,#1\n\t  movle r2,#2\n\t  movle r3,#3")
+        TEST_IT("iteee  le","movle r0,#0\n\t  movgt r1,#1\n\t  movgt r2,#2\n\t  movgt r3,#3")
+)
+
+        TEST_GROUP("Load and store multiple")
+
+        TEST_P("ldmia   r",4, 16*4,"!, {r0,r7}")
+        TEST_P("ldmia   r",7, 16*4,"!, {r0-r6}")
+        TEST_P("stmia   r",4, 16*4,"!, {r0,r7}")
+        TEST_P("stmia   r",0, 16*4,"!, {r0-r7}")
+
+        TEST_GROUP("Conditional branch and Supervisor Call instructions")
+
+CONDITION_INSTRUCTIONS(8,
+        TEST_BF("beq    2f")
+        TEST_BB("bne    2b")
+        TEST_BF("bgt    2f")
+        TEST_BB("blt    2b")
+)
+        TEST_UNSUPPORTED(".short 0xde00")
+        TEST_UNSUPPORTED(".short 0xdeff")
+        TEST_UNSUPPORTED("svc   #0x00")
+        TEST_UNSUPPORTED("svc   #0xff")
+
+        TEST_GROUP("Unconditional branch")
+
+        TEST_BF(  "b    2f")
+        TEST_BB(  "b    2b")
+        TEST_BF_X("b    2f", 0x400)
+        TEST_BB_X("b    2b", 0x400)
+
+        TEST_GROUP("Testing instructions in IT blocks")
+
+        TEST_ITBLOCK("subs.n r0, r0")
+
+        verbose("\n");
+}
+
+
+void kprobe_thumb32_test_cases(void)
+{
+        kprobe_test_flags = 0;
+
+        TEST_GROUP("Load/store multiple")
+
+        TEST_UNSUPPORTED("rfedb sp")
+        TEST_UNSUPPORTED("rfeia sp")
+        TEST_UNSUPPORTED("rfedb sp!")
+        TEST_UNSUPPORTED("rfeia sp!")
+
+        TEST_P(   "stmia        r",0, 16*4,", {r0,r8}")
+        TEST_P(   "stmia        r",4, 16*4,", {r0-r12,r14}")
+        TEST_P(   "stmia        r",7, 16*4,"!, {r8-r12,r14}")
+        TEST_P(   "stmia        r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
+
+        TEST_P(   "ldmia        r",0, 16*4,", {r0,r8}")
+        TEST_P(   "ldmia        r",4, 0,   ", {r0-r12,r14}")
+        TEST_BF_P("ldmia        r",5, 8*4, "!, {r6-r12,r15}")
+        TEST_P(   "ldmia        r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
+        TEST_BF_P("ldmia        r",14,14*4,"!, {r4,pc}")
+
+        TEST_P(   "stmdb        r",0, 16*4,", {r0,r8}")
+        TEST_P(   "stmdb        r",4, 16*4,", {r0-r12,r14}")
+        TEST_P(   "stmdb        r",5, 16*4,"!, {r8-r12,r14}")
+        TEST_P(   "stmdb        r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
+
+        TEST_P(   "ldmdb        r",0, 16*4,", {r0,r8}")
+        TEST_P(   "ldmdb        r",4, 16*4,", {r0-r12,r14}")
+        TEST_BF_P("ldmdb        r",5, 16*4,"!, {r6-r12,r15}")
+        TEST_P(   "ldmdb        r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
+        TEST_BF_P("ldmdb        r",14,16*4,"!, {r4,pc}")
+
+        TEST_P(   "stmdb        r",13,16*4,"!, {r3-r12,lr}")
+        TEST_P(   "stmdb        r",13,16*4,"!, {r3-r12}")
+        TEST_P(   "stmdb        r",2, 16*4,", {r3-r12,lr}")
+        TEST_P(   "stmdb        r",13,16*4,"!, {r2-r12,lr}")
+        TEST_P(   "stmdb        r",0, 16*4,", {r0-r12}")
+        TEST_P(   "stmdb        r",0, 16*4,", {r0-r12,lr}")
+
+        TEST_BF_P("ldmia        r",13,5*4, "!, {r3-r12,pc}")
+        TEST_P(   "ldmia        r",13,5*4, "!, {r3-r12}")
+        TEST_BF_P("ldmia        r",2, 5*4, "!, {r3-r12,pc}")
+        TEST_BF_P("ldmia        r",13,4*4, "!, {r2-r12,pc}")
+        TEST_P(   "ldmia        r",0, 16*4,", {r0-r12}")
+        TEST_P(   "ldmia        r",0, 16*4,", {r0-r12,lr}")
+
+        TEST_THUMB_TO_ARM_INTERWORK_P("ldmia    r",0,14*4,", {r12,pc}")
+        TEST_THUMB_TO_ARM_INTERWORK_P("ldmia    r",13,2*4,", {r0-r12,pc}")
+
+        TEST_UNSUPPORTED(".short 0xe88f,0x0101  @ stmia pc, {r0,r8}")
+        TEST_UNSUPPORTED(".short 0xe92f,0x5f00  @ stmdb pc!, {r8-r12,r14}")
+        TEST_UNSUPPORTED(".short 0xe8bd,0xc000  @ ldmia r13!, {r14,pc}")
+        TEST_UNSUPPORTED(".short 0xe93e,0xc000  @ ldmdb r14!, {r14,pc}")
+        TEST_UNSUPPORTED(".short 0xe8a7,0x3f00  @ stmia r7!, {r8-r12,sp}")
+        TEST_UNSUPPORTED(".short 0xe8a7,0x9f00  @ stmia r7!, {r8-r12,pc}")
+        TEST_UNSUPPORTED(".short 0xe93e,0x2010  @ ldmdb r14!, {r4,sp}")
+
+        TEST_GROUP("Load/store double or exclusive, table branch")
+
+        TEST_P(  "ldrd  r0, r1, [r",1, 24,", #-16]")
+        TEST(    "ldrd  r12, r14, [sp, #16]")
+        TEST_P(  "ldrd  r1, r0, [r",7, 24,", #-16]!")
+        TEST(    "ldrd  r14, r12, [sp, #16]!")
+        TEST_P(  "ldrd  r1, r0, [r",7, 24,"], #16")
+        TEST(    "ldrd  r7, r8, [sp], #-16")
+
+        TEST_X( "ldrd   r12, r14, 3f",
+                ".align 3                               \n\t"
+                "3:     .word   "__stringify(VAL1)"     \n\t"
+                "       .word   "__stringify(VAL2))
+
+        TEST_UNSUPPORTED(".short 0xe9ff,0xec04  @ ldrd  r14, r12, [pc, #16]!")
+        TEST_UNSUPPORTED(".short 0xe8ff,0xec04  @ ldrd  r14, r12, [pc], #16")
+        TEST_UNSUPPORTED(".short 0xe9d4,0xd800  @ ldrd  sp, r8, [r4]")
+        TEST_UNSUPPORTED(".short 0xe9d4,0xf800  @ ldrd  pc, r8, [r4]")
+        TEST_UNSUPPORTED(".short 0xe9d4,0x7d00  @ ldrd  r7, sp, [r4]")
+        TEST_UNSUPPORTED(".short 0xe9d4,0x7f00  @ ldrd  r7, pc, [r4]")
+
+        TEST_RRP("strd  r",0, VAL1,", r",1, VAL2,", [r",1, 24,", #-16]")
+        TEST_RR( "strd  r",12,VAL2,", r",14,VAL1,", [sp, #16]")
+        TEST_RRP("strd  r",1, VAL1,", r",0, VAL2,", [r",7, 24,", #-16]!")
+        TEST_RR( "strd  r",14,VAL2,", r",12,VAL1,", [sp, #16]!")
+        TEST_RRP("strd  r",1, VAL1,", r",0, VAL2,", [r",7, 24,"], #16")
+        TEST_RR( "strd  r",7, VAL2,", r",8, VAL1,", [sp], #-16")
+        TEST_UNSUPPORTED(".short 0xe9ef,0xec04  @ strd  r14, r12, [pc, #16]!")
+        TEST_UNSUPPORTED(".short 0xe8ef,0xec04  @ strd  r14, r12, [pc], #16")
+
+        TEST_RX("tbb    [pc, r",0, (9f-(1f+4)),"]",
+                "9:                     \n\t"
+                ".byte  (2f-1b-4)>>1    \n\t"
+                ".byte  (3f-1b-4)>>1    \n\t"
+                "3:     mvn     r0, r0  \n\t"
+                "2:     nop             \n\t")
+
+        TEST_RX("tbb    [pc, r",4, (9f-(1f+4)+1),"]",
+                "9:                     \n\t"
+                ".byte  (2f-1b-4)>>1    \n\t"
+                ".byte  (3f-1b-4)>>1    \n\t"
+                "3:     mvn     r0, r0  \n\t"
+                "2:     nop             \n\t")
+
+        TEST_RRX("tbb   [r",1,9f,", r",2,0,"]",
+                "9:                     \n\t"
+                ".byte  (2f-1b-4)>>1    \n\t"
+                ".byte  (3f-1b-4)>>1    \n\t"
+                "3:     mvn     r0, r0  \n\t"
+                "2:     nop             \n\t")
+
+        TEST_RX("tbh    [pc, r",7, (9f-(1f+4))>>1,"]",
+                "9:                     \n\t"
+                ".short (2f-1b-4)>>1    \n\t"
+                ".short (3f-1b-4)>>1    \n\t"
+                "3:     mvn     r0, r0  \n\t"
+                "2:     nop             \n\t")
+
+        TEST_RX("tbh    [pc, r",12, ((9f-(1f+4))>>1)+1,"]",
+                "9:                     \n\t"
+                ".short (2f-1b-4)>>1    \n\t"
+                ".short (3f-1b-4)>>1    \n\t"
+                "3:     mvn     r0, r0  \n\t"
+                "2:     nop             \n\t")
+
+        TEST_RRX("tbh   [r",1,9f, ", r",14,1,"]",
+                "9:                     \n\t"
+                ".short (2f-1b-4)>>1    \n\t"
+                ".short (3f-1b-4)>>1    \n\t"
+                "3:     mvn     r0, r0  \n\t"
+                "2:     nop             \n\t")
+
+        TEST_UNSUPPORTED(".short 0xe8d1,0xf01f  @ tbh [r1, pc]")
+        TEST_UNSUPPORTED(".short 0xe8d1,0xf01d  @ tbh [r1, sp]")
+        TEST_UNSUPPORTED(".short 0xe8dd,0xf012  @ tbh [sp, r2]")
+
+        TEST_UNSUPPORTED("strexb        r0, r1, [r2]")
+        TEST_UNSUPPORTED("strexh        r0, r1, [r2]")
+        TEST_UNSUPPORTED("strexd        r0, r1, [r2]")
+        TEST_UNSUPPORTED("ldrexb        r0, [r1]")
+        TEST_UNSUPPORTED("ldrexh        r0, [r1]")
+        TEST_UNSUPPORTED("ldrexd        r0, [r1]")
+
+        TEST_GROUP("Data-processing (shifted register) and (modified immediate)")
+
+#define _DATA_PROCESSING32_DNM(op,s,val)                                        \
+        TEST_RR(op s".w r0,  r",1, VAL1,", r",2, val, "")                       \
+        TEST_RR(op s"   r1,  r",1, VAL1,", r",2, val, ", lsl #3")               \
+        TEST_RR(op s"   r2,  r",3, VAL1,", r",2, val, ", lsr #4")               \
+        TEST_RR(op s"   r3,  r",3, VAL1,", r",2, val, ", asr #5")               \
+        TEST_RR(op s"   r4,  r",5, VAL1,", r",2, N(val),", asr #6")             \
+        TEST_RR(op s"   r5,  r",5, VAL1,", r",2, val, ", ror #7")               \
+        TEST_RR(op s"   r8,  r",9, VAL1,", r",10,val, ", rrx")                  \
+        TEST_R( op s"   r0,  r",11,VAL1,", #0x00010001")                        \
+        TEST_R( op s"   r11, r",0, VAL1,", #0xf5000000")                        \
+        TEST_R( op s"   r7,  r",8, VAL2,", #0x000af000")
+
+#define DATA_PROCESSING32_DNM(op,val)           \
+        _DATA_PROCESSING32_DNM(op,"",val)       \
+        _DATA_PROCESSING32_DNM(op,"s",val)
+
+#define DATA_PROCESSING32_NM(op,val)                                    \
+        TEST_RR(op".w   r",1, VAL1,", r",2, val, "")                    \
+        TEST_RR(op"     r",1, VAL1,", r",2, val, ", lsl #3")            \
+        TEST_RR(op"     r",3, VAL1,", r",2, val, ", lsr #4")            \
+        TEST_RR(op"     r",3, VAL1,", r",2, val, ", asr #5")            \
+        TEST_RR(op"     r",5, VAL1,", r",2, N(val),", asr #6")          \
+        TEST_RR(op"     r",5, VAL1,", r",2, val, ", ror #7")            \
+        TEST_RR(op"     r",9, VAL1,", r",10,val, ", rrx")               \
+        TEST_R( op"     r",11,VAL1,", #0x00010001")                     \
+        TEST_R( op"     r",0, VAL1,", #0xf5000000")                     \
+        TEST_R( op"     r",8, VAL2,", #0x000af000")
+
+#define _DATA_PROCESSING32_DM(op,s,val)                         \
+        TEST_R( op s".w r0,  r",14, val, "")                    \
+        TEST_R( op s"   r1,  r",12, val, ", lsl #3")            \
+        TEST_R( op s"   r2,  r",11, val, ", lsr #4")            \
+        TEST_R( op s"   r3,  r",10, val, ", asr #5")            \
+        TEST_R( op s"   r4,  r",9, N(val),", asr #6")           \
+        TEST_R( op s"   r5,  r",8, val, ", ror #7")             \
+        TEST_R( op s"   r8,  r",7,val, ", rrx")                 \
+        TEST(   op s"   r0,  #0x00010001")                      \
+        TEST(   op s"   r11, #0xf5000000")                      \
+        TEST(   op s"   r7,  #0x000af000")                      \
+        TEST(   op s"   r4,  #0x00005a00")
+
+#define DATA_PROCESSING32_DM(op,val)            \
+        _DATA_PROCESSING32_DM(op,"",val)        \
+        _DATA_PROCESSING32_DM(op,"s",val)
+
+        DATA_PROCESSING32_DNM("and",0xf00f00ff)
+        DATA_PROCESSING32_NM("tst",0xf00f00ff)
+        DATA_PROCESSING32_DNM("bic",0xf00f00ff)
+        DATA_PROCESSING32_DNM("orr",0xf00f00ff)
+        DATA_PROCESSING32_DM("mov",VAL2)
+        DATA_PROCESSING32_DNM("orn",0xf00f00ff)
+        DATA_PROCESSING32_DM("mvn",VAL2)
+        DATA_PROCESSING32_DNM("eor",0xf00f00ff)
+        DATA_PROCESSING32_NM("teq",0xf00f00ff)
+        DATA_PROCESSING32_DNM("add",VAL2)
+        DATA_PROCESSING32_NM("cmn",VAL2)
+        DATA_PROCESSING32_DNM("adc",VAL2)
+        DATA_PROCESSING32_DNM("sbc",VAL2)
+        DATA_PROCESSING32_DNM("sub",VAL2)
+        DATA_PROCESSING32_NM("cmp",VAL2)
+        DATA_PROCESSING32_DNM("rsb",VAL2)
+
+        TEST_RR("pkhbt  r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR("pkhbt  r14,r",12, HH1,", r",10,HH2,", lsl #2")
+        TEST_RR("pkhtb  r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR("pkhtb  r14,r",12, HH1,", r",10,HH2,", asr #2")
+
+        TEST_UNSUPPORTED(".short 0xea17,0x0f0d  @ tst.w r7, sp")
+        TEST_UNSUPPORTED(".short 0xea17,0x0f0f  @ tst.w r7, pc")
+        TEST_UNSUPPORTED(".short 0xea1d,0x0f07  @ tst.w sp, r7")
+        TEST_UNSUPPORTED(".short 0xea1f,0x0f07  @ tst.w pc, r7")
+        TEST_UNSUPPORTED(".short 0xf01d,0x1f08  @ tst sp, #0x00080008")
+        TEST_UNSUPPORTED(".short 0xf01f,0x1f08  @ tst pc, #0x00080008")
+
+        TEST_UNSUPPORTED(".short 0xea97,0x0f0d  @ teq.w r7, sp")
+        TEST_UNSUPPORTED(".short 0xea97,0x0f0f  @ teq.w r7, pc")
+        TEST_UNSUPPORTED(".short 0xea9d,0x0f07  @ teq.w sp, r7")
+        TEST_UNSUPPORTED(".short 0xea9f,0x0f07  @ teq.w pc, r7")
+        TEST_UNSUPPORTED(".short 0xf09d,0x1f08  @ tst sp, #0x00080008")
+        TEST_UNSUPPORTED(".short 0xf09f,0x1f08  @ tst pc, #0x00080008")
+
+        TEST_UNSUPPORTED(".short 0xeb17,0x0f0d  @ cmn.w r7, sp")
+        TEST_UNSUPPORTED(".short 0xeb17,0x0f0f  @ cmn.w r7, pc")
+        TEST_P("cmn.w   sp, r",7,0,"")
+        TEST_UNSUPPORTED(".short 0xeb1f,0x0f07  @ cmn.w pc, r7")
+        TEST(  "cmn     sp, #0x00080008")
+        TEST_UNSUPPORTED(".short 0xf11f,0x1f08  @ cmn pc, #0x00080008")
+
+        TEST_UNSUPPORTED(".short 0xebb7,0x0f0d  @ cmp.w r7, sp")
+        TEST_UNSUPPORTED(".short 0xebb7,0x0f0f  @ cmp.w r7, pc")
+        TEST_P("cmp.w   sp, r",7,0,"")
+        TEST_UNSUPPORTED(".short 0xebbf,0x0f07  @ cmp.w pc, r7")
+        TEST(  "cmp     sp, #0x00080008")
+        TEST_UNSUPPORTED(".short 0xf1bf,0x1f08  @ cmp pc, #0x00080008")
+
+        TEST_UNSUPPORTED(".short 0xea5f,0x070d  @ movs.w r7, sp")
+        TEST_UNSUPPORTED(".short 0xea5f,0x070f  @ movs.w r7, pc")
+        TEST_UNSUPPORTED(".short 0xea5f,0x0d07  @ movs.w sp, r7")
+        TEST_UNSUPPORTED(".short 0xea4f,0x0f07  @ mov.w  pc, r7")
+        TEST_UNSUPPORTED(".short 0xf04f,0x1d08  @ mov sp, #0x00080008")
+        TEST_UNSUPPORTED(".short 0xf04f,0x1f08  @ mov pc, #0x00080008")
+
+        TEST_R("add.w   r0, sp, r",1, 4,"")
+        TEST_R("adds    r0, sp, r",1, 4,", asl #3")
+        TEST_R("add     r0, sp, r",1, 4,", asl #4")
+        TEST_R("add     r0, sp, r",1, 16,", ror #1")
+        TEST_R("add.w   sp, sp, r",1, 4,"")
+        TEST_R("add     sp, sp, r",1, 4,", asl #3")
+        TEST_UNSUPPORTED(".short 0xeb0d,0x1d01  @ add sp, sp, r1, asl #4")
+        TEST_UNSUPPORTED(".short 0xeb0d,0x0d71  @ add sp, sp, r1, ror #1")
+        TEST(  "add.w   r0, sp, #24")
+        TEST(  "add.w   sp, sp, #24")
+        TEST_UNSUPPORTED(".short 0xeb0d,0x0f01  @ add pc, sp, r1")
+        TEST_UNSUPPORTED(".short 0xeb0d,0x000f  @ add r0, sp, pc")
+        TEST_UNSUPPORTED(".short 0xeb0d,0x000d  @ add r0, sp, sp")
+        TEST_UNSUPPORTED(".short 0xeb0d,0x0d0f  @ add sp, sp, pc")
+        TEST_UNSUPPORTED(".short 0xeb0d,0x0d0d  @ add sp, sp, sp")
+
+        TEST_R("sub.w   r0, sp, r",1, 4,"")
+        TEST_R("subs    r0, sp, r",1, 4,", asl #3")
+        TEST_R("sub     r0, sp, r",1, 4,", asl #4")
+        TEST_R("sub     r0, sp, r",1, 16,", ror #1")
+        TEST_R("sub.w   sp, sp, r",1, 4,"")
+        TEST_R("sub     sp, sp, r",1, 4,", asl #3")
+        TEST_UNSUPPORTED(".short 0xebad,0x1d01  @ sub sp, sp, r1, asl #4")
+        TEST_UNSUPPORTED(".short 0xebad,0x0d71  @ sub sp, sp, r1, ror #1")
+        TEST_UNSUPPORTED(".short 0xebad,0x0f01  @ sub pc, sp, r1")
+        TEST(  "sub.w   r0, sp, #24")
+        TEST(  "sub.w   sp, sp, #24")
+
+        TEST_UNSUPPORTED(".short 0xea02,0x010f  @ and r1, r2, pc")
+        TEST_UNSUPPORTED(".short 0xea0f,0x0103  @ and r1, pc, r3")
+        TEST_UNSUPPORTED(".short 0xea02,0x0f03  @ and pc, r2, r3")
+        TEST_UNSUPPORTED(".short 0xea02,0x010d  @ and r1, r2, sp")
+        TEST_UNSUPPORTED(".short 0xea0d,0x0103  @ and r1, sp, r3")
+        TEST_UNSUPPORTED(".short 0xea02,0x0d03  @ and sp, r2, r3")
+        TEST_UNSUPPORTED(".short 0xf00d,0x1108  @ and r1, sp, #0x00080008")
+        TEST_UNSUPPORTED(".short 0xf00f,0x1108  @ and r1, pc, #0x00080008")
+        TEST_UNSUPPORTED(".short 0xf002,0x1d08  @ and sp, r8, #0x00080008")
+        TEST_UNSUPPORTED(".short 0xf002,0x1f08  @ and pc, r8, #0x00080008")
+
+        TEST_UNSUPPORTED(".short 0xeb02,0x010f  @ add r1, r2, pc")
+        TEST_UNSUPPORTED(".short 0xeb0f,0x0103  @ add r1, pc, r3")
+        TEST_UNSUPPORTED(".short 0xeb02,0x0f03  @ add pc, r2, r3")
+        TEST_UNSUPPORTED(".short 0xeb02,0x010d  @ add r1, r2, sp")
+        TEST_SUPPORTED(  ".short 0xeb0d,0x0103  @ add r1, sp, r3")
+        TEST_UNSUPPORTED(".short 0xeb02,0x0d03  @ add sp, r2, r3")
+        TEST_SUPPORTED(  ".short 0xf10d,0x1108  @ add r1, sp, #0x00080008")
+        TEST_UNSUPPORTED(".short 0xf10d,0x1f08  @ add pc, sp, #0x00080008")
+        TEST_UNSUPPORTED(".short 0xf10f,0x1108  @ add r1, pc, #0x00080008")
+        TEST_UNSUPPORTED(".short 0xf102,0x1d08  @ add sp, r8, #0x00080008")
+        TEST_UNSUPPORTED(".short 0xf102,0x1f08  @ add pc, r8, #0x00080008")
+
+        TEST_UNSUPPORTED(".short 0xeaa0,0x0000")
+        TEST_UNSUPPORTED(".short 0xeaf0,0x0000")
+        TEST_UNSUPPORTED(".short 0xeb20,0x0000")
+        TEST_UNSUPPORTED(".short 0xeb80,0x0000")
+        TEST_UNSUPPORTED(".short 0xebe0,0x0000")
+
+        TEST_UNSUPPORTED(".short 0xf0a0,0x0000")
+        TEST_UNSUPPORTED(".short 0xf0c0,0x0000")
+        TEST_UNSUPPORTED(".short 0xf0f0,0x0000")
+        TEST_UNSUPPORTED(".short 0xf120,0x0000")
+        TEST_UNSUPPORTED(".short 0xf180,0x0000")
+        TEST_UNSUPPORTED(".short 0xf1e0,0x0000")
+
+        TEST_GROUP("Coprocessor instructions")
+
+        TEST_UNSUPPORTED(".short 0xec00,0x0000")
+        TEST_UNSUPPORTED(".short 0xeff0,0x0000")
+        TEST_UNSUPPORTED(".short 0xfc00,0x0000")
+        TEST_UNSUPPORTED(".short 0xfff0,0x0000")
+
+        TEST_GROUP("Data-processing (plain binary immediate)")
+
+        TEST_R("addw    r0,  r",1, VAL1,", #0x123")
+        TEST(  "addw    r14, sp, #0xf5a")
+        TEST(  "addw    sp, sp, #0x20")
+        TEST(  "addw    r7,  pc, #0x888")
+        TEST_UNSUPPORTED(".short 0xf20f,0x1f20  @ addw pc, pc, #0x120")
+        TEST_UNSUPPORTED(".short 0xf20d,0x1f20  @ addw pc, sp, #0x120")
+        TEST_UNSUPPORTED(".short 0xf20f,0x1d20  @ addw sp, pc, #0x120")
+        TEST_UNSUPPORTED(".short 0xf200,0x1d20  @ addw sp, r0, #0x120")
+
+        TEST_R("subw    r0,  r",1, VAL1,", #0x123")
+        TEST(  "subw    r14, sp, #0xf5a")
+        TEST(  "subw    sp, sp, #0x20")
+        TEST(  "subw    r7,  pc, #0x888")
+        TEST_UNSUPPORTED(".short 0xf2af,0x1f20  @ subw pc, pc, #0x120")
+        TEST_UNSUPPORTED(".short 0xf2ad,0x1f20  @ subw pc, sp, #0x120")
+        TEST_UNSUPPORTED(".short 0xf2af,0x1d20  @ subw sp, pc, #0x120")
+        TEST_UNSUPPORTED(".short 0xf2a0,0x1d20  @ subw sp, r0, #0x120")
+
+        TEST("movw      r0, #0")
+        TEST("movw      r0, #0xffff")
+        TEST("movw      lr, #0xffff")
+        TEST_UNSUPPORTED(".short 0xf240,0x0d00  @ movw sp, #0")
+        TEST_UNSUPPORTED(".short 0xf240,0x0f00  @ movw pc, #0")
+
+        TEST_R("movt    r",0, VAL1,", #0")
+        TEST_R("movt    r",0, VAL2,", #0xffff")
+        TEST_R("movt    r",14,VAL1,", #0xffff")
+        TEST_UNSUPPORTED(".short 0xf2c0,0x0d00  @ movt sp, #0")
+        TEST_UNSUPPORTED(".short 0xf2c0,0x0f00  @ movt pc, #0")
+
+        TEST_R(     "ssat       r0, #24, r",0,   VAL1,"")
+        TEST_R(     "ssat       r14, #24, r",12, VAL2,"")
+        TEST_R(     "ssat       r0, #24, r",0,   VAL1,", lsl #8")
+        TEST_R(     "ssat       r14, #24, r",12, VAL2,", asr #8")
+        TEST_UNSUPPORTED(".short 0xf30c,0x0d17  @ ssat  sp, #24, r12")
+        TEST_UNSUPPORTED(".short 0xf30c,0x0f17  @ ssat  pc, #24, r12")
+        TEST_UNSUPPORTED(".short 0xf30d,0x0c17  @ ssat  r12, #24, sp")
+        TEST_UNSUPPORTED(".short 0xf30f,0x0c17  @ ssat  r12, #24, pc")
+
+        TEST_R(     "usat       r0, #24, r",0,   VAL1,"")
+        TEST_R(     "usat       r14, #24, r",12, VAL2,"")
+        TEST_R(     "usat       r0, #24, r",0,   VAL1,", lsl #8")
+        TEST_R(     "usat       r14, #24, r",12, VAL2,", asr #8")
+        TEST_UNSUPPORTED(".short 0xf38c,0x0d17  @ usat  sp, #24, r12")
+        TEST_UNSUPPORTED(".short 0xf38c,0x0f17  @ usat  pc, #24, r12")
+        TEST_UNSUPPORTED(".short 0xf38d,0x0c17  @ usat  r12, #24, sp")
+        TEST_UNSUPPORTED(".short 0xf38f,0x0c17  @ usat  r12, #24, pc")
+
+        TEST_R(     "ssat16     r0, #12, r",0,   HH1,"")
+        TEST_R(     "ssat16     r14, #12, r",12, HH2,"")
+        TEST_UNSUPPORTED(".short 0xf32c,0x0d0b  @ ssat16        sp, #12, r12")
+        TEST_UNSUPPORTED(".short 0xf32c,0x0f0b  @ ssat16        pc, #12, r12")
+        TEST_UNSUPPORTED(".short 0xf32d,0x0c0b  @ ssat16        r12, #12, sp")
+        TEST_UNSUPPORTED(".short 0xf32f,0x0c0b  @ ssat16        r12, #12, pc")
+
+        TEST_R(     "usat16     r0, #12, r",0,   HH1,"")
+        TEST_R(     "usat16     r14, #12, r",12, HH2,"")
+        TEST_UNSUPPORTED(".short 0xf3ac,0x0d0b  @ usat16        sp, #12, r12")
+        TEST_UNSUPPORTED(".short 0xf3ac,0x0f0b  @ usat16        pc, #12, r12")
+        TEST_UNSUPPORTED(".short 0xf3ad,0x0c0b  @ usat16        r12, #12, sp")
+        TEST_UNSUPPORTED(".short 0xf3af,0x0c0b  @ usat16        r12, #12, pc")
+
+        TEST_R(     "sbfx       r0, r",0  , VAL1,", #0, #31")
+        TEST_R(     "sbfx       r14, r",12, VAL2,", #8, #16")
+        TEST_R(     "sbfx       r4, r",10,  VAL1,", #16, #15")
+        TEST_UNSUPPORTED(".short 0xf34c,0x2d0f  @ sbfx  sp, r12, #8, #16")
+        TEST_UNSUPPORTED(".short 0xf34c,0x2f0f  @ sbfx  pc, r12, #8, #16")
+        TEST_UNSUPPORTED(".short 0xf34d,0x2c0f  @ sbfx  r12, sp, #8, #16")
+        TEST_UNSUPPORTED(".short 0xf34f,0x2c0f  @ sbfx  r12, pc, #8, #16")
+
+        TEST_R(     "ubfx       r0, r",0  , VAL1,", #0, #31")
+        TEST_R(     "ubfx       r14, r",12, VAL2,", #8, #16")
+        TEST_R(     "ubfx       r4, r",10,  VAL1,", #16, #15")
+        TEST_UNSUPPORTED(".short 0xf3cc,0x2d0f  @ ubfx  sp, r12, #8, #16")
+        TEST_UNSUPPORTED(".short 0xf3cc,0x2f0f  @ ubfx  pc, r12, #8, #16")
+        TEST_UNSUPPORTED(".short 0xf3cd,0x2c0f  @ ubfx  r12, sp, #8, #16")
+        TEST_UNSUPPORTED(".short 0xf3cf,0x2c0f  @ ubfx  r12, pc, #8, #16")
+
+        TEST_R(     "bfc        r",0, VAL1,", #4, #20")
+        TEST_R(     "bfc        r",14,VAL2,", #4, #20")
+        TEST_R(     "bfc        r",7, VAL1,", #0, #31")
+        TEST_R(     "bfc        r",8, VAL2,", #0, #31")
+        TEST_UNSUPPORTED(".short 0xf36f,0x0d1e  @ bfc   sp, #0, #31")
+        TEST_UNSUPPORTED(".short 0xf36f,0x0f1e  @ bfc   pc, #0, #31")
+
+        TEST_RR(    "bfi        r",0, VAL1,", r",0  , VAL2,", #0, #31")
+        TEST_RR(    "bfi        r",12,VAL1,", r",14 , VAL2,", #4, #20")
+        TEST_UNSUPPORTED(".short 0xf36e,0x1d17  @ bfi   sp, r14, #4, #20")
+        TEST_UNSUPPORTED(".short 0xf36e,0x1f17  @ bfi   pc, r14, #4, #20")
+        TEST_UNSUPPORTED(".short 0xf36d,0x1e17  @ bfi   r14, sp, #4, #20")
+
+        TEST_GROUP("Branches and miscellaneous control")
+
+CONDITION_INSTRUCTIONS(22,
+        TEST_BF("beq.w  2f")
+        TEST_BB("bne.w  2b")
+        TEST_BF("bgt.w  2f")
+        TEST_BB("blt.w  2b")
+        TEST_BF_X("bpl.w        2f",0x1000)
+)
+
+        TEST_UNSUPPORTED("msr   cpsr, r0")
+        TEST_UNSUPPORTED("msr   cpsr_f, r1")
+        TEST_UNSUPPORTED("msr   spsr, r2")
+
+        TEST_UNSUPPORTED("cpsie.w       i")
+        TEST_UNSUPPORTED("cpsid.w       i")
+        TEST_UNSUPPORTED("cps   0x13")
+
+        TEST_SUPPORTED("yield.w")
+        TEST("sev.w")
+        TEST("nop.w")
+        TEST("wfi.w")
+        TEST_SUPPORTED("wfe.w")
+        TEST_UNSUPPORTED("dbg.w #0")
+
+        TEST_UNSUPPORTED("clrex")
+        TEST_UNSUPPORTED("dsb")
+        TEST_UNSUPPORTED("dmb")
+        TEST_UNSUPPORTED("isb")
+
+        TEST_UNSUPPORTED("bxj   r0")
+
+        TEST_UNSUPPORTED("subs  pc, lr, #4")
+
+        TEST("mrs       r0, cpsr")
+        TEST("mrs       r14, cpsr")
+        TEST_UNSUPPORTED(".short 0xf3ef,0x8d00  @ mrs   sp, spsr")
+        TEST_UNSUPPORTED(".short 0xf3ef,0x8f00  @ mrs   pc, spsr")
+        TEST_UNSUPPORTED("mrs   r0, spsr")
+        TEST_UNSUPPORTED("mrs   lr, spsr")
+
+        TEST_UNSUPPORTED(".short 0xf7f0,0x8000 @ smc #0")
+
+        TEST_UNSUPPORTED(".short 0xf7f0,0xa000 @ undefeined")
+
+        TEST_BF(  "b.w  2f")
+        TEST_BB(  "b.w  2b")
+        TEST_BF_X("b.w  2f", 0x1000)
+
+        TEST_BF(  "bl.w 2f")
+        TEST_BB(  "bl.w 2b")
+        TEST_BB_X("bl.w 2b", 0x1000)
+
+        TEST_X( "blx    __dummy_arm_subroutine",
+                ".arm                           \n\t"
+                ".align                         \n\t"
+                ".type __dummy_arm_subroutine, %%function \n\t"
+                "__dummy_arm_subroutine:        \n\t"
+                "mov    r0, pc                  \n\t"
+                "bx     lr                      \n\t"
+                ".thumb                         \n\t"
+        )
+        TEST(   "blx    __dummy_arm_subroutine")
+
+        TEST_GROUP("Store single data item")
+
+#define SINGLE_STORE(size)                                                      \
+        TEST_RP( "str"size"     r",0, VAL1,", [r",11,-1024,", #1024]")          \
+        TEST_RP( "str"size"     r",14,VAL2,", [r",1, -1024,", #1080]")          \
+        TEST_RP( "str"size"     r",0, VAL1,", [r",11,256,  ", #-120]")          \
+        TEST_RP( "str"size"     r",14,VAL2,", [r",1, 256,  ", #-128]")          \
+        TEST_RP( "str"size"     r",0, VAL1,", [r",11,24,  "], #120")            \
+        TEST_RP( "str"size"     r",14,VAL2,", [r",1, 24,  "], #128")            \
+        TEST_RP( "str"size"     r",0, VAL1,", [r",11,24,  "], #-120")           \
+        TEST_RP( "str"size"     r",14,VAL2,", [r",1, 24,  "], #-128")           \
+        TEST_RP( "str"size"     r",0, VAL1,", [r",11,24,   ", #120]!")          \
+        TEST_RP( "str"size"     r",14,VAL2,", [r",1, 24,   ", #128]!")          \
+        TEST_RP( "str"size"     r",0, VAL1,", [r",11,256,  ", #-120]!")         \
+        TEST_RP( "str"size"     r",14,VAL2,", [r",1, 256,  ", #-128]!")         \
+        TEST_RPR("str"size".w   r",0, VAL1,", [r",1, 0,", r",2, 4,"]")          \
+        TEST_RPR("str"size"     r",14,VAL2,", [r",10,0,", r",11,4,", lsl #1]")  \
+        TEST_R(  "str"size".w   r",7, VAL1,", [sp, #24]")                       \
+        TEST_RP( "str"size".w   r",0, VAL2,", [r",0,0, "]")                     \
+        TEST_UNSUPPORTED("str"size"t    r0, [r1, #4]")
+
+        SINGLE_STORE("b")
+        SINGLE_STORE("h")
+        SINGLE_STORE("")
+
+        TEST("str       sp, [sp]")
+        TEST_UNSUPPORTED(".short 0xf8cf,0xe000  @ str   r14, [pc]")
+        TEST_UNSUPPORTED(".short 0xf8ce,0xf000  @ str   pc, [r14]")
+
+        TEST_GROUP("Advanced SIMD element or structure load/store instructions")
+
+        TEST_UNSUPPORTED(".short 0xf900,0x0000")
+        TEST_UNSUPPORTED(".short 0xf92f,0xffff")
+        TEST_UNSUPPORTED(".short 0xf980,0x0000")
+        TEST_UNSUPPORTED(".short 0xf9ef,0xffff")
+
+        TEST_GROUP("Load single data item and memory hints")
+
+#define SINGLE_LOAD(size)                                               \
+        TEST_P( "ldr"size"      r0, [r",11,-1024, ", #1024]")           \
+        TEST_P( "ldr"size"      r14, [r",1, -1024,", #1080]")           \
+        TEST_P( "ldr"size"      r0, [r",11,256,   ", #-120]")           \
+        TEST_P( "ldr"size"      r14, [r",1, 256,  ", #-128]")           \
+        TEST_P( "ldr"size"      r0, [r",11,24,   "], #120")             \
+        TEST_P( "ldr"size"      r14, [r",1, 24,  "], #128")             \
+        TEST_P( "ldr"size"      r0, [r",11,24,   "], #-120")            \
+        TEST_P( "ldr"size"      r14, [r",1,24,   "], #-128")            \
+        TEST_P( "ldr"size"      r0, [r",11,24,    ", #120]!")           \
+        TEST_P( "ldr"size"      r14, [r",1, 24,   ", #128]!")           \
+        TEST_P( "ldr"size"      r0, [r",11,256,   ", #-120]!")          \
+        TEST_P( "ldr"size"      r14, [r",1, 256,  ", #-128]!")          \
+        TEST_PR("ldr"size".w    r0, [r",1, 0,", r",2, 4,"]")            \
+        TEST_PR("ldr"size"      r14, [r",10,0,", r",11,4,", lsl #1]")   \
+        TEST_X( "ldr"size".w    r0, 3f",                                \
+                ".align 3                               \n\t"           \
+                "3:     .word   "__stringify(VAL1))                     \
+        TEST_X( "ldr"size".w    r14, 3f",                               \
+                ".align 3                               \n\t"           \
+                "3:     .word   "__stringify(VAL2))                     \
+        TEST(   "ldr"size".w    r7, 3b")                                \
+        TEST(   "ldr"size".w    r7, [sp, #24]")                         \
+        TEST_P( "ldr"size".w    r0, [r",0,0, "]")                       \
+        TEST_UNSUPPORTED("ldr"size"t    r0, [r1, #4]")
+
+        SINGLE_LOAD("b")
+        SINGLE_LOAD("sb")
+        SINGLE_LOAD("h")
+        SINGLE_LOAD("sh")
+        SINGLE_LOAD("")
+
+        TEST_BF_P("ldr  pc, [r",14, 15*4,"]")
+        TEST_P(   "ldr  sp, [r",14, 13*4,"]")
+        TEST_BF_R("ldr  pc, [sp, r",14, 15*4,"]")
+        TEST_R(   "ldr  sp, [sp, r",14, 13*4,"]")
+        TEST_THUMB_TO_ARM_INTERWORK_P("ldr      pc, [r",0,0,", #15*4]")
+        TEST_SUPPORTED("ldr     sp, 99f")
+        TEST_SUPPORTED("ldr     pc, 99f")
+
+        TEST_UNSUPPORTED(".short 0xf854,0x700d  @ ldr   r7, [r4, sp]")
+        TEST_UNSUPPORTED(".short 0xf854,0x700f  @ ldr   r7, [r4, pc]")
+        TEST_UNSUPPORTED(".short 0xf814,0x700d  @ ldrb  r7, [r4, sp]")
+        TEST_UNSUPPORTED(".short 0xf814,0x700f  @ ldrb  r7, [r4, pc]")
+        TEST_UNSUPPORTED(".short 0xf89f,0xd004  @ ldrb  sp, 99f")
+        TEST_UNSUPPORTED(".short 0xf814,0xd008  @ ldrb  sp, [r4, r8]")
+        TEST_UNSUPPORTED(".short 0xf894,0xd000  @ ldrb  sp, [r4]")
+
+        TEST_UNSUPPORTED(".short 0xf860,0x0000") /* Unallocated space */
+        TEST_UNSUPPORTED(".short 0xf9ff,0xffff") /* Unallocated space */
+        TEST_UNSUPPORTED(".short 0xf950,0x0000") /* Unallocated space */
+        TEST_UNSUPPORTED(".short 0xf95f,0xffff") /* Unallocated space */
+        TEST_UNSUPPORTED(".short 0xf800,0x0800") /* Unallocated space */
+        TEST_UNSUPPORTED(".short 0xf97f,0xfaff") /* Unallocated space */
+
+        TEST(   "pli    [pc, #4]")
+        TEST(   "pli    [pc, #-4]")
+        TEST(   "pld    [pc, #4]")
+        TEST(   "pld    [pc, #-4]")
+
+        TEST_P( "pld    [r",0,-1024,", #1024]")
+        TEST(   ".short 0xf8b0,0xf400   @ pldw  [r0, #1024]")
+        TEST_P( "pli    [r",4, 0b,", #1024]")
+        TEST_P( "pld    [r",7, 120,", #-120]")
+        TEST(   ".short 0xf837,0xfc78   @ pldw  [r7, #-120]")
+        TEST_P( "pli    [r",11,120,", #-120]")
+        TEST(   "pld    [sp, #0]")
+
+        TEST_PR("pld    [r",7, 24, ", r",0, 16,"]")
+        TEST_PR("pld    [r",8, 24, ", r",12,16,", lsl #3]")
+        TEST_SUPPORTED(".short 0xf837,0xf000    @ pldw  [r7, r0]")
+        TEST_SUPPORTED(".short 0xf838,0xf03c    @ pldw  [r8, r12, lsl #3]");
+        TEST_RR("pli    [r",12,0b,", r",0, 16,"]")
+        TEST_RR("pli    [r",0, 0b,", r",12,16,", lsl #3]")
+        TEST_R( "pld    [sp, r",1, 16,"]")
+        TEST_UNSUPPORTED(".short 0xf817,0xf00d  @pld    [r7, sp]")
+        TEST_UNSUPPORTED(".short 0xf817,0xf00f  @pld    [r7, pc]")
+
+        TEST_GROUP("Data-processing (register)")
+
+#define SHIFTS32(op)                                    \
+        TEST_RR(op"     r0,  r",1, VAL1,", r",2, 3, "") \
+        TEST_RR(op"     r14, r",12,VAL2,", r",11,10,"")
+
+        SHIFTS32("lsl")
+        SHIFTS32("lsls")
+        SHIFTS32("lsr")
+        SHIFTS32("lsrs")
+        SHIFTS32("asr")
+        SHIFTS32("asrs")
+        SHIFTS32("ror")
+        SHIFTS32("rors")
+
+        TEST_UNSUPPORTED(".short 0xfa01,0xff02  @ lsl   pc, r1, r2")
+        TEST_UNSUPPORTED(".short 0xfa01,0xfd02  @ lsl   sp, r1, r2")
+        TEST_UNSUPPORTED(".short 0xfa0f,0xf002  @ lsl   r0, pc, r2")
+        TEST_UNSUPPORTED(".short 0xfa0d,0xf002  @ lsl   r0, sp, r2")
+        TEST_UNSUPPORTED(".short 0xfa01,0xf00f  @ lsl   r0, r1, pc")
+        TEST_UNSUPPORTED(".short 0xfa01,0xf00d  @ lsl   r0, r1, sp")
+
+        TEST_RR(    "sxtah      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "sxtah      r14,r",12, HH2,", r",10,HH1,", ror #8")
+        TEST_R(     "sxth       r8, r",7,  HH1,"")
+
+        TEST_UNSUPPORTED(".short 0xfa0f,0xff87  @ sxth  pc, r7");
+        TEST_UNSUPPORTED(".short 0xfa0f,0xfd87  @ sxth  sp, r7");
+        TEST_UNSUPPORTED(".short 0xfa0f,0xf88f  @ sxth  r8, pc");
+        TEST_UNSUPPORTED(".short 0xfa0f,0xf88d  @ sxth  r8, sp");
+
+        TEST_RR(    "uxtah      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uxtah      r14,r",12, HH2,", r",10,HH1,", ror #8")
+        TEST_R(     "uxth       r8, r",7,  HH1,"")
+
+        TEST_RR(    "sxtab16    r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "sxtab16    r14,r",12, HH2,", r",10,HH1,", ror #8")
+        TEST_R(     "sxtb16     r8, r",7,  HH1,"")
+
+        TEST_RR(    "uxtab16    r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uxtab16    r14,r",12, HH2,", r",10,HH1,", ror #8")
+        TEST_R(     "uxtb16     r8, r",7,  HH1,"")
+
+        TEST_RR(    "sxtab      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "sxtab      r14,r",12, HH2,", r",10,HH1,", ror #8")
+        TEST_R(     "sxtb       r8, r",7,  HH1,"")
+
+        TEST_RR(    "uxtab      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "uxtab      r14,r",12, HH2,", r",10,HH1,", ror #8")
+        TEST_R(     "uxtb       r8, r",7,  HH1,"")
+
+        TEST_UNSUPPORTED(".short 0xfa60,0x00f0")
+        TEST_UNSUPPORTED(".short 0xfa7f,0xffff")
+
+#define PARALLEL_ADD_SUB(op)                                    \
+        TEST_RR(  op"add16      r0, r",0,  HH1,", r",1, HH2,"") \
+        TEST_RR(  op"add16      r14, r",12,HH2,", r",10,HH1,"") \
+        TEST_RR(  op"asx        r0, r",0,  HH1,", r",1, HH2,"") \
+        TEST_RR(  op"asx        r14, r",12,HH2,", r",10,HH1,"") \
+        TEST_RR(  op"sax        r0, r",0,  HH1,", r",1, HH2,"") \
+        TEST_RR(  op"sax        r14, r",12,HH2,", r",10,HH1,"") \
+        TEST_RR(  op"sub16      r0, r",0,  HH1,", r",1, HH2,"") \
+        TEST_RR(  op"sub16      r14, r",12,HH2,", r",10,HH1,"") \
+        TEST_RR(  op"add8       r0, r",0,  HH1,", r",1, HH2,"") \
+        TEST_RR(  op"add8       r14, r",12,HH2,", r",10,HH1,"") \
+        TEST_RR(  op"sub8       r0, r",0,  HH1,", r",1, HH2,"") \
+        TEST_RR(  op"sub8       r14, r",12,HH2,", r",10,HH1,"")
+
+        TEST_GROUP("Parallel addition and subtraction, signed")
+
+        PARALLEL_ADD_SUB("s")
+        PARALLEL_ADD_SUB("q")
+        PARALLEL_ADD_SUB("sh")
+
+        TEST_GROUP("Parallel addition and subtraction, unsigned")
+
+        PARALLEL_ADD_SUB("u")
+        PARALLEL_ADD_SUB("uq")
+        PARALLEL_ADD_SUB("uh")
+
+        TEST_GROUP("Miscellaneous operations")
+
+        TEST_RR("qadd   r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR("qadd   lr, r",9, VAL2,", r",8, VAL1,"")
+        TEST_RR("qsub   r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR("qsub   lr, r",9, VAL2,", r",8, VAL1,"")
+        TEST_RR("qdadd  r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR("qdadd  lr, r",9, VAL2,", r",8, VAL1,"")
+        TEST_RR("qdsub  r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR("qdsub  lr, r",9, VAL2,", r",8, VAL1,"")
+
+        TEST_R("rev.w   r0, r",0,   VAL1,"")
+        TEST_R("rev     r14, r",12, VAL2,"")
+        TEST_R("rev16.w r0, r",0,   VAL1,"")
+        TEST_R("rev16   r14, r",12, VAL2,"")
+        TEST_R("rbit    r0, r",0,   VAL1,"")
+        TEST_R("rbit    r14, r",12, VAL2,"")
+        TEST_R("revsh.w r0, r",0,   VAL1,"")
+        TEST_R("revsh   r14, r",12, VAL2,"")
+
+        TEST_UNSUPPORTED(".short 0xfa9c,0xff8c  @ rev   pc, r12");
+        TEST_UNSUPPORTED(".short 0xfa9c,0xfd8c  @ rev   sp, r12");
+        TEST_UNSUPPORTED(".short 0xfa9f,0xfe8f  @ rev   r14, pc");
+        TEST_UNSUPPORTED(".short 0xfa9d,0xfe8d  @ rev   r14, sp");
+
+        TEST_RR("sel    r0, r",0,  VAL1,", r",1, VAL2,"")
+        TEST_RR("sel    r14, r",12,VAL1,", r",10, VAL2,"")
+
+        TEST_R("clz     r0, r",0, 0x0,"")
+        TEST_R("clz     r7, r",14,0x1,"")
+        TEST_R("clz     lr, r",7, 0xffffffff,"")
+
+        TEST_UNSUPPORTED(".short 0xfa80,0xf030") /* Unallocated space */
+        TEST_UNSUPPORTED(".short 0xfaff,0xff7f") /* Unallocated space */
+        TEST_UNSUPPORTED(".short 0xfab0,0xf000") /* Unallocated space */
+        TEST_UNSUPPORTED(".short 0xfaff,0xff7f") /* Unallocated space */
+
+        TEST_GROUP("Multiply, multiply accumulate, and absolute difference operations")
+
+        TEST_RR(    "mul        r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(    "mul        r7, r",8, VAL2,", r",9, VAL2,"")
+        TEST_UNSUPPORTED(".short 0xfb08,0xff09  @ mul   pc, r8, r9")
+        TEST_UNSUPPORTED(".short 0xfb08,0xfd09  @ mul   sp, r8, r9")
+        TEST_UNSUPPORTED(".short 0xfb0f,0xf709  @ mul   r7, pc, r9")
+        TEST_UNSUPPORTED(".short 0xfb0d,0xf709  @ mul   r7, sp, r9")
+        TEST_UNSUPPORTED(".short 0xfb08,0xf70f  @ mul   r7, r8, pc")
+        TEST_UNSUPPORTED(".short 0xfb08,0xf70d  @ mul   r7, r8, sp")
+
+        TEST_RRR(   "mla        r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(   "mla        r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+        TEST_UNSUPPORTED(".short 0xfb08,0xaf09  @ mla   pc, r8, r9, r10");
+        TEST_UNSUPPORTED(".short 0xfb08,0xad09  @ mla   sp, r8, r9, r10");
+        TEST_UNSUPPORTED(".short 0xfb0f,0xa709  @ mla   r7, pc, r9, r10");
+        TEST_UNSUPPORTED(".short 0xfb0d,0xa709  @ mla   r7, sp, r9, r10");
+        TEST_UNSUPPORTED(".short 0xfb08,0xa70f  @ mla   r7, r8, pc, r10");
+        TEST_UNSUPPORTED(".short 0xfb08,0xa70d  @ mla   r7, r8, sp, r10");
+        TEST_UNSUPPORTED(".short 0xfb08,0xd709  @ mla   r7, r8, r9, sp");
+
+        TEST_RRR(   "mls        r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(   "mls        r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+
+        TEST_RRR(   "smlabb     r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(   "smlabb     r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+        TEST_RRR(   "smlatb     r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(   "smlatb     r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+        TEST_RRR(   "smlabt     r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(   "smlabt     r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+        TEST_RRR(   "smlatt     r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(   "smlatt     r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+        TEST_RR(    "smulbb     r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(    "smulbb     r7, r",8, VAL3,", r",9, VAL1,"")
+        TEST_RR(    "smultb     r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(    "smultb     r7, r",8, VAL3,", r",9, VAL1,"")
+        TEST_RR(    "smulbt     r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(    "smulbt     r7, r",8, VAL3,", r",9, VAL1,"")
+        TEST_RR(    "smultt     r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(    "smultt     r7, r",8, VAL3,", r",9, VAL1,"")
+
+        TEST_RRR(   "smlad      r0, r",0,  HH1,", r",1, HH2,", r",2, VAL1,"")
+        TEST_RRR(   "smlad      r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
+        TEST_RRR(   "smladx     r0, r",0,  HH1,", r",1, HH2,", r",2, VAL1,"")
+        TEST_RRR(   "smladx     r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
+        TEST_RR(    "smuad      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "smuad      r14, r",12,HH2,", r",10,HH1,"")
+        TEST_RR(    "smuadx     r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "smuadx     r14, r",12,HH2,", r",10,HH1,"")
+
+        TEST_RRR(   "smlawb     r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(   "smlawb     r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+        TEST_RRR(   "smlawt     r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
+        TEST_RRR(   "smlawt     r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
+        TEST_RR(    "smulwb     r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(    "smulwb     r7, r",8, VAL3,", r",9, VAL1,"")
+        TEST_RR(    "smulwt     r0, r",1, VAL1,", r",2, VAL2,"")
+        TEST_RR(    "smulwt     r7, r",8, VAL3,", r",9, VAL1,"")
+
+        TEST_RRR(   "smlsd      r0, r",0,  HH1,", r",1, HH2,", r",2, VAL1,"")
+        TEST_RRR(   "smlsd      r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
+        TEST_RRR(   "smlsdx     r0, r",0,  HH1,", r",1, HH2,", r",2, VAL1,"")
+        TEST_RRR(   "smlsdx     r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
+        TEST_RR(    "smusd      r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "smusd      r14, r",12,HH2,", r",10,HH1,"")
+        TEST_RR(    "smusdx     r0, r",0,  HH1,", r",1, HH2,"")
+        TEST_RR(    "smusdx     r14, r",12,HH2,", r",10,HH1,"")
+
+        TEST_RRR(   "smmla      r0, r",0,  VAL1,", r",1, VAL2,", r",2, VAL1,"")
+        TEST_RRR(   "smmla      r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
+        TEST_RRR(   "smmlar     r0, r",0,  VAL1,", r",1, VAL2,", r",2, VAL1,"")
+        TEST_RRR(   "smmlar     r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
+        TEST_RR(    "smmul      r0, r",0,  VAL1,", r",1, VAL2,"")
+        TEST_RR(    "smmul      r14, r",12,VAL2,", r",10,VAL1,"")
+        TEST_RR(    "smmulr     r0, r",0,  VAL1,", r",1, VAL2,"")
+        TEST_RR(    "smmulr     r14, r",12,VAL2,", r",10,VAL1,"")
+
+        TEST_RRR(   "smmls      r0, r",0,  VAL1,", r",1, VAL2,", r",2, VAL1,"")
+        TEST_RRR(   "smmls      r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
+        TEST_RRR(   "smmlsr     r0, r",0,  VAL1,", r",1, VAL2,", r",2, VAL1,"")
+        TEST_RRR(   "smmlsr     r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
+
+        TEST_RRR(   "usada8     r0, r",0,  VAL1,", r",1, VAL2,", r",2, VAL3,"")
+        TEST_RRR(   "usada8     r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL3,"")
+        TEST_RR(    "usad8      r0, r",0,  VAL1,", r",1, VAL2,"")
+        TEST_RR(    "usad8      r14, r",12,VAL2,", r",10,VAL1,"")
+
+        TEST_UNSUPPORTED(".short 0xfb00,0xf010") /* Unallocated space */
+        TEST_UNSUPPORTED(".short 0xfb0f,0xff1f") /* Unallocated space */
+        TEST_UNSUPPORTED(".short 0xfb70,0xf010") /* Unallocated space */
+        TEST_UNSUPPORTED(".short 0xfb7f,0xff1f") /* Unallocated space */
+        TEST_UNSUPPORTED(".short 0xfb70,0x0010") /* Unallocated space */
+        TEST_UNSUPPORTED(".short 0xfb7f,0xff1f") /* Unallocated space */
+
+        TEST_GROUP("Long multiply, long multiply accumulate, and divide")
+
+        TEST_RR(   "smull       r0, r1, r",2, VAL1,", r",3, VAL2,"")
+        TEST_RR(   "smull       r7, r8, r",9, VAL2,", r",10, VAL1,"")
+        TEST_UNSUPPORTED(".short 0xfb89,0xf80a  @ smull pc, r8, r9, r10");
+        TEST_UNSUPPORTED(".short 0xfb89,0xd80a  @ smull sp, r8, r9, r10");
+        TEST_UNSUPPORTED(".short 0xfb89,0x7f0a  @ smull r7, pc, r9, r10");
+        TEST_UNSUPPORTED(".short 0xfb89,0x7d0a  @ smull r7, sp, r9, r10");
+        TEST_UNSUPPORTED(".short 0xfb8f,0x780a  @ smull r7, r8, pc, r10");
+        TEST_UNSUPPORTED(".short 0xfb8d,0x780a  @ smull r7, r8, sp, r10");
+        TEST_UNSUPPORTED(".short 0xfb89,0x780f  @ smull r7, r8, r9, pc");
+        TEST_UNSUPPORTED(".short 0xfb89,0x780d  @ smull r7, r8, r9, sp");
+
+        TEST_RR(   "umull       r0, r1, r",2, VAL1,", r",3, VAL2,"")
+        TEST_RR(   "umull       r7, r8, r",9, VAL2,", r",10, VAL1,"")
+
+        TEST_RRRR( "smlal       r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
+        TEST_RRRR( "smlal       r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
+
+        TEST_RRRR( "smlalbb     r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
+        TEST_RRRR( "smlalbb     r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
+        TEST_RRRR( "smlalbt     r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
+        TEST_RRRR( "smlalbt     r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
+        TEST_RRRR( "smlaltb     r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
+        TEST_RRRR( "smlaltb     r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
+        TEST_RRRR( "smlaltt     r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
+        TEST_RRRR( "smlaltt     r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
+
+        TEST_RRRR( "smlald      r",0, VAL1,", r",1, VAL2, ", r",0, HH1,", r",1, HH2)
+        TEST_RRRR( "smlald      r",11,VAL2,", r",10,VAL1, ", r",9, HH2,", r",8, HH1)
+        TEST_RRRR( "smlaldx     r",0, VAL1,", r",1, VAL2, ", r",0, HH1,", r",1, HH2)
+        TEST_RRRR( "smlaldx     r",11,VAL2,", r",10,VAL1, ", r",9, HH2,", r",8, HH1)
+
+        TEST_RRRR( "smlsld      r",0, VAL1,", r",1, VAL2, ", r",0, HH1,", r",1, HH2)
+        TEST_RRRR( "smlsld      r",11,VAL2,", r",10,VAL1, ", r",9, HH2,", r",8, HH1)
+        TEST_RRRR( "smlsldx     r",0, VAL1,", r",1, VAL2, ", r",0, HH1,", r",1, HH2)
+        TEST_RRRR( "smlsldx     r",11,VAL2,", r",10,VAL1, ", r",9, HH2,", r",8, HH1)
+
+        TEST_RRRR( "umlal       r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
+        TEST_RRRR( "umlal       r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
+        TEST_RRRR( "umaal       r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
+        TEST_RRRR( "umaal       r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
+
+        TEST_GROUP("Coprocessor instructions")
+
+        TEST_UNSUPPORTED(".short 0xfc00,0x0000")
+        TEST_UNSUPPORTED(".short 0xffff,0xffff")
+
+        TEST_GROUP("Testing instructions in IT blocks")
+
+        TEST_ITBLOCK("sub.w     r0, r0")
+
+        verbose("\n");
+}
+
diff --git a/arch/arm/kernel/kprobes-test.c b/arch/arm/kernel/kprobes-test.c
new file mode 100644
index 000000000000..e17cdd6d90d8
--- /dev/null
+++ b/arch/arm/kernel/kprobes-test.c
@@ -0,0 +1,1748 @@
+/*
+ * arch/arm/kernel/kprobes-test.c
+ *
+ * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * This file contains test code for ARM kprobes.
+ *
+ * The top level function run_all_tests() executes tests for all of the
+ * supported instruction sets: ARM, 16-bit Thumb, and 32-bit Thumb. These tests
+ * fall into two categories; run_api_tests() checks basic functionality of the
+ * kprobes API, and run_test_cases() is a comprehensive test for kprobes
+ * instruction decoding and simulation.
+ *
+ * run_test_cases() first checks the kprobes decoding table for self consistency
+ * (using table_test()) then executes a series of test cases for each of the CPU
+ * instruction forms. coverage_start() and coverage_end() are used to verify
+ * that these test cases cover all of the possible combinations of instructions
+ * described by the kprobes decoding tables.
+ *
+ * The individual test cases are in kprobes-test-arm.c and kprobes-test-thumb.c
+ * which use the macros defined in kprobes-test.h. The rest of this
+ * documentation will describe the operation of the framework used by these
+ * test cases.
+ */
+
+/*
+ * TESTING METHODOLOGY
+ * -------------------
+ *
+ * The methodology used to test an ARM instruction 'test_insn' is to use
+ * inline assembler like:
+ *
+ * test_before: nop
+ * test_case:   test_insn
+ * test_after:  nop
+ *
+ * When the test case is run a kprobe is placed of each nop. The
+ * post-handler of the test_before probe is used to modify the saved CPU
+ * register context to that which we require for the test case. The
+ * pre-handler of the of the test_after probe saves a copy of the CPU
+ * register context. In this way we can execute test_insn with a specific
+ * register context and see the results afterwards.
+ *
+ * To actually test the kprobes instruction emulation we perform the above
+ * step a second time but with an additional kprobe on the test_case
+ * instruction itself. If the emulation is accurate then the results seen
+ * by the test_after probe will be identical to the first run which didn't
+ * have a probe on test_case.
+ *
+ * Each test case is run several times with a variety of variations in the
+ * flags value of stored in CPSR, and for Thumb code, different ITState.
+ *
+ * For instructions which can modify PC, a second test_after probe is used
+ * like this:
+ *
+ * test_before: nop
+ * test_case:   test_insn
+ * test_after:  nop
+ *              b test_done
+ * test_after2: nop
+ * test_done:
+ *
+ * The test case is constructed such that test_insn branches to
+ * test_after2, or, if testing a conditional instruction, it may just
+ * continue to test_after. The probes inserted at both locations let us
+ * determine which happened. A similar approach is used for testing
+ * backwards branches...
+ *
+ *              b test_before
+ *              b test_done  @ helps to cope with off by 1 branches
+ * test_after2: nop
+ *              b test_done
+ * test_before: nop
+ * test_case:   test_insn
+ * test_after:  nop
+ * test_done:
+ *
+ * The macros used to generate the assembler instructions describe above
+ * are TEST_INSTRUCTION, TEST_BRANCH_F (branch forwards) and TEST_BRANCH_B
+ * (branch backwards). In these, the local variables numbered 1, 50, 2 and
+ * 99 represent: test_before, test_case, test_after2 and test_done.
+ *
+ * FRAMEWORK
+ * ---------
+ *
+ * Each test case is wrapped between the pair of macros TESTCASE_START and
+ * TESTCASE_END. As well as performing the inline assembler boilerplate,
+ * these call out to the kprobes_test_case_start() and
+ * kprobes_test_case_end() functions which drive the execution of the test
+ * case. The specific arguments to use for each test case are stored as
+ * inline data constructed using the various TEST_ARG_* macros. Putting
+ * this all together, a simple test case may look like:
+ *
+ *      TESTCASE_START("Testing mov r0, r7")
+ *      TEST_ARG_REG(7, 0x12345678) // Set r7=0x12345678
+ *      TEST_ARG_END("")
+ *      TEST_INSTRUCTION("mov r0, r7")
+ *      TESTCASE_END
+ *
+ * Note, in practice the single convenience macro TEST_R would be used for this
+ * instead.
+ *
+ * The above would expand to assembler looking something like:
+ *
+ *      @ TESTCASE_START
+ *      bl      __kprobes_test_case_start
+ *      @ start of inline data...
+ *      .ascii "mov r0, r7"     @ text title for test case
+ *      .byte   0
+ *      .align  2
+ *
+ *      @ TEST_ARG_REG
+ *      .byte   ARG_TYPE_REG
+ *      .byte   7
+ *      .short  0
+ *      .word   0x1234567
+ *
+ *      @ TEST_ARG_END
+ *      .byte   ARG_TYPE_END
+ *      .byte   TEST_ISA        @ flags, including ISA being tested
+ *      .short  50f-0f          @ offset of 'test_before'
+ *      .short  2f-0f           @ offset of 'test_after2' (if relevent)
+ *      .short  99f-0f          @ offset of 'test_done'
+ *      @ start of test case code...
+ *      0:
+ *      .code   TEST_ISA        @ switch to ISA being tested
+ *
+ *      @ TEST_INSTRUCTION
+ *      50:     nop             @ location for 'test_before' probe
+ *      1:      mov r0, r7      @ the test case instruction 'test_insn'
+ *              nop             @ location for 'test_after' probe
+ *
+ *      // TESTCASE_END
+ *      2:
+ *      99:     bl __kprobes_test_case_end_##TEST_ISA
+ *      .code   NONMAL_ISA
+ *
+ * When the above is execute the following happens...
+ *
+ * __kprobes_test_case_start() is an assembler wrapper which sets up space
+ * for a stack buffer and calls the C function kprobes_test_case_start().
+ * This C function will do some initial processing of the inline data and
+ * setup some global state. It then inserts the test_before and test_after
+ * kprobes and returns a value which causes the assembler wrapper to jump
+ * to the start of the test case code, (local label '0').
+ *
+ * When the test case code executes, the test_before probe will be hit and
+ * test_before_post_handler will call setup_test_context(). This fills the
+ * stack buffer and CPU registers with a test pattern and then processes
+ * the test case arguments. In our example there is one TEST_ARG_REG which
+ * indicates that R7 should be loaded with the value 0x12345678.
+ *
+ * When the test_before probe ends, the test case continues and executes
+ * the "mov r0, r7" instruction. It then hits the test_after probe and the
+ * pre-handler for this (test_after_pre_handler) will save a copy of the
+ * CPU register context. This should now have R0 holding the same value as
+ * R7.
+ *
+ * Finally we get to the call to __kprobes_test_case_end_{32,16}. This is
+ * an assembler wrapper which switches back to the ISA used by the test
+ * code and calls the C function kprobes_test_case_end().
+ *
+ * For each run through the test case, test_case_run_count is incremented
+ * by one. For even runs, kprobes_test_case_end() saves a copy of the
+ * register and stack buffer contents from the test case just run. It then
+ * inserts a kprobe on the test case instruction 'test_insn' and returns a
+ * value to cause the test case code to be re-run.
+ *
+ * For odd numbered runs, kprobes_test_case_end() compares the register and
+ * stack buffer contents to those that were saved on the previous even
+ * numbered run (the one without the kprobe on test_insn). These should be
+ * the same if the kprobe instruction simulation routine is correct.
+ *
+ * The pair of test case runs is repeated with different combinations of
+ * flag values in CPSR and, for Thumb, different ITState. This is
+ * controlled by test_context_cpsr().
+ *
+ * BUILDING TEST CASES
+ * -------------------
+ *
+ *
+ * As an aid to building test cases, the stack buffer is initialised with
+ * some special values:
+ *
+ *   [SP+13*4]  Contains SP+120. This can be used to test instructions
+ *              which load a value into SP.
+ *
+ *   [SP+15*4]  When testing branching instructions using TEST_BRANCH_{F,B},
+ *              this holds the target address of the branch, 'test_after2'.
+ *              This can be used to test instructions which load a PC value
+ *              from memory.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/kprobes.h>
+
+#include "kprobes.h"
+#include "kprobes-test.h"
+
+
+#define BENCHMARKING    1
+
+
+/*
+ * Test basic API
+ */
+
+static bool test_regs_ok;
+static int test_func_instance;
+static int pre_handler_called;
+static int post_handler_called;
+static int jprobe_func_called;
+static int kretprobe_handler_called;
+
+#define FUNC_ARG1 0x12345678
+#define FUNC_ARG2 0xabcdef
+
+
+#ifndef CONFIG_THUMB2_KERNEL
+
+long arm_func(long r0, long r1);
+
+static void __used __naked __arm_kprobes_test_func(void)
+{
+        __asm__ __volatile__ (
+                ".arm                                   \n\t"
+                ".type arm_func, %%function             \n\t"
+                "arm_func:                              \n\t"
+                "adds   r0, r0, r1                      \n\t"
+                "bx     lr                              \n\t"
+                ".code "NORMAL_ISA       /* Back to Thumb if necessary */
+                : : : "r0", "r1", "cc"
+        );
+}
+
+#else /* CONFIG_THUMB2_KERNEL */
+
+long thumb16_func(long r0, long r1);
+long thumb32even_func(long r0, long r1);
+long thumb32odd_func(long r0, long r1);
+
+static void __used __naked __thumb_kprobes_test_funcs(void)
+{
+        __asm__ __volatile__ (
+                ".type thumb16_func, %%function         \n\t"
+                "thumb16_func:                          \n\t"
+                "adds.n r0, r0, r1                      \n\t"
+                "bx     lr                              \n\t"
+
+                ".align                                 \n\t"
+                ".type thumb32even_func, %%function     \n\t"
+                "thumb32even_func:                      \n\t"
+                "adds.w r0, r0, r1                      \n\t"
+                "bx     lr                              \n\t"
+
+                ".align                                 \n\t"
+                "nop.n                                  \n\t"
+                ".type thumb32odd_func, %%function      \n\t"
+                "thumb32odd_func:                       \n\t"
+                "adds.w r0, r0, r1                      \n\t"
+                "bx     lr                              \n\t"
+
+                : : : "r0", "r1", "cc"
+        );
+}
+
+#endif /* CONFIG_THUMB2_KERNEL */
+
+
+static int call_test_func(long (*func)(long, long), bool check_test_regs)
+{
+        long ret;
+
+        ++test_func_instance;
+        test_regs_ok = false;
+
+        ret = (*func)(FUNC_ARG1, FUNC_ARG2);
+        if (ret != FUNC_ARG1 + FUNC_ARG2) {
+                pr_err("FAIL: call_test_func: func returned %lx\n", ret);
+                return false;
+        }
+
+        if (check_test_regs && !test_regs_ok) {
+                pr_err("FAIL: test regs not OK\n");
+                return false;
+        }
+
+        return true;
+}
+
+static int __kprobes pre_handler(struct kprobe *p, struct pt_regs *regs)
+{
+        pre_handler_called = test_func_instance;
+        if (regs->ARM_r0 == FUNC_ARG1 && regs->ARM_r1 == FUNC_ARG2)
+                test_regs_ok = true;
+        return 0;
+}
+
+static void __kprobes post_handler(struct kprobe *p, struct pt_regs *regs,
+                                unsigned long flags)
+{
+        post_handler_called = test_func_instance;
+        if (regs->ARM_r0 != FUNC_ARG1 + FUNC_ARG2 || regs->ARM_r1 != FUNC_ARG2)
+                test_regs_ok = false;
+}
+
+static struct kprobe the_kprobe = {
+        .addr           = 0,
+        .pre_handler    = pre_handler,
+        .post_handler   = post_handler
+};
+
+static int test_kprobe(long (*func)(long, long))
+{
+        int ret;
+
+        the_kprobe.addr = (kprobe_opcode_t *)func;
+        ret = register_kprobe(&the_kprobe);
+        if (ret < 0) {
+                pr_err("FAIL: register_kprobe failed with %d\n", ret);
+                return ret;
+        }
+
+        ret = call_test_func(func, true);
+
+        unregister_kprobe(&the_kprobe);
+        the_kprobe.flags = 0; /* Clear disable flag to allow reuse */
+
+        if (!ret)
+                return -EINVAL;
+        if (pre_handler_called != test_func_instance) {
+                pr_err("FAIL: kprobe pre_handler not called\n");
+                return -EINVAL;
+        }
+        if (post_handler_called != test_func_instance) {
+                pr_err("FAIL: kprobe post_handler not called\n");
+                return -EINVAL;
+        }
+        if (!call_test_func(func, false))
+                return -EINVAL;
+        if (pre_handler_called == test_func_instance ||
+                                post_handler_called == test_func_instance) {
+                pr_err("FAIL: probe called after unregistering\n");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static void __kprobes jprobe_func(long r0, long r1)
+{
+        jprobe_func_called = test_func_instance;
+        if (r0 == FUNC_ARG1 && r1 == FUNC_ARG2)
+                test_regs_ok = true;
+        jprobe_return();
+}
+
+static struct jprobe the_jprobe = {
+        .entry          = jprobe_func,
+};
+
+static int test_jprobe(long (*func)(long, long))
+{
+        int ret;
+
+        the_jprobe.kp.addr = (kprobe_opcode_t *)func;
+        ret = register_jprobe(&the_jprobe);
+        if (ret < 0) {
+                pr_err("FAIL: register_jprobe failed with %d\n", ret);
+                return ret;
+        }
+
+        ret = call_test_func(func, true);
+
+        unregister_jprobe(&the_jprobe);
+        the_jprobe.kp.flags = 0; /* Clear disable flag to allow reuse */
+
+        if (!ret)
+                return -EINVAL;
+        if (jprobe_func_called != test_func_instance) {
+                pr_err("FAIL: jprobe handler function not called\n");
+                return -EINVAL;
+        }
+        if (!call_test_func(func, false))
+                return -EINVAL;
+        if (jprobe_func_called == test_func_instance) {
+                pr_err("FAIL: probe called after unregistering\n");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int __kprobes
+kretprobe_handler(struct kretprobe_instance *ri, struct pt_regs *regs)
+{
+        kretprobe_handler_called = test_func_instance;
+        if (regs_return_value(regs) == FUNC_ARG1 + FUNC_ARG2)
+                test_regs_ok = true;
+        return 0;
+}
+
+static struct kretprobe the_kretprobe = {
+        .handler        = kretprobe_handler,
+};
+
+static int test_kretprobe(long (*func)(long, long))
+{
+        int ret;
+
+        the_kretprobe.kp.addr = (kprobe_opcode_t *)func;
+        ret = register_kretprobe(&the_kretprobe);
+        if (ret < 0) {
+                pr_err("FAIL: register_kretprobe failed with %d\n", ret);
+                return ret;
+        }
+
+        ret = call_test_func(func, true);
+
+        unregister_kretprobe(&the_kretprobe);
+        the_kretprobe.kp.flags = 0; /* Clear disable flag to allow reuse */
+
+        if (!ret)
+                return -EINVAL;
+        if (kretprobe_handler_called != test_func_instance) {
+                pr_err("FAIL: kretprobe handler not called\n");
+                return -EINVAL;
+        }
+        if (!call_test_func(func, false))
+                return -EINVAL;
+        if (jprobe_func_called == test_func_instance) {
+                pr_err("FAIL: kretprobe called after unregistering\n");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int run_api_tests(long (*func)(long, long))
+{
+        int ret;
+
+        pr_info("    kprobe\n");
+        ret = test_kprobe(func);
+        if (ret < 0)
+                return ret;
+
+        pr_info("    jprobe\n");
+        ret = test_jprobe(func);
+        if (ret < 0)
+                return ret;
+
+        pr_info("    kretprobe\n");
+        ret = test_kretprobe(func);
+        if (ret < 0)
+                return ret;
+
+        return 0;
+}
+
+
+/*
+ * Benchmarking
+ */
+
+#if BENCHMARKING
+
+static void __naked benchmark_nop(void)
+{
+        __asm__ __volatile__ (
+                "nop            \n\t"
+                "bx     lr"
+        );
+}
+
+#ifdef CONFIG_THUMB2_KERNEL
+#define wide ".w"
+#else
+#define wide
+#endif
+
+static void __naked benchmark_pushpop1(void)
+{
+        __asm__ __volatile__ (
+                "stmdb"wide"    sp!, {r3-r11,lr}  \n\t"
+                "ldmia"wide"    sp!, {r3-r11,pc}"
+        );
+}
+
+static void __naked benchmark_pushpop2(void)
+{
+        __asm__ __volatile__ (
+                "stmdb"wide"    sp!, {r0-r8,lr}  \n\t"
+                "ldmia"wide"    sp!, {r0-r8,pc}"
+        );
+}
+
+static void __naked benchmark_pushpop3(void)
+{
+        __asm__ __volatile__ (
+                "stmdb"wide"    sp!, {r4,lr}  \n\t"
+                "ldmia"wide"    sp!, {r4,pc}"
+        );
+}
+
+static void __naked benchmark_pushpop4(void)
+{
+        __asm__ __volatile__ (
+                "stmdb"wide"    sp!, {r0,lr}  \n\t"
+                "ldmia"wide"    sp!, {r0,pc}"
+        );
+}
+
+
+#ifdef CONFIG_THUMB2_KERNEL
+
+static void __naked benchmark_pushpop_thumb(void)
+{
+        __asm__ __volatile__ (
+                "push.n {r0-r7,lr}  \n\t"
+                "pop.n  {r0-r7,pc}"
+        );
+}
+
+#endif
+
+static int __kprobes
+benchmark_pre_handler(struct kprobe *p, struct pt_regs *regs)
+{
+        return 0;
+}
+
+static int benchmark(void(*fn)(void))
+{
+        unsigned n, i, t, t0;
+
+        for (n = 1000; ; n *= 2) {
+                t0 = sched_clock();
+                for (i = n; i > 0; --i)
+                        fn();
+                t = sched_clock() - t0;
+                if (t >= 250000000)
+                        break; /* Stop once we took more than 0.25 seconds */
+        }
+        return t / n; /* Time for one iteration in nanoseconds */
+};
+
+static int kprobe_benchmark(void(*fn)(void), unsigned offset)
+{
+        struct kprobe k = {
+                .addr           = (kprobe_opcode_t *)((uintptr_t)fn + offset),
+                .pre_handler    = benchmark_pre_handler,
+        };
+
+        int ret = register_kprobe(&k);
+        if (ret < 0) {
+                pr_err("FAIL: register_kprobe failed with %d\n", ret);
+                return ret;
+        }
+
+        ret = benchmark(fn);
+
+        unregister_kprobe(&k);
+        return ret;
+};
+
+struct benchmarks {
+        void            (*fn)(void);
+        unsigned        offset;
+        const char      *title;
+};
+
+static int run_benchmarks(void)
+{
+        int ret;
+        struct benchmarks list[] = {
+                {&benchmark_nop, 0, "nop"},
+                /*
+                 * benchmark_pushpop{1,3} will have the optimised
+                 * instruction emulation, whilst benchmark_pushpop{2,4} will
+                 * be the equivalent unoptimised instructions.
+                 */
+                {&benchmark_pushpop1, 0, "stmdb sp!, {r3-r11,lr}"},
+                {&benchmark_pushpop1, 4, "ldmia sp!, {r3-r11,pc}"},
+                {&benchmark_pushpop2, 0, "stmdb sp!, {r0-r8,lr}"},
+                {&benchmark_pushpop2, 4, "ldmia sp!, {r0-r8,pc}"},
+                {&benchmark_pushpop3, 0, "stmdb sp!, {r4,lr}"},
+                {&benchmark_pushpop3, 4, "ldmia sp!, {r4,pc}"},
+                {&benchmark_pushpop4, 0, "stmdb sp!, {r0,lr}"},
+                {&benchmark_pushpop4, 4, "ldmia sp!, {r0,pc}"},
+#ifdef CONFIG_THUMB2_KERNEL
+                {&benchmark_pushpop_thumb, 0, "push.n   {r0-r7,lr}"},
+                {&benchmark_pushpop_thumb, 2, "pop.n    {r0-r7,pc}"},
+#endif
+                {0}
+        };
+
+        struct benchmarks *b;
+        for (b = list; b->fn; ++b) {
+                ret = kprobe_benchmark(b->fn, b->offset);
+                if (ret < 0)
+                        return ret;
+                pr_info("    %dns for kprobe %s\n", ret, b->title);
+        }
+
+        pr_info("\n");
+        return 0;
+}
+
+#endif /* BENCHMARKING */
+
+
+/*
+ * Decoding table self-consistency tests
+ */
+
+static const int decode_struct_sizes[NUM_DECODE_TYPES] = {
+        [DECODE_TYPE_TABLE]     = sizeof(struct decode_table),
+        [DECODE_TYPE_CUSTOM]    = sizeof(struct decode_custom),
+        [DECODE_TYPE_SIMULATE]  = sizeof(struct decode_simulate),
+        [DECODE_TYPE_EMULATE]   = sizeof(struct decode_emulate),
+        [DECODE_TYPE_OR]        = sizeof(struct decode_or),
+        [DECODE_TYPE_REJECT]    = sizeof(struct decode_reject)
+};
+
+static int table_iter(const union decode_item *table,
+                        int (*fn)(const struct decode_header *, void *),
+                        void *args)
+{
+        const struct decode_header *h = (struct decode_header *)table;
+        int result;
+
+        for (;;) {
+                enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK;
+
+                if (type == DECODE_TYPE_END)
+                        return 0;
+
+                result = fn(h, args);
+                if (result)
+                        return result;
+
+                h = (struct decode_header *)
+                        ((uintptr_t)h + decode_struct_sizes[type]);
+
+        }
+}
+
+static int table_test_fail(const struct decode_header *h, const char* message)
+{
+
+        pr_err("FAIL: kprobes test failure \"%s\" (mask %08x, value %08x)\n",
+                                        message, h->mask.bits, h->value.bits);
+        return -EINVAL;
+}
+
+struct table_test_args {
+        const union decode_item *root_table;
+        u32                     parent_mask;
+        u32                     parent_value;
+};
+
+static int table_test_fn(const struct decode_header *h, void *args)
+{
+        struct table_test_args *a = (struct table_test_args *)args;
+        enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK;
+
+        if (h->value.bits & ~h->mask.bits)
+                return table_test_fail(h, "Match value has bits not in mask");
+
+        if ((h->mask.bits & a->parent_mask) != a->parent_mask)
+                return table_test_fail(h, "Mask has bits not in parent mask");
+
+        if ((h->value.bits ^ a->parent_value) & a->parent_mask)
+                return table_test_fail(h, "Value is inconsistent with parent");
+
+        if (type == DECODE_TYPE_TABLE) {
+                struct decode_table *d = (struct decode_table *)h;
+                struct table_test_args args2 = *a;
+                args2.parent_mask = h->mask.bits;
+                args2.parent_value = h->value.bits;
+                return table_iter(d->table.table, table_test_fn, &args2);
+        }
+
+        return 0;
+}
+
+static int table_test(const union decode_item *table)
+{
+        struct table_test_args args = {
+                .root_table     = table,
+                .parent_mask    = 0,
+                .parent_value   = 0
+        };
+        return table_iter(args.root_table, table_test_fn, &args);
+}
+
+
+/*
+ * Decoding table test coverage analysis
+ *
+ * coverage_start() builds a coverage_table which contains a list of
+ * coverage_entry's to match each entry in the specified kprobes instruction
+ * decoding table.
+ *
+ * When test cases are run, coverage_add() is called to process each case.
+ * This looks up the corresponding entry in the coverage_table and sets it as
+ * being matched, as well as clearing the regs flag appropriate for the test.
+ *
+ * After all test cases have been run, coverage_end() is called to check that
+ * all entries in coverage_table have been matched and that all regs flags are
+ * cleared. I.e. that all possible combinations of instructions described by
+ * the kprobes decoding tables have had a test case executed for them.
+ */
+
+bool coverage_fail;
+
+#define MAX_COVERAGE_ENTRIES 256
+
+struct coverage_entry {
+        const struct decode_header      *header;
+        unsigned                        regs;
+        unsigned                        nesting;
+        char                            matched;
+};
+
+struct coverage_table {
+        struct coverage_entry   *base;
+        unsigned                num_entries;
+        unsigned                nesting;
+};
+
+struct coverage_table coverage;
+
+#define COVERAGE_ANY_REG        (1<<0)
+#define COVERAGE_SP             (1<<1)
+#define COVERAGE_PC             (1<<2)
+#define COVERAGE_PCWB           (1<<3)
+
+static const char coverage_register_lookup[16] = {
+        [REG_TYPE_ANY]          = COVERAGE_ANY_REG | COVERAGE_SP | COVERAGE_PC,
+        [REG_TYPE_SAMEAS16]     = COVERAGE_ANY_REG,
+        [REG_TYPE_SP]           = COVERAGE_SP,
+        [REG_TYPE_PC]           = COVERAGE_PC,
+        [REG_TYPE_NOSP]         = COVERAGE_ANY_REG | COVERAGE_SP,
+        [REG_TYPE_NOSPPC]       = COVERAGE_ANY_REG | COVERAGE_SP | COVERAGE_PC,
+        [REG_TYPE_NOPC]         = COVERAGE_ANY_REG | COVERAGE_PC,
+        [REG_TYPE_NOPCWB]       = COVERAGE_ANY_REG | COVERAGE_PC | COVERAGE_PCWB,
+        [REG_TYPE_NOPCX]        = COVERAGE_ANY_REG,
+        [REG_TYPE_NOSPPCX]      = COVERAGE_ANY_REG | COVERAGE_SP,
+};
+
+unsigned coverage_start_registers(const struct decode_header *h)
+{
+        unsigned regs = 0;
+        int i;
+        for (i = 0; i < 20; i += 4) {
+                int r = (h->type_regs.bits >> (DECODE_TYPE_BITS + i)) & 0xf;
+                regs |= coverage_register_lookup[r] << i;
+        }
+        return regs;
+}
+
+static int coverage_start_fn(const struct decode_header *h, void *args)
+{
+        struct coverage_table *coverage = (struct coverage_table *)args;
+        enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK;
+        struct coverage_entry *entry = coverage->base + coverage->num_entries;
+
+        if (coverage->num_entries == MAX_COVERAGE_ENTRIES - 1) {
+                pr_err("FAIL: Out of space for test coverage data");
+                return -ENOMEM;
+        }
+
+        ++coverage->num_entries;
+
+        entry->header = h;
+        entry->regs = coverage_start_registers(h);
+        entry->nesting = coverage->nesting;
+        entry->matched = false;
+
+        if (type == DECODE_TYPE_TABLE) {
+                struct decode_table *d = (struct decode_table *)h;
+                int ret;
+                ++coverage->nesting;
+                ret = table_iter(d->table.table, coverage_start_fn, coverage);
+                --coverage->nesting;
+                return ret;
+        }
+
+        return 0;
+}
+
+static int coverage_start(const union decode_item *table)
+{
+        coverage.base = kmalloc(MAX_COVERAGE_ENTRIES *
+                                sizeof(struct coverage_entry), GFP_KERNEL);
+        coverage.num_entries = 0;
+        coverage.nesting = 0;
+        return table_iter(table, coverage_start_fn, &coverage);
+}
+
+static void
+coverage_add_registers(struct coverage_entry *entry, kprobe_opcode_t insn)
+{
+        int regs = entry->header->type_regs.bits >> DECODE_TYPE_BITS;
+        int i;
+        for (i = 0; i < 20; i += 4) {
+                enum decode_reg_type reg_type = (regs >> i) & 0xf;
+                int reg = (insn >> i) & 0xf;
+                int flag;
+
+                if (!reg_type)
+                        continue;
+
+                if (reg == 13)
+                        flag = COVERAGE_SP;
+                else if (reg == 15)
+                        flag = COVERAGE_PC;
+                else
+                        flag = COVERAGE_ANY_REG;
+                entry->regs &= ~(flag << i);
+
+                switch (reg_type) {
+
+                case REG_TYPE_NONE:
+                case REG_TYPE_ANY:
+                case REG_TYPE_SAMEAS16:
+                        break;
+
+                case REG_TYPE_SP:
+                        if (reg != 13)
+                                return;
+                        break;
+
+                case REG_TYPE_PC:
+                        if (reg != 15)
+                                return;
+                        break;
+
+                case REG_TYPE_NOSP:
+                        if (reg == 13)
+                                return;
+                        break;
+
+                case REG_TYPE_NOSPPC:
+                case REG_TYPE_NOSPPCX:
+                        if (reg == 13 || reg == 15)
+                                return;
+                        break;
+
+                case REG_TYPE_NOPCWB:
+                        if (!is_writeback(insn))
+                                break;
+                        if (reg == 15) {
+                                entry->regs &= ~(COVERAGE_PCWB << i);
+                                return;
+                        }
+                        break;
+
+                case REG_TYPE_NOPC:
+                case REG_TYPE_NOPCX:
+                        if (reg == 15)
+                                return;
+                        break;
+                }
+
+        }
+}
+
+static void coverage_add(kprobe_opcode_t insn)
+{
+        struct coverage_entry *entry = coverage.base;
+        struct coverage_entry *end = coverage.base + coverage.num_entries;
+        bool matched = false;
+        unsigned nesting = 0;
+
+        for (; entry < end; ++entry) {
+                const struct decode_header *h = entry->header;
+                enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK;
+
+                if (entry->nesting > nesting)
+                        continue; /* Skip sub-table we didn't match */
+
+                if (entry->nesting < nesting)
+                        break; /* End of sub-table we were scanning */
+
+                if (!matched) {
+                        if ((insn & h->mask.bits) != h->value.bits)
+                                continue;
+                        entry->matched = true;
+                }
+
+                switch (type) {
+
+                case DECODE_TYPE_TABLE:
+                        ++nesting;
+                        break;
+
+                case DECODE_TYPE_CUSTOM:
+                case DECODE_TYPE_SIMULATE:
+                case DECODE_TYPE_EMULATE:
+                        coverage_add_registers(entry, insn);
+                        return;
+
+                case DECODE_TYPE_OR:
+                        matched = true;
+                        break;
+
+                case DECODE_TYPE_REJECT:
+                default:
+                        return;
+                }
+
+        }
+}
+
+static void coverage_end(void)
+{
+        struct coverage_entry *entry = coverage.base;
+        struct coverage_entry *end = coverage.base + coverage.num_entries;
+
+        for (; entry < end; ++entry) {
+                u32 mask = entry->header->mask.bits;
+                u32 value = entry->header->value.bits;
+
+                if (entry->regs) {
+                        pr_err("FAIL: Register test coverage missing for %08x %08x (%05x)\n",
+                                mask, value, entry->regs);
+                        coverage_fail = true;
+                }
+                if (!entry->matched) {
+                        pr_err("FAIL: Test coverage entry missing for %08x %08x\n",
+                                mask, value);
+                        coverage_fail = true;
+                }
+        }
+
+        kfree(coverage.base);
+}
+
+
+/*
+ * Framework for instruction set test cases
+ */
+
+void __naked __kprobes_test_case_start(void)
+{
+        __asm__ __volatile__ (
+                "stmdb  sp!, {r4-r11}                           \n\t"
+                "sub    sp, sp, #"__stringify(TEST_MEMORY_SIZE)"\n\t"
+                "bic    r0, lr, #1  @ r0 = inline title string  \n\t"
+                "mov    r1, sp                                  \n\t"
+                "bl     kprobes_test_case_start                 \n\t"
+                "bx     r0                                      \n\t"
+        );
+}
+
+#ifndef CONFIG_THUMB2_KERNEL
+
+void __naked __kprobes_test_case_end_32(void)
+{
+        __asm__ __volatile__ (
+                "mov    r4, lr                                  \n\t"
+                "bl     kprobes_test_case_end                   \n\t"
+                "cmp    r0, #0                                  \n\t"
+                "movne  pc, r0                                  \n\t"
+                "mov    r0, r4                                  \n\t"
+                "add    sp, sp, #"__stringify(TEST_MEMORY_SIZE)"\n\t"
+                "ldmia  sp!, {r4-r11}                           \n\t"
+                "mov    pc, r0                                  \n\t"
+        );
+}
+
+#else /* CONFIG_THUMB2_KERNEL */
+
+void __naked __kprobes_test_case_end_16(void)
+{
+        __asm__ __volatile__ (
+                "mov    r4, lr                                  \n\t"
+                "bl     kprobes_test_case_end                   \n\t"
+                "cmp    r0, #0                                  \n\t"
+                "bxne   r0                                      \n\t"
+                "mov    r0, r4                                  \n\t"
+                "add    sp, sp, #"__stringify(TEST_MEMORY_SIZE)"\n\t"
+                "ldmia  sp!, {r4-r11}                           \n\t"
+                "bx     r0                                      \n\t"
+        );
+}
+
+void __naked __kprobes_test_case_end_32(void)
+{
+        __asm__ __volatile__ (
+                ".arm                                           \n\t"
+                "orr    lr, lr, #1  @ will return to Thumb code \n\t"
+                "ldr    pc, 1f                                  \n\t"
+                "1:                                             \n\t"
+                ".word  __kprobes_test_case_end_16              \n\t"
+        );
+}
+
+#endif
+
+
+int kprobe_test_flags;
+int kprobe_test_cc_position;
+
+static int test_try_count;
+static int test_pass_count;
+static int test_fail_count;
+
+static struct pt_regs initial_regs;
+static struct pt_regs expected_regs;
+static struct pt_regs result_regs;
+
+static u32 expected_memory[TEST_MEMORY_SIZE/sizeof(u32)];
+
+static const char *current_title;
+static struct test_arg *current_args;
+static u32 *current_stack;
+static uintptr_t current_branch_target;
+
+static uintptr_t current_code_start;
+static kprobe_opcode_t current_instruction;
+
+
+#define TEST_CASE_PASSED -1
+#define TEST_CASE_FAILED -2
+
+static int test_case_run_count;
+static bool test_case_is_thumb;
+static int test_instance;
+
+/*
+ * We ignore the state of the imprecise abort disable flag (CPSR.A) because this
+ * can change randomly as the kernel doesn't take care to preserve or initialise
+ * this across context switches. Also, with Security Extentions, the flag may
+ * not be under control of the kernel; for this reason we ignore the state of
+ * the FIQ disable flag CPSR.F as well.
+ */
+#define PSR_IGNORE_BITS (PSR_A_BIT | PSR_F_BIT)
+
+static unsigned long test_check_cc(int cc, unsigned long cpsr)
+{
+        unsigned long temp;
+
+        switch (cc) {
+        case 0x0: /* eq */
+                return cpsr & PSR_Z_BIT;
+
+        case 0x1: /* ne */
+                return (~cpsr) & PSR_Z_BIT;
+
+        case 0x2: /* cs */
+                return cpsr & PSR_C_BIT;
+
+        case 0x3: /* cc */
+                return (~cpsr) & PSR_C_BIT;
+
+        case 0x4: /* mi */
+                return cpsr & PSR_N_BIT;
+
+        case 0x5: /* pl */
+                return (~cpsr) & PSR_N_BIT;
+
+        case 0x6: /* vs */
+                return cpsr & PSR_V_BIT;
+
+        case 0x7: /* vc */
+                return (~cpsr) & PSR_V_BIT;
+
+        case 0x8: /* hi */
+                cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
+                return cpsr & PSR_C_BIT;
+
+        case 0x9: /* ls */
+                cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
+                return (~cpsr) & PSR_C_BIT;
+
+        case 0xa: /* ge */
+                cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
+                return (~cpsr) & PSR_N_BIT;
+
+        case 0xb: /* lt */
+                cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
+                return cpsr & PSR_N_BIT;
+
+        case 0xc: /* gt */
+                temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
+                temp |= (cpsr << 1);       /* PSR_N_BIT |= PSR_Z_BIT */
+                return (~temp) & PSR_N_BIT;
+
+        case 0xd: /* le */
+                temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
+                temp |= (cpsr << 1);       /* PSR_N_BIT |= PSR_Z_BIT */
+                return temp & PSR_N_BIT;
+
+        case 0xe: /* al */
+        case 0xf: /* unconditional */
+                return true;
+        }
+        BUG();
+        return false;
+}
+
+static int is_last_scenario;
+static int probe_should_run; /* 0 = no, 1 = yes, -1 = unknown */
+static int memory_needs_checking;
+
+static unsigned long test_context_cpsr(int scenario)
+{
+        unsigned long cpsr;
+
+        probe_should_run = 1;
+
+        /* Default case is that we cycle through 16 combinations of flags */
+        cpsr  = (scenario & 0xf) << 28; /* N,Z,C,V flags */
+        cpsr |= (scenario & 0xf) << 16; /* GE flags */
+        cpsr |= (scenario & 0x1) << 27; /* Toggle Q flag */
+
+        if (!test_case_is_thumb) {
+                /* Testing ARM code */
+                probe_should_run = test_check_cc(current_instruction >> 28, cpsr) != 0;
+                if (scenario == 15)
+                        is_last_scenario = true;
+
+        } else if (kprobe_test_flags & TEST_FLAG_NO_ITBLOCK) {
+                /* Testing Thumb code without setting ITSTATE */
+                if (kprobe_test_cc_position) {
+                        int cc = (current_instruction >> kprobe_test_cc_position) & 0xf;
+                        probe_should_run = test_check_cc(cc, cpsr) != 0;
+                }
+
+                if (scenario == 15)
+                        is_last_scenario = true;
+
+        } else if (kprobe_test_flags & TEST_FLAG_FULL_ITBLOCK) {
+                /* Testing Thumb code with all combinations of ITSTATE */
+                unsigned x = (scenario >> 4);
+                unsigned cond_base = x % 7; /* ITSTATE<7:5> */
+                unsigned mask = x / 7 + 2;  /* ITSTATE<4:0>, bits reversed */
+
+                if (mask > 0x1f) {
+                        /* Finish by testing state from instruction 'itt al' */
+                        cond_base = 7;
+                        mask = 0x4;
+                        if ((scenario & 0xf) == 0xf)
+                                is_last_scenario = true;
+                }
+
+                cpsr |= cond_base << 13;        /* ITSTATE<7:5> */
+                cpsr |= (mask & 0x1) << 12;     /* ITSTATE<4> */
+                cpsr |= (mask & 0x2) << 10;     /* ITSTATE<3> */
+                cpsr |= (mask & 0x4) << 8;      /* ITSTATE<2> */
+                cpsr |= (mask & 0x8) << 23;     /* ITSTATE<1> */
+                cpsr |= (mask & 0x10) << 21;    /* ITSTATE<0> */
+
+                probe_should_run = test_check_cc((cpsr >> 12) & 0xf, cpsr) != 0;
+
+        } else {
+                /* Testing Thumb code with several combinations of ITSTATE */
+                switch (scenario) {
+                case 16: /* Clear NZCV flags and 'it eq' state (false as Z=0) */
+                        cpsr = 0x00000800;
+                        probe_should_run = 0;
+                        break;
+                case 17: /* Set NZCV flags and 'it vc' state (false as V=1) */
+                        cpsr = 0xf0007800;
+                        probe_should_run = 0;
+                        break;
+                case 18: /* Clear NZCV flags and 'it ls' state (true as C=0) */
+                        cpsr = 0x00009800;
+                        break;
+                case 19: /* Set NZCV flags and 'it cs' state (true as C=1) */
+                        cpsr = 0xf0002800;
+                        is_last_scenario = true;
+                        break;
+                }
+        }
+
+        return cpsr;
+}
+
+static void setup_test_context(struct pt_regs *regs)
+{
+        int scenario = test_case_run_count>>1;
+        unsigned long val;
+        struct test_arg *args;
+        int i;
+
+        is_last_scenario = false;
+        memory_needs_checking = false;
+
+        /* Initialise test memory on stack */
+        val = (scenario & 1) ? VALM : ~VALM;
+        for (i = 0; i < TEST_MEMORY_SIZE / sizeof(current_stack[0]); ++i)
+                current_stack[i] = val + (i << 8);
+        /* Put target of branch on stack for tests which load PC from memory */
+        if (current_branch_target)
+                current_stack[15] = current_branch_target;
+        /* Put a value for SP on stack for tests which load SP from memory */
+        current_stack[13] = (u32)current_stack + 120;
+
+        /* Initialise register values to their default state */
+        val = (scenario & 2) ? VALR : ~VALR;
+        for (i = 0; i < 13; ++i)
+                regs->uregs[i] = val ^ (i << 8);
+        regs->ARM_lr = val ^ (14 << 8);
+        regs->ARM_cpsr &= ~(APSR_MASK | PSR_IT_MASK);
+        regs->ARM_cpsr |= test_context_cpsr(scenario);
+
+        /* Perform testcase specific register setup  */
+        args = current_args;
+        for (; args[0].type != ARG_TYPE_END; ++args)
+                switch (args[0].type) {
+                case ARG_TYPE_REG: {
+                        struct test_arg_regptr *arg =
+                                (struct test_arg_regptr *)args;
+                        regs->uregs[arg->reg] = arg->val;
+                        break;
+                }
+                case ARG_TYPE_PTR: {
+                        struct test_arg_regptr *arg =
+                                (struct test_arg_regptr *)args;
+                        regs->uregs[arg->reg] =
+                                (unsigned long)current_stack + arg->val;
+                        memory_needs_checking = true;
+                        break;
+                }
+                case ARG_TYPE_MEM: {
+                        struct test_arg_mem *arg = (struct test_arg_mem *)args;
+                        current_stack[arg->index] = arg->val;
+                        break;
+                }
+                default:
+                        break;
+                }
+}
+
+struct test_probe {
+        struct kprobe   kprobe;
+        bool            registered;
+        int             hit;
+};
+
+static void unregister_test_probe(struct test_probe *probe)
+{
+        if (probe->registered) {
+                unregister_kprobe(&probe->kprobe);
+                probe->kprobe.flags = 0; /* Clear disable flag to allow reuse */
+        }
+        probe->registered = false;
+}
+
+static int register_test_probe(struct test_probe *probe)
+{
+        int ret;
+
+        if (probe->registered)
+                BUG();
+
+        ret = register_kprobe(&probe->kprobe);
+        if (ret >= 0) {
+                probe->registered = true;
+                probe->hit = -1;
+        }
+        return ret;
+}
+
+static int __kprobes
+test_before_pre_handler(struct kprobe *p, struct pt_regs *regs)
+{
+        container_of(p, struct test_probe, kprobe)->hit = test_instance;
+        return 0;
+}
+
+static void __kprobes
+test_before_post_handler(struct kprobe *p, struct pt_regs *regs,
+                                                        unsigned long flags)
+{
+        setup_test_context(regs);
+        initial_regs = *regs;
+        initial_regs.ARM_cpsr &= ~PSR_IGNORE_BITS;
+}
+
+static int __kprobes
+test_case_pre_handler(struct kprobe *p, struct pt_regs *regs)
+{
+        container_of(p, struct test_probe, kprobe)->hit = test_instance;
+        return 0;
+}
+
+static int __kprobes
+test_after_pre_handler(struct kprobe *p, struct pt_regs *regs)
+{
+        if (container_of(p, struct test_probe, kprobe)->hit == test_instance)
+                return 0; /* Already run for this test instance */
+
+        result_regs = *regs;
+        result_regs.ARM_cpsr &= ~PSR_IGNORE_BITS;
+
+        /* Undo any changes done to SP by the test case */
+        regs->ARM_sp = (unsigned long)current_stack;
+
+        container_of(p, struct test_probe, kprobe)->hit = test_instance;
+        return 0;
+}
+
+static struct test_probe test_before_probe = {
+        .kprobe.pre_handler     = test_before_pre_handler,
+        .kprobe.post_handler    = test_before_post_handler,
+};
+
+static struct test_probe test_case_probe = {
+        .kprobe.pre_handler     = test_case_pre_handler,
+};
+
+static struct test_probe test_after_probe = {
+        .kprobe.pre_handler     = test_after_pre_handler,
+};
+
+static struct test_probe test_after2_probe = {
+        .kprobe.pre_handler     = test_after_pre_handler,
+};
+
+static void test_case_cleanup(void)
+{
+        unregister_test_probe(&test_before_probe);
+        unregister_test_probe(&test_case_probe);
+        unregister_test_probe(&test_after_probe);
+        unregister_test_probe(&test_after2_probe);
+}
+
+static void print_registers(struct pt_regs *regs)
+{
+        pr_err("r0  %08lx | r1  %08lx | r2  %08lx | r3  %08lx\n",
+                regs->ARM_r0, regs->ARM_r1, regs->ARM_r2, regs->ARM_r3);
+        pr_err("r4  %08lx | r5  %08lx | r6  %08lx | r7  %08lx\n",
+                regs->ARM_r4, regs->ARM_r5, regs->ARM_r6, regs->ARM_r7);
+        pr_err("r8  %08lx | r9  %08lx | r10 %08lx | r11 %08lx\n",
+                regs->ARM_r8, regs->ARM_r9, regs->ARM_r10, regs->ARM_fp);
+        pr_err("r12 %08lx | sp  %08lx | lr  %08lx | pc  %08lx\n",
+                regs->ARM_ip, regs->ARM_sp, regs->ARM_lr, regs->ARM_pc);
+        pr_err("cpsr %08lx\n", regs->ARM_cpsr);
+}
+
+static void print_memory(u32 *mem, size_t size)
+{
+        int i;
+        for (i = 0; i < size / sizeof(u32); i += 4)
+                pr_err("%08x %08x %08x %08x\n", mem[i], mem[i+1],
+                                                mem[i+2], mem[i+3]);
+}
+
+static size_t expected_memory_size(u32 *sp)
+{
+        size_t size = sizeof(expected_memory);
+        int offset = (uintptr_t)sp - (uintptr_t)current_stack;
+        if (offset > 0)
+                size -= offset;
+        return size;
+}
+
+static void test_case_failed(const char *message)
+{
+        test_case_cleanup();
+
+        pr_err("FAIL: %s\n", message);
+        pr_err("FAIL: Test %s\n", current_title);
+        pr_err("FAIL: Scenario %d\n", test_case_run_count >> 1);
+}
+
+static unsigned long next_instruction(unsigned long pc)
+{
+#ifdef CONFIG_THUMB2_KERNEL
+        if ((pc & 1) && !is_wide_instruction(*(u16 *)(pc - 1)))
+                return pc + 2;
+        else
+#endif
+        return pc + 4;
+}
+
+static uintptr_t __used kprobes_test_case_start(const char *title, void *stack)
+{
+        struct test_arg *args;
+        struct test_arg_end *end_arg;
+        unsigned long test_code;
+
+        args = (struct test_arg *)PTR_ALIGN(title + strlen(title) + 1, 4);
+
+        current_title = title;
+        current_args = args;
+        current_stack = stack;
+
+        ++test_try_count;
+
+        while (args->type != ARG_TYPE_END)
+                ++args;
+        end_arg = (struct test_arg_end *)args;
+
+        test_code = (unsigned long)(args + 1); /* Code starts after args */
+
+        test_case_is_thumb = end_arg->flags & ARG_FLAG_THUMB;
+        if (test_case_is_thumb)
+                test_code |= 1;
+
+        current_code_start = test_code;
+
+        current_branch_target = 0;
+        if (end_arg->branch_offset != end_arg->end_offset)
+                current_branch_target = test_code + end_arg->branch_offset;
+
+        test_code += end_arg->code_offset;
+        test_before_probe.kprobe.addr = (kprobe_opcode_t *)test_code;
+
+        test_code = next_instruction(test_code);
+        test_case_probe.kprobe.addr = (kprobe_opcode_t *)test_code;
+
+        if (test_case_is_thumb) {
+                u16 *p = (u16 *)(test_code & ~1);
+                current_instruction = p[0];
+                if (is_wide_instruction(current_instruction)) {
+                        current_instruction <<= 16;
+                        current_instruction |= p[1];
+                }
+        } else {
+                current_instruction = *(u32 *)test_code;
+        }
+
+        if (current_title[0] == '.')
+                verbose("%s\n", current_title);
+        else
+                verbose("%s\t@ %0*x\n", current_title,
+                                        test_case_is_thumb ? 4 : 8,
+                                        current_instruction);
+
+        test_code = next_instruction(test_code);
+        test_after_probe.kprobe.addr = (kprobe_opcode_t *)test_code;
+
+        if (kprobe_test_flags & TEST_FLAG_NARROW_INSTR) {
+                if (!test_case_is_thumb ||
+                        is_wide_instruction(current_instruction)) {
+                                test_case_failed("expected 16-bit instruction");
+                                goto fail;
+                }
+        } else {
+                if (test_case_is_thumb &&
+                        !is_wide_instruction(current_instruction)) {
+                                test_case_failed("expected 32-bit instruction");
+                                goto fail;
+                }
+        }
+
+        coverage_add(current_instruction);
+
+        if (end_arg->flags & ARG_FLAG_UNSUPPORTED) {
+                if (register_test_probe(&test_case_probe) < 0)
+                        goto pass;
+                test_case_failed("registered probe for unsupported instruction");
+                goto fail;
+        }
+
+        if (end_arg->flags & ARG_FLAG_SUPPORTED) {
+                if (register_test_probe(&test_case_probe) >= 0)
+                        goto pass;
+                test_case_failed("couldn't register probe for supported instruction");
+                goto fail;
+        }
+
+        if (register_test_probe(&test_before_probe) < 0) {
+                test_case_failed("register test_before_probe failed");
+                goto fail;
+        }
+        if (register_test_probe(&test_after_probe) < 0) {
+                test_case_failed("register test_after_probe failed");
+                goto fail;
+        }
+        if (current_branch_target) {
+                test_after2_probe.kprobe.addr =
+                                (kprobe_opcode_t *)current_branch_target;
+                if (register_test_probe(&test_after2_probe) < 0) {
+                        test_case_failed("register test_after2_probe failed");
+                        goto fail;
+                }
+        }
+
+        /* Start first run of test case */
+        test_case_run_count = 0;
+        ++test_instance;
+        return current_code_start;
+pass:
+        test_case_run_count = TEST_CASE_PASSED;
+        return (uintptr_t)test_after_probe.kprobe.addr;
+fail:
+        test_case_run_count = TEST_CASE_FAILED;
+        return (uintptr_t)test_after_probe.kprobe.addr;
+}
+
+static bool check_test_results(void)
+{
+        size_t mem_size = 0;
+        u32 *mem = 0;
+
+        if (memcmp(&expected_regs, &result_regs, sizeof(expected_regs))) {
+                test_case_failed("registers differ");
+                goto fail;
+        }
+
+        if (memory_needs_checking) {
+                mem = (u32 *)result_regs.ARM_sp;
+                mem_size = expected_memory_size(mem);
+                if (memcmp(expected_memory, mem, mem_size)) {
+                        test_case_failed("test memory differs");
+                        goto fail;
+                }
+        }
+
+        return true;
+
+fail:
+        pr_err("initial_regs:\n");
+        print_registers(&initial_regs);
+        pr_err("expected_regs:\n");
+        print_registers(&expected_regs);
+        pr_err("result_regs:\n");
+        print_registers(&result_regs);
+
+        if (mem) {
+                pr_err("current_stack=%p\n", current_stack);
+                pr_err("expected_memory:\n");
+                print_memory(expected_memory, mem_size);
+                pr_err("result_memory:\n");
+                print_memory(mem, mem_size);
+        }
+
+        return false;
+}
+
+static uintptr_t __used kprobes_test_case_end(void)
+{
+        if (test_case_run_count < 0) {
+                if (test_case_run_count == TEST_CASE_PASSED)
+                        /* kprobes_test_case_start did all the needed testing */
+                        goto pass;
+                else
+                        /* kprobes_test_case_start failed */
+                        goto fail;
+        }
+
+        if (test_before_probe.hit != test_instance) {
+                test_case_failed("test_before_handler not run");
+                goto fail;
+        }
+
+        if (test_after_probe.hit != test_instance &&
+                                test_after2_probe.hit != test_instance) {
+                test_case_failed("test_after_handler not run");
+                goto fail;
+        }
+
+        /*
+         * Even numbered test runs ran without a probe on the test case so
+         * we can gather reference results. The subsequent odd numbered run
+         * will have the probe inserted.
+        */
+        if ((test_case_run_count & 1) == 0) {
+                /* Save results from run without probe */
+                u32 *mem = (u32 *)result_regs.ARM_sp;
+                expected_regs = result_regs;
+                memcpy(expected_memory, mem, expected_memory_size(mem));
+
+                /* Insert probe onto test case instruction */
+                if (register_test_probe(&test_case_probe) < 0) {
+                        test_case_failed("register test_case_probe failed");
+                        goto fail;
+                }
+        } else {
+                /* Check probe ran as expected */
+                if (probe_should_run == 1) {
+                        if (test_case_probe.hit != test_instance) {
+                                test_case_failed("test_case_handler not run");
+                                goto fail;
+                        }
+                } else if (probe_should_run == 0) {
+                        if (test_case_probe.hit == test_instance) {
+                                test_case_failed("test_case_handler ran");
+                                goto fail;
+                        }
+                }
+
+                /* Remove probe for any subsequent reference run */
+                unregister_test_probe(&test_case_probe);
+
+                if (!check_test_results())
+                        goto fail;
+
+                if (is_last_scenario)
+                        goto pass;
+        }
+
+        /* Do next test run */
+        ++test_case_run_count;
+        ++test_instance;
+        return current_code_start;
+fail:
+        ++test_fail_count;
+        goto end;
+pass:
+        ++test_pass_count;
+end:
+        test_case_cleanup();
+        return 0;
+}
+
+
+/*
+ * Top level test functions
+ */
+
+static int run_test_cases(void (*tests)(void), const union decode_item *table)
+{
+        int ret;
+
+        pr_info("    Check decoding tables\n");
+        ret = table_test(table);
+        if (ret)
+                return ret;
+
+        pr_info("    Run test cases\n");
+        ret = coverage_start(table);
+        if (ret)
+                return ret;
+
+        tests();
+
+        coverage_end();
+        return 0;
+}
+
+
+static int __init run_all_tests(void)
+{
+        int ret = 0;
+
+        pr_info("Begining kprobe tests...\n");
+
+#ifndef CONFIG_THUMB2_KERNEL
+
+        pr_info("Probe ARM code\n");
+        ret = run_api_tests(arm_func);
+        if (ret)
+                goto out;
+
+        pr_info("ARM instruction simulation\n");
+        ret = run_test_cases(kprobe_arm_test_cases, kprobe_decode_arm_table);
+        if (ret)
+                goto out;
+
+#else /* CONFIG_THUMB2_KERNEL */
+
+        pr_info("Probe 16-bit Thumb code\n");
+        ret = run_api_tests(thumb16_func);
+        if (ret)
+                goto out;
+
+        pr_info("Probe 32-bit Thumb code, even halfword\n");
+        ret = run_api_tests(thumb32even_func);
+        if (ret)
+                goto out;
+
+        pr_info("Probe 32-bit Thumb code, odd halfword\n");
+        ret = run_api_tests(thumb32odd_func);
+        if (ret)
+                goto out;
+
+        pr_info("16-bit Thumb instruction simulation\n");
+        ret = run_test_cases(kprobe_thumb16_test_cases,
+                                kprobe_decode_thumb16_table);
+        if (ret)
+                goto out;
+
+        pr_info("32-bit Thumb instruction simulation\n");
+        ret = run_test_cases(kprobe_thumb32_test_cases,
+                                kprobe_decode_thumb32_table);
+        if (ret)
+                goto out;
+#endif
+
+        pr_info("Total instruction simulation tests=%d, pass=%d fail=%d\n",
+                test_try_count, test_pass_count, test_fail_count);
+        if (test_fail_count) {
+                ret = -EINVAL;
+                goto out;
+        }
+
+#if BENCHMARKING
+        pr_info("Benchmarks\n");
+        ret = run_benchmarks();
+        if (ret)
+                goto out;
+#endif
+
+#if __LINUX_ARM_ARCH__ >= 7
+        /* We are able to run all test cases so coverage should be complete */
+        if (coverage_fail) {
+                pr_err("FAIL: Test coverage checks failed\n");
+                ret = -EINVAL;
+                goto out;
+        }
+#endif
+
+out:
+        if (ret == 0)
+                pr_info("Finished kprobe tests OK\n");
+        else
+                pr_err("kprobe tests failed\n");
+
+        return ret;
+}
+
+
+/*
+ * Module setup
+ */
+
+#ifdef MODULE
+
+static void __exit kprobe_test_exit(void)
+{
+}
+
+module_init(run_all_tests)
+module_exit(kprobe_test_exit)
+MODULE_LICENSE("GPL");
+
+#else /* !MODULE */
+
+late_initcall(run_all_tests);
+
+#endif
diff --git a/arch/arm/kernel/kprobes-test.h b/arch/arm/kernel/kprobes-test.h
new file mode 100644
index 000000000000..0dc5d77b9356
--- /dev/null
+++ b/arch/arm/kernel/kprobes-test.h
@@ -0,0 +1,392 @@
+/*
+ * arch/arm/kernel/kprobes-test.h
+ *
+ * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define VERBOSE 0 /* Set to '1' for more logging of test cases */
+
+#ifdef CONFIG_THUMB2_KERNEL
+#define NORMAL_ISA "16"
+#else
+#define NORMAL_ISA "32"
+#endif
+
+
+/* Flags used in kprobe_test_flags */
+#define TEST_FLAG_NO_ITBLOCK    (1<<0)
+#define TEST_FLAG_FULL_ITBLOCK  (1<<1)
+#define TEST_FLAG_NARROW_INSTR  (1<<2)
+
+extern int kprobe_test_flags;
+extern int kprobe_test_cc_position;
+
+
+#define TEST_MEMORY_SIZE 256
+
+
+/*
+ * Test case structures.
+ *
+ * The arguments given to test cases can be one of three types.
+ *
+ *   ARG_TYPE_REG
+ *      Load a register with the given value.
+ *
+ *   ARG_TYPE_PTR
+ *      Load a register with a pointer into the stack buffer (SP + given value).
+ *
+ *   ARG_TYPE_MEM
+ *      Store the given value into the stack buffer at [SP+index].
+ *
+ */
+
+#define ARG_TYPE_END    0
+#define ARG_TYPE_REG    1
+#define ARG_TYPE_PTR    2
+#define ARG_TYPE_MEM    3
+
+#define ARG_FLAG_UNSUPPORTED    0x01
+#define ARG_FLAG_SUPPORTED      0x02
+#define ARG_FLAG_THUMB          0x10    /* Must be 16 so TEST_ISA can be used */
+#define ARG_FLAG_ARM            0x20    /* Must be 32 so TEST_ISA can be used */
+
+struct test_arg {
+        u8      type;           /* ARG_TYPE_x */
+        u8      _padding[7];
+};
+
+struct test_arg_regptr {
+        u8      type;           /* ARG_TYPE_REG or ARG_TYPE_PTR */
+        u8      reg;
+        u8      _padding[2];
+        u32     val;
+};
+
+struct test_arg_mem {
+        u8      type;           /* ARG_TYPE_MEM */
+        u8      index;
+        u8      _padding[2];
+        u32     val;
+};
+
+struct test_arg_end {
+        u8      type;           /* ARG_TYPE_END */
+        u8      flags;          /* ARG_FLAG_x */
+        u16     code_offset;
+        u16     branch_offset;
+        u16     end_offset;
+};
+
+
+/*
+ * Building blocks for test cases.
+ *
+ * Each test case is wrapped between TESTCASE_START and TESTCASE_END.
+ *
+ * To specify arguments for a test case the TEST_ARG_{REG,PTR,MEM} macros are
+ * used followed by a terminating TEST_ARG_END.
+ *
+ * After this, the instruction to be tested is defined with TEST_INSTRUCTION.
+ * Or for branches, TEST_BRANCH_B and TEST_BRANCH_F (branch forwards/backwards).
+ *
+ * Some specific test cases may make use of other custom constructs.
+ */
+
+#if VERBOSE
+#define verbose(fmt, ...) pr_info(fmt, ##__VA_ARGS__)
+#else
+#define verbose(fmt, ...)
+#endif
+
+#define TEST_GROUP(title)                                       \
+        verbose("\n");                                          \
+        verbose(title"\n");                                     \
+        verbose("---------------------------------------------------------\n");
+
+#define TESTCASE_START(title)                                   \
+        __asm__ __volatile__ (                                  \
+        "bl     __kprobes_test_case_start               \n\t"   \
+        /* don't use .asciz here as 'title' may be */           \
+        /* multiple strings to be concatenated.  */             \
+        ".ascii "#title"                                \n\t"   \
+        ".byte  0                                       \n\t"   \
+        ".align 2                                       \n\t"
+
+#define TEST_ARG_REG(reg, val)                                  \
+        ".byte  "__stringify(ARG_TYPE_REG)"             \n\t"   \
+        ".byte  "#reg"                                  \n\t"   \
+        ".short 0                                       \n\t"   \
+        ".word  "#val"                                  \n\t"
+
+#define TEST_ARG_PTR(reg, val)                                  \
+        ".byte  "__stringify(ARG_TYPE_PTR)"             \n\t"   \
+        ".byte  "#reg"                                  \n\t"   \
+        ".short 0                                       \n\t"   \
+        ".word  "#val"                                  \n\t"
+
+#define TEST_ARG_MEM(index, val)                                \
+        ".byte  "__stringify(ARG_TYPE_MEM)"             \n\t"   \
+        ".byte  "#index"                                \n\t"   \
+        ".short 0                                       \n\t"   \
+        ".word  "#val"                                  \n\t"
+
+#define TEST_ARG_END(flags)                                     \
+        ".byte  "__stringify(ARG_TYPE_END)"             \n\t"   \
+        ".byte  "TEST_ISA flags"                        \n\t"   \
+        ".short 50f-0f                                  \n\t"   \
+        ".short 2f-0f                                   \n\t"   \
+        ".short 99f-0f                                  \n\t"   \
+        ".code "TEST_ISA"                               \n\t"   \
+        "0:                                             \n\t"
+
+#define TEST_INSTRUCTION(instruction)                           \
+        "50:    nop                                     \n\t"   \
+        "1:     "instruction"                           \n\t"   \
+        "       nop                                     \n\t"
+
+#define TEST_BRANCH_F(instruction, xtra_dist)                   \
+        TEST_INSTRUCTION(instruction)                           \
+        ".if "#xtra_dist"                               \n\t"   \
+        "       b       99f                             \n\t"   \
+        ".space "#xtra_dist"                            \n\t"   \
+        ".endif                                         \n\t"   \
+        "       b       99f                             \n\t"   \
+        "2:     nop                                     \n\t"
+
+#define TEST_BRANCH_B(instruction, xtra_dist)                   \
+        "       b       50f                             \n\t"   \
+        "       b       99f                             \n\t"   \
+        "2:     nop                                     \n\t"   \
+        "       b       99f                             \n\t"   \
+        ".if "#xtra_dist"                               \n\t"   \
+        ".space "#xtra_dist"                            \n\t"   \
+        ".endif                                         \n\t"   \
+        TEST_INSTRUCTION(instruction)
+
+#define TESTCASE_END                                            \
+        "2:                                             \n\t"   \
+        "99:                                            \n\t"   \
+        "       bl __kprobes_test_case_end_"TEST_ISA"   \n\t"   \
+        ".code "NORMAL_ISA"                             \n\t"   \
+        : :                                                     \
+        : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"    \
+        );
+
+
+/*
+ * Macros to define test cases.
+ *
+ * Those of the form TEST_{R,P,M}* can be used to define test cases
+ * which take combinations of the three basic types of arguments. E.g.
+ *
+ *   TEST_R     One register argument
+ *   TEST_RR    Two register arguments
+ *   TEST_RPR   A register, a pointer, then a register argument
+ *
+ * For testing instructions which may branch, there are macros TEST_BF_*
+ * and TEST_BB_* for branching forwards and backwards.
+ *
+ * TEST_SUPPORTED and TEST_UNSUPPORTED don't cause the code to be executed,
+ * the just verify that a kprobe is or is not allowed on the given instruction.
+ */
+
+#define TEST(code)                              \
+        TESTCASE_START(code)                    \
+        TEST_ARG_END("")                        \
+        TEST_INSTRUCTION(code)                  \
+        TESTCASE_END
+
+#define TEST_UNSUPPORTED(code)                                  \
+        TESTCASE_START(code)                                    \
+        TEST_ARG_END("|"__stringify(ARG_FLAG_UNSUPPORTED))      \
+        TEST_INSTRUCTION(code)                                  \
+        TESTCASE_END
+
+#define TEST_SUPPORTED(code)                                    \
+        TESTCASE_START(code)                                    \
+        TEST_ARG_END("|"__stringify(ARG_FLAG_SUPPORTED))        \
+        TEST_INSTRUCTION(code)                                  \
+        TESTCASE_END
+
+#define TEST_R(code1, reg, val, code2)                  \
+        TESTCASE_START(code1 #reg code2)                \
+        TEST_ARG_REG(reg, val)                          \
+        TEST_ARG_END("")                                \
+        TEST_INSTRUCTION(code1 #reg code2)              \
+        TESTCASE_END
+
+#define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3)    \
+        TESTCASE_START(code1 #reg1 code2 #reg2 code3)           \
+        TEST_ARG_REG(reg1, val1)                                \
+        TEST_ARG_REG(reg2, val2)                                \
+        TEST_ARG_END("")                                        \
+        TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3)         \
+        TESTCASE_END
+
+#define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\
+        TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4)               \
+        TEST_ARG_REG(reg1, val1)                                                \
+        TEST_ARG_REG(reg2, val2)                                                \
+        TEST_ARG_REG(reg3, val3)                                                \
+        TEST_ARG_END("")                                                        \
+        TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4)             \
+        TESTCASE_END
+
+#define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4)   \
+        TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4)         \
+        TEST_ARG_REG(reg1, val1)                                                \
+        TEST_ARG_REG(reg2, val2)                                                \
+        TEST_ARG_REG(reg3, val3)                                                \
+        TEST_ARG_REG(reg4, val4)                                                \
+        TEST_ARG_END("")                                                        \
+        TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4)       \
+        TESTCASE_END
+
+#define TEST_P(code1, reg1, val1, code2)        \
+        TESTCASE_START(code1 #reg1 code2)       \
+        TEST_ARG_PTR(reg1, val1)                \
+        TEST_ARG_END("")                        \
+        TEST_INSTRUCTION(code1 #reg1 code2)     \
+        TESTCASE_END
+
+#define TEST_PR(code1, reg1, val1, code2, reg2, val2, code3)    \
+        TESTCASE_START(code1 #reg1 code2 #reg2 code3)           \
+        TEST_ARG_PTR(reg1, val1)                                \
+        TEST_ARG_REG(reg2, val2)                                \
+        TEST_ARG_END("")                                        \
+        TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3)         \
+        TESTCASE_END
+
+#define TEST_RP(code1, reg1, val1, code2, reg2, val2, code3)    \
+        TESTCASE_START(code1 #reg1 code2 #reg2 code3)           \
+        TEST_ARG_REG(reg1, val1)                                \
+        TEST_ARG_PTR(reg2, val2)                                \
+        TEST_ARG_END("")                                        \
+        TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3)         \
+        TESTCASE_END
+
+#define TEST_PRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\
+        TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4)               \
+        TEST_ARG_PTR(reg1, val1)                                                \
+        TEST_ARG_REG(reg2, val2)                                                \
+        TEST_ARG_REG(reg3, val3)                                                \
+        TEST_ARG_END("")                                                        \
+        TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4)             \
+        TESTCASE_END
+
+#define TEST_RPR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\
+        TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4)               \
+        TEST_ARG_REG(reg1, val1)                                                \
+        TEST_ARG_PTR(reg2, val2)                                                \
+        TEST_ARG_REG(reg3, val3)                                                \
+        TEST_ARG_END("")                                                        \
+        TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4)             \
+        TESTCASE_END
+
+#define TEST_RRP(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\
+        TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4)               \
+        TEST_ARG_REG(reg1, val1)                                                \
+        TEST_ARG_REG(reg2, val2)                                                \
+        TEST_ARG_PTR(reg3, val3)                                                \
+        TEST_ARG_END("")                                                        \
+        TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4)             \
+        TESTCASE_END
+
+#define TEST_BF_P(code1, reg1, val1, code2)     \
+        TESTCASE_START(code1 #reg1 code2)       \
+        TEST_ARG_PTR(reg1, val1)                \
+        TEST_ARG_END("")                        \
+        TEST_BRANCH_F(code1 #reg1 code2, 0)     \
+        TESTCASE_END
+
+#define TEST_BF_X(code, xtra_dist)              \
+        TESTCASE_START(code)                    \
+        TEST_ARG_END("")                        \
+        TEST_BRANCH_F(code, xtra_dist)          \
+        TESTCASE_END
+
+#define TEST_BB_X(code, xtra_dist)              \
+        TESTCASE_START(code)                    \
+        TEST_ARG_END("")                        \
+        TEST_BRANCH_B(code, xtra_dist)          \
+        TESTCASE_END
+
+#define TEST_BF_RX(code1, reg, val, code2, xtra_dist)   \
+        TESTCASE_START(code1 #reg code2)                \
+        TEST_ARG_REG(reg, val)                          \
+        TEST_ARG_END("")                                \
+        TEST_BRANCH_F(code1 #reg code2, xtra_dist)      \
+        TESTCASE_END
+
+#define TEST_BB_RX(code1, reg, val, code2, xtra_dist)   \
+        TESTCASE_START(code1 #reg code2)                \
+        TEST_ARG_REG(reg, val)                          \
+        TEST_ARG_END("")                                \
+        TEST_BRANCH_B(code1 #reg code2, xtra_dist)      \
+        TESTCASE_END
+
+#define TEST_BF(code)   TEST_BF_X(code, 0)
+#define TEST_BB(code)   TEST_BB_X(code, 0)
+
+#define TEST_BF_R(code1, reg, val, code2) TEST_BF_RX(code1, reg, val, code2, 0)
+#define TEST_BB_R(code1, reg, val, code2) TEST_BB_RX(code1, reg, val, code2, 0)
+
+#define TEST_BF_RR(code1, reg1, val1, code2, reg2, val2, code3) \
+        TESTCASE_START(code1 #reg1 code2 #reg2 code3)           \
+        TEST_ARG_REG(reg1, val1)                                \
+        TEST_ARG_REG(reg2, val2)                                \
+        TEST_ARG_END("")                                        \
+        TEST_BRANCH_F(code1 #reg1 code2 #reg2 code3, 0)         \
+        TESTCASE_END
+
+#define TEST_X(code, codex)                     \
+        TESTCASE_START(code)                    \
+        TEST_ARG_END("")                        \
+        TEST_INSTRUCTION(code)                  \
+        "       b       99f             \n\t"   \
+        "       "codex"                 \n\t"   \
+        TESTCASE_END
+
+#define TEST_RX(code1, reg, val, code2, codex)          \
+        TESTCASE_START(code1 #reg code2)                \
+        TEST_ARG_REG(reg, val)                          \
+        TEST_ARG_END("")                                \
+        TEST_INSTRUCTION(code1 __stringify(reg) code2)  \
+        "       b       99f             \n\t"           \
+        "       "codex"                 \n\t"           \
+        TESTCASE_END
+
+#define TEST_RRX(code1, reg1, val1, code2, reg2, val2, code3, codex)            \
+        TESTCASE_START(code1 #reg1 code2 #reg2 code3)                           \
+        TEST_ARG_REG(reg1, val1)                                                \
+        TEST_ARG_REG(reg2, val2)                                                \
+        TEST_ARG_END("")                                                        \
+        TEST_INSTRUCTION(code1 __stringify(reg1) code2 __stringify(reg2) code3) \
+        "       b       99f             \n\t"                                   \
+        "       "codex"                 \n\t"                                   \
+        TESTCASE_END
+
+
+/* Various values used in test cases... */
+#define N(val)  (val ^ 0xffffffff)
+#define VAL1    0x12345678
+#define VAL2    N(VAL1)
+#define VAL3    0xa5f801
+#define VAL4    N(VAL3)
+#define VALM    0x456789ab
+#define VALR    0xdeaddead
+#define HH1     0x0123fecb
+#define HH2     0xa9874567
+
+
+#ifdef CONFIG_THUMB2_KERNEL
+void kprobe_thumb16_test_cases(void);
+void kprobe_thumb32_test_cases(void);
+#else
+void kprobe_arm_test_cases(void);
+#endif
diff --git a/arch/arm/kernel/kprobes-thumb.c b/arch/arm/kernel/kprobes-thumb.c
index 902ca59e8b11..8f96ec778e8d 100644
--- a/arch/arm/kernel/kprobes-thumb.c
+++ b/arch/arm/kernel/kprobes-thumb.c
@@ -10,6 +10,7 @@
 
 #include <linux/kernel.h>
 #include <linux/kprobes.h>
+#include <linux/module.h>
 
 #include "kprobes.h"
 
@@ -943,6 +944,9 @@ const union decode_item kprobe_decode_thumb32_table[] = {
          */
         DECODE_END
 };
+#ifdef CONFIG_ARM_KPROBES_TEST_MODULE
+EXPORT_SYMBOL_GPL(kprobe_decode_thumb32_table);
+#endif
 
 static void __kprobes
 t16_simulate_bxblx(struct kprobe *p, struct pt_regs *regs)
@@ -1423,6 +1427,9 @@ const union decode_item kprobe_decode_thumb16_table[] = {
 
         DECODE_END
 };
+#ifdef CONFIG_ARM_KPROBES_TEST_MODULE
+EXPORT_SYMBOL_GPL(kprobe_decode_thumb16_table);
+#endif
 
 static unsigned long __kprobes thumb_check_cc(unsigned long cpsr)
 {
diff --git a/arch/arm/kernel/kprobes.h b/arch/arm/kernel/kprobes.h
index a6aeda0a6c7f..38945f78f9f1 100644
--- a/arch/arm/kernel/kprobes.h
+++ b/arch/arm/kernel/kprobes.h
@@ -413,6 +413,14 @@ struct decode_reject {
         DECODE_HEADER(DECODE_TYPE_REJECT, _mask, _value, 0)
 
 
+#ifdef CONFIG_THUMB2_KERNEL
+extern const union decode_item kprobe_decode_thumb16_table[];
+extern const union decode_item kprobe_decode_thumb32_table[];
+#else
+extern const union decode_item kprobe_decode_arm_table[];
+#endif
+
+
 int kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
                         const union decode_item *table, bool thumb16);
 
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 53c9c2610cbc..e6e5d7c84f1a 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -12,6 +12,7 @@
  */
 #define pr_fmt(fmt) "hw perfevents: " fmt
 
+#include <linux/bitmap.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
@@ -26,16 +27,8 @@
 #include <asm/pmu.h>
 #include <asm/stacktrace.h>
 
-static struct platform_device *pmu_device;
-
-/*
- * Hardware lock to serialize accesses to PMU registers. Needed for the
- * read/modify/write sequences.
- */
-static DEFINE_RAW_SPINLOCK(pmu_lock);
-
 /*
- * ARMv6 supports a maximum of 3 events, starting from index 1. If we add
+ * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
  * another platform that supports more, we need to increase this to be the
  * largest of all platforms.
  *
@@ -43,62 +36,24 @@ static DEFINE_RAW_SPINLOCK(pmu_lock);
  *  cycle counter CCNT + 31 events counters CNT0..30.
  *  Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
  */
-#define ARMPMU_MAX_HWEVENTS             33
+#define ARMPMU_MAX_HWEVENTS             32
 
-/* The events for a given CPU. */
-struct cpu_hw_events {
-        /*
-         * The events that are active on the CPU for the given index. Index 0
-         * is reserved.
-         */
-        struct perf_event       *events[ARMPMU_MAX_HWEVENTS];
-
-        /*
-         * A 1 bit for an index indicates that the counter is being used for
-         * an event. A 0 means that the counter can be used.
-         */
-        unsigned long           used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
+static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
+static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
+static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
 
-        /*
-         * A 1 bit for an index indicates that the counter is actively being
-         * used.
-         */
-        unsigned long           active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
-};
-static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
-
-struct arm_pmu {
-        enum arm_perf_pmu_ids id;
-        const char      *name;
-        irqreturn_t     (*handle_irq)(int irq_num, void *dev);
-        void            (*enable)(struct hw_perf_event *evt, int idx);
-        void            (*disable)(struct hw_perf_event *evt, int idx);
-        int             (*get_event_idx)(struct cpu_hw_events *cpuc,
-                                         struct hw_perf_event *hwc);
-        u32             (*read_counter)(int idx);
-        void            (*write_counter)(int idx, u32 val);
-        void            (*start)(void);
-        void            (*stop)(void);
-        void            (*reset)(void *);
-        const unsigned  (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
-                                    [PERF_COUNT_HW_CACHE_OP_MAX]
-                                    [PERF_COUNT_HW_CACHE_RESULT_MAX];
-        const unsigned  (*event_map)[PERF_COUNT_HW_MAX];
-        u32             raw_event_mask;
-        int             num_events;
-        u64             max_period;
-};
+#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
 
 /* Set at runtime when we know what CPU type we are. */
-static const struct arm_pmu *armpmu;
+static struct arm_pmu *cpu_pmu;
 
 enum arm_perf_pmu_ids
 armpmu_get_pmu_id(void)
 {
         int id = -ENODEV;
 
-        if (armpmu != NULL)
-                id = armpmu->id;
+        if (cpu_pmu != NULL)
+                id = cpu_pmu->id;
 
         return id;
 }
@@ -109,8 +64,8 @@ armpmu_get_max_events(void)
 {
         int max_events = 0;
 
-        if (armpmu != NULL)
-                max_events = armpmu->num_events;
+        if (cpu_pmu != NULL)
+                max_events = cpu_pmu->num_events;
 
         return max_events;
 }
@@ -130,7 +85,11 @@ EXPORT_SYMBOL_GPL(perf_num_counters);
 #define CACHE_OP_UNSUPPORTED            0xFFFF
 
 static int
-armpmu_map_cache_event(u64 config)
+armpmu_map_cache_event(const unsigned (*cache_map)
+                                      [PERF_COUNT_HW_CACHE_MAX]
+                                      [PERF_COUNT_HW_CACHE_OP_MAX]
+                                      [PERF_COUNT_HW_CACHE_RESULT_MAX],
+                       u64 config)
 {
         unsigned int cache_type, cache_op, cache_result, ret;
 
@@ -146,7 +105,7 @@ armpmu_map_cache_event(u64 config)
         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
                 return -EINVAL;
 
-        ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result];
+        ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
 
         if (ret == CACHE_OP_UNSUPPORTED)
                 return -ENOENT;
@@ -155,23 +114,46 @@ armpmu_map_cache_event(u64 config)
 }
 
 static int
-armpmu_map_event(u64 config)
+armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
 {
-        int mapping = (*armpmu->event_map)[config];
-        return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping;
+        int mapping = (*event_map)[config];
+        return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
 }
 
 static int
-armpmu_map_raw_event(u64 config)
+armpmu_map_raw_event(u32 raw_event_mask, u64 config)
 {
-        return (int)(config & armpmu->raw_event_mask);
+        return (int)(config & raw_event_mask);
 }
 
-static int
+static int map_cpu_event(struct perf_event *event,
+                         const unsigned (*event_map)[PERF_COUNT_HW_MAX],
+                         const unsigned (*cache_map)
+                                        [PERF_COUNT_HW_CACHE_MAX]
+                                        [PERF_COUNT_HW_CACHE_OP_MAX]
+                                        [PERF_COUNT_HW_CACHE_RESULT_MAX],
+                         u32 raw_event_mask)
+{
+        u64 config = event->attr.config;
+
+        switch (event->attr.type) {
+        case PERF_TYPE_HARDWARE:
+                return armpmu_map_event(event_map, config);
+        case PERF_TYPE_HW_CACHE:
+                return armpmu_map_cache_event(cache_map, config);
+        case PERF_TYPE_RAW:
+                return armpmu_map_raw_event(raw_event_mask, config);
+        }
+
+        return -ENOENT;
+}
+
+int
 armpmu_event_set_period(struct perf_event *event,
                         struct hw_perf_event *hwc,
                         int idx)
 {
+        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
         s64 left = local64_read(&hwc->period_left);
         s64 period = hwc->sample_period;
         int ret = 0;
@@ -202,11 +184,12 @@ armpmu_event_set_period(struct perf_event *event,
         return ret;
 }
 
-static u64
+u64
 armpmu_event_update(struct perf_event *event,
                     struct hw_perf_event *hwc,
                     int idx, int overflow)
 {
+        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
         u64 delta, prev_raw_count, new_raw_count;
 
 again:
@@ -246,11 +229,9 @@ armpmu_read(struct perf_event *event)
 static void
 armpmu_stop(struct perf_event *event, int flags)
 {
+        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
         struct hw_perf_event *hwc = &event->hw;
 
-        if (!armpmu)
-                return;
-
         /*
          * ARM pmu always has to update the counter, so ignore
          * PERF_EF_UPDATE, see comments in armpmu_start().
@@ -266,11 +247,9 @@ armpmu_stop(struct perf_event *event, int flags)
 static void
 armpmu_start(struct perf_event *event, int flags)
 {
+        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
         struct hw_perf_event *hwc = &event->hw;
 
-        if (!armpmu)
-                return;
-
         /*
          * ARM pmu always has to reprogram the period, so ignore
          * PERF_EF_RELOAD, see the comment below.
@@ -293,16 +272,16 @@ armpmu_start(struct perf_event *event, int flags)
 static void
 armpmu_del(struct perf_event *event, int flags)
 {
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+        struct pmu_hw_events *hw_events = armpmu->get_hw_events();
         struct hw_perf_event *hwc = &event->hw;
         int idx = hwc->idx;
 
         WARN_ON(idx < 0);
 
-        clear_bit(idx, cpuc->active_mask);
         armpmu_stop(event, PERF_EF_UPDATE);
-        cpuc->events[idx] = NULL;
-        clear_bit(idx, cpuc->used_mask);
+        hw_events->events[idx] = NULL;
+        clear_bit(idx, hw_events->used_mask);
 
         perf_event_update_userpage(event);
 }
@@ -310,7 +289,8 @@ armpmu_del(struct perf_event *event, int flags)
 static int
 armpmu_add(struct perf_event *event, int flags)
 {
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+        struct pmu_hw_events *hw_events = armpmu->get_hw_events();
         struct hw_perf_event *hwc = &event->hw;
         int idx;
         int err = 0;
@@ -318,7 +298,7 @@ armpmu_add(struct perf_event *event, int flags)
         perf_pmu_disable(event->pmu);
 
         /* If we don't have a space for the counter then finish early. */
-        idx = armpmu->get_event_idx(cpuc, hwc);
+        idx = armpmu->get_event_idx(hw_events, hwc);
         if (idx < 0) {
                 err = idx;
                 goto out;
@@ -330,8 +310,7 @@ armpmu_add(struct perf_event *event, int flags)
          */
         event->hw.idx = idx;
         armpmu->disable(hwc, idx);
-        cpuc->events[idx] = event;
-        set_bit(idx, cpuc->active_mask);
+        hw_events->events[idx] = event;
 
         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
         if (flags & PERF_EF_START)
@@ -345,25 +324,25 @@ out:
         return err;
 }
 
-static struct pmu pmu;
-
 static int
-validate_event(struct cpu_hw_events *cpuc,
+validate_event(struct pmu_hw_events *hw_events,
                struct perf_event *event)
 {
+        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
         struct hw_perf_event fake_event = event->hw;
+        struct pmu *leader_pmu = event->group_leader->pmu;
 
-        if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF)
+        if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
                 return 1;
 
-        return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
+        return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
 }
 
 static int
 validate_group(struct perf_event *event)
 {
         struct perf_event *sibling, *leader = event->group_leader;
-        struct cpu_hw_events fake_pmu;
+        struct pmu_hw_events fake_pmu;
 
         memset(&fake_pmu, 0, sizeof(fake_pmu));
 
@@ -383,110 +362,119 @@ validate_group(struct perf_event *event)
 
 static irqreturn_t armpmu_platform_irq(int irq, void *dev)
 {
-        struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev);
+        struct arm_pmu *armpmu = (struct arm_pmu *) dev;
+        struct platform_device *plat_device = armpmu->plat_device;
+        struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
 
         return plat->handle_irq(irq, dev, armpmu->handle_irq);
 }
 
+static void
+armpmu_release_hardware(struct arm_pmu *armpmu)
+{
+        int i, irq, irqs;
+        struct platform_device *pmu_device = armpmu->plat_device;
+
+        irqs = min(pmu_device->num_resources, num_possible_cpus());
+
+        for (i = 0; i < irqs; ++i) {
+                if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
+                        continue;
+                irq = platform_get_irq(pmu_device, i);
+                if (irq >= 0)
+                        free_irq(irq, armpmu);
+        }
+
+        release_pmu(armpmu->type);
+}
+
 static int
-armpmu_reserve_hardware(void)
+armpmu_reserve_hardware(struct arm_pmu *armpmu)
 {
         struct arm_pmu_platdata *plat;
         irq_handler_t handle_irq;
-        int i, err = -ENODEV, irq;
+        int i, err, irq, irqs;
+        struct platform_device *pmu_device = armpmu->plat_device;
 
-        pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU);
-        if (IS_ERR(pmu_device)) {
+        err = reserve_pmu(armpmu->type);
+        if (err) {
                 pr_warning("unable to reserve pmu\n");
-                return PTR_ERR(pmu_device);
+                return err;
         }
 
-        init_pmu(ARM_PMU_DEVICE_CPU);
-
         plat = dev_get_platdata(&pmu_device->dev);
         if (plat && plat->handle_irq)
                 handle_irq = armpmu_platform_irq;
         else
                 handle_irq = armpmu->handle_irq;
 
-        if (pmu_device->num_resources < 1) {
+        irqs = min(pmu_device->num_resources, num_possible_cpus());
+        if (irqs < 1) {
                 pr_err("no irqs for PMUs defined\n");
                 return -ENODEV;
         }
 
-        for (i = 0; i < pmu_device->num_resources; ++i) {
+        for (i = 0; i < irqs; ++i) {
+                err = 0;
                 irq = platform_get_irq(pmu_device, i);
                 if (irq < 0)
                         continue;
 
+                /*
+                 * If we have a single PMU interrupt that we can't shift,
+                 * assume that we're running on a uniprocessor machine and
+                 * continue. Otherwise, continue without this interrupt.
+                 */
+                if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
+                        pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
+                                    irq, i);
+                        continue;
+                }
+
                 err = request_irq(irq, handle_irq,
                                   IRQF_DISABLED | IRQF_NOBALANCING,
-                                  "armpmu", NULL);
+                                  "arm-pmu", armpmu);
                 if (err) {
-                        pr_warning("unable to request IRQ%d for ARM perf "
-                                "counters\n", irq);
-                        break;
+                        pr_err("unable to request IRQ%d for ARM PMU counters\n",
+                                irq);
+                        armpmu_release_hardware(armpmu);
+                        return err;
                 }
-        }
 
-        if (err) {
-                for (i = i - 1; i >= 0; --i) {
-                        irq = platform_get_irq(pmu_device, i);
-                        if (irq >= 0)
-                                free_irq(irq, NULL);
-                }
-                release_pmu(ARM_PMU_DEVICE_CPU);
-                pmu_device = NULL;
+                cpumask_set_cpu(i, &armpmu->active_irqs);
         }
 
-        return err;
+        return 0;
 }
 
 static void
-armpmu_release_hardware(void)
+hw_perf_event_destroy(struct perf_event *event)
 {
-        int i, irq;
+        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+        atomic_t *active_events  = &armpmu->active_events;
+        struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
 
-        for (i = pmu_device->num_resources - 1; i >= 0; --i) {
-                irq = platform_get_irq(pmu_device, i);
-                if (irq >= 0)
-                        free_irq(irq, NULL);
+        if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
+                armpmu_release_hardware(armpmu);
+                mutex_unlock(pmu_reserve_mutex);
         }
-        armpmu->stop();
-
-        release_pmu(ARM_PMU_DEVICE_CPU);
-        pmu_device = NULL;
 }
 
-static atomic_t active_events = ATOMIC_INIT(0);
-static DEFINE_MUTEX(pmu_reserve_mutex);
-
-static void
-hw_perf_event_destroy(struct perf_event *event)
+static int
+event_requires_mode_exclusion(struct perf_event_attr *attr)
 {
-        if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) {
-                armpmu_release_hardware();
-                mutex_unlock(&pmu_reserve_mutex);
-        }
+        return attr->exclude_idle || attr->exclude_user ||
+               attr->exclude_kernel || attr->exclude_hv;
 }
 
 static int
 __hw_perf_event_init(struct perf_event *event)
 {
+        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
         struct hw_perf_event *hwc = &event->hw;
         int mapping, err;
 
-        /* Decode the generic type into an ARM event identifier. */
-        if (PERF_TYPE_HARDWARE == event->attr.type) {
-                mapping = armpmu_map_event(event->attr.config);
-        } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
-                mapping = armpmu_map_cache_event(event->attr.config);
-        } else if (PERF_TYPE_RAW == event->attr.type) {
-                mapping = armpmu_map_raw_event(event->attr.config);
-        } else {
-                pr_debug("event type %x not supported\n", event->attr.type);
-                return -EOPNOTSUPP;
-        }
+        mapping = armpmu->map_event(event);
 
         if (mapping < 0) {
                 pr_debug("event %x:%llx not supported\n", event->attr.type,
@@ -495,34 +483,31 @@ __hw_perf_event_init(struct perf_event *event)
         }
 
         /*
+         * We don't assign an index until we actually place the event onto
+         * hardware. Use -1 to signify that we haven't decided where to put it
+         * yet. For SMP systems, each core has it's own PMU so we can't do any
+         * clever allocation or constraints checking at this point.
+         */
+        hwc->idx                = -1;
+        hwc->config_base        = 0;
+        hwc->config             = 0;
+        hwc->event_base         = 0;
+
+        /*
          * Check whether we need to exclude the counter from certain modes.
-         * The ARM performance counters are on all of the time so if someone
-         * has asked us for some excludes then we have to fail.
          */
-        if (event->attr.exclude_kernel || event->attr.exclude_user ||
-            event->attr.exclude_hv || event->attr.exclude_idle) {
+        if ((!armpmu->set_event_filter ||
+             armpmu->set_event_filter(hwc, &event->attr)) &&
+             event_requires_mode_exclusion(&event->attr)) {
                 pr_debug("ARM performance counters do not support "
                          "mode exclusion\n");
                 return -EPERM;
         }
 
         /*
-         * We don't assign an index until we actually place the event onto
-         * hardware. Use -1 to signify that we haven't decided where to put it
-         * yet. For SMP systems, each core has it's own PMU so we can't do any
-         * clever allocation or constraints checking at this point.
+         * Store the event encoding into the config_base field.
          */
-        hwc->idx = -1;
-
-        /*
-         * Store the event encoding into the config_base field. config and
-         * event_base are unused as the only 2 things we need to know are
-         * the event mapping and the counter to use. The counter to use is
-         * also the indx and the config_base is the event type.
-         */
-        hwc->config_base            = (unsigned long)mapping;
-        hwc->config                 = 0;
-        hwc->event_base             = 0;
+        hwc->config_base            |= (unsigned long)mapping;
 
         if (!hwc->sample_period) {
                 hwc->sample_period  = armpmu->max_period;
@@ -542,32 +527,23 @@ __hw_perf_event_init(struct perf_event *event)
 
 static int armpmu_event_init(struct perf_event *event)
 {
+        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
         int err = 0;
+        atomic_t *active_events = &armpmu->active_events;
 
-        switch (event->attr.type) {
-        case PERF_TYPE_RAW:
-        case PERF_TYPE_HARDWARE:
-        case PERF_TYPE_HW_CACHE:
-                break;
-
-        default:
+        if (armpmu->map_event(event) == -ENOENT)
                 return -ENOENT;
-        }
-
-        if (!armpmu)
-                return -ENODEV;
 
         event->destroy = hw_perf_event_destroy;
 
-        if (!atomic_inc_not_zero(&active_events)) {
-                mutex_lock(&pmu_reserve_mutex);
-                if (atomic_read(&active_events) == 0) {
-                        err = armpmu_reserve_hardware();
-                }
+        if (!atomic_inc_not_zero(active_events)) {
+                mutex_lock(&armpmu->reserve_mutex);
+                if (atomic_read(active_events) == 0)
+                        err = armpmu_reserve_hardware(armpmu);
 
                 if (!err)
-                        atomic_inc(&active_events);
-                mutex_unlock(&pmu_reserve_mutex);
+                        atomic_inc(active_events);
+                mutex_unlock(&armpmu->reserve_mutex);
         }
 
         if (err)
@@ -582,22 +558,9 @@ static int armpmu_event_init(struct perf_event *event)
 
 static void armpmu_enable(struct pmu *pmu)
 {
-        /* Enable all of the perf events on hardware. */
-        int idx, enabled = 0;
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-
-        if (!armpmu)
-                return;
-
-        for (idx = 0; idx <= armpmu->num_events; ++idx) {
-                struct perf_event *event = cpuc->events[idx];
-
-                if (!event)
-                        continue;
-
-                armpmu->enable(&event->hw, idx);
-                enabled = 1;
-        }
+        struct arm_pmu *armpmu = to_arm_pmu(pmu);
+        struct pmu_hw_events *hw_events = armpmu->get_hw_events();
+        int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 
         if (enabled)
                 armpmu->start();
@@ -605,20 +568,32 @@ static void armpmu_enable(struct pmu *pmu)
 
 static void armpmu_disable(struct pmu *pmu)
 {
-        if (armpmu)
-                armpmu->stop();
+        struct arm_pmu *armpmu = to_arm_pmu(pmu);
+        armpmu->stop();
 }
 
-static struct pmu pmu = {
-        .pmu_enable     = armpmu_enable,
-        .pmu_disable    = armpmu_disable,
-        .event_init     = armpmu_event_init,
-        .add            = armpmu_add,
-        .del            = armpmu_del,
-        .start          = armpmu_start,
-        .stop           = armpmu_stop,
-        .read           = armpmu_read,
-};
+static void __init armpmu_init(struct arm_pmu *armpmu)
+{
+        atomic_set(&armpmu->active_events, 0);
+        mutex_init(&armpmu->reserve_mutex);
+
+        armpmu->pmu = (struct pmu) {
+                .pmu_enable     = armpmu_enable,
+                .pmu_disable    = armpmu_disable,
+                .event_init     = armpmu_event_init,
+                .add            = armpmu_add,
+                .del            = armpmu_del,
+                .start          = armpmu_start,
+                .stop           = armpmu_stop,
+                .read           = armpmu_read,
+        };
+}
+
+int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
+{
+        armpmu_init(armpmu);
+        return perf_pmu_register(&armpmu->pmu, name, type);
+}
 
 /* Include the PMU-specific implementations. */
 #include "perf_event_xscale.c"
@@ -630,14 +605,72 @@ static struct pmu pmu = {
  * This requires SMP to be available, so exists as a separate initcall.
  */
 static int __init
-armpmu_reset(void)
+cpu_pmu_reset(void)
+{
+        if (cpu_pmu && cpu_pmu->reset)
+                return on_each_cpu(cpu_pmu->reset, NULL, 1);
+        return 0;
+}
+arch_initcall(cpu_pmu_reset);
+
+/*
+ * PMU platform driver and devicetree bindings.
+ */
+static struct of_device_id armpmu_of_device_ids[] = {
+        {.compatible = "arm,cortex-a9-pmu"},
+        {.compatible = "arm,cortex-a8-pmu"},
+        {.compatible = "arm,arm1136-pmu"},
+        {.compatible = "arm,arm1176-pmu"},
+        {},
+};
+
+static struct platform_device_id armpmu_plat_device_ids[] = {
+        {.name = "arm-pmu"},
+        {},
+};
+
+static int __devinit armpmu_device_probe(struct platform_device *pdev)
 {
-        if (armpmu && armpmu->reset)
-                return on_each_cpu(armpmu->reset, NULL, 1);
+        cpu_pmu->plat_device = pdev;
         return 0;
 }
-arch_initcall(armpmu_reset);
 
+static struct platform_driver armpmu_driver = {
+        .driver         = {
+                .name   = "arm-pmu",
+                .of_match_table = armpmu_of_device_ids,
+        },
+        .probe          = armpmu_device_probe,
+        .id_table       = armpmu_plat_device_ids,
+};
+
+static int __init register_pmu_driver(void)
+{
+        return platform_driver_register(&armpmu_driver);
+}
+device_initcall(register_pmu_driver);
+
+static struct pmu_hw_events *armpmu_get_cpu_events(void)
+{
+        return &__get_cpu_var(cpu_hw_events);
+}
+
+static void __init cpu_pmu_init(struct arm_pmu *armpmu)
+{
+        int cpu;
+        for_each_possible_cpu(cpu) {
+                struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
+                events->events = per_cpu(hw_events, cpu);
+                events->used_mask = per_cpu(used_mask, cpu);
+                raw_spin_lock_init(&events->pmu_lock);
+        }
+        armpmu->get_hw_events = armpmu_get_cpu_events;
+        armpmu->type = ARM_PMU_DEVICE_CPU;
+}
+
+/*
+ * CPU PMU identification and registration.
+ */
 static int __init
 init_hw_perf_events(void)
 {
@@ -651,22 +684,22 @@ init_hw_perf_events(void)
                 case 0xB360:    /* ARM1136 */
                 case 0xB560:    /* ARM1156 */
                 case 0xB760:    /* ARM1176 */
-                        armpmu = armv6pmu_init();
+                        cpu_pmu = armv6pmu_init();
                         break;
                 case 0xB020:    /* ARM11mpcore */
-                        armpmu = armv6mpcore_pmu_init();
+                        cpu_pmu = armv6mpcore_pmu_init();
                         break;
                 case 0xC080:    /* Cortex-A8 */
-                        armpmu = armv7_a8_pmu_init();
+                        cpu_pmu = armv7_a8_pmu_init();
                         break;
                 case 0xC090:    /* Cortex-A9 */
-                        armpmu = armv7_a9_pmu_init();
+                        cpu_pmu = armv7_a9_pmu_init();
                         break;
                 case 0xC050:    /* Cortex-A5 */
-                        armpmu = armv7_a5_pmu_init();
+                        cpu_pmu = armv7_a5_pmu_init();
                         break;
                 case 0xC0F0:    /* Cortex-A15 */
-                        armpmu = armv7_a15_pmu_init();
+                        cpu_pmu = armv7_a15_pmu_init();
                         break;
                 }
         /* Intel CPUs [xscale]. */
@@ -674,23 +707,23 @@ init_hw_perf_events(void)
                 part_number = (cpuid >> 13) & 0x7;
                 switch (part_number) {
                 case 1:
-                        armpmu = xscale1pmu_init();
+                        cpu_pmu = xscale1pmu_init();
                         break;
                 case 2:
-                        armpmu = xscale2pmu_init();
+                        cpu_pmu = xscale2pmu_init();
                         break;
                 }
         }
 
-        if (armpmu) {
+        if (cpu_pmu) {
                 pr_info("enabled with %s PMU driver, %d counters available\n",
-                        armpmu->name, armpmu->num_events);
+                        cpu_pmu->name, cpu_pmu->num_events);
+                cpu_pmu_init(cpu_pmu);
+                armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
         } else {
                 pr_info("no hardware support available\n");
         }
 
-        perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
-
         return 0;
 }
 early_initcall(init_hw_perf_events);
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index dd7f3b9f4cb3..e63d8115c01b 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -54,7 +54,7 @@ enum armv6_perf_types {
 };
 
 enum armv6_counters {
-        ARMV6_CYCLE_COUNTER = 1,
+        ARMV6_CYCLE_COUNTER = 0,
         ARMV6_COUNTER0,
         ARMV6_COUNTER1,
 };
@@ -433,6 +433,7 @@ armv6pmu_enable_event(struct hw_perf_event *hwc,
                       int idx)
 {
         unsigned long val, mask, evt, flags;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
         if (ARMV6_CYCLE_COUNTER == idx) {
                 mask    = 0;
@@ -454,12 +455,29 @@ armv6pmu_enable_event(struct hw_perf_event *hwc,
          * Mask out the current event and set the counter to count the event
          * that we're interested in.
          */
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
         val = armv6_pmcr_read();
         val &= ~mask;
         val |= evt;
         armv6_pmcr_write(val);
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
+}
+
+static int counter_is_active(unsigned long pmcr, int idx)
+{
+        unsigned long mask = 0;
+        if (idx == ARMV6_CYCLE_COUNTER)
+                mask = ARMV6_PMCR_CCOUNT_IEN;
+        else if (idx == ARMV6_COUNTER0)
+                mask = ARMV6_PMCR_COUNT0_IEN;
+        else if (idx == ARMV6_COUNTER1)
+                mask = ARMV6_PMCR_COUNT1_IEN;
+
+        if (mask)
+                return pmcr & mask;
+
+        WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+        return 0;
 }
 
 static irqreturn_t
@@ -468,7 +486,7 @@ armv6pmu_handle_irq(int irq_num,
 {
         unsigned long pmcr = armv6_pmcr_read();
         struct perf_sample_data data;
-        struct cpu_hw_events *cpuc;
+        struct pmu_hw_events *cpuc;
         struct pt_regs *regs;
         int idx;
 
@@ -487,11 +505,11 @@ armv6pmu_handle_irq(int irq_num,
         perf_sample_data_init(&data, 0);
 
         cpuc = &__get_cpu_var(cpu_hw_events);
-        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+        for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
                 struct perf_event *event = cpuc->events[idx];
                 struct hw_perf_event *hwc;
 
-                if (!test_bit(idx, cpuc->active_mask))
+                if (!counter_is_active(pmcr, idx))
                         continue;
 
                 /*
@@ -508,7 +526,7 @@ armv6pmu_handle_irq(int irq_num,
                         continue;
 
                 if (perf_event_overflow(event, &data, regs))
-                        armpmu->disable(hwc, idx);
+                        cpu_pmu->disable(hwc, idx);
         }
 
         /*
@@ -527,28 +545,30 @@ static void
 armv6pmu_start(void)
 {
         unsigned long flags, val;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
         val = armv6_pmcr_read();
         val |= ARMV6_PMCR_ENABLE;
         armv6_pmcr_write(val);
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static void
 armv6pmu_stop(void)
 {
         unsigned long flags, val;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
         val = armv6_pmcr_read();
         val &= ~ARMV6_PMCR_ENABLE;
         armv6_pmcr_write(val);
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static int
-armv6pmu_get_event_idx(struct cpu_hw_events *cpuc,
+armv6pmu_get_event_idx(struct pmu_hw_events *cpuc,
                        struct hw_perf_event *event)
 {
         /* Always place a cycle counter into the cycle counter. */
@@ -578,6 +598,7 @@ armv6pmu_disable_event(struct hw_perf_event *hwc,
                        int idx)
 {
         unsigned long val, mask, evt, flags;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
         if (ARMV6_CYCLE_COUNTER == idx) {
                 mask    = ARMV6_PMCR_CCOUNT_IEN;
@@ -598,12 +619,12 @@ armv6pmu_disable_event(struct hw_perf_event *hwc,
          * of ETM bus signal assertion cycles. The external reporting should
          * be disabled and so this should never increment.
          */
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
         val = armv6_pmcr_read();
         val &= ~mask;
         val |= evt;
         armv6_pmcr_write(val);
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static void
@@ -611,6 +632,7 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
                               int idx)
 {
         unsigned long val, mask, flags, evt = 0;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
         if (ARMV6_CYCLE_COUNTER == idx) {
                 mask    = ARMV6_PMCR_CCOUNT_IEN;
@@ -627,15 +649,21 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
          * Unlike UP ARMv6, we don't have a way of stopping the counters. We
          * simply disable the interrupt reporting.
          */
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
         val = armv6_pmcr_read();
         val &= ~mask;
         val |= evt;
         armv6_pmcr_write(val);
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
+}
+
+static int armv6_map_event(struct perf_event *event)
+{
+        return map_cpu_event(event, &armv6_perf_map,
+                                &armv6_perf_cache_map, 0xFF);
 }
 
-static const struct arm_pmu armv6pmu = {
+static struct arm_pmu armv6pmu = {
         .id                     = ARM_PERF_PMU_ID_V6,
         .name                   = "v6",
         .handle_irq             = armv6pmu_handle_irq,
@@ -646,14 +674,12 @@ static const struct arm_pmu armv6pmu = {
         .get_event_idx          = armv6pmu_get_event_idx,
         .start                  = armv6pmu_start,
         .stop                   = armv6pmu_stop,
-        .cache_map              = &armv6_perf_cache_map,
-        .event_map              = &armv6_perf_map,
-        .raw_event_mask         = 0xFF,
+        .map_event              = armv6_map_event,
         .num_events             = 3,
         .max_period             = (1LLU << 32) - 1,
 };
 
-static const struct arm_pmu *__init armv6pmu_init(void)
+static struct arm_pmu *__init armv6pmu_init(void)
 {
         return &armv6pmu;
 }
@@ -665,7 +691,14 @@ static const struct arm_pmu *__init armv6pmu_init(void)
  * disable the interrupt reporting and update the event. When unthrottling we
  * reset the period and enable the interrupt reporting.
  */
-static const struct arm_pmu armv6mpcore_pmu = {
+
+static int armv6mpcore_map_event(struct perf_event *event)
+{
+        return map_cpu_event(event, &armv6mpcore_perf_map,
+                                &armv6mpcore_perf_cache_map, 0xFF);
+}
+
+static struct arm_pmu armv6mpcore_pmu = {
         .id                     = ARM_PERF_PMU_ID_V6MP,
         .name                   = "v6mpcore",
         .handle_irq             = armv6pmu_handle_irq,
@@ -676,24 +709,22 @@ static const struct arm_pmu armv6mpcore_pmu = {
         .get_event_idx          = armv6pmu_get_event_idx,
         .start                  = armv6pmu_start,
         .stop                   = armv6pmu_stop,
-        .cache_map              = &armv6mpcore_perf_cache_map,
-        .event_map              = &armv6mpcore_perf_map,
-        .raw_event_mask         = 0xFF,
+        .map_event              = armv6mpcore_map_event,
         .num_events             = 3,
         .max_period             = (1LLU << 32) - 1,
 };
 
-static const struct arm_pmu *__init armv6mpcore_pmu_init(void)
+static struct arm_pmu *__init armv6mpcore_pmu_init(void)
 {
         return &armv6mpcore_pmu;
 }
 #else
-static const struct arm_pmu *__init armv6pmu_init(void)
+static struct arm_pmu *__init armv6pmu_init(void)
 {
         return NULL;
 }
 
-static const struct arm_pmu *__init armv6mpcore_pmu_init(void)
+static struct arm_pmu *__init armv6mpcore_pmu_init(void)
 {
         return NULL;
 }
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 4c851834f68e..98b75738345e 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -17,6 +17,9 @@
  */
 
 #ifdef CONFIG_CPU_V7
+
+static struct arm_pmu armv7pmu;
+
 /*
  * Common ARMv7 event types
  *
@@ -676,23 +679,24 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 };
 
 /*
- * Perf Events counters
+ * Perf Events' indices
  */
-enum armv7_counters {
-        ARMV7_CYCLE_COUNTER             = 1,    /* Cycle counter */
-        ARMV7_COUNTER0                  = 2,    /* First event counter */
-};
+#define ARMV7_IDX_CYCLE_COUNTER 0
+#define ARMV7_IDX_COUNTER0      1
+#define ARMV7_IDX_COUNTER_LAST  (ARMV7_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
+
+#define ARMV7_MAX_COUNTERS      32
+#define ARMV7_COUNTER_MASK      (ARMV7_MAX_COUNTERS - 1)
 
 /*
- * The cycle counter is ARMV7_CYCLE_COUNTER.
- * The first event counter is ARMV7_COUNTER0.
- * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1).
+ * ARMv7 low level PMNC access
  */
-#define ARMV7_COUNTER_LAST      (ARMV7_COUNTER0 + armpmu->num_events - 1)
 
 /*
- * ARMv7 low level PMNC access
+ * Perf Event to low level counters mapping
  */
+#define ARMV7_IDX_TO_COUNTER(x) \
+        (((x) - ARMV7_IDX_COUNTER0) & ARMV7_COUNTER_MASK)
 
 /*
  * Per-CPU PMNC: config reg
@@ -708,103 +712,76 @@ enum armv7_counters {
 #define ARMV7_PMNC_MASK         0x3f     /* Mask for writable bits */
 
 /*
- * Available counters
- */
-#define ARMV7_CNT0              0       /* First event counter */
-#define ARMV7_CCNT              31      /* Cycle counter */
-
-/* Perf Event to low level counters mapping */
-#define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0)
-
-/*
- * CNTENS: counters enable reg
- */
-#define ARMV7_CNTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
-#define ARMV7_CNTENS_C          (1 << ARMV7_CCNT)
-
-/*
- * CNTENC: counters disable reg
- */
-#define ARMV7_CNTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
-#define ARMV7_CNTENC_C          (1 << ARMV7_CCNT)
-
-/*
- * INTENS: counters overflow interrupt enable reg
- */
-#define ARMV7_INTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
-#define ARMV7_INTENS_C          (1 << ARMV7_CCNT)
-
-/*
- * INTENC: counters overflow interrupt disable reg
- */
-#define ARMV7_INTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
-#define ARMV7_INTENC_C          (1 << ARMV7_CCNT)
-
-/*
- * EVTSEL: Event selection reg
+ * FLAG: counters overflow flag status reg
  */
-#define ARMV7_EVTSEL_MASK       0xff            /* Mask for writable bits */
+#define ARMV7_FLAG_MASK         0xffffffff      /* Mask for writable bits */
+#define ARMV7_OVERFLOWED_MASK   ARMV7_FLAG_MASK
 
 /*
- * SELECT: Counter selection reg
+ * PMXEVTYPER: Event selection reg
  */
-#define ARMV7_SELECT_MASK       0x1f            /* Mask for writable bits */
+#define ARMV7_EVTYPE_MASK       0xc00000ff      /* Mask for writable bits */
+#define ARMV7_EVTYPE_EVENT      0xff            /* Mask for EVENT bits */
 
 /*
- * FLAG: counters overflow flag status reg
+ * Event filters for PMUv2
  */
-#define ARMV7_FLAG_P(idx)       (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
-#define ARMV7_FLAG_C            (1 << ARMV7_CCNT)
-#define ARMV7_FLAG_MASK         0xffffffff      /* Mask for writable bits */
-#define ARMV7_OVERFLOWED_MASK   ARMV7_FLAG_MASK
+#define ARMV7_EXCLUDE_PL1       (1 << 31)
+#define ARMV7_EXCLUDE_USER      (1 << 30)
+#define ARMV7_INCLUDE_HYP       (1 << 27)
 
-static inline unsigned long armv7_pmnc_read(void)
+static inline u32 armv7_pmnc_read(void)
 {
         u32 val;
         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));
         return val;
 }
 
-static inline void armv7_pmnc_write(unsigned long val)
+static inline void armv7_pmnc_write(u32 val)
 {
         val &= ARMV7_PMNC_MASK;
         isb();
         asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
 }
 
-static inline int armv7_pmnc_has_overflowed(unsigned long pmnc)
+static inline int armv7_pmnc_has_overflowed(u32 pmnc)
 {
         return pmnc & ARMV7_OVERFLOWED_MASK;
 }
 
-static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc,
-                                        enum armv7_counters counter)
+static inline int armv7_pmnc_counter_valid(int idx)
+{
+        return idx >= ARMV7_IDX_CYCLE_COUNTER && idx <= ARMV7_IDX_COUNTER_LAST;
+}
+
+static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc, int idx)
 {
         int ret = 0;
+        u32 counter;
 
-        if (counter == ARMV7_CYCLE_COUNTER)
-                ret = pmnc & ARMV7_FLAG_C;
-        else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST))
-                ret = pmnc & ARMV7_FLAG_P(counter);
-        else
+        if (!armv7_pmnc_counter_valid(idx)) {
                 pr_err("CPU%u checking wrong counter %d overflow status\n",
-                        smp_processor_id(), counter);
+                        smp_processor_id(), idx);
+        } else {
+                counter = ARMV7_IDX_TO_COUNTER(idx);
+                ret = pmnc & BIT(counter);
+        }
 
         return ret;
 }
 
-static inline int armv7_pmnc_select_counter(unsigned int idx)
+static inline int armv7_pmnc_select_counter(int idx)
 {
-        u32 val;
+        u32 counter;
 
-        if ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST)) {
-                pr_err("CPU%u selecting wrong PMNC counter"
-                        " %d\n", smp_processor_id(), idx);
-                return -1;
+        if (!armv7_pmnc_counter_valid(idx)) {
+                pr_err("CPU%u selecting wrong PMNC counter %d\n",
+                        smp_processor_id(), idx);
+                return -EINVAL;
         }
 
-        val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK;
-        asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
+        counter = ARMV7_IDX_TO_COUNTER(idx);
+        asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter));
         isb();
 
         return idx;
@@ -812,124 +789,95 @@ static inline int armv7_pmnc_select_counter(unsigned int idx)
 
 static inline u32 armv7pmu_read_counter(int idx)
 {
-        unsigned long value = 0;
+        u32 value = 0;
 
-        if (idx == ARMV7_CYCLE_COUNTER)
-                asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
-        else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
-                if (armv7_pmnc_select_counter(idx) == idx)
-                        asm volatile("mrc p15, 0, %0, c9, c13, 2"
-                                     : "=r" (value));
-        } else
+        if (!armv7_pmnc_counter_valid(idx))
                 pr_err("CPU%u reading wrong counter %d\n",
                         smp_processor_id(), idx);
+        else if (idx == ARMV7_IDX_CYCLE_COUNTER)
+                asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
+        else if (armv7_pmnc_select_counter(idx) == idx)
+                asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value));
 
         return value;
 }
 
 static inline void armv7pmu_write_counter(int idx, u32 value)
 {
-        if (idx == ARMV7_CYCLE_COUNTER)
-                asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
-        else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
-                if (armv7_pmnc_select_counter(idx) == idx)
-                        asm volatile("mcr p15, 0, %0, c9, c13, 2"
-                                     : : "r" (value));
-        } else
+        if (!armv7_pmnc_counter_valid(idx))
                 pr_err("CPU%u writing wrong counter %d\n",
                         smp_processor_id(), idx);
+        else if (idx == ARMV7_IDX_CYCLE_COUNTER)
+                asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
+        else if (armv7_pmnc_select_counter(idx) == idx)
+                asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (value));
 }
 
-static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val)
+static inline void armv7_pmnc_write_evtsel(int idx, u32 val)
 {
         if (armv7_pmnc_select_counter(idx) == idx) {
-                val &= ARMV7_EVTSEL_MASK;
+                val &= ARMV7_EVTYPE_MASK;
                 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
         }
 }
 
-static inline u32 armv7_pmnc_enable_counter(unsigned int idx)
+static inline int armv7_pmnc_enable_counter(int idx)
 {
-        u32 val;
+        u32 counter;
 
-        if ((idx != ARMV7_CYCLE_COUNTER) &&
-            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
-                pr_err("CPU%u enabling wrong PMNC counter"
-                        " %d\n", smp_processor_id(), idx);
-                return -1;
+        if (!armv7_pmnc_counter_valid(idx)) {
+                pr_err("CPU%u enabling wrong PMNC counter %d\n",
+                        smp_processor_id(), idx);
+                return -EINVAL;
         }
 
-        if (idx == ARMV7_CYCLE_COUNTER)
-                val = ARMV7_CNTENS_C;
-        else
-                val = ARMV7_CNTENS_P(idx);
-
-        asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
-
+        counter = ARMV7_IDX_TO_COUNTER(idx);
+        asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter)));
         return idx;
 }
 
-static inline u32 armv7_pmnc_disable_counter(unsigned int idx)
+static inline int armv7_pmnc_disable_counter(int idx)
 {
-        u32 val;
-
+        u32 counter;
 
-        if ((idx != ARMV7_CYCLE_COUNTER) &&
-            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
-                pr_err("CPU%u disabling wrong PMNC counter"
-                        " %d\n", smp_processor_id(), idx);
-                return -1;
+        if (!armv7_pmnc_counter_valid(idx)) {
+                pr_err("CPU%u disabling wrong PMNC counter %d\n",
+                        smp_processor_id(), idx);
+                return -EINVAL;
         }
 
-        if (idx == ARMV7_CYCLE_COUNTER)
-                val = ARMV7_CNTENC_C;
-        else
-                val = ARMV7_CNTENC_P(idx);
-
-        asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
-
+        counter = ARMV7_IDX_TO_COUNTER(idx);
+        asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter)));
         return idx;
 }
 
-static inline u32 armv7_pmnc_enable_intens(unsigned int idx)
+static inline int armv7_pmnc_enable_intens(int idx)
 {
-        u32 val;
+        u32 counter;
 
-        if ((idx != ARMV7_CYCLE_COUNTER) &&
-            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
-                pr_err("CPU%u enabling wrong PMNC counter"
-                        " interrupt enable %d\n", smp_processor_id(), idx);
-                return -1;
+        if (!armv7_pmnc_counter_valid(idx)) {
+                pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n",
+                        smp_processor_id(), idx);
+                return -EINVAL;
         }
 
-        if (idx == ARMV7_CYCLE_COUNTER)
-                val = ARMV7_INTENS_C;
-        else
-                val = ARMV7_INTENS_P(idx);
-
-        asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
-
+        counter = ARMV7_IDX_TO_COUNTER(idx);
+        asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter)));
         return idx;
 }
 
-static inline u32 armv7_pmnc_disable_intens(unsigned int idx)
+static inline int armv7_pmnc_disable_intens(int idx)
 {
-        u32 val;
+        u32 counter;
 
-        if ((idx != ARMV7_CYCLE_COUNTER) &&
-            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
-                pr_err("CPU%u disabling wrong PMNC counter"
-                        " interrupt enable %d\n", smp_processor_id(), idx);
-                return -1;
+        if (!armv7_pmnc_counter_valid(idx)) {
+                pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n",
+                        smp_processor_id(), idx);
+                return -EINVAL;
         }
 
-        if (idx == ARMV7_CYCLE_COUNTER)
-                val = ARMV7_INTENC_C;
-        else
-                val = ARMV7_INTENC_P(idx);
-
-        asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
-
+        counter = ARMV7_IDX_TO_COUNTER(idx);
+        asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter)));
         return idx;
 }
 
@@ -973,14 +921,14 @@ static void armv7_pmnc_dump_regs(void)
         asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
         printk(KERN_INFO "CCNT  =0x%08x\n", val);
 
-        for (cnt = ARMV7_COUNTER0; cnt < ARMV7_COUNTER_LAST; cnt++) {
+        for (cnt = ARMV7_IDX_COUNTER0; cnt <= ARMV7_IDX_COUNTER_LAST; cnt++) {
                 armv7_pmnc_select_counter(cnt);
                 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
                 printk(KERN_INFO "CNT[%d] count =0x%08x\n",
-                        cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
+                        ARMV7_IDX_TO_COUNTER(cnt), val);
                 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
                 printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n",
-                        cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
+                        ARMV7_IDX_TO_COUNTER(cnt), val);
         }
 }
 #endif
@@ -988,12 +936,13 @@ static void armv7_pmnc_dump_regs(void)
 static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
 {
         unsigned long flags;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
         /*
          * Enable counter and interrupt, and set the counter to count
          * the event that we're interested in.
          */
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
 
         /*
          * Disable counter
@@ -1002,9 +951,10 @@ static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
 
         /*
          * Set event (if destined for PMNx counters)
-         * We don't need to set the event if it's a cycle count
+         * We only need to set the event for the cycle counter if we
+         * have the ability to perform event filtering.
          */
-        if (idx != ARMV7_CYCLE_COUNTER)
+        if (armv7pmu.set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER)
                 armv7_pmnc_write_evtsel(idx, hwc->config_base);
 
         /*
@@ -1017,17 +967,18 @@ static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
          */
         armv7_pmnc_enable_counter(idx);
 
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
 {
         unsigned long flags;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
         /*
          * Disable counter and interrupt
          */
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
 
         /*
          * Disable counter
@@ -1039,14 +990,14 @@ static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
          */
         armv7_pmnc_disable_intens(idx);
 
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
 {
-        unsigned long pmnc;
+        u32 pmnc;
         struct perf_sample_data data;
-        struct cpu_hw_events *cpuc;
+        struct pmu_hw_events *cpuc;
         struct pt_regs *regs;
         int idx;
 
@@ -1069,13 +1020,10 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
         perf_sample_data_init(&data, 0);
 
         cpuc = &__get_cpu_var(cpu_hw_events);
-        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+        for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
                 struct perf_event *event = cpuc->events[idx];
                 struct hw_perf_event *hwc;
 
-                if (!test_bit(idx, cpuc->active_mask))
-                        continue;
-
                 /*
                  * We have a single interrupt for all counters. Check that
                  * each counter has overflowed before we process it.
@@ -1090,7 +1038,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
                         continue;
 
                 if (perf_event_overflow(event, &data, regs))
-                        armpmu->disable(hwc, idx);
+                        cpu_pmu->disable(hwc, idx);
         }
 
         /*
@@ -1108,61 +1056,114 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
 static void armv7pmu_start(void)
 {
         unsigned long flags;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
         /* Enable all counters */
         armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static void armv7pmu_stop(void)
 {
         unsigned long flags;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
         /* Disable all counters */
         armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
-static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc,
+static int armv7pmu_get_event_idx(struct pmu_hw_events *cpuc,
                                   struct hw_perf_event *event)
 {
         int idx;
+        unsigned long evtype = event->config_base & ARMV7_EVTYPE_EVENT;
 
         /* Always place a cycle counter into the cycle counter. */
-        if (event->config_base == ARMV7_PERFCTR_CPU_CYCLES) {
-                if (test_and_set_bit(ARMV7_CYCLE_COUNTER, cpuc->used_mask))
+        if (evtype == ARMV7_PERFCTR_CPU_CYCLES) {
+                if (test_and_set_bit(ARMV7_IDX_CYCLE_COUNTER, cpuc->used_mask))
                         return -EAGAIN;
 
-                return ARMV7_CYCLE_COUNTER;
-        } else {
-                /*
-                 * For anything other than a cycle counter, try and use
-                 * the events counters
-                 */
-                for (idx = ARMV7_COUNTER0; idx <= armpmu->num_events; ++idx) {
-                        if (!test_and_set_bit(idx, cpuc->used_mask))
-                                return idx;
-                }
+                return ARMV7_IDX_CYCLE_COUNTER;
+        }
 
-                /* The counters are all in use. */
-                return -EAGAIN;
+        /*
+         * For anything other than a cycle counter, try and use
+         * the events counters
+         */
+        for (idx = ARMV7_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
+                if (!test_and_set_bit(idx, cpuc->used_mask))
+                        return idx;
         }
+
+        /* The counters are all in use. */
+        return -EAGAIN;
+}
+
+/*
+ * Add an event filter to a given event. This will only work for PMUv2 PMUs.
+ */
+static int armv7pmu_set_event_filter(struct hw_perf_event *event,
+                                     struct perf_event_attr *attr)
+{
+        unsigned long config_base = 0;
+
+        if (attr->exclude_idle)
+                return -EPERM;
+        if (attr->exclude_user)
+                config_base |= ARMV7_EXCLUDE_USER;
+        if (attr->exclude_kernel)
+                config_base |= ARMV7_EXCLUDE_PL1;
+        if (!attr->exclude_hv)
+                config_base |= ARMV7_INCLUDE_HYP;
+
+        /*
+         * Install the filter into config_base as this is used to
+         * construct the event type.
+         */
+        event->config_base = config_base;
+
+        return 0;
 }
 
 static void armv7pmu_reset(void *info)
 {
-        u32 idx, nb_cnt = armpmu->num_events;
+        u32 idx, nb_cnt = cpu_pmu->num_events;
 
         /* The counter and interrupt enable registers are unknown at reset. */
-        for (idx = 1; idx < nb_cnt; ++idx)
+        for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx)
                 armv7pmu_disable_event(NULL, idx);
 
         /* Initialize & Reset PMNC: C and P bits */
         armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
 }
 
+static int armv7_a8_map_event(struct perf_event *event)
+{
+        return map_cpu_event(event, &armv7_a8_perf_map,
+                                &armv7_a8_perf_cache_map, 0xFF);
+}
+
+static int armv7_a9_map_event(struct perf_event *event)
+{
+        return map_cpu_event(event, &armv7_a9_perf_map,
+                                &armv7_a9_perf_cache_map, 0xFF);
+}
+
+static int armv7_a5_map_event(struct perf_event *event)
+{
+        return map_cpu_event(event, &armv7_a5_perf_map,
+                                &armv7_a5_perf_cache_map, 0xFF);
+}
+
+static int armv7_a15_map_event(struct perf_event *event)
+{
+        return map_cpu_event(event, &armv7_a15_perf_map,
+                                &armv7_a15_perf_cache_map, 0xFF);
+}
+
 static struct arm_pmu armv7pmu = {
         .handle_irq             = armv7pmu_handle_irq,
         .enable                 = armv7pmu_enable_event,
@@ -1173,7 +1174,6 @@ static struct arm_pmu armv7pmu = {
         .start                  = armv7pmu_start,
         .stop                   = armv7pmu_stop,
         .reset                  = armv7pmu_reset,
-        .raw_event_mask         = 0xFF,
         .max_period             = (1LLU << 32) - 1,
 };
 
@@ -1188,62 +1188,59 @@ static u32 __init armv7_read_num_pmnc_events(void)
         return nb_cnt + 1;
 }
 
-static const struct arm_pmu *__init armv7_a8_pmu_init(void)
+static struct arm_pmu *__init armv7_a8_pmu_init(void)
 {
         armv7pmu.id             = ARM_PERF_PMU_ID_CA8;
         armv7pmu.name           = "ARMv7 Cortex-A8";
-        armv7pmu.cache_map      = &armv7_a8_perf_cache_map;
-        armv7pmu.event_map      = &armv7_a8_perf_map;
+        armv7pmu.map_event      = armv7_a8_map_event;
         armv7pmu.num_events     = armv7_read_num_pmnc_events();
         return &armv7pmu;
 }
 
-static const struct arm_pmu *__init armv7_a9_pmu_init(void)
+static struct arm_pmu *__init armv7_a9_pmu_init(void)
 {
         armv7pmu.id             = ARM_PERF_PMU_ID_CA9;
         armv7pmu.name           = "ARMv7 Cortex-A9";
-        armv7pmu.cache_map      = &armv7_a9_perf_cache_map;
-        armv7pmu.event_map      = &armv7_a9_perf_map;
+        armv7pmu.map_event      = armv7_a9_map_event;
         armv7pmu.num_events     = armv7_read_num_pmnc_events();
         return &armv7pmu;
 }
 
-static const struct arm_pmu *__init armv7_a5_pmu_init(void)
+static struct arm_pmu *__init armv7_a5_pmu_init(void)
 {
         armv7pmu.id             = ARM_PERF_PMU_ID_CA5;
         armv7pmu.name           = "ARMv7 Cortex-A5";
-        armv7pmu.cache_map      = &armv7_a5_perf_cache_map;
-        armv7pmu.event_map      = &armv7_a5_perf_map;
+        armv7pmu.map_event      = armv7_a5_map_event;
         armv7pmu.num_events     = armv7_read_num_pmnc_events();
         return &armv7pmu;
 }
 
-static const struct arm_pmu *__init armv7_a15_pmu_init(void)
+static struct arm_pmu *__init armv7_a15_pmu_init(void)
 {
         armv7pmu.id             = ARM_PERF_PMU_ID_CA15;
         armv7pmu.name           = "ARMv7 Cortex-A15";
-        armv7pmu.cache_map      = &armv7_a15_perf_cache_map;
-        armv7pmu.event_map      = &armv7_a15_perf_map;
+        armv7pmu.map_event      = armv7_a15_map_event;
         armv7pmu.num_events     = armv7_read_num_pmnc_events();
+        armv7pmu.set_event_filter = armv7pmu_set_event_filter;
         return &armv7pmu;
 }
 #else
-static const struct arm_pmu *__init armv7_a8_pmu_init(void)
+static struct arm_pmu *__init armv7_a8_pmu_init(void)
 {
         return NULL;
 }
 
-static const struct arm_pmu *__init armv7_a9_pmu_init(void)
+static struct arm_pmu *__init armv7_a9_pmu_init(void)
 {
         return NULL;
 }
 
-static const struct arm_pmu *__init armv7_a5_pmu_init(void)
+static struct arm_pmu *__init armv7_a5_pmu_init(void)
 {
         return NULL;
 }
 
-static const struct arm_pmu *__init armv7_a15_pmu_init(void)
+static struct arm_pmu *__init armv7_a15_pmu_init(void)
 {
         return NULL;
 }
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index 3c4397491d08..e0cca10a8411 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -40,7 +40,7 @@ enum xscale_perf_types {
 };
 
 enum xscale_counters {
-        XSCALE_CYCLE_COUNTER    = 1,
+        XSCALE_CYCLE_COUNTER    = 0,
         XSCALE_COUNTER0,
         XSCALE_COUNTER1,
         XSCALE_COUNTER2,
@@ -222,7 +222,7 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
 {
         unsigned long pmnc;
         struct perf_sample_data data;
-        struct cpu_hw_events *cpuc;
+        struct pmu_hw_events *cpuc;
         struct pt_regs *regs;
         int idx;
 
@@ -249,13 +249,10 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
         perf_sample_data_init(&data, 0);
 
         cpuc = &__get_cpu_var(cpu_hw_events);
-        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+        for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
                 struct perf_event *event = cpuc->events[idx];
                 struct hw_perf_event *hwc;
 
-                if (!test_bit(idx, cpuc->active_mask))
-                        continue;
-
                 if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
                         continue;
 
@@ -266,7 +263,7 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
                         continue;
 
                 if (perf_event_overflow(event, &data, regs))
-                        armpmu->disable(hwc, idx);
+                        cpu_pmu->disable(hwc, idx);
         }
 
         irq_work_run();
@@ -284,6 +281,7 @@ static void
 xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
 {
         unsigned long val, mask, evt, flags;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
         switch (idx) {
         case XSCALE_CYCLE_COUNTER:
@@ -305,18 +303,19 @@ xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
                 return;
         }
 
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
         val = xscale1pmu_read_pmnc();
         val &= ~mask;
         val |= evt;
         xscale1pmu_write_pmnc(val);
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static void
 xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
 {
         unsigned long val, mask, evt, flags;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
         switch (idx) {
         case XSCALE_CYCLE_COUNTER:
@@ -336,16 +335,16 @@ xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
                 return;
         }
 
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
         val = xscale1pmu_read_pmnc();
         val &= ~mask;
         val |= evt;
         xscale1pmu_write_pmnc(val);
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static int
-xscale1pmu_get_event_idx(struct cpu_hw_events *cpuc,
+xscale1pmu_get_event_idx(struct pmu_hw_events *cpuc,
                         struct hw_perf_event *event)
 {
         if (XSCALE_PERFCTR_CCNT == event->config_base) {
@@ -368,24 +367,26 @@ static void
 xscale1pmu_start(void)
 {
         unsigned long flags, val;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
         val = xscale1pmu_read_pmnc();
         val |= XSCALE_PMU_ENABLE;
         xscale1pmu_write_pmnc(val);
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static void
 xscale1pmu_stop(void)
 {
         unsigned long flags, val;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
         val = xscale1pmu_read_pmnc();
         val &= ~XSCALE_PMU_ENABLE;
         xscale1pmu_write_pmnc(val);
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static inline u32
@@ -424,7 +425,13 @@ xscale1pmu_write_counter(int counter, u32 val)
         }
 }
 
-static const struct arm_pmu xscale1pmu = {
+static int xscale_map_event(struct perf_event *event)
+{
+        return map_cpu_event(event, &xscale_perf_map,
+                                &xscale_perf_cache_map, 0xFF);
+}
+
+static struct arm_pmu xscale1pmu = {
         .id             = ARM_PERF_PMU_ID_XSCALE1,
         .name           = "xscale1",
         .handle_irq     = xscale1pmu_handle_irq,
@@ -435,14 +442,12 @@ static const struct arm_pmu xscale1pmu = {
         .get_event_idx  = xscale1pmu_get_event_idx,
         .start          = xscale1pmu_start,
         .stop           = xscale1pmu_stop,
-        .cache_map      = &xscale_perf_cache_map,
-        .event_map      = &xscale_perf_map,
-        .raw_event_mask = 0xFF,
+        .map_event      = xscale_map_event,
         .num_events     = 3,
         .max_period     = (1LLU << 32) - 1,
 };
 
-static const struct arm_pmu *__init xscale1pmu_init(void)
+static struct arm_pmu *__init xscale1pmu_init(void)
 {
         return &xscale1pmu;
 }
@@ -560,7 +565,7 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
 {
         unsigned long pmnc, of_flags;
         struct perf_sample_data data;
-        struct cpu_hw_events *cpuc;
+        struct pmu_hw_events *cpuc;
         struct pt_regs *regs;
         int idx;
 
@@ -581,13 +586,10 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
         perf_sample_data_init(&data, 0);
 
         cpuc = &__get_cpu_var(cpu_hw_events);
-        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+        for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
                 struct perf_event *event = cpuc->events[idx];
                 struct hw_perf_event *hwc;
 
-                if (!test_bit(idx, cpuc->active_mask))
-                        continue;
-
                 if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx))
                         continue;
 
@@ -598,7 +600,7 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
                         continue;
 
                 if (perf_event_overflow(event, &data, regs))
-                        armpmu->disable(hwc, idx);
+                        cpu_pmu->disable(hwc, idx);
         }
 
         irq_work_run();
@@ -616,6 +618,7 @@ static void
 xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
 {
         unsigned long flags, ien, evtsel;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
         ien = xscale2pmu_read_int_enable();
         evtsel = xscale2pmu_read_event_select();
@@ -649,16 +652,17 @@ xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
                 return;
         }
 
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
         xscale2pmu_write_event_select(evtsel);
         xscale2pmu_write_int_enable(ien);
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static void
 xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
 {
         unsigned long flags, ien, evtsel;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
         ien = xscale2pmu_read_int_enable();
         evtsel = xscale2pmu_read_event_select();
@@ -692,14 +696,14 @@ xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
                 return;
         }
 
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
         xscale2pmu_write_event_select(evtsel);
         xscale2pmu_write_int_enable(ien);
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static int
-xscale2pmu_get_event_idx(struct cpu_hw_events *cpuc,
+xscale2pmu_get_event_idx(struct pmu_hw_events *cpuc,
                         struct hw_perf_event *event)
 {
         int idx = xscale1pmu_get_event_idx(cpuc, event);
@@ -718,24 +722,26 @@ static void
 xscale2pmu_start(void)
 {
         unsigned long flags, val;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
         val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64;
         val |= XSCALE_PMU_ENABLE;
         xscale2pmu_write_pmnc(val);
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static void
 xscale2pmu_stop(void)
 {
         unsigned long flags, val;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
-        raw_spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
         val = xscale2pmu_read_pmnc();
         val &= ~XSCALE_PMU_ENABLE;
         xscale2pmu_write_pmnc(val);
-        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static inline u32
@@ -786,7 +792,7 @@ xscale2pmu_write_counter(int counter, u32 val)
         }
 }
 
-static const struct arm_pmu xscale2pmu = {
+static struct arm_pmu xscale2pmu = {
         .id             = ARM_PERF_PMU_ID_XSCALE2,
         .name           = "xscale2",
         .handle_irq     = xscale2pmu_handle_irq,
@@ -797,24 +803,22 @@ static const struct arm_pmu xscale2pmu = {
         .get_event_idx  = xscale2pmu_get_event_idx,
         .start          = xscale2pmu_start,
         .stop           = xscale2pmu_stop,
-        .cache_map      = &xscale_perf_cache_map,
-        .event_map      = &xscale_perf_map,
-        .raw_event_mask = 0xFF,
+        .map_event      = xscale_map_event,
         .num_events     = 5,
         .max_period     = (1LLU << 32) - 1,
 };
 
-static const struct arm_pmu *__init xscale2pmu_init(void)
+static struct arm_pmu *__init xscale2pmu_init(void)
 {
         return &xscale2pmu;
 }
 #else
-static const struct arm_pmu *__init xscale1pmu_init(void)
+static struct arm_pmu *__init xscale1pmu_init(void)
 {
         return NULL;
 }
 
-static const struct arm_pmu *__init xscale2pmu_init(void)
+static struct arm_pmu *__init xscale2pmu_init(void)
 {
         return NULL;
 }
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
index c53474fe84df..2c3407ee8576 100644
--- a/arch/arm/kernel/pmu.c
+++ b/arch/arm/kernel/pmu.c
@@ -10,192 +10,26 @@
  *
  */
 
-#define pr_fmt(fmt) "PMU: " fmt
-
-#include <linux/cpumask.h>
 #include <linux/err.h>
-#include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
 
 #include <asm/pmu.h>
 
-static volatile long pmu_lock;
-
-static struct platform_device *pmu_devices[ARM_NUM_PMU_DEVICES];
-
-static int __devinit pmu_register(struct platform_device *pdev,
-                                        enum arm_pmu_type type)
-{
-        if (type < 0 || type >= ARM_NUM_PMU_DEVICES) {
-                pr_warning("received registration request for unknown "
-                                "PMU device type %d\n", type);
-                return -EINVAL;
-        }
-
-        if (pmu_devices[type]) {
-                pr_warning("rejecting duplicate registration of PMU device "
-                        "type %d.", type);
-                return -ENOSPC;
-        }
-
-        pr_info("registered new PMU device of type %d\n", type);
-        pmu_devices[type] = pdev;
-        return 0;
-}
-
-#define OF_MATCH_PMU(_name, _type) {    \
-        .compatible = _name,            \
-        .data = (void *)_type,          \
-}
-
-#define OF_MATCH_CPU(name)      OF_MATCH_PMU(name, ARM_PMU_DEVICE_CPU)
-
-static struct of_device_id armpmu_of_device_ids[] = {
-        OF_MATCH_CPU("arm,cortex-a9-pmu"),
-        OF_MATCH_CPU("arm,cortex-a8-pmu"),
-        OF_MATCH_CPU("arm,arm1136-pmu"),
-        OF_MATCH_CPU("arm,arm1176-pmu"),
-        {},
-};
-
-#define PLAT_MATCH_PMU(_name, _type) {  \
-        .name           = _name,        \
-        .driver_data    = _type,        \
-}
-
-#define PLAT_MATCH_CPU(_name)   PLAT_MATCH_PMU(_name, ARM_PMU_DEVICE_CPU)
-
-static struct platform_device_id armpmu_plat_device_ids[] = {
-        PLAT_MATCH_CPU("arm-pmu"),
-        {},
-};
-
-enum arm_pmu_type armpmu_device_type(struct platform_device *pdev)
-{
-        const struct of_device_id       *of_id;
-        const struct platform_device_id *pdev_id;
-
-        /* provided by of_device_id table */
-        if (pdev->dev.of_node) {
-                of_id = of_match_device(armpmu_of_device_ids, &pdev->dev);
-                BUG_ON(!of_id);
-                return (enum arm_pmu_type)of_id->data;
-        }
-
-        /* Provided by platform_device_id table */
-        pdev_id = platform_get_device_id(pdev);
-        BUG_ON(!pdev_id);
-        return pdev_id->driver_data;
-}
-
-static int __devinit armpmu_device_probe(struct platform_device *pdev)
-{
-        return pmu_register(pdev, armpmu_device_type(pdev));
-}
-
-static struct platform_driver armpmu_driver = {
-        .driver         = {
-                .name   = "arm-pmu",
-                .of_match_table = armpmu_of_device_ids,
-        },
-        .probe          = armpmu_device_probe,
-        .id_table       = armpmu_plat_device_ids,
-};
-
-static int __init register_pmu_driver(void)
-{
-        return platform_driver_register(&armpmu_driver);
-}
-device_initcall(register_pmu_driver);
+/*
+ * PMU locking to ensure mutual exclusion between different subsystems.
+ */
+static unsigned long pmu_lock[BITS_TO_LONGS(ARM_NUM_PMU_DEVICES)];
 
-struct platform_device *
+int
 reserve_pmu(enum arm_pmu_type type)
 {
-        struct platform_device *pdev;
-
-        if (test_and_set_bit_lock(type, &pmu_lock)) {
-                pdev = ERR_PTR(-EBUSY);
-        } else if (pmu_devices[type] == NULL) {
-                clear_bit_unlock(type, &pmu_lock);
-                pdev = ERR_PTR(-ENODEV);
-        } else {
-                pdev = pmu_devices[type];
-        }
-
-        return pdev;
+        return test_and_set_bit_lock(type, pmu_lock) ? -EBUSY : 0;
 }
 EXPORT_SYMBOL_GPL(reserve_pmu);
 
-int
+void
 release_pmu(enum arm_pmu_type type)
 {
-        if (WARN_ON(!pmu_devices[type]))
-                return -EINVAL;
-        clear_bit_unlock(type, &pmu_lock);
-        return 0;
-}
-EXPORT_SYMBOL_GPL(release_pmu);
-
-static int
-set_irq_affinity(int irq,
-                 unsigned int cpu)
-{
-#ifdef CONFIG_SMP
-        int err = irq_set_affinity(irq, cpumask_of(cpu));
-        if (err)
-                pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
-                           irq, cpu);
-        return err;
-#else
-        return -EINVAL;
-#endif
-}
-
-static int
-init_cpu_pmu(void)
-{
-        int i, irqs, err = 0;
-        struct platform_device *pdev = pmu_devices[ARM_PMU_DEVICE_CPU];
-
-        if (!pdev)
-                return -ENODEV;
-
-        irqs = pdev->num_resources;
-
-        /*
-         * If we have a single PMU interrupt that we can't shift, assume that
-         * we're running on a uniprocessor machine and continue.
-         */
-        if (irqs == 1 && !irq_can_set_affinity(platform_get_irq(pdev, 0)))
-                return 0;
-
-        for (i = 0; i < irqs; ++i) {
-                err = set_irq_affinity(platform_get_irq(pdev, i), i);
-                if (err)
-                        break;
-        }
-
-        return err;
-}
-
-int
-init_pmu(enum arm_pmu_type type)
-{
-        int err = 0;
-
-        switch (type) {
-        case ARM_PMU_DEVICE_CPU:
-                err = init_cpu_pmu();
-                break;
-        default:
-                pr_warning("attempt to initialise PMU of unknown "
-                           "type %d\n", type);
-                err = -EINVAL;
-        }
-
-        return err;
+        clear_bit_unlock(type, pmu_lock);
 }
-EXPORT_SYMBOL_GPL(init_pmu);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index e514c76043b4..6136144f8f8d 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -820,25 +820,8 @@ static struct machine_desc * __init setup_machine_tags(unsigned int nr)
 
         if (__atags_pointer)
                 tags = phys_to_virt(__atags_pointer);
-        else if (mdesc->boot_params) {
-#ifdef CONFIG_MMU
-                /*
-                 * We still are executing with a minimal MMU mapping created
-                 * with the presumption that the machine default for this
-                 * is located in the first MB of RAM.  Anything else will
-                 * fault and silently hang the kernel at this point.
-                 */
-                if (mdesc->boot_params < PHYS_OFFSET ||
-                    mdesc->boot_params >= PHYS_OFFSET + SZ_1M) {
-                        printk(KERN_WARNING
-                               "Default boot params at physical 0x%08lx out of reach\n",
-                               mdesc->boot_params);
-                } else
-#endif
-                {
-                        tags = phys_to_virt(mdesc->boot_params);
-                }
-        }
+        else if (mdesc->atag_offset)
+                tags = (void *)(PAGE_OFFSET + mdesc->atag_offset);
 
 #if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
         /*
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index dc902f2c6845..020e99c845e7 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -8,92 +8,61 @@
         .text
 
 /*
- * Save CPU state for a suspend
- *  r1 = v:p offset
- *  r2 = suspend function arg0
- *  r3 = suspend function
+ * Save CPU state for a suspend.  This saves the CPU general purpose
+ * registers, and allocates space on the kernel stack to save the CPU
+ * specific registers and some other data for resume.
+ *  r0 = suspend function arg0
+ *  r1 = suspend function
  */
 ENTRY(__cpu_suspend)
         stmfd   sp!, {r4 - r11, lr}
 #ifdef MULTI_CPU
         ldr     r10, =processor
-        ldr     r5, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
-        ldr     ip, [r10, #CPU_DO_RESUME] @ virtual resume function
+        ldr     r4, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
 #else
-        ldr     r5, =cpu_suspend_size
-        ldr     ip, =cpu_do_resume
+        ldr     r4, =cpu_suspend_size
 #endif
-        mov     r6, sp                  @ current virtual SP
-        sub     sp, sp, r5              @ allocate CPU state on stack
-        mov     r0, sp                  @ save pointer to CPU save block
-        add     ip, ip, r1              @ convert resume fn to phys
-        stmfd   sp!, {r1, r6, ip}       @ save v:p, virt SP, phys resume fn
-        ldr     r5, =sleep_save_sp
-        add     r6, sp, r1              @ convert SP to phys
-        stmfd   sp!, {r2, r3}           @ save suspend func arg and pointer
+        mov     r5, sp                  @ current virtual SP
+        add     r4, r4, #12             @ Space for pgd, virt sp, phys resume fn
+        sub     sp, sp, r4              @ allocate CPU state on stack
+        stmfd   sp!, {r0, r1}           @ save suspend func arg and pointer
+        add     r0, sp, #8              @ save pointer to save block
+        mov     r1, r4                  @ size of save block
+        mov     r2, r5                  @ virtual SP
+        ldr     r3, =sleep_save_sp
 #ifdef CONFIG_SMP
         ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
         ALT_UP(mov lr, #0)
         and     lr, lr, #15
-        str     r6, [r5, lr, lsl #2]    @ save phys SP
-#else
-        str     r6, [r5]                @ save phys SP
-#endif
-#ifdef MULTI_CPU
-        mov     lr, pc
-        ldr     pc, [r10, #CPU_DO_SUSPEND] @ save CPU state
-#else
-        bl      cpu_do_suspend
-#endif
-
-        @ flush data cache
-#ifdef MULTI_CACHE
-        ldr     r10, =cpu_cache
-        mov     lr, pc
-        ldr     pc, [r10, #CACHE_FLUSH_KERN_ALL]
-#else
-        bl      __cpuc_flush_kern_all
+        add     r3, r3, lr, lsl #2
 #endif
+        bl      __cpu_suspend_save
         adr     lr, BSYM(cpu_suspend_abort)
         ldmfd   sp!, {r0, pc}           @ call suspend fn
 ENDPROC(__cpu_suspend)
         .ltorg
 
 cpu_suspend_abort:
-        ldmia   sp!, {r1 - r3}          @ pop v:p, virt SP, phys resume fn
+        ldmia   sp!, {r1 - r3}          @ pop phys pgd, virt SP, phys resume fn
+        teq     r0, #0
+        moveq   r0, #1                  @ force non-zero value
         mov     sp, r2
         ldmfd   sp!, {r4 - r11, pc}
 ENDPROC(cpu_suspend_abort)
 
 /*
  * r0 = control register value
- * r1 = v:p offset (preserved by cpu_do_resume)
- * r2 = phys page table base
- * r3 = L1 section flags
  */
+        .align  5
 ENTRY(cpu_resume_mmu)
-        adr     r4, cpu_resume_turn_mmu_on
-        mov     r4, r4, lsr #20
-        orr     r3, r3, r4, lsl #20
-        ldr     r5, [r2, r4, lsl #2]    @ save old mapping
-        str     r3, [r2, r4, lsl #2]    @ setup 1:1 mapping for mmu code
-        sub     r2, r2, r1
         ldr     r3, =cpu_resume_after_mmu
-        bic     r1, r0, #CR_C           @ ensure D-cache is disabled
-        b       cpu_resume_turn_mmu_on
-ENDPROC(cpu_resume_mmu)
-        .ltorg
-        .align  5
-cpu_resume_turn_mmu_on:
-        mcr     p15, 0, r1, c1, c0, 0   @ turn on MMU, I-cache, etc
-        mrc     p15, 0, r1, c0, c0, 0   @ read id reg
-        mov     r1, r1
-        mov     r1, r1
+        mcr     p15, 0, r0, c1, c0, 0   @ turn on MMU, I-cache, etc
+        mrc     p15, 0, r0, c0, c0, 0   @ read id reg
+        mov     r0, r0
+        mov     r0, r0
         mov     pc, r3                  @ jump to virtual address
-ENDPROC(cpu_resume_turn_mmu_on)
+ENDPROC(cpu_resume_mmu)
 cpu_resume_after_mmu:
-        str     r5, [r2, r4, lsl #2]    @ restore old mapping
-        mcr     p15, 0, r0, c1, c0, 0   @ turn on D-cache
         bl      cpu_init                @ restore the und/abt/irq banked regs
         mov     r0, #0                  @ return zero on success
         ldmfd   sp!, {r4 - r11, pc}
@@ -119,7 +88,7 @@ ENTRY(cpu_resume)
         ldr     r0, sleep_save_sp       @ stack phys addr
 #endif
         setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1  @ set SVC, irqs off
-        @ load v:p, stack, resume fn
+        @ load phys pgd, stack, resume fn
   ARM(  ldmia   r0!, {r1, sp, pc}       )
 THUMB(  ldmia   r0!, {r1, r2, r3}       )
 THUMB(  mov     sp, r2                  )
diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c
new file mode 100644
index 000000000000..93a22d282c16
--- /dev/null
+++ b/arch/arm/kernel/suspend.c
@@ -0,0 +1,72 @@
+#include <linux/init.h>
+
+#include <asm/pgalloc.h>
+#include <asm/pgtable.h>
+#include <asm/memory.h>
+#include <asm/suspend.h>
+#include <asm/tlbflush.h>
+
+static pgd_t *suspend_pgd;
+
+extern int __cpu_suspend(unsigned long, int (*)(unsigned long));
+extern void cpu_resume_mmu(void);
+
+/*
+ * This is called by __cpu_suspend() to save the state, and do whatever
+ * flushing is required to ensure that when the CPU goes to sleep we have
+ * the necessary data available when the caches are not searched.
+ */
+void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
+{
+        *save_ptr = virt_to_phys(ptr);
+
+        /* This must correspond to the LDM in cpu_resume() assembly */
+        *ptr++ = virt_to_phys(suspend_pgd);
+        *ptr++ = sp;
+        *ptr++ = virt_to_phys(cpu_do_resume);
+
+        cpu_do_suspend(ptr);
+
+        flush_cache_all();
+        outer_clean_range(*save_ptr, *save_ptr + ptrsz);
+        outer_clean_range(virt_to_phys(save_ptr),
+                          virt_to_phys(save_ptr) + sizeof(*save_ptr));
+}
+
+/*
+ * Hide the first two arguments to __cpu_suspend - these are an implementation
+ * detail which platform code shouldn't have to know about.
+ */
+int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
+{
+        struct mm_struct *mm = current->active_mm;
+        int ret;
+
+        if (!suspend_pgd)
+                return -EINVAL;
+
+        /*
+         * Provide a temporary page table with an identity mapping for
+         * the MMU-enable code, required for resuming.  On successful
+         * resume (indicated by a zero return code), we need to switch
+         * back to the correct page tables.
+         */
+        ret = __cpu_suspend(arg, fn);
+        if (ret == 0) {
+                cpu_switch_mm(mm->pgd, mm);
+                local_flush_tlb_all();
+        }
+
+        return ret;
+}
+
+static int __init cpu_suspend_init(void)
+{
+        suspend_pgd = pgd_alloc(&init_mm);
+        if (suspend_pgd) {
+                unsigned long addr = virt_to_phys(cpu_resume_mmu);
+                identity_mapping_add(suspend_pgd, addr, addr + SECTION_SIZE);
+        }
+        return suspend_pgd ? 0 : -ENOMEM;
+}
+core_initcall(cpu_suspend_init);
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index e04c5fb6f1ee..1532b508c814 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -12,6 +12,7 @@
 
 #include <linux/module.h>
 #include <linux/pm.h>
+#include <linux/dma-mapping.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -319,6 +320,7 @@ static void at91sam9g45_poweroff(void)
 static void __init at91sam9g45_map_io(void)
 {
         at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
+        init_consistent_dma_size(SZ_4M);
 }
 
 static void __init at91sam9g45_initialize(void)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 2c611b9a0138..406bb6496805 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -128,8 +128,6 @@
 #define AT91SAM9G45_EHCI_BASE   0x00800000      /* USB Host controller (EHCI) */
 #define AT91SAM9G45_VDEC_BASE   0x00900000      /* Video Decoder Controller */
 
-#define CONSISTENT_DMA_SIZE     SZ_4M
-
 /*
  * DMA peripheral identifiers
  * for hardware handshaking interface
diff --git a/arch/arm/mach-bcmring/include/mach/memory.h b/arch/arm/mach-bcmring/include/mach/memory.h
index 15162e4c75f9..8848a5bb3445 100644
--- a/arch/arm/mach-bcmring/include/mach/memory.h
+++ b/arch/arm/mach-bcmring/include/mach/memory.h
@@ -25,9 +25,4 @@
 
 #define PLAT_PHYS_OFFSET CFG_GLOBAL_RAM_BASE
 
-/*
- * Maximum DMA memory allowed is 14M
- */
-#define CONSISTENT_DMA_SIZE (SZ_16M - SZ_2M)
-
 #endif
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
index 0f1c37e4523a..8616876abb9f 100644
--- a/arch/arm/mach-bcmring/mm.c
+++ b/arch/arm/mach-bcmring/mm.c
@@ -13,6 +13,7 @@
 *****************************************************************************/
 
 #include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
 #include <asm/mach/map.h>
 
 #include <mach/hardware.h>
@@ -53,4 +54,6 @@ void __init bcmring_map_io(void)
 {
 
         iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc));
+        /* Maximum DMA memory allowed is 14M */
+        init_consistent_dma_size(14 << 20);
 }
diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c
index 4a74b2c959bd..0276091b7f86 100644
--- a/arch/arm/mach-clps711x/autcpu12.c
+++ b/arch/arm/mach-clps711x/autcpu12.c
@@ -64,7 +64,7 @@ void __init autcpu12_map_io(void)
 
 MACHINE_START(AUTCPU12, "autronix autcpu12")
         /* Maintainer: Thomas Gleixner */
-        .boot_params    = 0xc0020000,
+        .atag_offset    = 0x20000,
         .map_io         = autcpu12_map_io,
         .init_irq       = clps711x_init_irq,
         .timer          = &clps711x_timer,
diff --git a/arch/arm/mach-clps711x/cdb89712.c b/arch/arm/mach-clps711x/cdb89712.c
index 5a1689d48793..25b3bfd0e85a 100644
--- a/arch/arm/mach-clps711x/cdb89712.c
+++ b/arch/arm/mach-clps711x/cdb89712.c
@@ -55,7 +55,7 @@ static void __init cdb89712_map_io(void)
 
 MACHINE_START(CDB89712, "Cirrus-CDB89712")
         /* Maintainer: Ray Lehtiniemi */
-        .boot_params    = 0xc0000100,
+        .atag_offset    = 0x100,
         .map_io         = cdb89712_map_io,
         .init_irq       = clps711x_init_irq,
         .timer          = &clps711x_timer,
diff --git a/arch/arm/mach-clps711x/ceiva.c b/arch/arm/mach-clps711x/ceiva.c
index 16481cf3e931..1df9ec67aa92 100644
--- a/arch/arm/mach-clps711x/ceiva.c
+++ b/arch/arm/mach-clps711x/ceiva.c
@@ -56,7 +56,7 @@ static void __init ceiva_map_io(void)
 
 MACHINE_START(CEIVA, "CEIVA/Polaroid Photo MAX Digital Picture Frame")
         /* Maintainer: Rob Scott */
-        .boot_params    = 0xc0000100,
+        .atag_offset    = 0x100,
         .map_io         = ceiva_map_io,
         .init_irq       = clps711x_init_irq,
         .timer          = &clps711x_timer,
diff --git a/arch/arm/mach-clps711x/clep7312.c b/arch/arm/mach-clps711x/clep7312.c
index 67b5abb4a60a..06c8abd9371f 100644
--- a/arch/arm/mach-clps711x/clep7312.c
+++ b/arch/arm/mach-clps711x/clep7312.c
@@ -37,7 +37,7 @@ fixup_clep7312(struct machine_desc *desc, struct tag *tags,
 
 MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
         /* Maintainer: Nobody */
-        .boot_params    = 0xc0000100,
+        .atag_offset    = 0x0100,
         .fixup          = fixup_clep7312,
         .map_io         = clps711x_map_io,
         .init_irq       = clps711x_init_irq,
diff --git a/arch/arm/mach-clps711x/edb7211-arch.c b/arch/arm/mach-clps711x/edb7211-arch.c
index 98ca5b2e940d..abf522d1ec9b 100644
--- a/arch/arm/mach-clps711x/edb7211-arch.c
+++ b/arch/arm/mach-clps711x/edb7211-arch.c
@@ -57,7 +57,7 @@ fixup_edb7211(struct machine_desc *desc, struct tag *tags,
 
 MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
         /* Maintainer: Jon McClintock */
-        .boot_params    = 0xc0020100,   /* 0xc0000000 - 0xc001ffff can be video RAM */
+        .atag_offset    = 0x20100,      /* 0xc0000000 - 0xc001ffff can be video RAM */
         .fixup          = fixup_edb7211,
         .map_io         = edb7211_map_io,
         .reserve        = edb7211_reserve,
diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/fortunet.c
index b1cb479e71e9..b6f7d86bb1c9 100644
--- a/arch/arm/mach-clps711x/fortunet.c
+++ b/arch/arm/mach-clps711x/fortunet.c
@@ -75,7 +75,6 @@ fortunet_fixup(struct machine_desc *desc, struct tag *tags,
 
 MACHINE_START(FORTUNET, "ARM-FortuNet")
         /* Maintainer: FortuNet Inc. */
-        .boot_params    = 0x00000000,
         .fixup          = fortunet_fixup,
         .map_io         = clps711x_map_io,
         .init_irq       = clps711x_init_irq,
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index cefbce0480b9..e7f75aeb1e5b 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -89,7 +89,7 @@ static void __init p720t_map_io(void)
 
 MACHINE_START(P720T, "ARM-Prospector720T")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .boot_params    = 0xc0000100,
+        .atag_offset    = 0x100,
         .fixup          = fixup_p720t,
         .map_io         = p720t_map_io,
         .init_irq       = clps711x_init_irq,
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 3e7d1496cb47..55f7b4b08ab9 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -197,7 +197,7 @@ static void __init cns3420_map_io(void)
 }
 
 MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = cns3420_map_io,
         .init_irq       = cns3xxx_init_irq,
         .timer          = &cns3xxx_timer,
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 84fd78684868..26d94c0b555c 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -676,7 +676,7 @@ static void __init da830_evm_map_io(void)
 }
 
 MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
-        .boot_params    = (DA8XX_DDR_BASE + 0x100),
+        .atag_offset    = 0x100,
         .map_io         = da830_evm_map_io,
         .init_irq       = cp_intc_init,
         .timer          = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 008d51407cd7..6e41cb5baeb4 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -1291,7 +1291,7 @@ static void __init da850_evm_map_io(void)
 }
 
 MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
-        .boot_params    = (DA8XX_DDR_BASE + 0x100),
+        .atag_offset    = 0x100,
         .map_io         = da850_evm_map_io,
         .init_irq       = cp_intc_init,
         .timer          = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 241a6bd67408..65566280b7c9 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -351,7 +351,7 @@ static __init void dm355_evm_init(void)
 }
 
 MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
-        .boot_params  = (0x80000100),
+        .atag_offset  = 0x100,
         .map_io       = dm355_evm_map_io,
         .init_irq     = davinci_irq_init,
         .timer        = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index bee284ca7fd6..b307470b071d 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -270,7 +270,7 @@ static __init void dm355_leopard_init(void)
 }
 
 MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
-        .boot_params  = (0x80000100),
+        .atag_offset  = 0x100,
         .map_io       = dm355_leopard_map_io,
         .init_irq     = davinci_irq_init,
         .timer        = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 9818f214d4f0..04c43abcca66 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -612,7 +612,7 @@ static __init void dm365_evm_init(void)
 }
 
 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
-        .boot_params    = (0x80000100),
+        .atag_offset    = 0x100,
         .map_io         = dm365_evm_map_io,
         .init_irq       = davinci_irq_init,
         .timer          = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 95607a191e03..a005e7691ddd 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -712,7 +712,7 @@ static __init void davinci_evm_init(void)
 
 MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
         /* Maintainer: MontaVista Software <source@mvista.com> */
-        .boot_params  = (DAVINCI_DDR_BASE + 0x100),
+        .atag_offset  = 0x100,
         .map_io       = davinci_evm_map_io,
         .init_irq     = davinci_irq_init,
         .timer        = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 993a3146fd35..337c45e3e44d 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -792,7 +792,7 @@ static __init void evm_init(void)
 }
 
 MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
-        .boot_params  = (0x80000100),
+        .atag_offset  = 0x100,
         .map_io       = davinci_map_io,
         .init_irq     = davinci_irq_init,
         .timer        = &davinci_timer,
@@ -801,7 +801,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
 MACHINE_END
 
 MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
-        .boot_params  = (0x80000100),
+        .atag_offset  = 0x100,
         .map_io       = davinci_map_io,
         .init_irq     = davinci_irq_init,
         .timer        = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index c278226627ad..6efc84cceca0 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -566,7 +566,7 @@ static void __init mityomapl138_map_io(void)
 }
 
 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
-        .boot_params    = (DA8XX_DDR_BASE + 0x100),
+        .atag_offset    = 0x100,
         .map_io         = mityomapl138_map_io,
         .init_irq       = cp_intc_init,
         .timer          = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index d60a80028ba3..38d6f644d8b9 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -272,7 +272,7 @@ static __init void davinci_ntosd2_init(void)
 
 MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
         /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
-        .boot_params    = (DAVINCI_DDR_BASE + 0x100),
+        .atag_offset    = 0x100,
         .map_io          = davinci_ntosd2_map_io,
         .init_irq       = davinci_irq_init,
         .timer          = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 237332a11421..c6701e4a795c 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -338,7 +338,7 @@ static void __init omapl138_hawk_map_io(void)
 }
 
 MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
-        .boot_params    = (DA8XX_DDR_BASE + 0x100),
+        .atag_offset    = 0x100,
         .map_io         = omapl138_hawk_map_io,
         .init_irq       = cp_intc_init,
         .timer          = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 5f4385c0a089..5dd4da9d2308 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -151,7 +151,7 @@ static __init void davinci_sffsdr_init(void)
 
 MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
         /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */
-        .boot_params  = (DAVINCI_DDR_BASE + 0x100),
+        .atag_offset  = 0x100,
         .map_io       = davinci_sffsdr_map_io,
         .init_irq     = davinci_irq_init,
         .timer        = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index 782892065682..90ee7b5aabdc 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -277,7 +277,7 @@ console_initcall(tnetv107x_evm_console_init);
 #endif
 
 MACHINE_START(TNETV107X, "TNETV107X EVM")
-        .boot_params    = (TNETV107X_DDR_BASE + 0x100),
+        .atag_offset    = 0x100,
         .map_io         = tnetv107x_init,
         .init_irq       = cp_intc_init,
         .timer          = &davinci_timer,
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 1d2557394235..865ffe5899ac 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -12,6 +12,7 @@
 #include <linux/io.h>
 #include <linux/etherdevice.h>
 #include <linux/davinci_emac.h>
+#include <linux/dma-mapping.h>
 
 #include <asm/tlb.h>
 #include <asm/mach/map.h>
@@ -86,6 +87,8 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
                 iotable_init(davinci_soc_info.io_desc,
                                 davinci_soc_info.io_desc_num);
 
+        init_consistent_dma_size(14 << 20);
+
         /*
          * Normally devicemaps_init() would flush caches and tlb after
          * mdesc->map_io(), but we must also do it here because of the CPU
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 2f7e719636f1..68def7188868 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -136,6 +136,7 @@ static struct edma_soc_info da830_edma_cc0_info = {
         .n_cc                   = 1,
         .queue_tc_mapping       = da8xx_queue_tc_mapping,
         .queue_priority_mapping = da8xx_queue_priority_mapping,
+        .default_queue          = EVENTQ_1,
 };
 
 static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
@@ -151,6 +152,7 @@ static struct edma_soc_info da850_edma_cc_info[] = {
                 .n_cc                   = 1,
                 .queue_tc_mapping       = da8xx_queue_tc_mapping,
                 .queue_priority_mapping = da8xx_queue_priority_mapping,
+                .default_queue          = EVENTQ_1,
         },
         {
                 .n_channel              = 32,
@@ -160,6 +162,7 @@ static struct edma_soc_info da850_edma_cc_info[] = {
                 .n_cc                   = 1,
                 .queue_tc_mapping       = da850_queue_tc_mapping,
                 .queue_priority_mapping = da850_queue_priority_mapping,
+                .default_queue          = EVENTQ_0,
         },
 };
 
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 6162cae7f868..29b17f7d3a5f 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -80,6 +80,7 @@ static struct edma_soc_info edma_cc0_info = {
         .n_cc                   = 1,
         .queue_tc_mapping       = edma_tc_mapping,
         .queue_priority_mapping = edma_priority_mapping,
+        .default_queue          = EVENTQ_1,
 };
 
 static struct edma_soc_info *tnetv107x_edma_info[EDMA_MAX_CC] = {
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index a3a94e9c9378..68fb18162459 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -591,6 +591,7 @@ static struct edma_soc_info edma_cc0_info = {
         .n_cc                   = 1,
         .queue_tc_mapping       = queue_tc_mapping,
         .queue_priority_mapping = queue_priority_mapping,
+        .default_queue          = EVENTQ_1,
 };
 
 static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = {
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 4c82c2716293..555ff5bdb220 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -514,6 +514,7 @@ static struct edma_soc_info edma_cc0_info = {
         .n_cc                   = 1,
         .queue_tc_mapping       = queue_tc_mapping,
         .queue_priority_mapping = queue_priority_mapping,
+        .default_queue          = EVENTQ_1,
 };
 
 static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = {
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 1802e711a2b8..b0c350a02484 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -555,6 +555,7 @@ static struct edma_soc_info edma_cc0_info = {
         .n_cc                   = 1,
         .queue_tc_mapping       = dm646x_queue_tc_mapping,
         .queue_priority_mapping = dm646x_queue_priority_mapping,
+        .default_queue          = EVENTQ_1,
 };
 
 static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 6b9669869c46..da90103a313d 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -1435,12 +1435,11 @@ static int __init edma_probe(struct platform_device *pdev)
                         goto fail1;
                 }
 
-                edma_cc[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
+                edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);
                 if (!edma_cc[j]) {
                         status = -ENOMEM;
                         goto fail1;
                 }
-                memset(edma_cc[j], 0, sizeof(struct edma));
 
                 edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
                                                         EDMA_MAX_DMACH);
@@ -1450,8 +1449,6 @@ static int __init edma_probe(struct platform_device *pdev)
                                                         EDMA_MAX_CC);
 
                 edma_cc[j]->default_queue = info[j]->default_queue;
-                if (!edma_cc[j]->default_queue)
-                        edma_cc[j]->default_queue = EVENTQ_1;
 
                 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
                         edmacc_regs_base[j]);
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index 78731944a70c..885d23319668 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -36,9 +36,4 @@
 #define DDR2_MCLKSTOPEN_BIT     BIT(30)
 #define DDR2_LPMODEN_BIT        BIT(31)
 
-/*
- * Increase size of DMA-consistent memory region
- */
-#define CONSISTENT_DMA_SIZE (14<<20)
-
 #endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
index 03e11f9dca97..c8a406f7e946 100644
--- a/arch/arm/mach-dove/cm-a510.c
+++ b/arch/arm/mach-dove/cm-a510.c
@@ -87,7 +87,7 @@ static void __init cm_a510_init(void)
 }
 
 MACHINE_START(CM_A510, "Compulab CM-A510 Board")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = cm_a510_init,
         .map_io         = dove_map_io,
         .init_early     = dove_init_early,
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index 2ac34ecfa745..11ea34e4fc76 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -94,7 +94,7 @@ static void __init dove_db_init(void)
 }
 
 MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = dove_db_init,
         .map_io         = dove_map_io,
         .init_early     = dove_init_early,
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 087bc771ac23..d0ce8abdd4b6 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -280,7 +280,7 @@ arch_initcall(ebsa110_init);
 
 MACHINE_START(EBSA110, "EBSA110")
         /* Maintainer: Russell King */
-        .boot_params    = 0x00000400,
+        .atag_offset    = 0x400,
         .reserve_lp0    = 1,
         .reserve_lp2    = 1,
         .soft_reboot    = 1,
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 61b98ce4b673..0713448206a5 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -33,7 +33,7 @@ static void __init adssphere_init_machine(void)
 
 MACHINE_START(ADSSPHERE, "ADS Sphere board")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 9969bb115f60..257175edc575 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -240,7 +240,7 @@ static void __init edb93xx_init_machine(void)
 #ifdef CONFIG_MACH_EDB9301
 MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board")
         /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
-        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
@@ -251,7 +251,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_EDB9302
 MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
         /* Maintainer: George Kashperko <george@chas.com.ua> */
-        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
@@ -262,7 +262,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_EDB9302A
 MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
@@ -273,7 +273,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_EDB9307
 MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
         /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
-        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
@@ -284,7 +284,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_EDB9307A
 MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
         /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
-        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
@@ -295,7 +295,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_EDB9312
 MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
         /* Maintainer: Toufeeq Hussain <toufeeq_hussain@infosys.com> */
-        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
@@ -306,7 +306,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_EDB9315
 MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
@@ -317,7 +317,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_EDB9315A
 MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index 9bd3152bff9a..45ee205856f8 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -33,7 +33,7 @@ static void __init gesbc9312_init_machine(void)
 
 MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 7adea6258efe..e72f7368876e 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -77,7 +77,7 @@ static void __init micro9_init_machine(void)
 #ifdef CONFIG_MACH_MICRO9H
 MACHINE_START(MICRO9, "Contec Micro9-High")
         /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
-        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
@@ -88,7 +88,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_MICRO9M
 MACHINE_START(MICRO9M, "Contec Micro9-Mid")
         /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
-        .boot_params    = EP93XX_SDCE3_PHYS_BASE_ASYNC + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
@@ -99,7 +99,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_MICRO9L
 MACHINE_START(MICRO9L, "Contec Micro9-Lite")
         /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
-        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
@@ -110,7 +110,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_MICRO9S
 MACHINE_START(MICRO9S, "Contec Micro9-Slim")
         /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
-        .boot_params    = EP93XX_SDCE3_PHYS_BASE_ASYNC + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index 8392e95d7cea..238bc603da86 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -65,8 +65,8 @@ static void __init simone_init_machine(void)
 }
 
 MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
-/* Maintainer: Ryan Mallon */
-        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
+        /* Maintainer: Ryan Mallon */
+        .atag_offset    = 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index 2e9c614757e4..3bdf3a2e5ad0 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -163,7 +163,7 @@ static void __init snappercl15_init_machine(void)
 
 MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
         /* Maintainer: Ryan Mallon */
-        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index c2d2cf40ead9..1ade3c340507 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -257,7 +257,7 @@ static void __init ts72xx_init_machine(void)
 
 MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ts72xx_map_io,
         .init_irq       = ep93xx_init_irq,
         .timer          = &ep93xx_timer,
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 0c77ab99fa16..bee8f77de2ab 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -113,22 +113,7 @@ menu "EXYNOS4 Machines"
 
 config MACH_SMDKC210
         bool "SMDKC210"
-        select CPU_EXYNOS4210
-        select S5P_DEV_FIMD0
-        select S3C_DEV_RTC
-        select S3C_DEV_WDT
-        select S3C_DEV_I2C1
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select SAMSUNG_DEV_PWM
-        select SAMSUNG_DEV_BACKLIGHT
-        select EXYNOS4_DEV_PD
-        select EXYNOS4_DEV_SYSMMU
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_I2C1
-        select EXYNOS4_SETUP_SDHCI
+        select MACH_SMDKV310
         help
           Machine support for Samsung SMDKC210
 
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index b7fe1d7b0b1f..e3e93ea41385 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -25,7 +25,7 @@ obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
 
 # machine support
 
-obj-$(CONFIG_MACH_SMDKC210)             += mach-smdkc210.o
+obj-$(CONFIG_MACH_SMDKC210)             += mach-smdkv310.o
 obj-$(CONFIG_MACH_SMDKV310)             += mach-smdkv310.o
 obj-$(CONFIG_MACH_ARMLEX4210)           += mach-armlex4210.o
 obj-$(CONFIG_MACH_UNIVERSAL_C210)       += mach-universal_c210.o
diff --git a/arch/arm/mach-exynos4/mach-armlex4210.c b/arch/arm/mach-exynos4/mach-armlex4210.c
index b482c6285fc4..f0ca6c157d29 100644
--- a/arch/arm/mach-exynos4/mach-armlex4210.c
+++ b/arch/arm/mach-exynos4/mach-armlex4210.c
@@ -207,7 +207,7 @@ static void __init armlex4210_machine_init(void)
 
 MACHINE_START(ARMLEX4210, "ARMLEX4210")
         /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
-        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
         .init_irq       = exynos4_init_irq,
         .map_io         = armlex4210_map_io,
         .init_machine   = armlex4210_machine_init,
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
index 43be71b799cb..6e0536818bf5 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -1152,7 +1152,7 @@ static void __init nuri_machine_init(void)
 
 MACHINE_START(NURI, "NURI")
         /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
-        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
         .init_irq       = exynos4_init_irq,
         .map_io         = nuri_map_io,
         .init_machine   = nuri_machine_init,
diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c
deleted file mode 100644
index a7c65e05c1eb..000000000000
--- a/arch/arm/mach-exynos4/mach-smdkc210.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-smdkc210.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/serial_core.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/lcd.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/smsc911x.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/pwm_backlight.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <video/platform_lcd.h>
-
-#include <plat/regs-serial.h>
-#include <plat/regs-srom.h>
-#include <plat/regs-fb-v4.h>
-#include <plat/exynos4.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
-#include <plat/sdhci.h>
-#include <plat/iic.h>
-#include <plat/pd.h>
-#include <plat/gpio-cfg.h>
-#include <plat/backlight.h>
-
-#include <mach/map.h>
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define SMDKC210_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define SMDKC210_ULCON_DEFAULT  S3C2410_LCON_CS8
-
-#define SMDKC210_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = SMDKC210_UCON_DEFAULT,
-                .ulcon          = SMDKC210_ULCON_DEFAULT,
-                .ufcon          = SMDKC210_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = SMDKC210_UCON_DEFAULT,
-                .ulcon          = SMDKC210_ULCON_DEFAULT,
-                .ufcon          = SMDKC210_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = SMDKC210_UCON_DEFAULT,
-                .ulcon          = SMDKC210_ULCON_DEFAULT,
-                .ufcon          = SMDKC210_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = SMDKC210_UCON_DEFAULT,
-                .ulcon          = SMDKC210_ULCON_DEFAULT,
-                .ufcon          = SMDKC210_UFCON_DEFAULT,
-        },
-};
-
-static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK0(2),
-        .ext_cd_gpio_invert     = 1,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK0(2),
-        .ext_cd_gpio_invert     = 1,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK2(2),
-        .ext_cd_gpio_invert     = 1,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK2(2),
-        .ext_cd_gpio_invert     = 1,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
-                                   unsigned int power)
-{
-        if (power) {
-#if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
-                gpio_free(EXYNOS4_GPD0(1));
-#endif
-                /* fire nRESET on power up */
-                gpio_request(EXYNOS4_GPX0(6), "GPX0");
-
-                gpio_direction_output(EXYNOS4_GPX0(6), 1);
-                mdelay(100);
-
-                gpio_set_value(EXYNOS4_GPX0(6), 0);
-                mdelay(10);
-
-                gpio_set_value(EXYNOS4_GPX0(6), 1);
-                mdelay(10);
-
-                gpio_free(EXYNOS4_GPX0(6));
-        } else {
-#if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
-                gpio_free(EXYNOS4_GPD0(1));
-#endif
-        }
-}
-
-static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
-        .set_power              = lcd_lte480wv_set_power,
-};
-
-static struct platform_device smdkc210_lcd_lte480wv = {
-        .name                   = "platform-lcd",
-        .dev.parent             = &s5p_device_fimd0.dev,
-        .dev.platform_data      = &smdkc210_lcd_lte480wv_data,
-};
-
-static struct s3c_fb_pd_win smdkc210_fb_win0 = {
-        .win_mode = {
-                .left_margin    = 13,
-                .right_margin   = 8,
-                .upper_margin   = 7,
-                .lower_margin   = 5,
-                .hsync_len      = 3,
-                .vsync_len      = 1,
-                .xres           = 800,
-                .yres           = 480,
-        },
-        .max_bpp                = 32,
-        .default_bpp            = 24,
-};
-
-static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
-        .win[0]         = &smdkc210_fb_win0,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-
-static struct resource smdkc210_smsc911x_resources[] = {
-        [0] = {
-                .start  = EXYNOS4_PA_SROM_BANK(1),
-                .end    = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_EINT(5),
-                .end    = IRQ_EINT(5),
-                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
-        },
-};
-
-static struct smsc911x_platform_config smsc9215_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-        .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
-};
-
-static struct platform_device smdkc210_smsc911x = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(smdkc210_smsc911x_resources),
-        .resource       = smdkc210_smsc911x_resources,
-        .dev            = {
-                .platform_data  = &smsc9215_config,
-        },
-};
-
-static struct i2c_board_info i2c_devs1[] __initdata = {
-        {I2C_BOARD_INFO("wm8994", 0x1a),},
-};
-
-static struct platform_device *smdkc210_devices[] __initdata = {
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc1,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_i2c1,
-        &s3c_device_rtc,
-        &s3c_device_wdt,
-        &exynos4_device_ac97,
-        &exynos4_device_i2s0,
-        &exynos4_device_pd[PD_MFC],
-        &exynos4_device_pd[PD_G3D],
-        &exynos4_device_pd[PD_LCD0],
-        &exynos4_device_pd[PD_LCD1],
-        &exynos4_device_pd[PD_CAM],
-        &exynos4_device_pd[PD_TV],
-        &exynos4_device_pd[PD_GPS],
-        &exynos4_device_sysmmu,
-        &samsung_asoc_dma,
-        &s5p_device_fimd0,
-        &smdkc210_lcd_lte480wv,
-        &smdkc210_smsc911x,
-};
-
-static void __init smdkc210_smsc911x_init(void)
-{
-        u32 cs1;
-
-        /* configure nCS1 width to 16 bits */
-        cs1 = __raw_readl(S5P_SROM_BW) &
-                ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
-        cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
-                (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
-                (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
-                S5P_SROM_BW__NCS1__SHIFT;
-        __raw_writel(cs1, S5P_SROM_BW);
-
-        /* set timing for nCS1 suitable for ethernet chip */
-        __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
-                     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
-                     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
-                     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
-}
-
-/* LCD Backlight data */
-static struct samsung_bl_gpio_info smdkc210_bl_gpio_info = {
-        .no = EXYNOS4_GPD0(1),
-        .func = S3C_GPIO_SFN(2),
-};
-
-static struct platform_pwm_backlight_data smdkc210_bl_data = {
-        .pwm_id = 1,
-        .pwm_period_ns  = 1000,
-};
-
-static void __init smdkc210_map_io(void)
-{
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
-        s3c24xx_init_clocks(24000000);
-        s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
-}
-
-static void __init smdkc210_machine_init(void)
-{
-        s3c_i2c1_set_platdata(NULL);
-        i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
-
-        smdkc210_smsc911x_init();
-
-        s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
-        s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata);
-        s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
-        s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
-
-        samsung_bl_set(&smdkc210_bl_gpio_info, &smdkc210_bl_data);
-        s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
-
-        platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
-}
-
-MACHINE_START(SMDKC210, "SMDKC210")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .boot_params    = S5P_PA_SDRAM + 0x100,
-        .init_irq       = exynos4_init_irq,
-        .map_io         = smdkc210_map_io,
-        .init_machine   = smdkc210_machine_init,
-        .timer          = &exynos4_timer,
-MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index ea4149556860..2c1a076c6a73 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -9,7 +9,9 @@
 */
 
 #include <linux/serial_core.h>
+#include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/lcd.h>
 #include <linux/mmc/host.h>
 #include <linux/platform_device.h>
 #include <linux/smsc911x.h>
@@ -21,11 +23,14 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
+#include <video/platform_lcd.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-srom.h>
+#include <plat/regs-fb-v4.h>
 #include <plat/exynos4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
+#include <plat/fb.h>
 #include <plat/keypad.h>
 #include <plat/sdhci.h>
 #include <plat/iic.h>
@@ -112,6 +117,67 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 
+static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
+                                   unsigned int power)
+{
+        if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
+                gpio_free(EXYNOS4_GPD0(1));
+#endif
+                /* fire nRESET on power up */
+                gpio_request(EXYNOS4_GPX0(6), "GPX0");
+
+                gpio_direction_output(EXYNOS4_GPX0(6), 1);
+                mdelay(100);
+
+                gpio_set_value(EXYNOS4_GPX0(6), 0);
+                mdelay(10);
+
+                gpio_set_value(EXYNOS4_GPX0(6), 1);
+                mdelay(10);
+
+                gpio_free(EXYNOS4_GPX0(6));
+        } else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
+                gpio_free(EXYNOS4_GPD0(1));
+#endif
+        }
+}
+
+static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
+        .set_power              = lcd_lte480wv_set_power,
+};
+
+static struct platform_device smdkv310_lcd_lte480wv = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s5p_device_fimd0.dev,
+        .dev.platform_data      = &smdkv310_lcd_lte480wv_data,
+};
+
+static struct s3c_fb_pd_win smdkv310_fb_win0 = {
+        .win_mode = {
+                .left_margin    = 13,
+                .right_margin   = 8,
+                .upper_margin   = 7,
+                .lower_margin   = 5,
+                .hsync_len      = 3,
+                .vsync_len      = 1,
+                .xres           = 800,
+                .yres           = 480,
+        },
+        .max_bpp                = 32,
+        .default_bpp            = 24,
+};
+
+static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
+        .win[0]         = &smdkv310_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
+};
+
 static struct resource smdkv310_smsc911x_resources[] = {
         [0] = {
                 .start  = EXYNOS4_PA_SROM_BANK(1),
@@ -188,6 +254,8 @@ static struct platform_device *smdkv310_devices[] __initdata = {
         &exynos4_device_sysmmu,
         &samsung_asoc_dma,
         &samsung_asoc_idma,
+        &s5p_device_fimd0,
+        &smdkv310_lcd_lte480wv,
         &smdkv310_smsc911x,
         &exynos4_device_ahci,
 };
@@ -248,6 +316,7 @@ static void __init smdkv310_machine_init(void)
         samsung_keypad_set_platdata(&smdkv310_keypad_data);
 
         samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
+        s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
 
         platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
 }
@@ -255,7 +324,16 @@ static void __init smdkv310_machine_init(void)
 MACHINE_START(SMDKV310, "SMDKV310")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
         /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
-        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
+        .init_irq       = exynos4_init_irq,
+        .map_io         = smdkv310_map_io,
+        .init_machine   = smdkv310_machine_init,
+        .timer          = &exynos4_timer,
+MACHINE_END
+
+MACHINE_START(SMDKC210, "SMDKC210")
+        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+        .atag_offset    = 0x100,
         .init_irq       = exynos4_init_irq,
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
index b3b5d8911004..2aac6f755c8e 100644
--- a/arch/arm/mach-exynos4/mach-universal_c210.c
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -762,7 +762,7 @@ static void __init universal_machine_init(void)
 
 MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
         /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
-        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
         .init_irq       = exynos4_init_irq,
         .map_io         = universal_map_io,
         .init_machine   = universal_machine_init,
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index 5b1a8db779be..a3da5d1106c2 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -86,7 +86,7 @@ fixup_cats(struct machine_desc *desc, struct tag *tags,
 
 MACHINE_START(CATS, "Chalice-CATS")
         /* Maintainer: Philip Blundell */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .soft_reboot    = 1,
         .fixup          = fixup_cats,
         .map_io         = footbridge_map_io,
diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c
index 2ef69ff44ba8..012210cf7d16 100644
--- a/arch/arm/mach-footbridge/ebsa285.c
+++ b/arch/arm/mach-footbridge/ebsa285.c
@@ -15,7 +15,7 @@
 
 MACHINE_START(EBSA285, "EBSA285")
         /* Maintainer: Russell King */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .video_start    = 0x000a0000,
         .video_end      = 0x000bffff,
         .map_io         = footbridge_map_io,
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index 06e514f372d0..d8c1c922e24c 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -648,7 +648,7 @@ fixup_netwinder(struct machine_desc *desc, struct tag *tags,
 
 MACHINE_START(NETWINDER, "Rebel-NetWinder")
         /* Maintainer: Russell King/Rebel.com */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .video_start    = 0x000a0000,
         .video_end      = 0x000bffff,
         .reserve_lp0    = 1,
diff --git a/arch/arm/mach-footbridge/personal.c b/arch/arm/mach-footbridge/personal.c
index 3285e91ca8c1..f41dba39b327 100644
--- a/arch/arm/mach-footbridge/personal.c
+++ b/arch/arm/mach-footbridge/personal.c
@@ -15,7 +15,7 @@
 
 MACHINE_START(PERSONAL_SERVER, "Compaq-PersonalServer")
         /* Maintainer: Jamey Hicks / George France */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = footbridge_map_io,
         .init_irq       = footbridge_init_irq,
         .timer          = &footbridge_timer,
diff --git a/arch/arm/mach-gemini/board-nas4220b.c b/arch/arm/mach-gemini/board-nas4220b.c
index 0cf7a07c3f3f..5927d3c253aa 100644
--- a/arch/arm/mach-gemini/board-nas4220b.c
+++ b/arch/arm/mach-gemini/board-nas4220b.c
@@ -102,7 +102,7 @@ static void __init ib4220b_init(void)
 }
 
 MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
-        .boot_params    = 0x100,
+        .atag_offset    = 0x100,
         .map_io         = gemini_map_io,
         .init_irq       = gemini_init_irq,
         .timer          = &ib4220b_timer,
diff --git a/arch/arm/mach-gemini/board-rut1xx.c b/arch/arm/mach-gemini/board-rut1xx.c
index 4fa09af99495..cd7437a1cea0 100644
--- a/arch/arm/mach-gemini/board-rut1xx.c
+++ b/arch/arm/mach-gemini/board-rut1xx.c
@@ -86,7 +86,7 @@ static void __init rut1xx_init(void)
 }
 
 MACHINE_START(RUT100, "Teltonika RUT100")
-        .boot_params    = 0x100,
+        .atag_offset    = 0x100,
         .map_io         = gemini_map_io,
         .init_irq       = gemini_init_irq,
         .timer          = &rut1xx_timer,
diff --git a/arch/arm/mach-gemini/board-wbd111.c b/arch/arm/mach-gemini/board-wbd111.c
index 88cc422ee444..a367880368f1 100644
--- a/arch/arm/mach-gemini/board-wbd111.c
+++ b/arch/arm/mach-gemini/board-wbd111.c
@@ -129,7 +129,7 @@ static void __init wbd111_init(void)
 }
 
 MACHINE_START(WBD111, "Wiliboard WBD-111")
-        .boot_params    = 0x100,
+        .atag_offset    = 0x100,
         .map_io         = gemini_map_io,
         .init_irq       = gemini_init_irq,
         .timer          = &wbd111_timer,
diff --git a/arch/arm/mach-gemini/board-wbd222.c b/arch/arm/mach-gemini/board-wbd222.c
index 3a220347bc88..f382811c1319 100644
--- a/arch/arm/mach-gemini/board-wbd222.c
+++ b/arch/arm/mach-gemini/board-wbd222.c
@@ -129,7 +129,7 @@ static void __init wbd222_init(void)
 }
 
 MACHINE_START(WBD222, "Wiliboard WBD-222")
-        .boot_params    = 0x100,
+        .atag_offset    = 0x100,
         .map_io         = gemini_map_io,
         .init_irq       = gemini_init_irq,
         .timer          = &wbd222_timer,
diff --git a/arch/arm/mach-h720x/h7201-eval.c b/arch/arm/mach-h720x/h7201-eval.c
index 65f1bea958e5..9886f19805f4 100644
--- a/arch/arm/mach-h720x/h7201-eval.c
+++ b/arch/arm/mach-h720x/h7201-eval.c
@@ -29,7 +29,7 @@
 
 MACHINE_START(H7201, "Hynix GMS30C7201")
         /* Maintainer: Robert Schwebel, Pengutronix */
-        .boot_params    = 0xc0001000,
+        .atag_offset    = 0x1000,
         .map_io         = h720x_map_io,
         .init_irq       = h720x_init_irq,
         .timer          = &h7201_timer,
diff --git a/arch/arm/mach-h720x/h7202-eval.c b/arch/arm/mach-h720x/h7202-eval.c
index 884584a09752..284a134819e1 100644
--- a/arch/arm/mach-h720x/h7202-eval.c
+++ b/arch/arm/mach-h720x/h7202-eval.c
@@ -71,7 +71,7 @@ static void __init init_eval_h7202(void)
 
 MACHINE_START(H7202, "Hynix HMS30C7202")
         /* Maintainer: Robert Schwebel, Pengutronix */
-        .boot_params    = 0x40000100,
+        .atag_offset    = 0x100,
         .map_io         = h720x_map_io,
         .init_irq       = h7202_init_irq,
         .timer          = &h7202_timer,
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index e9eb36dad888..6cc821384ccd 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,16 +1,15 @@
 obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
 
-obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
-obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
+obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
+obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
 
-obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o
+obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o
 
-obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
-obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
+obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
+obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
 
-obj-$(CONFIG_SOC_IMX31) += mm-imx31.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
-obj-$(CONFIG_SOC_IMX35) += mm-imx35.o cpu-imx35.o clock-imx35.o ehci-imx35.o
-obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
+obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
+obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
 
 # Support for CMOS sensor interface
 obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
diff --git a/arch/arm/mach-imx/cache-l2x0.c b/arch/arm/mach-imx/cache-l2x0.c
deleted file mode 100644
index 69d1322add3c..000000000000
--- a/arch/arm/mach-imx/cache-l2x0.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Sascha Hauer <s.hauer@pengutronix.de>
- * Juergen Beisert <j.beisert@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/kernel.h>
-
-#include <asm/hardware/cache-l2x0.h>
-
-#include <mach/hardware.h>
-
-static int mxc_init_l2x0(void)
-{
-        void __iomem *l2x0_base;
-        void __iomem *clkctl_base;
-
-        if (!cpu_is_mx31() && !cpu_is_mx35())
-                return 0;
-
-/*
- * First of all, we must repair broken chip settings. There are some
- * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
- * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
- * Workaraound is to setup the correct register setting prior enabling the
- * L2 cache. This should not hurt already working CPUs, as they are using the
- * same value.
- */
-#define L2_MEM_VAL 0x10
-
-        clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
-        if (clkctl_base != NULL) {
-                writel(0x00000515, clkctl_base + L2_MEM_VAL);
-                iounmap(clkctl_base);
-        } else {
-                pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
-        }
-
-        l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
-        if (IS_ERR(l2x0_base)) {
-                printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
-                                PTR_ERR(l2x0_base));
-                return 0;
-        }
-
-        l2x0_init(l2x0_base, 0x00030024, 0x00000000);
-
-        return 0;
-}
-arch_initcall(mxc_init_l2x0);
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index ede2710f8b76..fa2b97df5846 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -314,25 +314,19 @@ static struct mtd_partition armadillo5x0_nor_flash_partitions[] = {
         },
 };
 
-static struct physmap_flash_data armadillo5x0_nor_flash_pdata = {
+static const struct physmap_flash_data
+                armadillo5x0_nor_flash_pdata __initconst = {
         .width          = 2,
         .parts          = armadillo5x0_nor_flash_partitions,
         .nr_parts       = ARRAY_SIZE(armadillo5x0_nor_flash_partitions),
 };
 
-static struct resource armadillo5x0_nor_flash_resource = {
+static const struct resource armadillo5x0_nor_flash_resource __initconst = {
         .flags          = IORESOURCE_MEM,
         .start          = MX31_CS0_BASE_ADDR,
         .end            = MX31_CS0_BASE_ADDR + SZ_64M - 1,
 };
 
-static struct platform_device armadillo5x0_nor_flash = {
-        .name                   = "physmap-flash",
-        .id                     = -1,
-        .num_resources          = 1,
-        .resource               = &armadillo5x0_nor_flash_resource,
-};
-
 /*
  * FB support
  */
@@ -514,8 +508,10 @@ static void __init armadillo5x0_init(void)
         imx31_add_mx3_sdc_fb(&mx3fb_pdata);
 
         /* Register NOR Flash */
-        mxc_register_device(&armadillo5x0_nor_flash,
-                            &armadillo5x0_nor_flash_pdata);
+        platform_device_register_resndata(NULL, "physmap-flash", -1,
+                        &armadillo5x0_nor_flash_resource, 1,
+                        &armadillo5x0_nor_flash_pdata,
+                        sizeof(armadillo5x0_nor_flash_pdata));
 
         /* Register NAND Flash */
         imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
@@ -558,7 +554,7 @@ static struct sys_timer armadillo5x0_timer = {
 
 MACHINE_START(ARMADILLO5X0, "Armadillo-500")
         /* Maintainer: Alberto Panizzo  */
-        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx31_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index f851fe903687..b1ec2cf53bb0 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -311,7 +311,7 @@ static struct sys_timer eukrea_cpuimx27_timer = {
 };
 
 MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
-        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 4bd083ba9af2..ea6c9c3468a6 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -66,7 +66,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
                 I2C_BOARD_INFO("tsc2007", 0x48),
                 .type           = "tsc2007",
                 .platform_data  = &tsc2007_info,
-                .irq            = gpio_to_irq(TSC2007_IRQGPIO),
+                .irq            = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
         },
 };
 
@@ -194,7 +194,7 @@ struct sys_timer eukrea_cpuimx35_timer = {
 
 MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
         /* Maintainer: Eukrea Electromatique */
-        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx35_map_io,
         .init_early = imx35_init_early,
         .init_irq = mx35_init_irq,
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index 2442d5da883d..9163318e95a2 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -163,7 +163,7 @@ static struct sys_timer eukrea_cpuimx25_timer = {
 
 MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
         /* Maintainer: Eukrea Electromatique */
-        .boot_params = MX25_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx25_map_io,
         .init_early = imx25_init_early,
         .init_irq = mx25_init_irq,
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 6778f8193bc6..22306ce28658 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -275,7 +275,7 @@ static struct sys_timer visstrim_m10_timer = {
 };
 
 MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
-        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
index 272f793e9247..8da48b33fc53 100644
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -71,7 +71,7 @@ static struct sys_timer mx27ipcam_timer = {
 
 MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
         /* maintainer: Freescale Semiconductor, Inc. */
-        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index d81a769fe895..21a14a20e2c3 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -77,7 +77,7 @@ static struct sys_timer mx27lite_timer = {
 };
 
 MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
-        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index e472a1d88058..7c20e9e58006 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -271,7 +271,7 @@ static struct sys_timer kzm_timer = {
 };
 
 MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
-        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = kzm_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 5cd8bee46960..b4a5e0382634 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -68,23 +68,16 @@ static const struct imxuart_platform_data uart1_pdata __initconst = {
  * Physmap flash
  */
 
-static struct physmap_flash_data mx1ads_flash_data = {
+static const struct physmap_flash_data mx1ads_flash_data __initconst = {
         .width          = 4,            /* bankwidth in bytes */
 };
 
-static struct resource flash_resource = {
+static const struct resource flash_resource __initconst = {
         .start  = MX1_CS0_PHYS,
         .end    = MX1_CS0_PHYS + SZ_32M - 1,
         .flags  = IORESOURCE_MEM,
 };
 
-static struct platform_device flash_device = {
-        .name   = "physmap-flash",
-        .id     = 0,
-        .resource = &flash_resource,
-        .num_resources = 1,
-};
-
 /*
  * I2C
  */
@@ -125,7 +118,9 @@ static void __init mx1ads_init(void)
         imx1_add_imx_uart1(&uart1_pdata);
 
         /* Physmap flash */
-        mxc_register_device(&flash_device, &mx1ads_flash_data);
+        platform_device_register_resndata(NULL, "physmap-flash", 0,
+                        &flash_resource, 1,
+                        &mx1ads_flash_data, sizeof(mx1ads_flash_data));
 
         /* I2C */
         i2c_register_board_info(0, mx1ads_i2c_devices,
@@ -145,7 +140,7 @@ struct sys_timer mx1ads_timer = {
 
 MACHINE_START(MX1ADS, "Freescale MX1ADS")
         /* Maintainer: Sascha Hauer, Pengutronix */
-        .boot_params = MX1_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx1_map_io,
         .init_early = imx1_init_early,
         .init_irq = mx1_init_irq,
@@ -154,7 +149,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
 MACHINE_END
 
 MACHINE_START(MXLADS, "Freescale MXLADS")
-        .boot_params = MX1_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx1_map_io,
         .init_early = imx1_init_early,
         .init_irq = mx1_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index d389ecf9b5a8..e56828da26b2 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -305,7 +305,7 @@ static struct sys_timer mx21ads_timer = {
 
 MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
         /* maintainer: Freescale Semiconductor, Inc. */
-        .boot_params = MX21_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx21ads_map_io,
         .init_early = imx21_init_early,
         .init_irq = mx21_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 7f66a91df361..dd25ee82e70a 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -253,7 +253,7 @@ static struct sys_timer mx25pdk_timer = {
 
 MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .boot_params = MX25_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx25_map_io,
         .init_early = imx25_init_early,
         .init_irq = mx25_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 6fa6934ab150..bcf480b8a9f8 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -359,7 +359,7 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
                 .bus_num        = 1,
                 .chip_select    = 0, /* SS0 */
                 .platform_data  = &mc13783_pdata,
-                .irq = gpio_to_irq(PMIC_INT),
+                .irq = IMX_GPIO_TO_IRQ(PMIC_INT),
                 .mode = SPI_CS_HIGH,
         }, {
                 .modalias       = "l4f00242t03",
@@ -421,7 +421,7 @@ static struct sys_timer mx27pdk_timer = {
 
 MACHINE_START(MX27_3DS, "Freescale MX27PDK")
         /* maintainer: Freescale Semiconductor, Inc. */
-        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index fc26ed71b9ed..efe6109099fd 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -345,7 +345,7 @@ static void __init mx27ads_map_io(void)
 
 MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
         /* maintainer: Freescale Semiconductor, Inc. */
-        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx27ads_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index c20be7530927..589066fb3316 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -764,7 +764,7 @@ static void __init mx31_3ds_reserve(void)
 
 MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx31_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 29ca8907a780..910c4561d35f 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -535,7 +535,7 @@ static struct sys_timer mx31ads_timer = {
 
 MACHINE_START(MX31ADS, "Freescale MX31ADS")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx31ads_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31ads_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index 126913ad106a..e92eaf91a7be 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -295,7 +295,7 @@ static struct sys_timer mx31lilly_timer = {
 };
 
 MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
-        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx31_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index 4b47fd9fdd89..5242cb78b563 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -280,7 +280,7 @@ struct sys_timer mx31lite_timer = {
 
 MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx31lite_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index b358383120e7..1d01ef28f25d 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -567,7 +567,7 @@ static void __init mx31moboard_reserve(void)
 
 MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
         /* Maintainer: Valentin Longchamp, EPFL Mobots group */
-        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .reserve = mx31moboard_reserve,
         .map_io = mx31_map_io,
         .init_early = imx31_init_early,
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index b3b9bd8ac2a3..f2a873dc08ce 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -217,7 +217,7 @@ struct sys_timer mx35pdk_timer = {
 
 MACHINE_START(MX35_3DS, "Freescale MX35PDK")
         /* Maintainer: Freescale Semiconductor, Inc */
-        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx35_map_io,
         .init_early = imx35_init_early,
         .init_irq = mx35_init_irq,
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index c85876fed663..5ec3989704fd 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -267,7 +267,7 @@ static struct sys_timer mxt_td60_timer = {
 
 MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
         /* maintainer: Maxtrack Industrial */
-        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 71083aa16038..0f6bd1199038 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -435,7 +435,7 @@ static struct sys_timer pca100_timer = {
 };
 
 MACHINE_START(PCA100, "phyCARD-i.MX27")
-        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index f45b7cd72c8a..186d4eb90796 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -688,7 +688,7 @@ static void __init pcm037_reserve(void)
 
 MACHINE_START(PCM037, "Phytec Phycore pcm037")
         /* Maintainer: Pengutronix */
-        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .reserve = pcm037_reserve,
         .map_io = mx31_map_io,
         .init_early = imx31_init_early,
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 2d6a64bbac44..091bcf87e1a0 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -349,7 +349,7 @@ static struct sys_timer pcm038_timer = {
 };
 
 MACHINE_START(PCM038, "phyCORE-i.MX27")
-        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 660ec3e80cf8..0a4d31de7738 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -418,7 +418,7 @@ struct sys_timer pcm043_timer = {
 
 MACHINE_START(PCM043, "Phytec Phycore pcm043")
         /* Maintainer: Pengutronix */
-        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx35_map_io,
         .init_early = imx35_init_early,
         .init_irq = mx35_init_irq,
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index 3626f486498a..9e11359c324c 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -262,7 +262,7 @@ static struct sys_timer qong_timer = {
 
 MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
         /* Maintainer: DENX Software Engineering GmbH */
-        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx31_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index db2d60470e15..85d32845ee1e 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -137,7 +137,7 @@ static struct sys_timer scb9328_timer = {
 
 MACHINE_START(SCB9328, "Synertronixx scb9328")
         /* Sascha Hauer */
-        .boot_params = 0x08000100,
+        .atag_offset = 100,
         .map_io = mx1_map_io,
         .init_early = imx1_init_early,
         .init_irq = mx1_init_irq,
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 7d8e012a6335..5250283479e7 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -162,7 +162,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = {
         }, {
                 I2C_BOARD_INFO("mc13892", 0x08),
                 .platform_data = &vpr200_pmic,
-                .irq = gpio_to_irq(GPIO_PMIC_INT),
+                .irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
         }
 };
 
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
new file mode 100644
index 000000000000..9f0e82ec3398
--- /dev/null
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -0,0 +1,256 @@
+/*
+ *  Copyright (C) 1999,2000 Arm Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - add MX31 specific definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/err.h>
+
+#include <asm/pgtable.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/map.h>
+
+#include <mach/common.h>
+#include <mach/devices-common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-v3.h>
+#include <mach/irqs.h>
+
+static void imx3_idle(void)
+{
+        unsigned long reg = 0;
+        __asm__ __volatile__(
+                /* disable I and D cache */
+                "mrc p15, 0, %0, c1, c0, 0\n"
+                "bic %0, %0, #0x00001000\n"
+                "bic %0, %0, #0x00000004\n"
+                "mcr p15, 0, %0, c1, c0, 0\n"
+                /* invalidate I cache */
+                "mov %0, #0\n"
+                "mcr p15, 0, %0, c7, c5, 0\n"
+                /* clear and invalidate D cache */
+                "mov %0, #0\n"
+                "mcr p15, 0, %0, c7, c14, 0\n"
+                /* WFI */
+                "mov %0, #0\n"
+                "mcr p15, 0, %0, c7, c0, 4\n"
+                "nop\n" "nop\n" "nop\n" "nop\n"
+                "nop\n" "nop\n" "nop\n"
+                /* enable I and D cache */
+                "mrc p15, 0, %0, c1, c0, 0\n"
+                "orr %0, %0, #0x00001000\n"
+                "orr %0, %0, #0x00000004\n"
+                "mcr p15, 0, %0, c1, c0, 0\n"
+                : "=r" (reg));
+}
+
+static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
+                                  unsigned int mtype)
+{
+        if (mtype == MT_DEVICE) {
+                /*
+                 * Access all peripherals below 0x80000000 as nonshared device
+                 * on mx3, but leave l2cc alone.  Otherwise cache corruptions
+                 * can occur.
+                 */
+                if (phys_addr < 0x80000000 &&
+                                !addr_in_module(phys_addr, MX3x_L2CC))
+                        mtype = MT_DEVICE_NONSHARED;
+        }
+
+        return __arm_ioremap(phys_addr, size, mtype);
+}
+
+void imx3_init_l2x0(void)
+{
+        void __iomem *l2x0_base;
+        void __iomem *clkctl_base;
+
+/*
+ * First of all, we must repair broken chip settings. There are some
+ * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
+ * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
+ * Workaraound is to setup the correct register setting prior enabling the
+ * L2 cache. This should not hurt already working CPUs, as they are using the
+ * same value.
+ */
+#define L2_MEM_VAL 0x10
+
+        clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
+        if (clkctl_base != NULL) {
+                writel(0x00000515, clkctl_base + L2_MEM_VAL);
+                iounmap(clkctl_base);
+        } else {
+                pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
+        }
+
+        l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
+        if (IS_ERR(l2x0_base)) {
+                printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
+                                PTR_ERR(l2x0_base));
+                return;
+        }
+
+        l2x0_init(l2x0_base, 0x00030024, 0x00000000);
+}
+
+static struct map_desc mx31_io_desc[] __initdata = {
+        imx_map_entry(MX31, X_MEMC, MT_DEVICE),
+        imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
+};
+
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory mappings
+ * for the IO modules.
+ */
+void __init mx31_map_io(void)
+{
+        iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
+}
+
+static struct map_desc mx35_io_desc[] __initdata = {
+        imx_map_entry(MX35, X_MEMC, MT_DEVICE),
+        imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
+};
+
+void __init mx35_map_io(void)
+{
+        iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
+}
+
+void __init imx31_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX31);
+        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
+        imx_idle = imx3_idle;
+        imx_ioremap = imx3_ioremap;
+}
+
+void __init imx35_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX35);
+        mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
+        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
+        imx_idle = imx3_idle;
+        imx_ioremap = imx3_ioremap;
+}
+
+void __init mx31_init_irq(void)
+{
+        mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
+}
+
+void __init mx35_init_irq(void)
+{
+        mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
+}
+
+static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
+        .per_2_per_addr = 1677,
+};
+
+static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
+        .ap_2_ap_addr = 423,
+        .ap_2_bp_addr = 829,
+        .bp_2_ap_addr = 1029,
+};
+
+static struct sdma_platform_data imx31_sdma_pdata __initdata = {
+        .fw_name = "sdma-imx31-to2.bin",
+        .script_addrs = &imx31_to2_sdma_script,
+};
+
+void __init imx31_soc_init(void)
+{
+        int to_version = mx31_revision() >> 4;
+
+        imx3_init_l2x0();
+
+        mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
+        mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
+        mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
+
+        if (to_version == 1) {
+                strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
+                        strlen(imx31_sdma_pdata.fw_name));
+                imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
+        }
+
+        imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
+}
+
+static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
+        .ap_2_ap_addr = 642,
+        .uart_2_mcu_addr = 817,
+        .mcu_2_app_addr = 747,
+        .uartsh_2_mcu_addr = 1183,
+        .per_2_shp_addr = 1033,
+        .mcu_2_shp_addr = 961,
+        .ata_2_mcu_addr = 1333,
+        .mcu_2_ata_addr = 1252,
+        .app_2_mcu_addr = 683,
+        .shp_2_per_addr = 1111,
+        .shp_2_mcu_addr = 892,
+};
+
+static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
+        .ap_2_ap_addr = 729,
+        .uart_2_mcu_addr = 904,
+        .per_2_app_addr = 1597,
+        .mcu_2_app_addr = 834,
+        .uartsh_2_mcu_addr = 1270,
+        .per_2_shp_addr = 1120,
+        .mcu_2_shp_addr = 1048,
+        .ata_2_mcu_addr = 1429,
+        .mcu_2_ata_addr = 1339,
+        .app_2_per_addr = 1531,
+        .app_2_mcu_addr = 770,
+        .shp_2_per_addr = 1198,
+        .shp_2_mcu_addr = 979,
+};
+
+static struct sdma_platform_data imx35_sdma_pdata __initdata = {
+        .fw_name = "sdma-imx35-to2.bin",
+        .script_addrs = &imx35_to2_sdma_script,
+};
+
+void __init imx35_soc_init(void)
+{
+        int to_version = mx35_revision() >> 4;
+
+        imx3_init_l2x0();
+
+        /* i.mx35 has the i.mx31 type gpio */
+        mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
+        mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
+        mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
+
+        if (to_version == 1) {
+                strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
+                        strlen(imx35_sdma_pdata.fw_name));
+                imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
+        }
+
+        imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
+}
diff --git a/arch/arm/mach-imx/mm-imx31.c b/arch/arm/mach-imx/mm-imx31.c
deleted file mode 100644
index b7c55e7db000..000000000000
--- a/arch/arm/mach-imx/mm-imx31.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- *  Copyright (C) 1999,2000 Arm Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *    - add MX31 specific definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/err.h>
-
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-
-#include <mach/common.h>
-#include <mach/devices-common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-v3.h>
-#include <mach/irqs.h>
-
-static struct map_desc mx31_io_desc[] __initdata = {
-        imx_map_entry(MX31, X_MEMC, MT_DEVICE),
-        imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx31_map_io(void)
-{
-        iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
-}
-
-void __init imx31_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX31);
-        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
-}
-
-void __init mx31_init_irq(void)
-{
-        mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
-}
-
-static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
-        .per_2_per_addr = 1677,
-};
-
-static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
-        .ap_2_ap_addr = 423,
-        .ap_2_bp_addr = 829,
-        .bp_2_ap_addr = 1029,
-};
-
-static struct sdma_platform_data imx31_sdma_pdata __initdata = {
-        .fw_name = "sdma-imx31-to2.bin",
-        .script_addrs = &imx31_to2_sdma_script,
-};
-
-void __init imx31_soc_init(void)
-{
-        int to_version = mx31_revision() >> 4;
-
-        mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
-        mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
-        mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
-
-        if (to_version == 1) {
-                strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
-                        strlen(imx31_sdma_pdata.fw_name));
-                imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
-        }
-
-        imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
-}
diff --git a/arch/arm/mach-imx/mm-imx35.c b/arch/arm/mach-imx/mm-imx35.c
deleted file mode 100644
index f49bac7a1ede..000000000000
--- a/arch/arm/mach-imx/mm-imx35.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- *  Copyright (C) 1999,2000 Arm Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *    - add MX31 specific definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/err.h>
-
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-#include <asm/hardware/cache-l2x0.h>
-
-#include <mach/common.h>
-#include <mach/devices-common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-v3.h>
-#include <mach/irqs.h>
-
-static struct map_desc mx35_io_desc[] __initdata = {
-        imx_map_entry(MX35, X_MEMC, MT_DEVICE),
-        imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
-};
-
-void __init mx35_map_io(void)
-{
-        iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
-}
-
-void __init imx35_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX35);
-        mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
-}
-
-void __init mx35_init_irq(void)
-{
-        mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
-}
-
-static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
-        .ap_2_ap_addr = 642,
-        .uart_2_mcu_addr = 817,
-        .mcu_2_app_addr = 747,
-        .uartsh_2_mcu_addr = 1183,
-        .per_2_shp_addr = 1033,
-        .mcu_2_shp_addr = 961,
-        .ata_2_mcu_addr = 1333,
-        .mcu_2_ata_addr = 1252,
-        .app_2_mcu_addr = 683,
-        .shp_2_per_addr = 1111,
-        .shp_2_mcu_addr = 892,
-};
-
-static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
-        .ap_2_ap_addr = 729,
-        .uart_2_mcu_addr = 904,
-        .per_2_app_addr = 1597,
-        .mcu_2_app_addr = 834,
-        .uartsh_2_mcu_addr = 1270,
-        .per_2_shp_addr = 1120,
-        .mcu_2_shp_addr = 1048,
-        .ata_2_mcu_addr = 1429,
-        .mcu_2_ata_addr = 1339,
-        .app_2_per_addr = 1531,
-        .app_2_mcu_addr = 770,
-        .shp_2_per_addr = 1198,
-        .shp_2_mcu_addr = 979,
-};
-
-static struct sdma_platform_data imx35_sdma_pdata __initdata = {
-        .fw_name = "sdma-imx35-to2.bin",
-        .script_addrs = &imx35_to2_sdma_script,
-};
-
-void __init imx35_soc_init(void)
-{
-        int to_version = mx35_revision() >> 4;
-
-        /* i.mx35 has the i.mx31 type gpio */
-        mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
-        mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
-        mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
-
-        if (to_version == 1) {
-                strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
-                        strlen(imx35_sdma_pdata.fw_name));
-                imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
-        }
-
-        imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
-}
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
index acf17691d2cc..e455d2f855bf 100644
--- a/arch/arm/mach-imx/pm-imx27.c
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -11,7 +11,7 @@
 #include <linux/suspend.h>
 #include <linux/io.h>
 #include <mach/system.h>
-#include <mach/mx27.h>
+#include <mach/hardware.h>
 
 static int mx27_suspend_enter(suspend_state_t state)
 {
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 8cdc730dcb3a..a20fb3f2bc45 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -459,7 +459,7 @@ static struct sys_timer ap_timer = {
 
 MACHINE_START(INTEGRATOR, "ARM-Integrator")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .reserve        = integrator_reserve,
         .map_io         = ap_map_io,
         .init_early     = integrator_init_early,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 4eb03ab5cb46..5de49c33e4d4 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -492,7 +492,7 @@ static struct sys_timer cp_timer = {
 
 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .reserve        = integrator_reserve,
         .map_io         = intcp_map_io,
         .init_early     = intcp_init_early,
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index 23dfaffc586c..4cf2cc477eae 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -91,7 +91,7 @@ static struct sys_timer iq81340mc_timer = {
 
 MACHINE_START(IQ81340MC, "Intel IQ81340MC")
         /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = iop13xx_map_io,
         .init_irq       = iop13xx_init_irq,
         .timer          = &iq81340mc_timer,
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index df3492a9c280..cd9e27499a1e 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -93,7 +93,7 @@ static struct sys_timer iq81340sc_timer = {
 
 MACHINE_START(IQ81340SC, "Intel IQ81340SC")
         /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = iop13xx_map_io,
         .init_irq       = iop13xx_init_irq,
         .timer          = &iq81340sc_timer,
diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c
index 6cbffbfc2bba..4325055d4e19 100644
--- a/arch/arm/mach-iop32x/em7210.c
+++ b/arch/arm/mach-iop32x/em7210.c
@@ -203,7 +203,7 @@ static void __init em7210_init_machine(void)
 }
 
 MACHINE_START(EM7210, "Lanner EM7210")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = em7210_map_io,
         .init_irq       = iop32x_init_irq,
         .timer          = &em7210_timer,
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index ceef5d4dce1a..0edc88020577 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -207,7 +207,7 @@ static void __init glantank_init_machine(void)
 
 MACHINE_START(GLANTANK, "GLAN Tank")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = glantank_map_io,
         .init_irq       = iop32x_init_irq,
         .timer          = &glantank_timer,
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 3a62514dae7c..9e7aaccfeba0 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -313,7 +313,7 @@ __setup("force_ep80219", force_ep80219_setup);
 
 MACHINE_START(IQ31244, "Intel IQ31244")
         /* Maintainer: Intel Corp. */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = iq31244_map_io,
         .init_irq       = iop32x_init_irq,
         .timer          = &iq31244_timer,
@@ -327,7 +327,7 @@ MACHINE_END
  */
 MACHINE_START(EP80219, "Intel EP80219")
         /* Maintainer: Intel Corp. */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = iq31244_map_io,
         .init_irq       = iop32x_init_irq,
         .timer          = &iq31244_timer,
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index 35b7e6914d3b..53ea86f649dd 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -186,7 +186,7 @@ static void __init iq80321_init_machine(void)
 
 MACHINE_START(IQ80321, "Intel IQ80321")
         /* Maintainer: Intel Corp. */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = iq80321_map_io,
         .init_irq       = iop32x_init_irq,
         .timer          = &iq80321_timer,
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index 1a374eab6007..d7269279968c 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -327,7 +327,7 @@ static void __init n2100_init_machine(void)
 
 MACHINE_START(N2100, "Thecus N2100")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = n2100_map_io,
         .init_irq       = iop32x_init_irq,
         .timer          = &n2100_timer,
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index 637c0272d5e0..9e14ccc56f8e 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -141,7 +141,7 @@ static void __init iq80331_init_machine(void)
 
 MACHINE_START(IQ80331, "Intel IQ80331")
         /* Maintainer: Intel Corp. */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = iop3xx_map_io,
         .init_irq       = iop33x_init_irq,
         .timer          = &iq80331_timer,
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 90a0436d7255..09c899a2523f 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -141,7 +141,7 @@ static void __init iq80332_init_machine(void)
 
 MACHINE_START(IQ80332, "Intel IQ80332")
         /* Maintainer: Intel Corp. */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = iop3xx_map_io,
         .init_irq       = iop33x_init_irq,
         .timer          = &iq80332_timer,
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index 62c60ade5274..af9994537e01 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -254,7 +254,7 @@ static void __init enp2611_init_machine(void)
 
 MACHINE_START(ENP2611, "Radisys ENP-2611 PCI network processor board")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = enp2611_map_io,
         .init_irq       = ixp2000_init_irq,
         .timer          = &enp2611_timer,
diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c
index 5bad1a8419b7..f7dfd9700141 100644
--- a/arch/arm/mach-ixp2000/ixdp2400.c
+++ b/arch/arm/mach-ixp2000/ixdp2400.c
@@ -171,7 +171,7 @@ void __init ixdp2400_init_irq(void)
 
 MACHINE_START(IXDP2400, "Intel IXDP2400 Development Platform")
         /* Maintainer: MontaVista Software, Inc. */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = ixdp2x00_map_io,
         .init_irq       = ixdp2400_init_irq,
         .timer          = &ixdp2400_timer,
diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c
index 3d3cef876467..d33bcac1ec92 100644
--- a/arch/arm/mach-ixp2000/ixdp2800.c
+++ b/arch/arm/mach-ixp2000/ixdp2800.c
@@ -286,7 +286,7 @@ void __init ixdp2800_init_irq(void)
 
 MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform")
         /* Maintainer: MontaVista Software, Inc. */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = ixdp2x00_map_io,
         .init_irq       = ixdp2800_init_irq,
         .timer          = &ixdp2800_timer,
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index be2a254f1374..61a28676b5be 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -417,7 +417,7 @@ static void __init ixdp2x01_init_machine(void)
 #ifdef CONFIG_ARCH_IXDP2401
 MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
         /* Maintainer: MontaVista Software, Inc. */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = ixdp2x01_map_io,
         .init_irq       = ixdp2x01_init_irq,
         .timer          = &ixdp2x01_timer,
@@ -428,7 +428,7 @@ MACHINE_END
 #ifdef CONFIG_ARCH_IXDP2801
 MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
         /* Maintainer: MontaVista Software, Inc. */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = ixdp2x01_map_io,
         .init_irq       = ixdp2x01_init_irq,
         .timer          = &ixdp2x01_timer,
@@ -441,7 +441,7 @@ MACHINE_END
  */
 MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform")
         /* Maintainer: MontaVista Software, Inc. */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = ixdp2x01_map_io,
         .init_irq       = ixdp2x01_init_irq,
         .timer          = &ixdp2x01_timer,
diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c
index e25e5fe183ba..30dd31652e9d 100644
--- a/arch/arm/mach-ixp23xx/espresso.c
+++ b/arch/arm/mach-ixp23xx/espresso.c
@@ -88,6 +88,6 @@ MACHINE_START(ESPRESSO, "IP Fabrics Double Espresso")
         .map_io         = ixp23xx_map_io,
         .init_irq       = ixp23xx_init_irq,
         .timer          = &ixp23xx_timer,
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = espresso_init,
 MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index ec028e35f401..b3a57e0f3419 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -331,6 +331,6 @@ MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform")
         .map_io         = ixdp2351_map_io,
         .init_irq       = ixdp2351_init_irq,
         .timer          = &ixp23xx_timer,
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = ixdp2351_init,
 MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
index 844551d2368b..8f4dcbba9025 100644
--- a/arch/arm/mach-ixp23xx/roadrunner.c
+++ b/arch/arm/mach-ixp23xx/roadrunner.c
@@ -175,6 +175,6 @@ MACHINE_START(ROADRUNNER, "ADI Engineering RoadRunner Development Platform")
         .map_io         = ixp23xx_map_io,
         .init_irq       = ixp23xx_init_irq,
         .timer          = &ixp23xx_timer,
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = roadrunner_init,
 MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
index ee19c1d383aa..37609a22c450 100644
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -167,7 +167,7 @@ MACHINE_START(AVILA, "Gateworks Avila Network Platform")
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
-        .boot_params    = 0x0100,
+        .atag_offset    = 0x100,
         .init_machine   = avila_init,
 #if defined(CONFIG_PCI)
         .dma_zone_size  = SZ_64M,
@@ -185,7 +185,7 @@ MACHINE_START(LOFT, "Giant Shoulder Inc Loft board")
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
-        .boot_params    = 0x0100,
+        .atag_offset    = 0x100,
         .init_machine   = avila_init,
 #if defined(CONFIG_PCI)
         .dma_zone_size  = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index e24564b5d935..81dfec31842b 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -112,7 +112,7 @@ MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
-        .boot_params    = 0x0100,
+        .atag_offset    = 0x100,
         .init_machine   = coyote_init,
 #if defined(CONFIG_PCI)
         .dma_zone_size  = SZ_64M,
@@ -130,7 +130,7 @@ MACHINE_START(IXDPG425, "Intel IXDPG425")
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
-        .boot_params    = 0x0100,
+        .atag_offset    = 0x100,
         .init_machine   = coyote_init,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 03e54515e8b3..71607a7ecc7e 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -279,7 +279,7 @@ static void __init dsmg600_init(void)
 
 MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
         /* Maintainer: www.nslu2-linux.org */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &dsmg600_timer,
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index 23a8b3614568..a9540cd90375 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -273,7 +273,7 @@ MACHINE_START(FSG, "Freecom FSG-3")
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
-        .boot_params    = 0x0100,
+        .atag_offset    = 0x100,
         .init_machine   = fsg_init,
 #if defined(CONFIG_PCI)
         .dma_zone_size  = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c
index d4f851bdd9a4..d69d1b053bb7 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c
@@ -99,7 +99,7 @@ MACHINE_START(GATEWAY7001, "Gateway 7001 AP")
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
-        .boot_params    = 0x0100,
+        .atag_offset    = 0x100,
         .init_machine   = gateway7001_init,
 #if defined(CONFIG_PCI)
         .dma_zone_size  = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index 7548d9a2efe2..bf6678d1a929 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -499,7 +499,7 @@ MACHINE_START(GORAMO_MLR, "MultiLink")
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
-        .boot_params    = 0x0100,
+        .atag_offset    = 0x100,
         .init_machine   = gmlr_init,
 #if defined(CONFIG_PCI)
         .dma_zone_size  = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index 3790dffd3c30..aa029fc19140 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -167,7 +167,7 @@ MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)")
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
-        .boot_params    = 0x0100,
+        .atag_offset    = 0x100,
         .init_machine   = gtwx5715_init,
 #if defined(CONFIG_PCI)
         .dma_zone_size  = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index 6a2927956bf6..f235f829dfa6 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -256,7 +256,7 @@ MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
-        .boot_params    = 0x0100,
+        .atag_offset    = 0x100,
         .init_machine   = ixdp425_init,
 #if defined(CONFIG_PCI)
         .dma_zone_size  = SZ_64M,
@@ -270,7 +270,7 @@ MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
-        .boot_params    = 0x0100,
+        .atag_offset    = 0x100,
         .init_machine   = ixdp425_init,
 #if defined(CONFIG_PCI)
         .dma_zone_size  = SZ_64M,
@@ -284,7 +284,7 @@ MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
-        .boot_params    = 0x0100,
+        .atag_offset    = 0x100,
         .init_machine   = ixdp425_init,
 #if defined(CONFIG_PCI)
         .dma_zone_size  = SZ_64M,
@@ -298,7 +298,7 @@ MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
-        .boot_params    = 0x0100,
+        .atag_offset    = 0x100,
         .init_machine   = ixdp425_init,
 #if defined(CONFIG_PCI)
         .dma_zone_size  = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index afb51879d9a4..9f4669260d4c 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -314,7 +314,7 @@ static void __init nas100d_init(void)
 
 MACHINE_START(NAS100D, "Iomega NAS 100d")
         /* Maintainer: www.nslu2-linux.org */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index 69e40f2cf092..3676fbf6ef9c 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -300,7 +300,7 @@ static void __init nslu2_init(void)
 
 MACHINE_START(NSLU2, "Linksys NSLU2")
         /* Maintainer: www.nslu2-linux.org */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &nslu2_timer,
diff --git a/arch/arm/mach-ixp4xx/vulcan-setup.c b/arch/arm/mach-ixp4xx/vulcan-setup.c
index 045336c833af..27e469ef4523 100644
--- a/arch/arm/mach-ixp4xx/vulcan-setup.c
+++ b/arch/arm/mach-ixp4xx/vulcan-setup.c
@@ -239,7 +239,7 @@ MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan")
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
-        .boot_params    = 0x0100,
+        .atag_offset    = 0x100,
         .init_machine   = vulcan_init,
 #if defined(CONFIG_PCI)
         .dma_zone_size  = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/wg302v2-setup.c b/arch/arm/mach-ixp4xx/wg302v2-setup.c
index 40b9fad800b8..b14144b967a7 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c
@@ -100,7 +100,7 @@ MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2")
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
-        .boot_params    = 0x0100,
+        .atag_offset    = 0x100,
         .init_machine   = wg302v2_init,
 #if defined(CONFIG_PCI)
         .dma_zone_size  = SZ_64M,
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
index 043cfd5e140b..f457e07a65f0 100644
--- a/arch/arm/mach-kirkwood/d2net_v2-setup.c
+++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c
@@ -221,7 +221,7 @@ static void __init d2net_v2_init(void)
 }
 
 MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = d2net_v2_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index bff04e04d679..ff4c21c1f923 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -97,7 +97,7 @@ subsys_initcall(db88f6281_pci_init);
 
 MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
         /* Maintainer: Saeed Bishara <saeed@marvell.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = db88f6281_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
index f14dfb8508c5..e4d199b2b1e8 100644
--- a/arch/arm/mach-kirkwood/dockstar-setup.c
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -102,7 +102,7 @@ static void __init dockstar_init(void)
 }
 
 MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = dockstar_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index 41d1b40696a3..6c40f784b516 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -121,7 +121,7 @@ static void __init guruplug_init(void)
 
 MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board")
         /* Maintainer: Siddarth Gore <gores@marvell.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = guruplug_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 00cca22eca6f..9a1e917352f7 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -163,7 +163,7 @@ subsys_initcall(mv88f6281gtw_ge_pci_init);
 
 MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board")
         /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = mv88f6281gtw_ge_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 7cdab5776452..8849bcc7328e 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -258,7 +258,7 @@ static void __init netspace_v2_init(void)
 
 #ifdef CONFIG_MACH_NETSPACE_V2
 MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
@@ -269,7 +269,7 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_INETSPACE_V2
 MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
@@ -280,7 +280,7 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_NETSPACE_MAX_V2
 MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 6be627deb0fc..1ba12c4dff8f 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -399,7 +399,7 @@ static void __init netxbig_v2_init(void)
 
 #ifdef CONFIG_MACH_NET2BIG_V2
 MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = netxbig_v2_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
@@ -410,7 +410,7 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_NET5BIG_V2
 MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = netxbig_v2_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index f69beeff4450..5660ca6c3d88 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -214,7 +214,7 @@ subsys_initcall(openrd_pci_init);
 #ifdef CONFIG_MACH_OPENRD_BASE
 MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board")
         /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = openrd_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
@@ -226,7 +226,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_OPENRD_CLIENT
 MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
         /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = openrd_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
@@ -238,7 +238,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_OPENRD_ULTIMATE
 MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
         /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = openrd_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 75c6601b8d87..6663869773ab 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -79,7 +79,7 @@ subsys_initcall(rd88f6192_pci_init);
 
 MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
         /* Maintainer: Saeed Bishara <saeed@marvell.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = rd88f6192_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 0f75494d5902..66b3c05e37a6 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -115,7 +115,7 @@ subsys_initcall(rd88f6281_pci_init);
 
 MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
         /* Maintainer: Saeed Bishara <saeed@marvell.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = rd88f6281_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index 17de0bf53c08..8b102d62e82c 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -138,7 +138,7 @@ static void __init sheevaplug_init(void)
 #ifdef CONFIG_MACH_SHEEVAPLUG
 MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")
         /* Maintainer: shadi Ammouri <shadi@marvell.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = sheevaplug_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
@@ -149,7 +149,7 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_ESATA_SHEEVAPLUG
 MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = sheevaplug_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
index e6b9b1b22a35..ea104fb5ec3d 100644
--- a/arch/arm/mach-kirkwood/t5325-setup.c
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -201,7 +201,7 @@ subsys_initcall(hp_t5325_pci_init);
 
 MACHINE_START(T5325, "HP t5325 Thin Client")
         /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = hp_t5325_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 68f32f2bf552..262c034836d4 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -132,7 +132,7 @@ subsys_initcall(ts219_pci_init);
 
 MACHINE_START(TS219, "QNAP TS-119/TS-219")
         /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = qnap_ts219_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index d5d009970705..b68f5b4a9ec8 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -176,7 +176,7 @@ subsys_initcall(ts41x_pci_init);
 
 MACHINE_START(TS41X, "QNAP TS-41x")
         /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = qnap_ts41x_init,
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
diff --git a/arch/arm/mach-ks8695/board-acs5k.c b/arch/arm/mach-ks8695/board-acs5k.c
index 3ca4f8e6f54f..a5fcc7c7fe18 100644
--- a/arch/arm/mach-ks8695/board-acs5k.c
+++ b/arch/arm/mach-ks8695/board-acs5k.c
@@ -223,7 +223,7 @@ static void __init acs5k_init(void)
 
 MACHINE_START(ACS5K, "Brivo Systems LLC ACS-5000 Master board")
         /* Maintainer: Simtec Electronics. */
-        .boot_params    = KS8695_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ks8695_map_io,
         .init_irq       = ks8695_init_irq,
         .init_machine   = acs5k_init,
diff --git a/arch/arm/mach-ks8695/board-dsm320.c b/arch/arm/mach-ks8695/board-dsm320.c
index 1338cb3e9827..fb91a716a7db 100644
--- a/arch/arm/mach-ks8695/board-dsm320.c
+++ b/arch/arm/mach-ks8695/board-dsm320.c
@@ -121,7 +121,7 @@ static void __init dsm320_init(void)
 
 MACHINE_START(DSM320, "D-Link DSM-320 Wireless Media Player")
         /* Maintainer: Simtec Electronics. */
-        .boot_params    = KS8695_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ks8695_map_io,
         .init_irq       = ks8695_init_irq,
         .init_machine   = dsm320_init,
diff --git a/arch/arm/mach-ks8695/board-micrel.c b/arch/arm/mach-ks8695/board-micrel.c
index e2e3cba8dcdb..8f67a750b6c7 100644
--- a/arch/arm/mach-ks8695/board-micrel.c
+++ b/arch/arm/mach-ks8695/board-micrel.c
@@ -53,7 +53,7 @@ static void __init micrel_init(void)
 
 MACHINE_START(KS8695, "KS8695 Centaur Development Board")
         /* Maintainer: Micrel Semiconductor Inc. */
-        .boot_params    = KS8695_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = ks8695_map_io,
         .init_irq       = ks8695_init_irq,
         .init_machine   = micrel_init,
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 7993b096778e..9b621e14d16a 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -382,7 +382,7 @@ arch_initcall(lpc32xx_display_uid);
 
 MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
         /* Maintainer: Kevin Wells, NXP Semiconductors */
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .map_io         = lpc32xx_map_io,
         .init_irq       = lpc32xx_init_irq,
         .timer          = &lpc32xx_timer,
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 18a3c97bc863..16c86f8b4f3f 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -93,7 +93,7 @@ static void __init halibut_map_io(void)
 }
 
 MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .fixup          = halibut_fixup,
         .map_io         = halibut_map_io,
         .init_irq       = halibut_init_irq,
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index 7a9a03eb189c..8a1672ee4e4a 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -74,7 +74,7 @@ static void __init mahimahi_map_io(void)
 extern struct sys_timer msm_timer;
 
 MACHINE_START(MAHIMAHI, "mahimahi")
-        .boot_params    = 0x20000100,
+        .atag_offset    = 0x100,
         .fixup          = mahimahi_fixup,
         .map_io         = mahimahi_map_io,
         .init_irq       = msm_init_irq,
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c
index c03f269e2e4b..a80765533f13 100644
--- a/arch/arm/mach-msm/board-msm7x27.c
+++ b/arch/arm/mach-msm/board-msm7x27.c
@@ -130,7 +130,7 @@ static void __init msm7x2x_map_io(void)
 }
 
 MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
-        .boot_params    = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = msm7x2x_map_io,
         .init_irq       = msm7x2x_init_irq,
         .init_machine   = msm7x2x_init,
@@ -138,7 +138,7 @@ MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
 MACHINE_END
 
 MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
-        .boot_params    = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = msm7x2x_map_io,
         .init_irq       = msm7x2x_init_irq,
         .init_machine   = msm7x2x_init,
@@ -146,7 +146,7 @@ MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
 MACHINE_END
 
 MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
-        .boot_params    = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = msm7x2x_map_io,
         .init_irq       = msm7x2x_init_irq,
         .init_machine   = msm7x2x_init,
@@ -154,7 +154,7 @@ MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
 MACHINE_END
 
 MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA")
-        .boot_params    = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = msm7x2x_map_io,
         .init_irq       = msm7x2x_init_irq,
         .init_machine   = msm7x2x_init,
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index b7a84966b711..5a2ab6855183 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -106,7 +106,7 @@ static void __init msm7x30_map_io(void)
 }
 
 MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
-        .boot_params = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = msm7x30_map_io,
         .init_irq = msm7x30_init_irq,
         .init_machine = msm7x30_init,
@@ -114,7 +114,7 @@ MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
 MACHINE_END
 
 MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
-        .boot_params = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = msm7x30_map_io,
         .init_irq = msm7x30_init_irq,
         .init_machine = msm7x30_init,
@@ -122,7 +122,7 @@ MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
 MACHINE_END
 
 MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
-        .boot_params = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = msm7x30_map_io,
         .init_irq = msm7x30_init_irq,
         .init_machine = msm7x30_init,
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 6a96911b0ad5..51109b1f4342 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -193,7 +193,7 @@ static void __init qsd8x50_init(void)
 }
 
 MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
-        .boot_params = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = qsd8x50_map_io,
         .init_irq = qsd8x50_init_irq,
         .init_machine = qsd8x50_init,
@@ -201,7 +201,7 @@ MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
 MACHINE_END
 
 MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
-        .boot_params = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = qsd8x50_map_io,
         .init_irq = qsd8x50_init_irq,
         .init_machine = qsd8x50_init,
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 68f930f07d77..dc0bcb5a6b9a 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -105,7 +105,7 @@ static void __init sapphire_map_io(void)
 
 MACHINE_START(SAPPHIRE, "sapphire")
 /* Maintainer: Brian Swetland <swetland@google.com> */
-        .boot_params    = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset    = 0x100,
         .fixup          = sapphire_fixup,
         .map_io         = sapphire_map_io,
         .init_irq       = sapphire_init_irq,
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 814386772c66..22d5694f5fea 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -93,7 +93,7 @@ static void __init trout_map_io(void)
 }
 
 MACHINE_START(TROUT, "HTC Dream")
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .fixup          = trout_fixup,
         .map_io         = trout_map_io,
         .init_irq       = trout_init_irq,
diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
index 20f3f125ed2b..0e94268d6e6f 100644
--- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
+++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
@@ -145,7 +145,7 @@ subsys_initcall(wxl_pci_init);
 
 MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL")
         /* Maintainer: Sebastien Requiem <sebastien@requiem.fr> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = wxl_init,
         .map_io         = mv78xx0_map_io,
         .init_early     = mv78xx0_init_early,
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
index df5aebe5b0fa..50b85ae2da52 100644
--- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -93,7 +93,7 @@ subsys_initcall(db78x00_pci_init);
 
 MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
         /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = db78x00_init,
         .map_io         = mv78xx0_map_io,
         .init_early     = mv78xx0_init_early,
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
index d927f14c6810..e85222e53578 100644
--- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
+++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
@@ -78,7 +78,7 @@ subsys_initcall(rd78x00_pci_init);
 
 MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board")
         /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = rd78x00_masa_init,
         .map_io         = mv78xx0_map_io,
         .init_early     = mv78xx0_init_early,
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index b4e7c58bbb38..b4f5ab669e48 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -52,7 +52,6 @@ config MACH_MX50_RDP
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         select IMX_HAVE_PLATFORM_SPI_IMX
-        select IMX_HAVE_PLATFORM_FEC
         help
           Include support for MX50 reference design platform (RDP) board. This
           includes specific configurations for the board and its peripherals.
@@ -65,9 +64,11 @@ comment "i.MX51 machines:"
 config MACH_MX51_BABBAGE
         bool "Support MX51 BABBAGE platforms"
         select SOC_IMX51
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         select IMX_HAVE_PLATFORM_SPI_IMX
         help
@@ -91,8 +92,10 @@ config MACH_MX51_3DS
 config MACH_EUKREA_CPUIMX51
         bool "Support Eukrea CPUIMX51 module"
         select SOC_IMX51
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SPI_IMX
         help
@@ -119,10 +122,12 @@ endchoice
 config MACH_EUKREA_CPUIMX51SD
         bool "Support Eukrea CPUIMX51SD module"
         select SOC_IMX51
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_SPI_IMX
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SPI_IMX
         help
           Include support for Eukrea CPUIMX51SD platform. This includes
           specific configurations for the module and its peripherals.
@@ -147,6 +152,7 @@ config MX51_EFIKA_COMMON
         bool
         select SOC_IMX51
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_ULPI if USB_ULPI
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 383e7cd3fbcb..9565304b7282 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -3,8 +3,7 @@
 #
 
 # Object file lists.
-obj-y   := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o system.o
-obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
+obj-y   := cpu.o mm.o clock-mx51-mx53.o ehci.o system.o
 
 obj-$(CONFIG_PM) += pm-imx5.o
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpu_op-mx51.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index 68934ea8725a..190a6e73ec7b 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -22,21 +22,18 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
 
 #include <mach/eukrea-baseboards.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx51.h>
 
-#include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
 #include "devices-imx51.h"
-#include "devices.h"
 
 #define CPUIMX51_USBH1_STP      IMX_GPIO_NR(1, 27)
 #define CPUIMX51_QUARTA_GPIO    IMX_GPIO_NR(3, 28)
@@ -57,7 +54,7 @@
 static struct plat_serial8250_port serial_platform_data[] = {
         {
                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
-                .irq = gpio_to_irq(CPUIMX51_QUARTA_GPIO),
+                .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTA_GPIO),
                 .irqflags = IRQF_TRIGGER_HIGH,
                 .uartclk = CPUIMX51_QUART_XTAL,
                 .regshift = CPUIMX51_QUART_REGSHIFT,
@@ -65,7 +62,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
         }, {
                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
-                .irq = gpio_to_irq(CPUIMX51_QUARTB_GPIO),
+                .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTB_GPIO),
                 .irqflags = IRQF_TRIGGER_HIGH,
                 .uartclk = CPUIMX51_QUART_XTAL,
                 .regshift = CPUIMX51_QUART_REGSHIFT,
@@ -73,7 +70,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
         }, {
                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
-                .irq = gpio_to_irq(CPUIMX51_QUARTC_GPIO),
+                .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTC_GPIO),
                 .irqflags = IRQF_TRIGGER_HIGH,
                 .uartclk = CPUIMX51_QUART_XTAL,
                 .regshift = CPUIMX51_QUART_REGSHIFT,
@@ -81,7 +78,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
         }, {
                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
-                .irq = gpio_to_irq(CPUIMX51_QUARTD_GPIO),
+                .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTD_GPIO),
                 .irqflags = IRQF_TRIGGER_HIGH,
                 .uartclk = CPUIMX51_QUART_XTAL,
                 .regshift = CPUIMX51_QUART_REGSHIFT,
@@ -167,7 +164,7 @@ static int initialize_otg_port(struct platform_device *pdev)
         void __iomem *usb_base;
         void __iomem *usbother_base;
 
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
         if (!usb_base)
                 return -ENOMEM;
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -190,7 +187,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
         void __iomem *usb_base;
         void __iomem *usbother_base;
 
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
         if (!usb_base)
                 return -ENOMEM;
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -206,17 +203,17 @@ static int initialize_usbh1_port(struct platform_device *pdev)
                         MXC_EHCI_ITC_NO_THRESHOLD);
 }
 
-static struct mxc_usbh_platform_data dr_utmi_config = {
+static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
         .init           = initialize_otg_port,
         .portsc = MXC_EHCI_UTMI_16BIT,
 };
 
-static struct fsl_usb2_platform_data usb_pdata = {
+static const struct fsl_usb2_platform_data usb_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 };
 
-static struct mxc_usbh_platform_data usbh1_config = {
+static const struct mxc_usbh_platform_data usbh1_config __initconst = {
         .init           = initialize_usbh1_port,
         .portsc = MXC_EHCI_MODE_ULPI,
 };
@@ -270,12 +267,12 @@ static void __init eukrea_cpuimx51_init(void)
                                 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
 
         if (otg_mode_host)
-                mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+                imx51_add_mxc_ehci_otg(&dr_utmi_config);
         else {
                 initialize_otg_port(NULL);
-                mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
+                imx51_add_fsl_usb2_udc(&usb_pdata);
         }
-        mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+        imx51_add_mxc_ehci_hs(1, &usbh1_config);
 
 #ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
         eukrea_mbimx51_baseboard_init();
@@ -293,7 +290,7 @@ static struct sys_timer mxc_timer = {
 
 MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
         /* Maintainer: Eric Bénard <eric@eukrea.com> */
-        .boot_params = MX51_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx51_map_io,
         .init_early = imx51_init_early,
         .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index ff096d587299..72410d201f88 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -22,7 +22,6 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
 #include <linux/i2c-gpio.h>
 #include <linux/spi/spi.h>
 #include <linux/can/platform/mcp251x.h>
@@ -32,14 +31,12 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx51.h>
 
-#include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
 #include "devices-imx51.h"
-#include "devices.h"
 #include "cpu_op-mx51.h"
 
 #define USBH1_RST               IMX_GPIO_NR(2, 28)
@@ -108,7 +105,7 @@ static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
 
         /* Touchscreen */
         /* IRQ */
-        _MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
+        NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
                         PAD_CTL_PKE | PAD_CTL_SRE_FAST |
                         PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 };
@@ -129,7 +126,7 @@ static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
                 I2C_BOARD_INFO("tsc2007", 0x49),
                 .type           = "tsc2007",
                 .platform_data  = &tsc2007_info,
-                .irq            = gpio_to_irq(TSC2007_IRQGPIO),
+                .irq            = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
         },
 };
 
@@ -149,7 +146,7 @@ static int initialize_otg_port(struct platform_device *pdev)
         void __iomem *usb_base;
         void __iomem *usbother_base;
 
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
         if (!usb_base)
                 return -ENOMEM;
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -172,7 +169,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
         void __iomem *usb_base;
         void __iomem *usbother_base;
 
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
         if (!usb_base)
                 return -ENOMEM;
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -189,17 +186,17 @@ static int initialize_usbh1_port(struct platform_device *pdev)
                         MXC_EHCI_ITC_NO_THRESHOLD);
 }
 
-static struct mxc_usbh_platform_data dr_utmi_config = {
+static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
         .init           = initialize_otg_port,
         .portsc = MXC_EHCI_UTMI_16BIT,
 };
 
-static struct fsl_usb2_platform_data usb_pdata = {
+static const struct fsl_usb2_platform_data usb_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 };
 
-static struct mxc_usbh_platform_data usbh1_config = {
+static const struct mxc_usbh_platform_data usbh1_config __initconst = {
         .init           = initialize_usbh1_port,
         .portsc = MXC_EHCI_MODE_ULPI,
 };
@@ -245,7 +242,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = {
                 .mode           = SPI_MODE_0,
                 .chip_select     = 0,
                 .platform_data   = &mcp251x_info,
-                .irq             = gpio_to_irq(CAN_IRQGPIO)
+                .irq             = IMX_GPIO_TO_IRQ(CAN_IRQGPIO)
         },
 };
 
@@ -303,17 +300,17 @@ static void __init eukrea_cpuimx51sd_init(void)
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
         if (otg_mode_host)
-                mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+                imx51_add_mxc_ehci_otg(&dr_utmi_config);
         else {
                 initialize_otg_port(NULL);
-                mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
+                imx51_add_fsl_usb2_udc(&usb_pdata);
         }
 
         gpio_request(USBH1_RST, "usb_rst");
         gpio_direction_output(USBH1_RST, 0);
         msleep(20);
         gpio_set_value(USBH1_RST, 1);
-        mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+        imx51_add_mxc_ehci_hs(1, &usbh1_config);
 
 #ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
         eukrea_mbimxsd51_baseboard_init();
@@ -331,7 +328,7 @@ static struct sys_timer mxc_timer = {
 
 MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
         /* Maintainer: Eric Bénard <eric@eukrea.com> */
-        .boot_params = MX51_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx51_map_io,
         .init_early = imx51_init_early,
         .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index 07a38154da21..f988be7324fb 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -25,7 +25,6 @@
 #include <mach/3ds_debugboard.h>
 
 #include "devices-imx51.h"
-#include "devices.h"
 
 #define EXPIO_PARENT_INT        gpio_to_irq(IMX_GPIO_NR(1, 6))
 #define MX51_3DS_ECSPI2_CS      (GPIO_PORTC + 28)
@@ -169,7 +168,7 @@ static struct sys_timer mx51_3ds_timer = {
 
 MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .boot_params = MX51_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx51_map_io,
         .init_early = imx51_init_early,
         .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 11b0ff67f89d..622b2de7d0e8 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -24,14 +24,12 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx51.h>
 
-#include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
 #include "devices-imx51.h"
-#include "devices.h"
 #include "cpu_op-mx51.h"
 
 #define BABBAGE_USB_HUB_RESET   IMX_GPIO_NR(1, 7)
@@ -176,7 +174,7 @@ static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
         .bitrate = 100000,
 };
 
-static struct imxi2c_platform_data babbage_hsi2c_data = {
+static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = {
         .bitrate = 400000,
 };
 
@@ -249,7 +247,7 @@ static int initialize_otg_port(struct platform_device *pdev)
         void __iomem *usb_base;
         void __iomem *usbother_base;
 
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
         if (!usb_base)
                 return -ENOMEM;
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -272,7 +270,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
         void __iomem *usb_base;
         void __iomem *usbother_base;
 
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
         if (!usb_base)
                 return -ENOMEM;
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -288,17 +286,17 @@ static int initialize_usbh1_port(struct platform_device *pdev)
                         MXC_EHCI_ITC_NO_THRESHOLD);
 }
 
-static struct mxc_usbh_platform_data dr_utmi_config = {
+static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
         .init           = initialize_otg_port,
         .portsc = MXC_EHCI_UTMI_16BIT,
 };
 
-static struct fsl_usb2_platform_data usb_pdata = {
+static const struct fsl_usb2_platform_data usb_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 };
 
-static struct mxc_usbh_platform_data usbh1_config = {
+static const struct mxc_usbh_platform_data usbh1_config __initconst = {
         .init           = initialize_usbh1_port,
         .portsc = MXC_EHCI_MODE_ULPI,
 };
@@ -357,8 +355,8 @@ static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
 static void __init mx51_babbage_init(void)
 {
         iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
-        iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
-                MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
+        iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21,
+                PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
 
         imx51_soc_init();
 
@@ -381,17 +379,17 @@ static void __init mx51_babbage_init(void)
 
         imx51_add_imx_i2c(0, &babbage_i2c_data);
         imx51_add_imx_i2c(1, &babbage_i2c_data);
-        mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
+        imx51_add_hsi2c(&babbage_hsi2c_data);
 
         if (otg_mode_host)
-                mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+                imx51_add_mxc_ehci_otg(&dr_utmi_config);
         else {
                 initialize_otg_port(NULL);
-                mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
+                imx51_add_fsl_usb2_udc(&usb_pdata);
         }
 
         gpio_usbh1_active();
-        mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+        imx51_add_mxc_ehci_hs(1, &usbh1_config);
         /* setback USBH1_STP to be function */
         mxc_iomux_v3_setup_pad(usbh1stp);
         babbage_usbhub_reset();
@@ -416,7 +414,7 @@ static struct sys_timer mx51_babbage_timer = {
 
 MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
         /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
-        .boot_params = MX51_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx51_map_io,
         .init_early = imx51_init_early,
         .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
index 551daf85ff8c..d231b3e1e522 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -32,14 +32,12 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx51.h>
 
-#include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
 #include "devices-imx51.h"
-#include "devices.h"
 #include "efika.h"
 
 #define EFIKAMX_PCBID0          IMX_GPIO_NR(3, 16)
@@ -280,7 +278,7 @@ static struct sys_timer mx51_efikamx_timer = {
 
 MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
         /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
-        .boot_params = MX51_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx51_map_io,
         .init_early = imx51_init_early,
         .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
index 8a9bca22beb5..d4e98f0e33f5 100644
--- a/arch/arm/mach-mx5/board-mx51_efikasb.c
+++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
@@ -35,14 +35,12 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx51.h>
 
-#include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
 #include "devices-imx51.h"
-#include "devices.h"
 #include "efika.h"
 
 #define EFIKASB_USBH2_STP       IMX_GPIO_NR(2, 20)
@@ -119,7 +117,7 @@ static int initialize_usbh2_port(struct platform_device *pdev)
         return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
 }
 
-static struct mxc_usbh_platform_data usbh2_config = {
+static struct mxc_usbh_platform_data usbh2_config __initdata = {
         .init   = initialize_usbh2_port,
         .portsc = MXC_EHCI_MODE_ULPI,
 };
@@ -129,7 +127,7 @@ static void __init mx51_efikasb_usb(void)
         usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
                         ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
         if (usbh2_config.otg)
-                mxc_register_device(&mxc_usbh2_device, &usbh2_config);
+                imx51_add_mxc_ehci_hs(2, &usbh2_config);
 }
 
 static const struct gpio_led mx51_efikasb_leds[] __initconst = {
@@ -266,7 +264,7 @@ static struct sys_timer mx51_efikasb_timer = {
 };
 
 MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
-        .boot_params = MX51_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = mx51_map_io,
         .init_early = imx51_init_early,
         .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c
index 76a67c4a2a0b..ddc3015102d5 100644
--- a/arch/arm/mach-mx5/board-mx53_ard.c
+++ b/arch/arm/mach-mx5/board-mx53_ard.c
@@ -134,8 +134,8 @@ static struct resource ard_smsc911x_resources[] = {
                 .flags = IORESOURCE_MEM,
         },
         {
-                .start =  gpio_to_irq(ARD_ETHERNET_INT_B),
-                .end =  gpio_to_irq(ARD_ETHERNET_INT_B),
+                .start =  IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
+                .end =  IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
                 .flags = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index f7bf996f463b..a3db3557b7c9 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1568,7 +1568,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
 
         /* System timer */
         mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
-                MX51_MXC_INT_GPT);
+                MX51_INT_GPT);
         return 0;
 }
 
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
index e11bc0e0ec49..f311c9616bb1 100644
--- a/arch/arm/mach-mx5/devices-imx51.h
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -13,9 +13,15 @@ extern const struct imx_fec_data imx51_fec_data;
 #define imx51_add_fec(pdata)    \
         imx_add_fec(&imx51_fec_data, pdata)
 
+extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data;
+#define imx51_add_fsl_usb2_udc(pdata)   \
+        imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata)
+
 extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
 #define imx51_add_imx_i2c(id, pdata)    \
         imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
+#define imx51_add_hsi2c(pdata)  \
+        imx51_add_imx_i2c(2, pdata)
 
 extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
 #define imx51_add_imx_ssi(id, pdata)    \
@@ -25,6 +31,13 @@ extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
 #define imx51_add_imx_uart(id, pdata)   \
         imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
 
+extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data;
+#define imx51_add_mxc_ehci_otg(pdata)   \
+        imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata)
+extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[];
+#define imx51_add_mxc_ehci_hs(id, pdata)        \
+        imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata)
+
 extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
 #define imx51_add_mxc_nand(pdata)       \
         imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
deleted file mode 100644
index 371ca8c8414c..000000000000
--- a/arch/arm/mach-mx5/devices.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <mach/hardware.h>
-#include <mach/imx-uart.h>
-#include <mach/irqs.h>
-
-static struct resource mxc_hsi2c_resources[] = {
-        {
-                .start = MX51_HSI2C_DMA_BASE_ADDR,
-                .end = MX51_HSI2C_DMA_BASE_ADDR + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = MX51_MXC_INT_HS_I2C,
-                .end = MX51_MXC_INT_HS_I2C,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_hsi2c_device = {
-        .name = "imx-i2c",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(mxc_hsi2c_resources),
-        .resource = mxc_hsi2c_resources
-};
-
-static u64 usb_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource usbotg_resources[] = {
-        {
-                .start = MX51_OTG_BASE_ADDR,
-                .end = MX51_OTG_BASE_ADDR + 0x1ff,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = MX51_MXC_INT_USB_OTG,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-/* OTG gadget device */
-struct platform_device mxc_usbdr_udc_device = {
-        .name           = "fsl-usb2-udc",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(usbotg_resources),
-        .resource       = usbotg_resources,
-        .dev            = {
-                .dma_mask               = &usb_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-
-struct platform_device mxc_usbdr_host_device = {
-        .name = "mxc-ehci",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(usbotg_resources),
-        .resource = usbotg_resources,
-        .dev = {
-                .dma_mask = &usb_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-static struct resource usbh1_resources[] = {
-        {
-                .start = MX51_OTG_BASE_ADDR + 0x200,
-                .end = MX51_OTG_BASE_ADDR + 0x200 + 0x1ff,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = MX51_MXC_INT_USB_H1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_usbh1_device = {
-        .name = "mxc-ehci",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(usbh1_resources),
-        .resource = usbh1_resources,
-        .dev = {
-                .dma_mask = &usb_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-static struct resource usbh2_resources[] = {
-        {
-                .start = MX51_OTG_BASE_ADDR + 0x400,
-                .end = MX51_OTG_BASE_ADDR + 0x400 + 0x1ff,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = MX51_MXC_INT_USB_H2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_usbh2_device = {
-        .name = "mxc-ehci",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(usbh2_resources),
-        .resource = usbh2_resources,
-        .dev = {
-                .dma_mask = &usb_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
deleted file mode 100644
index 55a5129bc29f..000000000000
--- a/arch/arm/mach-mx5/devices.h
+++ /dev/null
@@ -1,5 +0,0 @@
-extern struct platform_device mxc_usbdr_host_device;
-extern struct platform_device mxc_usbh1_device;
-extern struct platform_device mxc_usbh2_device;
-extern struct platform_device mxc_usbdr_udc_device;
-extern struct platform_device mxc_hsi2c_device;
diff --git a/arch/arm/mach-mx5/ehci.c b/arch/arm/mach-mx5/ehci.c
index 7ce12c804a32..c17fa131728b 100644
--- a/arch/arm/mach-mx5/ehci.c
+++ b/arch/arm/mach-mx5/ehci.c
@@ -52,7 +52,7 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
         void __iomem *usbother_base;
         int ret = 0;
 
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
         if (!usb_base) {
                 printk(KERN_ERR "%s(): ioremap failed\n", __func__);
                 return -ENOMEM;
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index bbf4564bd050..a6a3ab8f1b1c 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -28,7 +28,6 @@
 #include <asm/mach/arch.h>
 
 #include "devices-imx51.h"
-#include "devices.h"
 
 #define MBIMX51_TSC2007_GPIO    IMX_GPIO_NR(3, 30)
 #define MBIMX51_LED0            IMX_GPIO_NR(3, 5)
@@ -160,7 +159,7 @@ struct tsc2007_platform_data tsc2007_data = {
 static struct i2c_board_info mbimx51_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("tsc2007", 0x49),
-                .irq  = gpio_to_irq(MBIMX51_TSC2007_GPIO),
+                .irq  = IMX_GPIO_TO_IRQ(MBIMX51_TSC2007_GPIO),
                 .platform_data = &tsc2007_data,
         }, {
                 I2C_BOARD_INFO("tlv320aic23", 0x1a),
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
index 261923997643..d817fc80b986 100644
--- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
@@ -24,7 +24,6 @@
 
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
 #include <linux/leds.h>
 #include <linux/platform_device.h>
 #include <linux/input.h>
@@ -41,13 +40,12 @@
 #include <mach/audmux.h>
 
 #include "devices-imx51.h"
-#include "devices.h"
 
 static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
         /* LED */
         MX51_PAD_NANDF_D10__GPIO3_30,
         /* SWITCH */
-        _MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
+        NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, PAD_CTL_PUS_22K_UP |
                         PAD_CTL_PKE | PAD_CTL_SRE_FAST |
                         PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
         /* UART2 */
@@ -66,7 +64,7 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
         MX51_PAD_SD1_DATA2__SD1_DATA2,
         MX51_PAD_SD1_DATA3__SD1_DATA3,
         /* SD1 CD */
-        _MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
+        NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_PUS_22K_UP |
                         PAD_CTL_PKE | PAD_CTL_SRE_FAST |
                         PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 };
diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c
deleted file mode 100644
index 77e374c726fa..000000000000
--- a/arch/arm/mach-mx5/mm-mx50.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Create static mapping between physical to virtual memory.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-v3.h>
-#include <mach/irqs.h>
-
-/*
- * Define the MX50 memory map.
- */
-static struct map_desc mx50_io_desc[] __initdata = {
-        imx_map_entry(MX50, TZIC, MT_DEVICE),
-        imx_map_entry(MX50, SPBA0, MT_DEVICE),
-        imx_map_entry(MX50, AIPS1, MT_DEVICE),
-        imx_map_entry(MX50, AIPS2, MT_DEVICE),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx50_map_io(void)
-{
-        iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
-}
-
-void __init imx50_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX50);
-        mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
-}
-
-void __init mx50_init_irq(void)
-{
-        tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
-}
-
-void __init imx50_soc_init(void)
-{
-        /* i.mx50 has the i.mx31 type gpio */
-        mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
-        mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
-        mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
-        mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
-        mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
-        mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
-}
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index baea6e5cddd9..26eacc9d0d90 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -21,12 +21,27 @@
 #include <mach/devices-common.h>
 #include <mach/iomux-v3.h>
 
+static void imx5_idle(void)
+{
+        mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+}
+
+/*
+ * Define the MX50 memory map.
+ */
+static struct map_desc mx50_io_desc[] __initdata = {
+        imx_map_entry(MX50, TZIC, MT_DEVICE),
+        imx_map_entry(MX50, SPBA0, MT_DEVICE),
+        imx_map_entry(MX50, AIPS1, MT_DEVICE),
+        imx_map_entry(MX50, AIPS2, MT_DEVICE),
+};
+
 /*
  * Define the MX51 memory map.
  */
 static struct map_desc mx51_io_desc[] __initdata = {
+        imx_map_entry(MX51, TZIC, MT_DEVICE),
         imx_map_entry(MX51, IRAM, MT_DEVICE),
-        imx_map_entry(MX51, DEBUG, MT_DEVICE),
         imx_map_entry(MX51, AIPS1, MT_DEVICE),
         imx_map_entry(MX51, SPBA0, MT_DEVICE),
         imx_map_entry(MX51, AIPS2, MT_DEVICE),
@@ -36,6 +51,7 @@ static struct map_desc mx51_io_desc[] __initdata = {
  * Define the MX53 memory map.
  */
 static struct map_desc mx53_io_desc[] __initdata = {
+        imx_map_entry(MX53, TZIC, MT_DEVICE),
         imx_map_entry(MX53, AIPS1, MT_DEVICE),
         imx_map_entry(MX53, SPBA0, MT_DEVICE),
         imx_map_entry(MX53, AIPS2, MT_DEVICE),
@@ -46,21 +62,34 @@ static struct map_desc mx53_io_desc[] __initdata = {
  * system startup to create static physical to virtual memory mappings
  * for the IO modules.
  */
+void __init mx50_map_io(void)
+{
+        iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
+}
+
 void __init mx51_map_io(void)
 {
         iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
 }
 
+void __init mx53_map_io(void)
+{
+        iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
+}
+
+void __init imx50_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX50);
+        mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
+        mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
+}
+
 void __init imx51_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX51);
         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
-}
-
-void __init mx53_map_io(void)
-{
-        iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
+        imx_idle = imx5_idle;
 }
 
 void __init imx53_init_early(void)
@@ -70,35 +99,19 @@ void __init imx53_init_early(void)
         mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
 }
 
-void __init mx51_init_irq(void)
+void __init mx50_init_irq(void)
 {
-        unsigned long tzic_addr;
-        void __iomem *tzic_virt;
-
-        if (mx51_revision() < IMX_CHIP_REVISION_2_0)
-                tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
-        else
-                tzic_addr = MX51_TZIC_BASE_ADDR;
-
-        tzic_virt = ioremap(tzic_addr, SZ_16K);
-        if (!tzic_virt)
-                panic("unable to map TZIC interrupt controller\n");
+        tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
+}
 
-        tzic_init_irq(tzic_virt);
+void __init mx51_init_irq(void)
+{
+        tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
 }
 
 void __init mx53_init_irq(void)
 {
-        unsigned long tzic_addr;
-        void __iomem *tzic_virt;
-
-        tzic_addr = MX53_TZIC_BASE_ADDR;
-
-        tzic_virt = ioremap(tzic_addr, SZ_16K);
-        if (!tzic_virt)
-                panic("unable to map TZIC interrupt controller\n");
-
-        tzic_init_irq(tzic_virt);
+        tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
 }
 
 static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
@@ -138,13 +151,24 @@ static struct sdma_platform_data imx53_sdma_pdata __initdata = {
         .script_addrs = &imx53_sdma_script,
 };
 
+void __init imx50_soc_init(void)
+{
+        /* i.mx50 has the i.mx31 type gpio */
+        mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
+        mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
+        mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
+        mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
+        mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
+        mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
+}
+
 void __init imx51_soc_init(void)
 {
         /* i.mx51 has the i.mx31 type gpio */
-        mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH);
-        mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH);
-        mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH);
-        mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH);
+        mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
+        mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
+        mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
+        mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
 
         /* i.mx51 has the i.mx35 type sdma */
         imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
index c9209454807a..d5bf95825533 100644
--- a/arch/arm/mach-mx5/mx51_efika.c
+++ b/arch/arm/mach-mx5/mx51_efika.c
@@ -34,14 +34,12 @@
 #include <linux/usb/ulpi.h>
 #include <mach/ulpi.h>
 
-#include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
 #include "devices-imx51.h"
-#include "devices.h"
 #include "efika.h"
 #include "cpu_op-mx51.h"
 
@@ -133,7 +131,7 @@ static int initialize_otg_port(struct platform_device *pdev)
         u32 v;
         void __iomem *usb_base;
         void __iomem *usbother_base;
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
         if (!usb_base)
                 return -ENOMEM;
         usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
@@ -150,7 +148,7 @@ static int initialize_otg_port(struct platform_device *pdev)
         return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
 }
 
-static struct mxc_usbh_platform_data dr_utmi_config = {
+static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
         .init   = initialize_otg_port,
         .portsc = MXC_EHCI_UTMI_16BIT,
 };
@@ -170,7 +168,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
         gpio_set_value(EFIKAMX_USBH1_STP, 1);
         msleep(1);
 
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
         socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
 
         /* The clock for the USBH1 ULPI port will come externally */
@@ -189,7 +187,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
         return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
 }
 
-static struct mxc_usbh_platform_data usbh1_config = {
+static struct mxc_usbh_platform_data usbh1_config __initdata = {
         .init   = initialize_usbh1_port,
         .portsc = MXC_EHCI_MODE_ULPI,
 };
@@ -217,9 +215,9 @@ static void __init mx51_efika_usb(void)
         usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
                         ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
 
-        mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+        imx51_add_mxc_ehci_otg(&dr_utmi_config);
         if (usbh1_config.otg)
-                mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+                imx51_add_mxc_ehci_hs(1, &usbh1_config);
 }
 
 static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
@@ -589,7 +587,7 @@ static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
                 .bus_num = 0,
                 .chip_select = 0,
                 .platform_data = &mx51_efika_mc13892_data,
-                .irq = gpio_to_irq(EFIKAMX_PMIC),
+                .irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC),
         },
 };
 
@@ -631,4 +629,3 @@ void __init efika_board_common_init(void)
         get_cpu_op = mx51_get_cpu_op;
 #endif
 }
-
diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c
index e4529af0da72..0624fb8edffb 100644
--- a/arch/arm/mach-mx5/pm-imx5.c
+++ b/arch/arm/mach-mx5/pm-imx5.c
@@ -14,7 +14,8 @@
 #include <linux/err.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
-#include <mach/system.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
 #include "crm_regs.h"
 
 static struct clk *gpc_dvfs_clk;
diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c
index 76ae8dc33e00..144ebebc4a61 100644
--- a/arch/arm/mach-mx5/system.c
+++ b/arch/arm/mach-mx5/system.c
@@ -13,6 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
+#include <mach/common.h>
 #include "crm_regs.h"
 
 /* set cpu low power mode before WFI instruction. This function is called
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 6c38262a3aaa..ea8dcb7742bc 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,11 +1,11 @@
 # Common support
-obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o
+obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o mm.o
 
 obj-$(CONFIG_MXS_OCOTP) += ocotp.o
 obj-$(CONFIG_PM) += pm.o
 
-obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
-obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
+obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
+obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
 
 obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
 obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
diff --git a/arch/arm/mach-mxs/include/mach/gpio.h b/arch/arm/mach-mxs/include/mach/gpio.h
index 828ccccb6aad..56025aa0a639 100644
--- a/arch/arm/mach-mxs/include/mach/gpio.h
+++ b/arch/arm/mach-mxs/include/mach/gpio.h
@@ -22,14 +22,10 @@
 
 #include <asm-generic/gpio.h>
 
-#define MXS_GPIO_NR(bank, nr)   ((bank) * 32 + (nr))
-
 /* use gpiolib dispatchers */
 #define gpio_get_value          __gpio_get_value
 #define gpio_set_value          __gpio_set_value
 #define gpio_cansleep           __gpio_cansleep
 #define gpio_to_irq             __gpio_to_irq
 
-#define irq_to_gpio(irq)        ((irq) - MXS_GPIO_IRQ_START)
-
 #endif /* __MACH_MXS_GPIO_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
index 35a89dd27242..5aa5f754c846 100644
--- a/arch/arm/mach-mxs/include/mach/mxs.h
+++ b/arch/arm/mach-mxs/include/mach/mxs.h
@@ -86,6 +86,8 @@
         .type = _type,                                                  \
 }
 
+#define MXS_GPIO_NR(bank, nr)   ((bank) * 32 + (nr))
+
 #define MXS_SET_ADDR            0x4
 #define MXS_CLR_ADDR            0x8
 #define MXS_TOG_ADDR            0xc
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index 3c2de33803ab..99b01e988c8d 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -15,7 +15,6 @@
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
-#include <linux/irq.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index eaaf6ff28990..8b3aa7afdae0 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -16,7 +16,6 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
-#include <linux/irq.h>
 #include <linux/clk.h>
 
 #include <asm/mach-types.h>
@@ -352,6 +351,11 @@ static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = {
         },
 };
 
+static struct gpio mx28evk_lcd_gpios[] = {
+        { MX28EVK_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, "lcd-enable" },
+        { MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" },
+};
+
 static void __init mx28evk_init(void)
 {
         int ret;
@@ -378,19 +382,12 @@ static void __init mx28evk_init(void)
                 mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
         }
 
-        ret = gpio_request_one(MX28EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
+        ret = gpio_request_array(mx28evk_lcd_gpios,
+                                 ARRAY_SIZE(mx28evk_lcd_gpios));
         if (ret)
-                pr_warn("failed to request gpio lcd-enable: %d\n", ret);
+                pr_warn("failed to request gpio pins for lcd: %d\n", ret);
         else
-                gpio_set_value(MX28EVK_LCD_ENABLE, 1);
-
-        ret = gpio_request_one(MX28EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
-        if (ret)
-                pr_warn("failed to request gpio bl-enable: %d\n", ret);
-        else
-                gpio_set_value(MX28EVK_BL_ENABLE, 1);
-
-        mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
+                mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
 
         /* power on mmc slot by writing 0 to the gpio */
         ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW,
@@ -403,7 +400,8 @@ static void __init mx28evk_init(void)
                                "mmc1-slot-power");
         if (ret)
                 pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret);
-        mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
+        else
+                mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
 
         gpio_led_register_device(0, &mx28evk_led_data);
 }
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
index 7f38d82b69af..3fe5dd532145 100644
--- a/arch/arm/mach-mxs/mach-stmp378x_devb.c
+++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c
@@ -19,7 +19,6 @@
 
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
-#include <linux/irq.h>
 #include <linux/spi/spi.h>
 
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-mxs/mm-mx23.c b/arch/arm/mach-mxs/mm-mx23.c
deleted file mode 100644
index 1b2345ac1a87..000000000000
--- a/arch/arm/mach-mxs/mm-mx23.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License.  You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- *
- * Create static mapping between physical to virtual memory.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/mx23.h>
-#include <mach/common.h>
-#include <mach/iomux.h>
-
-/*
- * Define the MX23 memory map.
- */
-static struct map_desc mx23_io_desc[] __initdata = {
-        mxs_map_entry(MX23, OCRAM, MT_DEVICE),
-        mxs_map_entry(MX23, IO, MT_DEVICE),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx23_map_io(void)
-{
-        iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
-}
-
-void __init mx23_init_irq(void)
-{
-        icoll_init_irq();
-}
diff --git a/arch/arm/mach-mxs/mm-mx28.c b/arch/arm/mach-mxs/mm.c
index b6e18ddb92c0..50af5ceebf6d 100644
--- a/arch/arm/mach-mxs/mm-mx28.c
+++ b/arch/arm/mach-mxs/mm.c
@@ -16,11 +16,20 @@
 
 #include <asm/mach/map.h>
 
+#include <mach/mx23.h>
 #include <mach/mx28.h>
 #include <mach/common.h>
 #include <mach/iomux.h>
 
 /*
+ * Define the MX23 memory map.
+ */
+static struct map_desc mx23_io_desc[] __initdata = {
+        mxs_map_entry(MX23, OCRAM, MT_DEVICE),
+        mxs_map_entry(MX23, IO, MT_DEVICE),
+};
+
+/*
  * Define the MX28 memory map.
  */
 static struct map_desc mx28_io_desc[] __initdata = {
@@ -33,6 +42,16 @@ static struct map_desc mx28_io_desc[] __initdata = {
  * system startup to create static physical to virtual memory mappings
  * for the IO modules.
  */
+void __init mx23_map_io(void)
+{
+        iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
+}
+
+void __init mx23_init_irq(void)
+{
+        icoll_init_irq();
+}
+
 void __init mx28_map_io(void)
 {
         iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
diff --git a/arch/arm/mach-netx/nxdb500.c b/arch/arm/mach-netx/nxdb500.c
index ca8b203a3c99..90903dd44cbc 100644
--- a/arch/arm/mach-netx/nxdb500.c
+++ b/arch/arm/mach-netx/nxdb500.c
@@ -200,7 +200,7 @@ static void __init nxdb500_init(void)
 }
 
 MACHINE_START(NXDB500, "Hilscher nxdb500")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .map_io         = netx_map_io,
         .init_irq       = netx_init_irq,
         .timer          = &netx_timer,
diff --git a/arch/arm/mach-netx/nxdkn.c b/arch/arm/mach-netx/nxdkn.c
index d775cbe07278..c63384aba500 100644
--- a/arch/arm/mach-netx/nxdkn.c
+++ b/arch/arm/mach-netx/nxdkn.c
@@ -93,7 +93,7 @@ static void __init nxdkn_init(void)
 }
 
 MACHINE_START(NXDKN, "Hilscher nxdkn")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .map_io         = netx_map_io,
         .init_irq       = netx_init_irq,
         .timer          = &netx_timer,
diff --git a/arch/arm/mach-netx/nxeb500hmi.c b/arch/arm/mach-netx/nxeb500hmi.c
index de369cd1dcbe..8f548ec83ad2 100644
--- a/arch/arm/mach-netx/nxeb500hmi.c
+++ b/arch/arm/mach-netx/nxeb500hmi.c
@@ -177,7 +177,7 @@ static void __init nxeb500hmi_init(void)
 }
 
 MACHINE_START(NXEB500HMI, "Hilscher nxeb500hmi")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .map_io         = netx_map_io,
         .init_irq       = netx_init_irq,
         .timer          = &netx_timer,
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index 139930350d93..398a75f62bee 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -276,7 +276,7 @@ static void __init nhk8815_platform_init(void)
 
 MACHINE_START(NOMADIK, "NHK8815")
         /* Maintainer: ST MicroElectronics */
-        .boot_params    = 0x100,
+        .atag_offset    = 0x100,
         .map_io         = cpu8815_map_io,
         .init_irq       = cpu8815_init_irq,
         .timer          = &nomadik_timer,
diff --git a/arch/arm/mach-nuc93x/mach-nuc932evb.c b/arch/arm/mach-nuc93x/mach-nuc932evb.c
index d70257042480..1f741b1c1604 100644
--- a/arch/arm/mach-nuc93x/mach-nuc932evb.c
+++ b/arch/arm/mach-nuc93x/mach-nuc932evb.c
@@ -35,7 +35,6 @@ static void __init nuc932evb_init(void)
 
 MACHINE_START(NUC932EVB, "NUC932EVB")
         /* Maintainer: Wan ZongShun */
-        .boot_params    = 0,
         .map_io         = nuc932evb_map_io,
         .init_irq       = nuc93x_init_irq,
         .init_machine   = nuc932evb_init,
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 312ea6b0409d..eb36b25450a0 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -386,7 +386,7 @@ static void __init ams_delta_map_io(void)
 
 MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
         /* Maintainer: Jonathan McDowell <noodles@earth.li> */
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .map_io         = ams_delta_map_io,
         .reserve        = omap_reserve,
         .init_irq       = ams_delta_init_irq,
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index a6b1bea50371..999789c4811d 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -389,7 +389,7 @@ static void __init omap_fsample_map_io(void)
 
 MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
 /* Maintainer: Brian Swetland <swetland@google.com> */
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .map_io         = omap_fsample_map_io,
         .reserve        = omap_reserve,
         .init_irq       = omap_fsample_init_irq,
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 04fc356c40fa..23cc9e4ad50d 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -94,7 +94,7 @@ static void __init omap_generic_map_io(void)
 
 MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
         /* Maintainer: Tony Lindgren <tony@atomide.com> */
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .map_io         = omap_generic_map_io,
         .reserve        = omap_reserve,
         .init_irq       = omap_generic_init_irq,
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index cb7fb1aa3dca..6c70c28d055c 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -461,7 +461,7 @@ static void __init h2_map_io(void)
 
 MACHINE_START(OMAP_H2, "TI-H2")
         /* Maintainer: Imre Deak <imre.deak@nokia.com> */
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .map_io         = h2_map_io,
         .reserve        = omap_reserve,
         .init_irq       = h2_init_irq,
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 31f34875ffad..8e2b64a46929 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -449,7 +449,7 @@ static void __init h3_map_io(void)
 
 MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
         /* Maintainer: Texas Instruments, Inc. */
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .map_io         = h3_map_io,
         .reserve        = omap_reserve,
         .init_irq       = h3_init_irq,
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 36e06ea7ec65..e81ead1c89ea 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -611,7 +611,7 @@ static void __init htcherald_init_irq(void)
 MACHINE_START(HERALD, "HTC Herald")
         /* Maintainer: Cory Maccarrone <darkstar6262@gmail.com> */
         /* Maintainer: wing-linux.sourceforge.net */
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .map_io         = htcherald_map_io,
         .reserve        = omap_reserve,
         .init_irq       = htcherald_init_irq,
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 0b1ba462d388..8b034594fbc7 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -459,7 +459,7 @@ static void __init innovator_map_io(void)
 
 MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
         /* Maintainer: MontaVista Software, Inc. */
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .map_io         = innovator_map_io,
         .reserve        = omap_reserve,
         .init_irq       = innovator_init_irq,
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 5469ce247ffe..6825635ac681 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -264,7 +264,7 @@ static void __init omap_nokia770_map_io(void)
 }
 
 MACHINE_START(NOKIA770, "Nokia 770")
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .map_io         = omap_nokia770_map_io,
         .reserve        = omap_reserve,
         .init_irq       = omap_nokia770_init_irq,
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index b08a21380772..44b8e9362bf4 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -583,7 +583,7 @@ static void __init osk_map_io(void)
 
 MACHINE_START(OMAP_OSK, "TI-OSK")
         /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .map_io         = osk_map_io,
         .reserve        = omap_reserve,
         .init_irq       = osk_init_irq,
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 459cb6bfed55..3d8cd90b1dbb 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -275,7 +275,7 @@ static void __init omap_palmte_map_io(void)
 }
 
 MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .map_io         = omap_palmte_map_io,
         .reserve        = omap_reserve,
         .init_irq       = omap_palmte_init_irq,
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index b214f45f646c..d0eefe81cd1b 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -321,7 +321,7 @@ static void __init omap_palmtt_map_io(void)
 }
 
 MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .map_io         = omap_palmtt_map_io,
         .reserve        = omap_reserve,
         .init_irq       = omap_palmtt_init_irq,
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 9b0ea48d35fd..98e79bc09213 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -341,7 +341,7 @@ omap_palmz71_map_io(void)
 }
 
 MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .map_io         = omap_palmz71_map_io,
         .reserve        = omap_reserve,
         .init_irq       = omap_palmz71_init_irq,
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 67acd4142639..ad3a1567604e 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -350,7 +350,7 @@ static void __init omap_perseus2_map_io(void)
 
 MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
         /* Maintainer: Kevin Hilman <kjh@hilman.org> */
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .map_io         = omap_perseus2_map_io,
         .reserve        = omap_reserve,
         .init_irq       = omap_perseus2_init_irq,
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 9c3b7c52d9cf..602b55c39d3d 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -421,7 +421,7 @@ static void __init omap_sx1_map_io(void)
 }
 
 MACHINE_START(SX1, "OMAP310 based Siemens SX1")
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .map_io         = omap_sx1_map_io,
         .reserve        = omap_reserve,
         .init_irq       = omap_sx1_init_irq,
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 036edc0ee9b6..80165154617a 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -301,7 +301,7 @@ static void __init voiceblue_init(void)
 
 MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
         /* Maintainer: Ladislav Michl <michl@2n.cz> */
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .map_io         = voiceblue_map_io,
         .reserve        = omap_reserve,
         .init_irq       = voiceblue_init_irq,
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 870886a29594..1cfa1b6bb62b 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -121,6 +121,7 @@ void __init omap1_map_common_io(void)
 #endif
 
         omap_sram_init();
+        omap_init_consistent_dma_size();
 }
 
 /*
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index ab7395d84bc8..91f9abbd3250 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -31,6 +31,7 @@
 static int dsp_use;
 static struct clk *api_clk;
 static struct clk *dsp_clk;
+static struct platform_device **omap_mcbsp_devices;
 
 static void omap1_mcbsp_request(unsigned int id)
 {
@@ -78,6 +79,17 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
         .free           = omap1_mcbsp_free,
 };
 
+#define OMAP7XX_MCBSP1_BASE     0xfffb1000
+#define OMAP7XX_MCBSP2_BASE     0xfffb1800
+
+#define OMAP1510_MCBSP1_BASE    0xe1011800
+#define OMAP1510_MCBSP2_BASE    0xfffb1000
+#define OMAP1510_MCBSP3_BASE    0xe1017000
+
+#define OMAP1610_MCBSP1_BASE    0xe1011800
+#define OMAP1610_MCBSP2_BASE    0xfffb1000
+#define OMAP1610_MCBSP3_BASE    0xe1017000
+
 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 struct resource omap7xx_mcbsp_res[][6] = {
         {
@@ -369,6 +381,39 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
 #define OMAP16XX_MCBSP_COUNT            0
 #endif
 
+static void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
+                        struct omap_mcbsp_platform_data *config, int size)
+{
+        int i;
+
+        omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *),
+                                     GFP_KERNEL);
+        if (!omap_mcbsp_devices) {
+                printk(KERN_ERR "Could not register McBSP devices\n");
+                return;
+        }
+
+        for (i = 0; i < size; i++) {
+                struct platform_device *new_mcbsp;
+                int ret;
+
+                new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
+                if (!new_mcbsp)
+                        continue;
+                platform_device_add_resources(new_mcbsp, &res[i * res_count],
+                                        res_count);
+                config[i].reg_size = 2;
+                config[i].reg_step = 2;
+                new_mcbsp->dev.platform_data = &config[i];
+                ret = platform_device_add(new_mcbsp);
+                if (ret) {
+                        platform_device_put(new_mcbsp);
+                        continue;
+                }
+                omap_mcbsp_devices[i] = new_mcbsp;
+        }
+}
+
 static int __init omap1_mcbsp_init(void)
 {
         if (!cpu_class_is_omap1())
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f34336560437..cd45c045ab8c 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -116,9 +116,12 @@ obj-$(CONFIG_ARCH_OMAP4)		+= $(powerdomain-common) \
 obj-$(CONFIG_ARCH_OMAP2)                += clockdomain.o \
                                            clockdomain2xxx_3xxx.o \
                                            clockdomains2xxx_3xxx_data.o
+obj-$(CONFIG_SOC_OMAP2420)              += clockdomains2420_data.o
+obj-$(CONFIG_SOC_OMAP2430)              += clockdomains2430_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += clockdomain.o \
                                            clockdomain2xxx_3xxx.o \
-                                           clockdomains2xxx_3xxx_data.o
+                                           clockdomains2xxx_3xxx_data.o \
+                                           clockdomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomain.o \
                                            clockdomain44xx.o \
                                            clockdomains44xx_data.o
@@ -185,78 +188,66 @@ endif
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o
 obj-$(CONFIG_MACH_OMAP_H4)              += board-h4.o
-obj-$(CONFIG_MACH_OMAP_2430SDP)         += board-2430sdp.o \
-                                           hsmmc.o
+obj-$(CONFIG_MACH_OMAP_2430SDP)         += board-2430sdp.o
 obj-$(CONFIG_MACH_OMAP_APOLLON)         += board-apollon.o
-obj-$(CONFIG_MACH_OMAP3_BEAGLE)         += board-omap3beagle.o \
-                                           hsmmc.o
-obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o \
-                                           hsmmc.o
-obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o \
-                                           board-flash.o \
-                                           hsmmc.o
-obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o \
-                                           hsmmc.o
-obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o \
-                                           hsmmc.o
-obj-$(CONFIG_MACH_OVERO)                += board-overo.o \
-                                           hsmmc.o
-obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o \
-                                           hsmmc.o
-obj-$(CONFIG_MACH_OMAP3_PANDORA)        += board-omap3pandora.o \
-                                           hsmmc.o
-obj-$(CONFIG_MACH_OMAP_3430SDP)         += board-3430sdp.o \
-                                           hsmmc.o \
-                                           board-flash.o
+obj-$(CONFIG_MACH_OMAP3_BEAGLE)         += board-omap3beagle.o
+obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o
+obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o
+obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
+obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
+obj-$(CONFIG_MACH_ENCORE)               += board-omap3encore.o
+obj-$(CONFIG_MACH_OVERO)                += board-overo.o
+obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o
+obj-$(CONFIG_MACH_OMAP3_PANDORA)        += board-omap3pandora.o
+obj-$(CONFIG_MACH_OMAP_3430SDP)         += board-3430sdp.o
 obj-$(CONFIG_MACH_NOKIA_N8X0)           += board-n8x0.o
 obj-$(CONFIG_MACH_NOKIA_RM680)          += board-rm680.o \
-                                           sdram-nokia.o \
-                                           hsmmc.o
+                                           sdram-nokia.o
 obj-$(CONFIG_MACH_NOKIA_RX51)           += board-rx51.o \
                                            sdram-nokia.o \
                                            board-rx51-peripherals.o \
-                                           board-rx51-video.o \
-                                           hsmmc.o
+                                           board-rx51-video.o
 obj-$(CONFIG_MACH_OMAP_ZOOM2)           += board-zoom.o \
                                            board-zoom-peripherals.o \
                                            board-zoom-display.o \
-                                           board-flash.o \
-                                           hsmmc.o \
                                            board-zoom-debugboard.o
 obj-$(CONFIG_MACH_OMAP_ZOOM3)           += board-zoom.o \
                                            board-zoom-peripherals.o \
                                            board-zoom-display.o \
-                                           board-flash.o \
-                                           hsmmc.o \
                                            board-zoom-debugboard.o
 obj-$(CONFIG_MACH_OMAP_3630SDP)         += board-3630sdp.o \
                                            board-zoom-peripherals.o \
-                                           board-zoom-display.o \
-                                           board-flash.o \
-                                           hsmmc.o
-obj-$(CONFIG_MACH_CM_T35)               += board-cm-t35.o \
-                                           hsmmc.o
+                                           board-zoom-display.o
+obj-$(CONFIG_MACH_CM_T35)               += board-cm-t35.o
 obj-$(CONFIG_MACH_CM_T3517)             += board-cm-t3517.o
-obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o \
-                                           hsmmc.o
-obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)      += board-omap3touchbook.o \
-                                           hsmmc.o
+obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o
+obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)      += board-omap3touchbook.o
 obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o \
-                                           hsmmc.o \
                                            omap_phy_internal.o
 obj-$(CONFIG_MACH_OMAP4_PANDA)          += board-omap4panda.o \
-                                           hsmmc.o \
+                                           omap_phy_internal.o
+
+obj-$(CONFIG_MACH_PCM049)               += board-omap4pcm049.o \
                                            omap_phy_internal.o
 
 obj-$(CONFIG_MACH_OMAP3517EVM)          += board-am3517evm.o \
-                                           omap_phy_internal.o \
+                                           omap_phy_internal.o
 
 obj-$(CONFIG_MACH_CRANEBOARD)           += board-am3517crane.o
 
-obj-$(CONFIG_MACH_SBC3530)              += board-omap3stalker.o \
-                                           hsmmc.o
+obj-$(CONFIG_MACH_SBC3530)              += board-omap3stalker.o
 obj-$(CONFIG_MACH_TI8168EVM)            += board-ti8168evm.o
+
 # Platform specific device init code
+
+omap-flash-$(CONFIG_MTD_NAND_OMAP2)     := board-flash.o
+omap-flash-$(CONFIG_MTD_ONENAND_OMAP2)  := board-flash.o
+obj-y                                   += $(omap-flash-y) $(omap-flash-m)
+
+omap-hsmmc-$(CONFIG_MMC_OMAP_HS)        := hsmmc.o
+obj-y                                   += $(omap-hsmmc-m) $(omap-hsmmc-y)
+
+
 usbfs-$(CONFIG_ARCH_OMAP_OTG)           := usb-fs.o
 obj-y                                   += $(usbfs-m) $(usbfs-y)
 obj-y                                   += usb-musb.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 2028464cf5b9..bb5452eb842d 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -141,12 +141,6 @@ static struct omap_board_config_kernel sdp2430_config[] __initdata = {
         {OMAP_TAG_LCD, &sdp2430_lcd_config},
 };
 
-static void __init omap_2430sdp_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
-
 static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
         REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
 };
@@ -235,6 +229,7 @@ static void __init omap_2430sdp_init(void)
 
         platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
         omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
         omap2_hsmmc_init(mmc);
         omap2_usbfs_init(&sdp2430_usb_config);
 
@@ -248,18 +243,12 @@ static void __init omap_2430sdp_init(void)
                          "Secondary LCD backlight");
 }
 
-static void __init omap_2430sdp_map_io(void)
-{
-        omap2_set_globals_243x();
-        omap243x_map_common_io();
-}
-
 MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
         /* Maintainer: Syed Khasim - Texas Instruments Inc */
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
-        .map_io         = omap_2430sdp_map_io,
-        .init_early     = omap_2430sdp_init_early,
+        .map_io         = omap243x_map_io,
+        .init_early     = omap2430_init_early,
         .init_irq       = omap2_init_irq,
         .init_machine   = omap_2430sdp_init,
         .timer          = &omap2_timer,
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index bd600cfb7f80..5b5999caf71d 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -225,12 +225,6 @@ static struct omap_dss_board_info sdp3430_dss_data = {
 static struct omap_board_config_kernel sdp3430_config[] __initdata = {
 };
 
-static void __init omap_3430sdp_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
-}
-
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
@@ -719,6 +713,7 @@ static void __init omap_3430sdp_init(void)
                 gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
         omap_ads7846_init(1, gpio_pendown, 310, NULL);
         board_serial_init();
+        omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
         usb_musb_init(NULL);
         board_smc91x_init();
         board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
@@ -729,10 +724,10 @@ static void __init omap_3430sdp_init(void)
 
 MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
         /* Maintainer: Syed Khasim - Texas Instruments Inc */
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = omap_3430sdp_init_early,
+        .init_early     = omap3430_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = omap_3430sdp_init,
         .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index e4f37b57a0c4..f552305162fc 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -70,13 +70,6 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 static struct omap_board_config_kernel sdp_config[] __initdata = {
 };
 
-static void __init omap_sdp_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
-                                  h8mbx00u0mer0em_sdrc_params);
-}
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -207,6 +200,8 @@ static void __init omap_sdp_init(void)
         omap_board_config = sdp_config;
         omap_board_config_size = ARRAY_SIZE(sdp_config);
         zoom_peripherals_init();
+        omap_sdrc_init(h8mbx00u0mer0em_sdrc_params,
+                                  h8mbx00u0mer0em_sdrc_params);
         zoom_display_init();
         board_smc91x_init();
         board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
@@ -215,10 +210,10 @@ static void __init omap_sdp_init(void)
 }
 
 MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = omap_sdp_init_early,
+        .init_early     = omap3630_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = omap_sdp_init,
         .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index c7cef44c75d4..6a4fbb2b4aaa 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -389,12 +389,6 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
         { OMAP_TAG_LCD,         &sdp4430_lcd_config },
 };
 
-static void __init omap_4430sdp_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
-
 static struct omap_musb_board_data musb_board_data = {
         .interface_type         = MUSB_INTERFACE_UTMI,
         .mode                   = MUSB_OTG,
@@ -809,6 +803,7 @@ static void __init omap_4430sdp_init(void)
         omap_sfh7741prox_init();
         platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
         board_serial_init();
+        omap_sdrc_init(NULL, NULL);
         omap4_sdp4430_wifi_init();
         omap4_twl6030_hsmmc_init(mmc);
 
@@ -830,18 +825,12 @@ static void __init omap_4430sdp_init(void)
         omap_4430sdp_display_init();
 }
 
-static void __init omap_4430sdp_map_io(void)
-{
-        omap2_set_globals_443x();
-        omap44xx_map_common_io();
-}
-
 MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
         /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
-        .map_io         = omap_4430sdp_map_io,
-        .init_early     = omap_4430sdp_init_early,
+        .map_io         = omap4_map_io,
+        .init_early     = omap4430_init_early,
         .init_irq       = gic_init_irq,
         .init_machine   = omap_4430sdp_init,
         .timer          = &omap4_timer,
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 933e9353cb37..7834536ab416 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -47,12 +47,6 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
-static void __init am3517_crane_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
-
 static struct usbhs_omap_board_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -70,6 +64,7 @@ static void __init am3517_crane_init(void)
 
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
 
         omap_board_config = am3517_crane_config;
         omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
@@ -98,10 +93,10 @@ static void __init am3517_crane_init(void)
 }
 
 MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = am3517_crane_init_early,
+        .init_early     = am35xx_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = am3517_crane_init,
         .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index f3006c304150..65a5912278ac 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -362,11 +362,6 @@ static struct omap_dss_board_info am3517_evm_dss_data = {
 /*
  * Board initialization
  */
-static void __init am3517_evm_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 
 static struct omap_musb_board_data musb_board_data = {
         .interface_type         = MUSB_INTERFACE_ULPI,
@@ -469,6 +464,7 @@ static void __init am3517_evm_init(void)
         am3517_evm_i2c_init();
         omap_display_init(&am3517_evm_dss_data);
         omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
 
         /* Configure GPIO for EHCI port */
         omap_mux_init_gpio(57, OMAP_PIN_OUTPUT);
@@ -490,10 +486,10 @@ static void __init am3517_evm_init(void)
 }
 
 MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = am3517_evm_init_early,
+        .init_early     = am35xx_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = am3517_evm_init,
         .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 70211703ff9f..29c409b68b52 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -273,12 +273,6 @@ static struct omap_board_config_kernel apollon_config[] __initdata = {
         { OMAP_TAG_LCD,         &apollon_lcd_config },
 };
 
-static void __init omap_apollon_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
-
 static struct gpio apollon_gpio_leds[] __initdata = {
         { LED0_GPIO13, GPIOF_OUT_INIT_LOW, "LED0" }, /* LED0 - AA10 */
         { LED1_GPIO14, GPIOF_OUT_INIT_LOW, "LED1" }, /* LED1 - AA6  */
@@ -340,20 +334,15 @@ static void __init omap_apollon_init(void)
          */
         platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices));
         omap_serial_init();
-}
-
-static void __init omap_apollon_map_io(void)
-{
-        omap2_set_globals_242x();
-        omap242x_map_common_io();
+        omap_sdrc_init(NULL, NULL);
 }
 
 MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
         /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
-        .map_io         = omap_apollon_map_io,
-        .init_early     = omap_apollon_init_early,
+        .map_io         = omap242x_map_io,
+        .init_early     = omap2420_init_early,
         .init_irq       = omap2_init_irq,
         .init_machine   = omap_apollon_init,
         .timer          = &omap2_timer,
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 3af8aab435b5..5665e688bd26 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -471,13 +471,6 @@ static void __init cm_t35_init_i2c(void)
         omap3_pmic_init("tps65930", &cm_t35_twldata);
 }
 
-static void __init cm_t35_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                             mt46h32m32lf6_sdrc_params);
-}
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         /* nCS and IRQ for CM-T35 ethernet */
@@ -610,6 +603,8 @@ static void __init cm_t3x_common_init(void)
         omap_board_config_size = ARRAY_SIZE(cm_t35_config);
         omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
         omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
         cm_t35_init_i2c();
         omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL);
         cm_t35_init_ethernet();
@@ -634,20 +629,20 @@ static void __init cm_t3730_init(void)
 }
 
 MACHINE_START(CM_T35, "Compulab CM-T35")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = cm_t35_init_early,
+        .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = cm_t35_init,
         .timer          = &omap3_timer,
 MACHINE_END
 
 MACHINE_START(CM_T3730, "Compulab CM-T3730")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = cm_t35_init_early,
+        .init_early     = omap3630_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = cm_t3730_init,
         .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 05c72f4c1b57..3f4dc6626845 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -251,12 +251,6 @@ static inline void cm_t3517_init_nand(void) {}
 static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
 };
 
-static void __init cm_t3517_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         /* GPIO186 - Green LED */
@@ -289,6 +283,7 @@ static void __init cm_t3517_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
         omap_board_config = cm_t3517_config;
         omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
         cm_t3517_init_leds();
@@ -299,10 +294,10 @@ static void __init cm_t3517_init(void)
 }
 
 MACHINE_START(CM_T3517, "Compulab CM-T3517")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = cm_t3517_init_early,
+        .init_early     = am35xx_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = cm_t3517_init,
         .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index b6002ec31c6a..556df32d88ea 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -397,19 +397,6 @@ static struct platform_device keys_gpio = {
         },
 };
 
-
-static void __init devkit8000_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
-}
-
-static void __init devkit8000_init_irq(void)
-{
-        omap3_init_irq();
-}
-
 #define OMAP_DM9000_BASE        0x2c000000
 
 static struct resource omap_dm9000_resources[] = {
@@ -645,6 +632,8 @@ static void __init devkit8000_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
         omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
 
         omap_dm9000_init();
 
@@ -667,11 +656,11 @@ static void __init devkit8000_init(void)
 }
 
 MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = devkit8000_init_early,
-        .init_irq       = devkit8000_init_irq,
+        .init_early     = omap35xx_init_early,
+        .init_irq       = omap3_init_irq,
         .init_machine   = devkit8000_init,
         .timer          = &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index aa1b0cbe19d2..30a6f527510c 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -148,11 +148,6 @@ __init board_nand_init(struct mtd_partition *nand_parts,
         board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
         gpmc_nand_init(&board_nand_data);
 }
-#else
-void
-__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, int nand_type)
-{
-}
 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
 
 /**
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index c240a3f8d163..d25503a98417 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -24,7 +24,26 @@ struct flash_partitions {
         int nr_parts;
 };
 
+#if defined(CONFIG_MTD_NAND_OMAP2) || \
+                defined(CONFIG_MTD_NAND_OMAP2_MODULE) || \
+                defined(CONFIG_MTD_ONENAND_OMAP2) || \
+                defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
 extern void board_flash_init(struct flash_partitions [],
                                 char chip_sel[][GPMC_CS_NUM], int nand_type);
+#else
+static inline void board_flash_init(struct flash_partitions part[],
+                                char chip_sel[][GPMC_CS_NUM], int nand_type)
+{
+}
+#endif
+
+#if defined(CONFIG_MTD_NAND_OMAP2) || \
+                defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 extern void board_nand_init(struct mtd_partition *nand_parts,
                                         u8 nr_parts, u8 cs, int nand_type);
+#else
+static inline void board_nand_init(struct mtd_partition *nand_parts,
+                                        u8 nr_parts, u8 cs, int nand_type)
+{
+}
+#endif
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 54db41a84a9b..e8d45d3bd3e0 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -36,12 +36,12 @@ static struct omap_board_config_kernel generic_config[] = {
 static void __init omap_generic_init_early(void)
 {
         omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
 }
 
 static void __init omap_generic_init(void)
 {
         omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
         omap_board_config = generic_config;
         omap_board_config_size = ARRAY_SIZE(generic_config);
 }
@@ -66,7 +66,7 @@ static void __init omap_generic_map_io(void)
 /* XXX This machine entry name should be updated */
 MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
         /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap_generic_map_io,
         .init_early     = omap_generic_init_early,
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 45de2b319ec9..fe75c195f69f 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -290,17 +290,6 @@ static struct omap_board_config_kernel h4_config[] __initdata = {
         { OMAP_TAG_LCD,         &h4_lcd_config },
 };
 
-static void __init omap_h4_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
-
-static void __init omap_h4_init_irq(void)
-{
-        omap2_init_irq();
-}
-
 static struct at24_platform_data m24c01 = {
         .byte_len       = SZ_1K / 8,
         .page_size      = 16,
@@ -371,22 +360,17 @@ static void __init omap_h4_init(void)
         platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
         omap2_usbfs_init(&h4_usb_config);
         omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
         h4_init_flash();
 }
 
-static void __init omap_h4_map_io(void)
-{
-        omap2_set_globals_242x();
-        omap242x_map_common_io();
-}
-
 MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
         /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
-        .map_io         = omap_h4_map_io,
-        .init_early     = omap_h4_init_early,
-        .init_irq       = omap_h4_init_irq,
+        .map_io         = omap242x_map_io,
+        .init_early     = omap2420_init_early,
+        .init_irq       = omap2_init_irq,
         .init_machine   = omap_h4_init,
         .timer          = &omap2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 35be778caf1b..e20cad6a0835 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -491,13 +491,6 @@ static struct platform_device *igep_devices[] __initdata = {
         &igep_vwlan_device,
 };
 
-static void __init igep_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(m65kxxxxam_sdrc_params,
-                                  m65kxxxxam_sdrc_params);
-}
-
 static int igep2_keymap[] = {
         KEY(0, 0, KEY_LEFT),
         KEY(0, 1, KEY_RIGHT),
@@ -650,6 +643,8 @@ static void __init igep_init(void)
         igep_i2c_init();
         platform_add_devices(igep_devices, ARRAY_SIZE(igep_devices));
         omap_serial_init();
+        omap_sdrc_init(m65kxxxxam_sdrc_params,
+                                  m65kxxxxam_sdrc_params);
         usb_musb_init(NULL);
 
         igep_flash_init();
@@ -672,20 +667,20 @@ static void __init igep_init(void)
 }
 
 MACHINE_START(IGEP0020, "IGEP v2 board")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = igep_init_early,
+        .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = igep_init,
         .timer          = &omap3_timer,
 MACHINE_END
 
 MACHINE_START(IGEP0030, "IGEP OMAP3 module")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = igep_init_early,
+        .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = igep_init,
         .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 218764c9377e..0fa28be2cfda 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -193,12 +193,6 @@ static struct omap_board_config_kernel ldp_config[] __initdata = {
         { OMAP_TAG_LCD,         &ldp_lcd_config },
 };
 
-static void __init omap_ldp_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
-
 static struct twl4030_gpio_platform_data ldp_gpio_data = {
         .gpio_base      = OMAP_MAX_GPIO_LINES,
         .irq_base       = TWL4030_GPIO_IRQ_BASE,
@@ -325,6 +319,7 @@ static void __init omap_ldp_init(void)
         platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
         omap_ads7846_init(1, 54, 310, NULL);
         omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
         usb_musb_init(NULL);
         board_nand_init(ldp_nand_partitions,
                 ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
@@ -333,10 +328,10 @@ static void __init omap_ldp_init(void)
 }
 
 MACHINE_START(OMAP_LDP, "OMAP LDP board")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = omap_ldp_init_early,
+        .init_early     = omap3430_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = omap_ldp_init,
         .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index e11f0c5d608a..e9d5f4a3d064 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -616,18 +616,6 @@ static struct i2c_board_info n810_i2c_board_info_2[] __initdata = {
         },
 };
 
-static void __init n8x0_map_io(void)
-{
-        omap2_set_globals_242x();
-        omap242x_map_common_io();
-}
-
-static void __init n8x0_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         /* I2S codec port pins for McBSP block */
@@ -689,36 +677,37 @@ static void __init n8x0_init_machine(void)
                 i2c_register_board_info(2, n810_i2c_board_info_2,
                                         ARRAY_SIZE(n810_i2c_board_info_2));
         board_serial_init();
+        omap_sdrc_init(NULL, NULL);
         gpmc_onenand_init(board_onenand_data);
         n8x0_mmc_init();
         n8x0_usb_init();
 }
 
 MACHINE_START(NOKIA_N800, "Nokia N800")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
-        .map_io         = n8x0_map_io,
-        .init_early     = n8x0_init_early,
+        .map_io         = omap242x_map_io,
+        .init_early     = omap2420_init_early,
         .init_irq       = omap2_init_irq,
         .init_machine   = n8x0_init_machine,
         .timer          = &omap2_timer,
 MACHINE_END
 
 MACHINE_START(NOKIA_N810, "Nokia N810")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
-        .map_io         = n8x0_map_io,
-        .init_early     = n8x0_init_early,
+        .map_io         = omap242x_map_io,
+        .init_early     = omap2420_init_early,
         .init_irq       = omap2_init_irq,
         .init_machine   = n8x0_init_machine,
         .timer          = &omap2_timer,
 MACHINE_END
 
 MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
-        .map_io         = n8x0_map_io,
-        .init_early     = n8x0_init_early,
+        .map_io         = omap242x_map_io,
+        .init_early     = omap2420_init_early,
         .init_irq       = omap2_init_irq,
         .init_machine   = n8x0_init_machine,
         .timer          = &omap2_timer,
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 3ae16b4e3f52..3826493d1b2b 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -447,13 +447,6 @@ static struct platform_device keys_gpio = {
 static void __init omap3_beagle_init_early(void)
 {
         omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
-}
-
-static void __init omap3_beagle_init_irq(void)
-{
-        omap3_init_irq();
 }
 
 static struct platform_device *omap3_beagle_devices[] __initdata = {
@@ -534,6 +527,8 @@ static void __init omap3_beagle_init(void)
                         ARRAY_SIZE(omap3_beagle_devices));
         omap_display_init(&beagle_dss_data);
         omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
 
         omap_mux_init_gpio(170, OMAP_PIN_INPUT);
         /* REVISIT leave DVI powered down until it's needed ... */
@@ -557,11 +552,11 @@ static void __init omap3_beagle_init(void)
 
 MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
         /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap3_beagle_init_early,
-        .init_irq       = omap3_beagle_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = omap3_beagle_init,
         .timer          = &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c452b3f3331a..aa6a9351ce48 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -520,12 +520,6 @@ static int __init omap3_evm_i2c_init(void)
 static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
 };
 
-static void __init omap3_evm_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
-}
-
 static struct usbhs_omap_board_data usbhs_bdata __initdata = {
 
         .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -640,6 +634,7 @@ static void __init omap3_evm_init(void)
         omap_display_init(&omap3_evm_dss_data);
 
         omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
 
         /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
         usb_nop_xceiv_register();
@@ -681,10 +676,10 @@ static void __init omap3_evm_init(void)
 
 MACHINE_START(OMAP3EVM, "OMAP3 EVM")
         /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = omap3_evm_init_early,
+        .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = omap3_evm_init,
         .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 703aeb5b8fd4..7c0f193f246d 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -182,12 +182,6 @@ static inline void __init board_smsc911x_init(void)
         gpmc_smsc911x_init(&board_smsc911x_data);
 }
 
-static void __init omap3logic_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -200,6 +194,7 @@ static void __init omap3logic_init(void)
         omap3torpedo_fix_pbias_voltage();
         omap3logic_i2c_init();
         omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
         board_mmc_init();
         board_smsc911x_init();
 
@@ -209,18 +204,18 @@ static void __init omap3logic_init(void)
 }
 
 MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .map_io         = omap3_map_io,
-        .init_early     = omap3logic_init_early,
+        .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = omap3logic_init,
         .timer          = &omap3_timer,
 MACHINE_END
 
 MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .map_io         = omap3_map_io,
-        .init_early     = omap3logic_init_early,
+        .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = omap3logic_init,
         .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 080d7bd6795e..fed2f7dfdf8b 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -525,13 +525,6 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
         }
 };
 
-static void __init omap3pandora_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
-}
-
 static void __init pandora_wl1251_init(void)
 {
         struct wl12xx_platform_data pandora_wl1251_pdata;
@@ -593,6 +586,8 @@ static void __init omap3pandora_init(void)
                         ARRAY_SIZE(omap3pandora_devices));
         omap_display_init(&pandora_dss_data);
         omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
         spi_register_board_info(omap3pandora_spi_board_info,
                         ARRAY_SIZE(omap3pandora_spi_board_info));
         omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);
@@ -606,10 +601,10 @@ static void __init omap3pandora_init(void)
 }
 
 MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = omap3pandora_init_early,
+        .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = omap3pandora_init,
         .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 8e104980ea26..170e1ebd6e62 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -428,17 +428,6 @@ static int __init omap3_stalker_i2c_init(void)
 static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
 };
 
-static void __init omap3_stalker_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
-}
-
-static void __init omap3_stalker_init_irq(void)
-{
-        omap3_init_irq();
-}
-
 static struct platform_device *omap3_stalker_devices[] __initdata = {
         &keys_gpio,
 };
@@ -478,6 +467,7 @@ static void __init omap3_stalker_init(void)
         omap_display_init(&omap3_stalker_dss_data);
 
         omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
         usb_musb_init(NULL);
         usbhs_init(&usbhs_bdata);
         omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL);
@@ -494,10 +484,10 @@ static void __init omap3_stalker_init(void)
 
 MACHINE_START(SBC3530, "OMAP3 STALKER")
         /* Maintainer: Jason Lam -lzg@ema-tech.com */
-        .boot_params            = 0x80000100,
+        .atag_offset            = 0x100,
         .map_io                 = omap3_map_io,
-        .init_early             = omap3_stalker_init_early,
-        .init_irq               = omap3_stalker_init_irq,
+        .init_early             = omap35xx_init_early,
+        .init_irq               = omap3_init_irq,
         .init_machine           = omap3_stalker_init,
         .timer                  = &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 852ea0464057..c2d5348f5422 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -326,18 +326,6 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
-static void __init omap3_touchbook_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
-}
-
-static void __init omap3_touchbook_init_irq(void)
-{
-        omap3_init_irq();
-}
-
 static struct platform_device *omap3_touchbook_devices[] __initdata = {
         &omap3_touchbook_lcd_device,
         &leds_gpio,
@@ -385,6 +373,8 @@ static void __init omap3_touchbook_init(void)
         platform_add_devices(omap3_touchbook_devices,
                         ARRAY_SIZE(omap3_touchbook_devices));
         omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
 
         omap_mux_init_gpio(170, OMAP_PIN_INPUT);
         /* REVISIT leave DVI powered down until it's needed ... */
@@ -404,11 +394,11 @@ static void __init omap3_touchbook_init(void)
 
 MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
         /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = omap3_touchbook_init_early,
-        .init_irq       = omap3_touchbook_init_irq,
+        .init_early     = omap3430_init_early,
+        .init_irq       = omap3_init_irq,
         .init_machine   = omap3_touchbook_init,
         .timer          = &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 9aaa96057666..2141894eb9f3 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -95,12 +95,6 @@ static struct platform_device *panda_devices[] __initdata = {
         &wl1271_device,
 };
 
-static void __init omap4_panda_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
-
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -569,24 +563,19 @@ static void __init omap4_panda_init(void)
         platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
         platform_device_register(&omap_vwlan_device);
         board_serial_init();
+        omap_sdrc_init(NULL, NULL);
         omap4_twl6030_hsmmc_init(mmc);
         omap4_ehci_init();
         usb_musb_init(&musb_board_data);
         omap4_panda_display_init();
 }
 
-static void __init omap4_panda_map_io(void)
-{
-        omap2_set_globals_443x();
-        omap44xx_map_common_io();
-}
-
 MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
         /* Maintainer: David Anders - Texas Instruments Inc */
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
-        .map_io         = omap4_panda_map_io,
-        .init_early     = omap4_panda_init_early,
+        .map_io         = omap4_map_io,
+        .init_early     = omap4430_init_early,
         .init_irq       = gic_init_irq,
         .init_machine   = omap4_panda_init,
         .timer          = &omap4_timer,
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index f949a9954d76..9f13dc22df77 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -478,13 +478,6 @@ static int __init overo_spi_init(void)
         return 0;
 }
 
-static void __init overo_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
-}
-
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
         .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
@@ -514,6 +507,8 @@ static void __init overo_init(void)
         overo_i2c_init();
         omap_display_init(&overo_dss_data);
         omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
         omap_nand_flash_init(0, overo_nand_partitions,
                              ARRAY_SIZE(overo_nand_partitions));
         usb_musb_init(NULL);
@@ -561,10 +556,10 @@ static void __init overo_init(void)
 }
 
 MACHINE_START(OVERO, "Gumstix Overo")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = overo_init_early,
+        .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = overo_init,
         .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 7dfed24ee12e..616fb39763b0 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -123,15 +123,6 @@ static void __init rm680_peripherals_init(void)
         omap2_hsmmc_init(mmc);
 }
 
-static void __init rm680_init_early(void)
-{
-        struct omap_sdrc_params *sdrc_params;
-
-        omap2_init_common_infrastructure();
-        sdrc_params = nokia_get_sdram_timings();
-        omap2_init_common_devices(sdrc_params, sdrc_params);
-}
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -140,23 +131,23 @@ static struct omap_board_mux board_mux[] __initdata = {
 
 static void __init rm680_init(void)
 {
+        struct omap_sdrc_params *sdrc_params;
+
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_serial_init();
+
+        sdrc_params = nokia_get_sdram_timings();
+        omap_sdrc_init(sdrc_params, sdrc_params);
+
         usb_musb_init(NULL);
         rm680_peripherals_init();
 }
 
-static void __init rm680_map_io(void)
-{
-        omap2_set_globals_3xxx();
-        omap34xx_map_common_io();
-}
-
 MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
-        .map_io         = rm680_map_io,
-        .init_early     = rm680_init_early,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3630_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = rm680_init,
         .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 5ea142f9bc97..74c8aadc0a19 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -102,15 +102,6 @@ static struct omap_board_config_kernel rx51_config[] = {
         { OMAP_TAG_LCD,         &rx51_lcd_config },
 };
 
-static void __init rx51_init_early(void)
-{
-        struct omap_sdrc_params *sdrc_params;
-
-        omap2_init_common_infrastructure();
-        sdrc_params = nokia_get_sdram_timings();
-        omap2_init_common_devices(sdrc_params, sdrc_params);
-}
-
 extern void __init rx51_peripherals_init(void);
 
 #ifdef CONFIG_OMAP_MUX
@@ -127,11 +118,17 @@ static struct omap_musb_board_data musb_board_data = {
 
 static void __init rx51_init(void)
 {
+        struct omap_sdrc_params *sdrc_params;
+
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_board_config = rx51_config;
         omap_board_config_size = ARRAY_SIZE(rx51_config);
         omap3_pm_init_cpuidle(rx51_cpuidle_params);
         omap_serial_init();
+
+        sdrc_params = nokia_get_sdram_timings();
+        omap_sdrc_init(sdrc_params, sdrc_params);
+
         usb_musb_init(&musb_board_data);
         rx51_peripherals_init();
 
@@ -142,12 +139,6 @@ static void __init rx51_init(void)
         platform_device_register(&leds_gpio);
 }
 
-static void __init rx51_map_io(void)
-{
-        omap2_set_globals_3xxx();
-        omap34xx_map_common_io();
-}
-
 static void __init rx51_reserve(void)
 {
         rx51_video_mem_init();
@@ -156,10 +147,10 @@ static void __init rx51_reserve(void)
 
 MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
         /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = rx51_reserve,
-        .map_io         = rx51_map_io,
-        .init_early     = rx51_init_early,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3430_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = rx51_init,
         .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index a85d5b0b11da..e26c79cb6ce9 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -27,15 +27,10 @@
 static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
 };
 
-static void __init ti8168_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
-
 static void __init ti8168_evm_init(void)
 {
         omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
         omap_board_config = ti8168_evm_config;
         omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
 }
@@ -48,9 +43,9 @@ static void __init ti8168_evm_map_io(void)
 
 MACHINE_START(TI8168EVM, "ti8168evm")
         /* Maintainer: Texas Instruments */
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .map_io         = ti8168_evm_map_io,
-        .init_early     = ti8168_init_early,
+        .init_early     = ti816x_init_early,
         .init_irq       = ti816x_init_irq,
         .timer          = &omap3_timer,
         .init_machine   = ti8168_evm_init,
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 8a98c3c303fc..be6684dc4f55 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -34,17 +34,6 @@
 
 #define ZOOM3_EHCI_RESET_GPIO           64
 
-static void __init omap_zoom_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        if (machine_is_omap_zoom2())
-                omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                          mt46h32m32lf6_sdrc_params);
-        else if (machine_is_omap_zoom3())
-                omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
-                                          h8mbx00u0mer0em_sdrc_params);
-}
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         /* WLAN IRQ - GPIO 162 */
@@ -129,24 +118,32 @@ static void __init omap_zoom_init(void)
                                                 ZOOM_NAND_CS, NAND_BUSWIDTH_16);
         zoom_debugboard_init();
         zoom_peripherals_init();
+
+        if (machine_is_omap_zoom2())
+                omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                          mt46h32m32lf6_sdrc_params);
+        else if (machine_is_omap_zoom3())
+                omap_sdrc_init(h8mbx00u0mer0em_sdrc_params,
+                                          h8mbx00u0mer0em_sdrc_params);
+
         zoom_display_init();
 }
 
 MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = omap_zoom_init_early,
+        .init_early     = omap3430_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = omap_zoom_init,
         .timer          = &omap3_timer,
 MACHINE_END
 
 MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
-        .boot_params    = 0x80000100,
+        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = omap_zoom_init_early,
+        .init_early     = omap3630_init_early,
         .init_irq       = omap3_init_irq,
         .init_machine   = omap_zoom_init,
         .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index b9b844683147..dadb8c6c0115 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3472,7 +3472,16 @@ int __init omap3xxx_clk_init(void)
         struct omap_clk *c;
         u32 cpu_clkflg = 0;
 
-        if (cpu_is_omap3517()) {
+        /*
+         * 3505 must be tested before 3517, since 3517 returns true
+         * for both AM3517 chips and AM3517 family chips, which
+         * includes 3505.  Unfortunately there's no obvious family
+         * test for 3517/3505 :-(
+         */
+        if (cpu_is_omap3505()) {
+                cpu_mask = RATE_IN_34XX;
+                cpu_clkflg = CK_3505;
+        } else if (cpu_is_omap3517()) {
                 cpu_mask = RATE_IN_34XX;
                 cpu_clkflg = CK_3517;
         } else if (cpu_is_omap3505()) {
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 8f0890685d7b..8480ee4344ea 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -73,9 +73,6 @@ static int _clkdm_register(struct clockdomain *clkdm)
         if (!clkdm || !clkdm->name)
                 return -EINVAL;
 
-        if (!omap_chip_is(clkdm->omap_chip))
-                return -EINVAL;
-
         pwrdm = pwrdm_lookup(clkdm->pwrdm.name);
         if (!pwrdm) {
                 pr_err("clockdomain: %s: powerdomain %s does not exist\n",
@@ -105,13 +102,10 @@ static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm,
 {
         struct clkdm_dep *cd;
 
-        if (!clkdm || !deps || !omap_chip_is(clkdm->omap_chip))
+        if (!clkdm || !deps)
                 return ERR_PTR(-EINVAL);
 
         for (cd = deps; cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
-
                 if (!cd->clkdm && cd->clkdm_name)
                         cd->clkdm = _clkdm_lookup(cd->clkdm_name);
 
@@ -148,9 +142,6 @@ static void _autodep_lookup(struct clkdm_autodep *autodep)
         if (!autodep)
                 return;
 
-        if (!omap_chip_is(autodep->omap_chip))
-                return;
-
         clkdm = clkdm_lookup(autodep->clkdm.name);
         if (!clkdm) {
                 pr_err("clockdomain: autodeps: clockdomain %s does not exist\n",
@@ -182,9 +173,6 @@ void _clkdm_add_autodeps(struct clockdomain *clkdm)
                 if (IS_ERR(autodep->clkdm.ptr))
                         continue;
 
-                if (!omap_chip_is(autodep->omap_chip))
-                        continue;
-
                 pr_debug("clockdomain: adding %s sleepdep/wkdep for "
                          "clkdm %s\n", autodep->clkdm.ptr->name,
                          clkdm->name);
@@ -216,9 +204,6 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm)
                 if (IS_ERR(autodep->clkdm.ptr))
                         continue;
 
-                if (!omap_chip_is(autodep->omap_chip))
-                        continue;
-
                 pr_debug("clockdomain: removing %s sleepdep/wkdep for "
                          "clkdm %s\n", autodep->clkdm.ptr->name,
                          clkdm->name);
@@ -243,8 +228,6 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm,
         struct clkdm_dep *cd;
 
         for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
                 if (cd->clkdm)
                         continue;
                 cd->clkdm = _clkdm_lookup(cd->clkdm_name);
@@ -257,43 +240,113 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm,
 /* Public functions */
 
 /**
- * clkdm_init - set up the clockdomain layer
- * @clkdms: optional pointer to an array of clockdomains to register
- * @init_autodeps: optional pointer to an array of autodeps to register
- * @custom_funcs: func pointers for arch specific implementations
- *
- * Set up internal state.  If a pointer to an array of clockdomains
- * @clkdms was supplied, loop through the list of clockdomains,
- * register all that are available on the current platform. Similarly,
- * if a pointer to an array of clockdomain autodependencies
- * @init_autodeps was provided, register those.  No return value.
+ * clkdm_register_platform_funcs - register clockdomain implementation fns
+ * @co: func pointers for arch specific implementations
+ *
+ * Register the list of function pointers used to implement the
+ * clockdomain functions on different OMAP SoCs.  Should be called
+ * before any other clkdm_register*() function.  Returns -EINVAL if
+ * @co is null, -EEXIST if platform functions have already been
+ * registered, or 0 upon success.
+ */
+int clkdm_register_platform_funcs(struct clkdm_ops *co)
+{
+        if (!co)
+                return -EINVAL;
+
+        if (arch_clkdm)
+                return -EEXIST;
+
+        arch_clkdm = co;
+
+        return 0;
+};
+
+/**
+ * clkdm_register_clkdms - register SoC clockdomains
+ * @cs: pointer to an array of struct clockdomain to register
+ *
+ * Register the clockdomains available on a particular OMAP SoC.  Must
+ * be called after clkdm_register_platform_funcs().  May be called
+ * multiple times.  Returns -EACCES if called before
+ * clkdm_register_platform_funcs(); -EINVAL if the argument @cs is
+ * null; or 0 upon success.
  */
-void clkdm_init(struct clockdomain **clkdms,
-                struct clkdm_autodep *init_autodeps,
-                struct clkdm_ops *custom_funcs)
+int clkdm_register_clkdms(struct clockdomain **cs)
 {
         struct clockdomain **c = NULL;
-        struct clockdomain *clkdm;
-        struct clkdm_autodep *autodep = NULL;
 
-        if (!custom_funcs)
-                WARN(1, "No custom clkdm functions registered\n");
-        else
-                arch_clkdm = custom_funcs;
+        if (!arch_clkdm)
+                return -EACCES;
+
+        if (!cs)
+                return -EINVAL;
+
+        for (c = cs; *c; c++)
+                _clkdm_register(*c);
+
+        return 0;
+}
+
+/**
+ * clkdm_register_autodeps - register autodeps (if required)
+ * @ia: pointer to a static array of struct clkdm_autodep to register
+ *
+ * Register clockdomain "automatic dependencies."  These are
+ * clockdomain wakeup and sleep dependencies that are automatically
+ * added whenever the first clock inside a clockdomain is enabled, and
+ * removed whenever the last clock inside a clockdomain is disabled.
+ * These are currently only used on OMAP3 devices, and are deprecated,
+ * since they waste energy.  However, until the OMAP2/3 IP block
+ * enable/disable sequence can be converted to match the OMAP4
+ * sequence, they are needed.
+ *
+ * Must be called only after all of the SoC clockdomains are
+ * registered, since the function will resolve autodep clockdomain
+ * names into clockdomain pointers.
+ *
+ * The struct clkdm_autodep @ia array must be static, as this function
+ * does not copy the array elements.
+ *
+ * Returns -EACCES if called before any clockdomains have been
+ * registered, -EINVAL if called with a null @ia argument, -EEXIST if
+ * autodeps have already been registered, or 0 upon success.
+ */
+int clkdm_register_autodeps(struct clkdm_autodep *ia)
+{
+        struct clkdm_autodep *a = NULL;
 
-        if (clkdms)
-                for (c = clkdms; *c; c++)
-                        _clkdm_register(*c);
+        if (list_empty(&clkdm_list))
+                return -EACCES;
+
+        if (!ia)
+                return -EINVAL;
 
-        autodeps = init_autodeps;
         if (autodeps)
-                for (autodep = autodeps; autodep->clkdm.ptr; autodep++)
-                        _autodep_lookup(autodep);
+                return -EEXIST;
+
+        autodeps = ia;
+        for (a = autodeps; a->clkdm.ptr; a++)
+                _autodep_lookup(a);
+
+        return 0;
+}
+
+/**
+ * clkdm_complete_init - set up the clockdomain layer
+ *
+ * Put all clockdomains into software-supervised mode; PM code should
+ * later enable hardware-supervised mode as appropriate.  Must be
+ * called after clkdm_register_clkdms().  Returns -EACCES if called
+ * before clkdm_register_clkdms(), or 0 upon success.
+ */
+int clkdm_complete_init(void)
+{
+        struct clockdomain *clkdm;
+
+        if (list_empty(&clkdm_list))
+                return -EACCES;
 
-        /*
-         * Put all clockdomains into software-supervised mode; PM code
-         * should later enable hardware-supervised mode as appropriate
-         */
         list_for_each_entry(clkdm, &clkdm_list, node) {
                 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
                         clkdm_wakeup(clkdm);
@@ -306,6 +359,8 @@ void clkdm_init(struct clockdomain **clkdms,
                 _resolve_clkdm_deps(clkdm, clkdm->sleepdep_srcs);
                 clkdm_clear_all_sleepdeps(clkdm);
         }
+
+        return 0;
 }
 
 /**
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 1e50c88b8a07..f7b58609bad8 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -45,7 +45,6 @@
 /**
  * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode
  * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only
- * @omap_chip: OMAP chip types that this autodep is valid on
  *
  * A clockdomain that should have wkdeps and sleepdeps added when a
  * clockdomain should stay active in hwsup mode; and conversely,
@@ -60,14 +59,12 @@ struct clkdm_autodep {
                 const char *name;
                 struct clockdomain *ptr;
         } clkdm;
-        const struct omap_chip_id omap_chip;
 };
 
 /**
  * struct clkdm_dep - encode dependencies between clockdomains
  * @clkdm_name: clockdomain name
  * @clkdm: pointer to the struct clockdomain of @clkdm_name
- * @omap_chip: OMAP chip types that this dependency is valid on
  * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake
  * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle
  *
@@ -81,7 +78,6 @@ struct clkdm_dep {
         struct clockdomain *clkdm;
         atomic_t wkdep_usecount;
         atomic_t sleepdep_usecount;
-        const struct omap_chip_id omap_chip;
 };
 
 /* Possible flags for struct clockdomain._flags */
@@ -101,7 +97,6 @@ struct clkdm_dep {
  * @clkdm_offs: (OMAP4 only) CM clockdomain register offset
  * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
  * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
- * @omap_chip: OMAP chip types that this clockdomain is valid on
  * @usecount: Usecount tracking
  * @node: list_head to link all clockdomains together
  *
@@ -126,7 +121,6 @@ struct clockdomain {
         const u16 clkdm_offs;
         struct clkdm_dep *wkdep_srcs;
         struct clkdm_dep *sleepdep_srcs;
-        const struct omap_chip_id omap_chip;
         atomic_t usecount;
         struct list_head node;
         spinlock_t lock;
@@ -166,8 +160,11 @@ struct clkdm_ops {
         int     (*clkdm_clk_disable)(struct clockdomain *clkdm);
 };
 
-void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps,
-                        struct clkdm_ops *custom_funcs);
+int clkdm_register_platform_funcs(struct clkdm_ops *co);
+int clkdm_register_autodeps(struct clkdm_autodep *ia);
+int clkdm_register_clkdms(struct clockdomain **c);
+int clkdm_complete_init(void);
+
 struct clockdomain *clkdm_lookup(const char *name);
 
 int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
@@ -195,7 +192,8 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
 int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh);
 int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
 
-extern void __init omap2xxx_clockdomains_init(void);
+extern void __init omap242x_clockdomains_init(void);
+extern void __init omap243x_clockdomains_init(void);
 extern void __init omap3xxx_clockdomains_init(void);
 extern void __init omap44xx_clockdomains_init(void);
 extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
@@ -205,4 +203,10 @@ extern struct clkdm_ops omap2_clkdm_operations;
 extern struct clkdm_ops omap3_clkdm_operations;
 extern struct clkdm_ops omap4_clkdm_operations;
 
+extern struct clkdm_dep gfx_24xx_wkdeps[];
+extern struct clkdm_dep dsp_24xx_wkdeps[];
+extern struct clockdomain wkup_common_clkdm;
+extern struct clockdomain prm_common_clkdm;
+extern struct clockdomain cm_common_clkdm;
+
 #endif
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
index f740edb111f4..a0d68dbecfa3 100644
--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -52,8 +52,6 @@ static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
         u32 mask = 0;
 
         for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
                 if (!cd->clkdm)
                         continue; /* only happens if data is erroneous */
 
@@ -98,8 +96,6 @@ static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
         u32 mask = 0;
 
         for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
                 if (!cd->clkdm)
                         continue; /* only happens if data is erroneous */
 
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index b43706aa08bd..935c7f03dab9 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -52,8 +52,6 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
         u32 mask = 0;
 
         for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
                 if (!cd->clkdm)
                         continue; /* only happens if data is erroneous */
 
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c
new file mode 100644
index 000000000000..0ab8e46d5b2b
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains2420_data.c
@@ -0,0 +1,154 @@
+/*
+ * OMAP2420 clockdomains
+ *
+ * Copyright (C) 2008-2011 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley, Jouni Högander
+ *
+ * This file contains clockdomains and clockdomain wakeup dependencies
+ * for OMAP2420 chips.  Some notes:
+ *
+ * A useful validation rule for struct clockdomain: Any clockdomain
+ * referenced by a wkdep_srcs must have a dep_bit assigned.  So
+ * wkdep_srcs are really just software-controllable dependencies.
+ * Non-software-controllable dependencies do exist, but they are not
+ * encoded below (yet).
+ *
+ * 24xx does not support programmable sleep dependencies (SLEEPDEP)
+ *
+ * The overly-specific dep_bit names are due to a bit name collision
+ * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
+ * value are the same for all powerdomains: 2
+ *
+ * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
+ * sanity check?
+ * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
+ */
+
+/*
+ * To-Do List
+ * -> Port the Sleep/Wakeup dependencies for the domains
+ *    from the Power domain framework
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+#include "prm-regbits-24xx.h"
+
+/*
+ * Clockdomain dependencies for wkdeps
+ *
+ * XXX Hardware dependencies (e.g., dependencies that cannot be
+ * changed in software) are not included here yet, but should be.
+ */
+
+/* Wakeup dependency source arrays */
+
+/* 2420-specific possible wakeup dependencies */
+
+/* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP */
+static struct clkdm_dep mpu_2420_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+
+/* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP */
+static struct clkdm_dep core_2420_wkdeps[] = {
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "gfx_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+
+/*
+ * 2420-only clockdomains
+ */
+
+static struct clockdomain mpu_2420_clkdm = {
+        .name           = "mpu_clkdm",
+        .pwrdm          = { .name = "mpu_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .wkdep_srcs     = mpu_2420_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
+};
+
+static struct clockdomain iva1_2420_clkdm = {
+        .name           = "iva1_clkdm",
+        .pwrdm          = { .name = "dsp_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
+        .wkdep_srcs     = dsp_24xx_wkdeps,
+        .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
+};
+
+static struct clockdomain dsp_2420_clkdm = {
+        .name           = "dsp_clkdm",
+        .pwrdm          = { .name = "dsp_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
+};
+
+static struct clockdomain gfx_2420_clkdm = {
+        .name           = "gfx_clkdm",
+        .pwrdm          = { .name = "gfx_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = gfx_24xx_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
+};
+
+static struct clockdomain core_l3_2420_clkdm = {
+        .name           = "core_l3_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .wkdep_srcs     = core_2420_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
+};
+
+static struct clockdomain core_l4_2420_clkdm = {
+        .name           = "core_l4_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .wkdep_srcs     = core_2420_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
+};
+
+static struct clockdomain dss_2420_clkdm = {
+        .name           = "dss_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
+};
+
+static struct clockdomain *clockdomains_omap242x[] __initdata = {
+        &wkup_common_clkdm,
+        &cm_common_clkdm,
+        &prm_common_clkdm,
+        &mpu_2420_clkdm,
+        &iva1_2420_clkdm,
+        &dsp_2420_clkdm,
+        &gfx_2420_clkdm,
+        &core_l3_2420_clkdm,
+        &core_l4_2420_clkdm,
+        &dss_2420_clkdm,
+        NULL,
+};
+
+void __init omap242x_clockdomains_init(void)
+{
+        if (!cpu_is_omap242x())
+                return;
+
+        clkdm_register_platform_funcs(&omap2_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_omap242x);
+        clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c
new file mode 100644
index 000000000000..3645ed044890
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains2430_data.c
@@ -0,0 +1,181 @@
+/*
+ * OMAP2xxx clockdomains
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley, Jouni Högander
+ *
+ * This file contains clockdomains and clockdomain wakeup dependencies
+ * for OMAP2xxx chips.  Some notes:
+ *
+ * A useful validation rule for struct clockdomain: Any clockdomain
+ * referenced by a wkdep_srcs must have a dep_bit assigned.  So
+ * wkdep_srcs are really just software-controllable dependencies.
+ * Non-software-controllable dependencies do exist, but they are not
+ * encoded below (yet).
+ *
+ * 24xx does not support programmable sleep dependencies (SLEEPDEP)
+ *
+ * The overly-specific dep_bit names are due to a bit name collision
+ * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
+ * value are the same for all powerdomains: 2
+ *
+ * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
+ * sanity check?
+ * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
+ */
+
+/*
+ * To-Do List
+ * -> Port the Sleep/Wakeup dependencies for the domains
+ *    from the Power domain framework
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+#include "prm-regbits-24xx.h"
+
+/*
+ * Clockdomain dependencies for wkdeps
+ *
+ * XXX Hardware dependencies (e.g., dependencies that cannot be
+ * changed in software) are not included here yet, but should be.
+ */
+
+/* Wakeup dependency source arrays */
+
+/* 2430-specific possible wakeup dependencies */
+
+/* 2430 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP, MDM */
+static struct clkdm_dep core_2430_wkdeps[] = {
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "gfx_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { .clkdm_name = "mdm_clkdm" },
+        { NULL },
+};
+
+/* 2430 PM_WKDEP_MPU: CORE, DSP, WKUP, MDM */
+static struct clkdm_dep mpu_2430_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { .clkdm_name = "mdm_clkdm" },
+        { NULL },
+};
+
+/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
+static struct clkdm_dep mdm_2430_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+
+/*
+ * 2430-only clockdomains
+ */
+
+static struct clockdomain mpu_2430_clkdm = {
+        .name           = "mpu_clkdm",
+        .pwrdm          = { .name = "mpu_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = mpu_2430_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
+};
+
+/* Another case of bit name collisions between several registers: EN_MDM */
+static struct clockdomain mdm_clkdm = {
+        .name           = "mdm_clkdm",
+        .pwrdm          = { .name = "mdm_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
+        .wkdep_srcs     = mdm_2430_wkdeps,
+        .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
+};
+
+static struct clockdomain dsp_2430_clkdm = {
+        .name           = "dsp_clkdm",
+        .pwrdm          = { .name = "dsp_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
+        .wkdep_srcs     = dsp_24xx_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
+};
+
+static struct clockdomain gfx_2430_clkdm = {
+        .name           = "gfx_clkdm",
+        .pwrdm          = { .name = "gfx_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = gfx_24xx_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
+};
+
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l3_2430_clkdm = {
+        .name           = "core_l3_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
+        .wkdep_srcs     = core_2430_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
+};
+
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l4_2430_clkdm = {
+        .name           = "core_l4_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
+        .wkdep_srcs     = core_2430_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
+};
+
+static struct clockdomain dss_2430_clkdm = {
+        .name           = "dss_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
+};
+
+static struct clockdomain *clockdomains_omap243x[] __initdata = {
+        &wkup_common_clkdm,
+        &cm_common_clkdm,
+        &prm_common_clkdm,
+        &mpu_2430_clkdm,
+        &mdm_clkdm,
+        &dsp_2430_clkdm,
+        &gfx_2430_clkdm,
+        &core_l3_2430_clkdm,
+        &core_l4_2430_clkdm,
+        &dss_2430_clkdm,
+        NULL,
+};
+
+void __init omap243x_clockdomains_init(void)
+{
+        if (!cpu_is_omap243x())
+                return;
+
+        clkdm_register_platform_funcs(&omap2_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_omap243x);
+        clkdm_complete_init();
+}
+
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 13bde95b6790..0a6a04897d89 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -1,7 +1,7 @@
 /*
- * OMAP2/3 clockdomains
+ * OMAP2/3 clockdomain common data
  *
- * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ * Copyright (C) 2008-2011 Texas Instruments, Inc.
  * Copyright (C) 2008-2010 Nokia Corporation
  *
  * Paul Walmsley, Jouni Högander
@@ -51,374 +51,28 @@
  * changed in software) are not included here yet, but should be.
  */
 
-/* OMAP2/3-common wakeup dependencies */
-
-/*
- * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
- * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
- * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
- * These can share data since they will never be present simultaneously
- * on the same device.
- */
-static struct clkdm_dep gfx_sgx_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
-                                            CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
-                                            CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-
-/* 24XX-specific possible dependencies */
-
-#ifdef CONFIG_ARCH_OMAP2
-
 /* Wakeup dependency source arrays */
 
-/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
-static struct clkdm_dep dsp_24xx_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        { NULL },
-};
-
-/*
- * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
- * 2430 adds MDM
- */
-static struct clkdm_dep mpu_24xx_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "dsp_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "mdm_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
-        },
-        { NULL },
-};
-
-/*
- * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
- * 2430 adds MDM
- */
-static struct clkdm_dep core_24xx_wkdeps[] = {
-        {
-                .clkdm_name = "dsp_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "gfx_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "mdm_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
-        },
-        { NULL },
-};
-
-#endif /* CONFIG_ARCH_OMAP2 */
-
-/* 2430-specific possible wakeup dependencies */
+/* 2xxx-specific possible dependencies */
 
-#ifdef CONFIG_SOC_OMAP2430
-
-/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
-static struct clkdm_dep mdm_2430_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        { NULL },
-};
-
-#endif /* CONFIG_SOC_OMAP2430 */
-
-
-/* OMAP3-specific possible dependencies */
-
-#ifdef CONFIG_ARCH_OMAP3
-
-/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
-static struct clkdm_dep per_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
-static struct clkdm_dep usbhost_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
+/* 2xxx PM_WKDEP_GFX: CORE, MPU, WKUP */
+struct clkdm_dep gfx_24xx_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
         { NULL },
 };
 
-/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
-static struct clkdm_dep mpu_3xxx_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "dss_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "per_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
+/* 2xxx PM_WKDEP_DSP: CORE, MPU, WKUP */
+struct clkdm_dep dsp_24xx_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
         { NULL },
 };
 
-/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
-static struct clkdm_dep iva2_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "dss_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "per_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-
-/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
-static struct clkdm_dep cam_wkdeps[] = {
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
-static struct clkdm_dep dss_wkdeps[] = {
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-/* 3430: PM_WKDEP_NEON: MPU */
-static struct clkdm_dep neon_wkdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-
-/* Sleep dependency source arrays for OMAP3-specific clkdms */
-
-/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
-static struct clkdm_dep dss_sleepdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
-static struct clkdm_dep per_sleepdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
-static struct clkdm_dep usbhost_sleepdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-/* 3430: CM_SLEEPDEP_CAM: MPU */
-static struct clkdm_dep cam_sleepdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-/*
- * 3430ES1: CM_SLEEPDEP_GFX: MPU
- * 3430ES2: CM_SLEEPDEP_SGX: MPU
- * These can share data since they will never be present simultaneously
- * on the same device.
- */
-static struct clkdm_dep gfx_sgx_sleepdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-#endif /* CONFIG_ARCH_OMAP3 */
-
 
 /*
  * OMAP2/3-common clockdomains
@@ -430,439 +84,18 @@ static struct clkdm_dep gfx_sgx_sleepdeps[] = {
  */
 
 /* This is an implicit clockdomain - it is never defined as such in TRM */
-static struct clockdomain wkup_clkdm = {
+struct clockdomain wkup_common_clkdm = {
         .name           = "wkup_clkdm",
         .pwrdm          = { .name = "wkup_pwrdm" },
         .dep_bit        = OMAP_EN_WKUP_SHIFT,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 };
 
-static struct clockdomain prm_clkdm = {
+struct clockdomain prm_common_clkdm = {
         .name           = "prm_clkdm",
         .pwrdm          = { .name = "wkup_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 };
 
-static struct clockdomain cm_clkdm = {
+struct clockdomain cm_common_clkdm = {
         .name           = "cm_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 };
-
-/*
- * 2420-only clockdomains
- */
-
-#if defined(CONFIG_SOC_OMAP2420)
-
-static struct clockdomain mpu_2420_clkdm = {
-        .name           = "mpu_clkdm",
-        .pwrdm          = { .name = "mpu_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .wkdep_srcs     = mpu_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-
-static struct clockdomain iva1_2420_clkdm = {
-        .name           = "iva1_clkdm",
-        .pwrdm          = { .name = "dsp_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
-        .wkdep_srcs     = dsp_24xx_wkdeps,
-        .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-
-static struct clockdomain dsp_2420_clkdm = {
-        .name           = "dsp_clkdm",
-        .pwrdm          = { .name = "dsp_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-
-static struct clockdomain gfx_2420_clkdm = {
-        .name           = "gfx_clkdm",
-        .pwrdm          = { .name = "gfx_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = gfx_sgx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-
-static struct clockdomain core_l3_2420_clkdm = {
-        .name           = "core_l3_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .wkdep_srcs     = core_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-
-static struct clockdomain core_l4_2420_clkdm = {
-        .name           = "core_l4_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .wkdep_srcs     = core_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-
-static struct clockdomain dss_2420_clkdm = {
-        .name           = "dss_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-
-#endif   /* CONFIG_SOC_OMAP2420 */
-
-
-/*
- * 2430-only clockdomains
- */
-
-#if defined(CONFIG_SOC_OMAP2430)
-
-static struct clockdomain mpu_2430_clkdm = {
-        .name           = "mpu_clkdm",
-        .pwrdm          = { .name = "mpu_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = mpu_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-
-/* Another case of bit name collisions between several registers: EN_MDM */
-static struct clockdomain mdm_clkdm = {
-        .name           = "mdm_clkdm",
-        .pwrdm          = { .name = "mdm_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
-        .wkdep_srcs     = mdm_2430_wkdeps,
-        .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-
-static struct clockdomain dsp_2430_clkdm = {
-        .name           = "dsp_clkdm",
-        .pwrdm          = { .name = "dsp_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
-        .wkdep_srcs     = dsp_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-
-static struct clockdomain gfx_2430_clkdm = {
-        .name           = "gfx_clkdm",
-        .pwrdm          = { .name = "gfx_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = gfx_sgx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-
-/*
- * XXX add usecounting for clkdm dependencies, otherwise the presence
- * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
- * could cause trouble
- */
-static struct clockdomain core_l3_2430_clkdm = {
-        .name           = "core_l3_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
-        .wkdep_srcs     = core_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-
-/*
- * XXX add usecounting for clkdm dependencies, otherwise the presence
- * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
- * could cause trouble
- */
-static struct clockdomain core_l4_2430_clkdm = {
-        .name           = "core_l4_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
-        .wkdep_srcs     = core_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-
-static struct clockdomain dss_2430_clkdm = {
-        .name           = "dss_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-
-#endif    /* CONFIG_SOC_OMAP2430 */
-
-
-/*
- * OMAP3 clockdomains
- */
-
-#if defined(CONFIG_ARCH_OMAP3)
-
-static struct clockdomain mpu_3xxx_clkdm = {
-        .name           = "mpu_clkdm",
-        .pwrdm          = { .name = "mpu_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
-        .dep_bit        = OMAP3430_EN_MPU_SHIFT,
-        .wkdep_srcs     = mpu_3xxx_wkdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-
-static struct clockdomain neon_clkdm = {
-        .name           = "neon_clkdm",
-        .pwrdm          = { .name = "neon_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = neon_wkdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-
-static struct clockdomain iva2_clkdm = {
-        .name           = "iva2_clkdm",
-        .pwrdm          = { .name = "iva2_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
-        .wkdep_srcs     = iva2_wkdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-
-static struct clockdomain gfx_3430es1_clkdm = {
-        .name           = "gfx_clkdm",
-        .pwrdm          = { .name = "gfx_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = gfx_sgx_wkdeps,
-        .sleepdep_srcs  = gfx_sgx_sleepdeps,
-        .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
-};
-
-static struct clockdomain sgx_clkdm = {
-        .name           = "sgx_clkdm",
-        .pwrdm          = { .name = "sgx_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = gfx_sgx_wkdeps,
-        .sleepdep_srcs  = gfx_sgx_sleepdeps,
-        .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
-};
-
-/*
- * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
- * then that information was removed from the 34xx ES2+ TRM.  It is
- * unclear whether the core is still there, but the clockdomain logic
- * is there, and must be programmed to an appropriate state if the
- * CORE clockdomain is to become inactive.
- */
-static struct clockdomain d2d_clkdm = {
-        .name           = "d2d_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-
-/*
- * XXX add usecounting for clkdm dependencies, otherwise the presence
- * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
- * could cause trouble
- */
-static struct clockdomain core_l3_3xxx_clkdm = {
-        .name           = "core_l3_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .dep_bit        = OMAP3430_EN_CORE_SHIFT,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-
-/*
- * XXX add usecounting for clkdm dependencies, otherwise the presence
- * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
- * could cause trouble
- */
-static struct clockdomain core_l4_3xxx_clkdm = {
-        .name           = "core_l4_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .dep_bit        = OMAP3430_EN_CORE_SHIFT,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-
-/* Another case of bit name collisions between several registers: EN_DSS */
-static struct clockdomain dss_3xxx_clkdm = {
-        .name           = "dss_clkdm",
-        .pwrdm          = { .name = "dss_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
-        .wkdep_srcs     = dss_wkdeps,
-        .sleepdep_srcs  = dss_sleepdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-
-static struct clockdomain cam_clkdm = {
-        .name           = "cam_clkdm",
-        .pwrdm          = { .name = "cam_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = cam_wkdeps,
-        .sleepdep_srcs  = cam_sleepdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-
-static struct clockdomain usbhost_clkdm = {
-        .name           = "usbhost_clkdm",
-        .pwrdm          = { .name = "usbhost_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = usbhost_wkdeps,
-        .sleepdep_srcs  = usbhost_sleepdeps,
-        .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
-};
-
-static struct clockdomain per_clkdm = {
-        .name           = "per_clkdm",
-        .pwrdm          = { .name = "per_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP3430_EN_PER_SHIFT,
-        .wkdep_srcs     = per_wkdeps,
-        .sleepdep_srcs  = per_sleepdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-
-/*
- * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
- * switched of even if sdti is in use
- */
-static struct clockdomain emu_clkdm = {
-        .name           = "emu_clkdm",
-        .pwrdm          = { .name = "emu_pwrdm" },
-        .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-
-static struct clockdomain dpll1_clkdm = {
-        .name           = "dpll1_clkdm",
-        .pwrdm          = { .name = "dpll1_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-
-static struct clockdomain dpll2_clkdm = {
-        .name           = "dpll2_clkdm",
-        .pwrdm          = { .name = "dpll2_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-
-static struct clockdomain dpll3_clkdm = {
-        .name           = "dpll3_clkdm",
-        .pwrdm          = { .name = "dpll3_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-
-static struct clockdomain dpll4_clkdm = {
-        .name           = "dpll4_clkdm",
-        .pwrdm          = { .name = "dpll4_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-
-static struct clockdomain dpll5_clkdm = {
-        .name           = "dpll5_clkdm",
-        .pwrdm          = { .name = "dpll5_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
-};
-
-#endif   /* CONFIG_ARCH_OMAP3 */
-
-/*
- * Clockdomain hwsup dependencies (OMAP3 only)
- */
-
-static struct clkdm_autodep clkdm_autodeps[] = {
-        {
-                .clkdm     = { .name = "mpu_clkdm" },
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm     = { .name = "iva2_clkdm" },
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm     = { .name = NULL },
-        }
-};
-
-static struct clockdomain *clockdomains_omap2[] __initdata = {
-        &wkup_clkdm,
-        &cm_clkdm,
-        &prm_clkdm,
-
-#ifdef CONFIG_SOC_OMAP2420
-        &mpu_2420_clkdm,
-        &iva1_2420_clkdm,
-        &dsp_2420_clkdm,
-        &gfx_2420_clkdm,
-        &core_l3_2420_clkdm,
-        &core_l4_2420_clkdm,
-        &dss_2420_clkdm,
-#endif
-
-#ifdef CONFIG_SOC_OMAP2430
-        &mpu_2430_clkdm,
-        &mdm_clkdm,
-        &dsp_2430_clkdm,
-        &gfx_2430_clkdm,
-        &core_l3_2430_clkdm,
-        &core_l4_2430_clkdm,
-        &dss_2430_clkdm,
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-        &mpu_3xxx_clkdm,
-        &neon_clkdm,
-        &iva2_clkdm,
-        &gfx_3430es1_clkdm,
-        &sgx_clkdm,
-        &d2d_clkdm,
-        &core_l3_3xxx_clkdm,
-        &core_l4_3xxx_clkdm,
-        &dss_3xxx_clkdm,
-        &cam_clkdm,
-        &usbhost_clkdm,
-        &per_clkdm,
-        &emu_clkdm,
-        &dpll1_clkdm,
-        &dpll2_clkdm,
-        &dpll3_clkdm,
-        &dpll4_clkdm,
-        &dpll5_clkdm,
-#endif
-        NULL,
-};
-
-void __init omap2xxx_clockdomains_init(void)
-{
-        clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap2_clkdm_operations);
-}
-
-void __init omap3xxx_clockdomains_init(void)
-{
-        clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap3_clkdm_operations);
-}
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
new file mode 100644
index 000000000000..b84e138d99c8
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -0,0 +1,398 @@
+/*
+ * OMAP3xxx clockdomains
+ *
+ * Copyright (C) 2008-2011 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley, Jouni Högander
+ *
+ * This file contains clockdomains and clockdomain wakeup/sleep
+ * dependencies for the OMAP3xxx chips.  Some notes:
+ *
+ * A useful validation rule for struct clockdomain: Any clockdomain
+ * referenced by a wkdep_srcs or sleepdep_srcs array must have a
+ * dep_bit assigned.  So wkdep_srcs/sleepdep_srcs are really just
+ * software-controllable dependencies.  Non-software-controllable
+ * dependencies do exist, but they are not encoded below (yet).
+ *
+ * The overly-specific dep_bit names are due to a bit name collision
+ * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
+ * value are the same for all powerdomains: 2
+ *
+ * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
+ * sanity check?
+ * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
+ */
+
+/*
+ * To-Do List
+ * -> Port the Sleep/Wakeup dependencies for the domains
+ *    from the Power domain framework
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-34xx.h"
+#include "prm-regbits-34xx.h"
+
+/*
+ * Clockdomain dependencies for wkdeps/sleepdeps
+ *
+ * XXX Hardware dependencies (e.g., dependencies that cannot be
+ * changed in software) are not included here yet, but should be.
+ */
+
+/* OMAP3-specific possible dependencies */
+
+/*
+ * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
+ * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
+ */
+static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
+        { .clkdm_name = "iva2_clkdm", },
+        { .clkdm_name = "mpu_clkdm", },
+        { .clkdm_name = "wkup_clkdm", },
+        { NULL },
+};
+
+/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
+static struct clkdm_dep per_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+
+/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
+static struct clkdm_dep usbhost_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+
+/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
+static struct clkdm_dep mpu_3xxx_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "per_clkdm" },
+        { NULL },
+};
+
+/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
+static struct clkdm_dep iva2_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "per_clkdm" },
+        { NULL },
+};
+
+/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
+static struct clkdm_dep cam_wkdeps[] = {
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+
+/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
+static struct clkdm_dep dss_wkdeps[] = {
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+
+/* 3430: PM_WKDEP_NEON: MPU */
+static struct clkdm_dep neon_wkdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { NULL },
+};
+
+/* Sleep dependency source arrays for OMAP3-specific clkdms */
+
+/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
+static struct clkdm_dep dss_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { NULL },
+};
+
+/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
+static struct clkdm_dep per_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { NULL },
+};
+
+/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
+static struct clkdm_dep usbhost_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { NULL },
+};
+
+/* 3430: CM_SLEEPDEP_CAM: MPU */
+static struct clkdm_dep cam_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { NULL },
+};
+
+/*
+ * 3430ES1: CM_SLEEPDEP_GFX: MPU
+ * 3430ES2: CM_SLEEPDEP_SGX: MPU
+ * These can share data since they will never be present simultaneously
+ * on the same device.
+ */
+static struct clkdm_dep gfx_sgx_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { NULL },
+};
+
+/*
+ * OMAP3 clockdomains
+ */
+
+static struct clockdomain mpu_3xxx_clkdm = {
+        .name           = "mpu_clkdm",
+        .pwrdm          = { .name = "mpu_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
+        .dep_bit        = OMAP3430_EN_MPU_SHIFT,
+        .wkdep_srcs     = mpu_3xxx_wkdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
+};
+
+static struct clockdomain neon_clkdm = {
+        .name           = "neon_clkdm",
+        .pwrdm          = { .name = "neon_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = neon_wkdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
+};
+
+static struct clockdomain iva2_clkdm = {
+        .name           = "iva2_clkdm",
+        .pwrdm          = { .name = "iva2_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
+        .wkdep_srcs     = iva2_wkdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
+};
+
+static struct clockdomain gfx_3430es1_clkdm = {
+        .name           = "gfx_clkdm",
+        .pwrdm          = { .name = "gfx_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = gfx_sgx_3xxx_wkdeps,
+        .sleepdep_srcs  = gfx_sgx_sleepdeps,
+        .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
+};
+
+static struct clockdomain sgx_clkdm = {
+        .name           = "sgx_clkdm",
+        .pwrdm          = { .name = "sgx_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = gfx_sgx_3xxx_wkdeps,
+        .sleepdep_srcs  = gfx_sgx_sleepdeps,
+        .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
+};
+
+/*
+ * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
+ * then that information was removed from the 34xx ES2+ TRM.  It is
+ * unclear whether the core is still there, but the clockdomain logic
+ * is there, and must be programmed to an appropriate state if the
+ * CORE clockdomain is to become inactive.
+ */
+static struct clockdomain d2d_clkdm = {
+        .name           = "d2d_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
+};
+
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l3_3xxx_clkdm = {
+        .name           = "core_l3_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .dep_bit        = OMAP3430_EN_CORE_SHIFT,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
+};
+
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l4_3xxx_clkdm = {
+        .name           = "core_l4_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .dep_bit        = OMAP3430_EN_CORE_SHIFT,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
+};
+
+/* Another case of bit name collisions between several registers: EN_DSS */
+static struct clockdomain dss_3xxx_clkdm = {
+        .name           = "dss_clkdm",
+        .pwrdm          = { .name = "dss_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
+        .wkdep_srcs     = dss_wkdeps,
+        .sleepdep_srcs  = dss_sleepdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
+};
+
+static struct clockdomain cam_clkdm = {
+        .name           = "cam_clkdm",
+        .pwrdm          = { .name = "cam_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = cam_wkdeps,
+        .sleepdep_srcs  = cam_sleepdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
+};
+
+static struct clockdomain usbhost_clkdm = {
+        .name           = "usbhost_clkdm",
+        .pwrdm          = { .name = "usbhost_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = usbhost_wkdeps,
+        .sleepdep_srcs  = usbhost_sleepdeps,
+        .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
+};
+
+static struct clockdomain per_clkdm = {
+        .name           = "per_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP3430_EN_PER_SHIFT,
+        .wkdep_srcs     = per_wkdeps,
+        .sleepdep_srcs  = per_sleepdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
+};
+
+/*
+ * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
+ * switched of even if sdti is in use
+ */
+static struct clockdomain emu_clkdm = {
+        .name           = "emu_clkdm",
+        .pwrdm          = { .name = "emu_pwrdm" },
+        .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
+};
+
+static struct clockdomain dpll1_clkdm = {
+        .name           = "dpll1_clkdm",
+        .pwrdm          = { .name = "dpll1_pwrdm" },
+};
+
+static struct clockdomain dpll2_clkdm = {
+        .name           = "dpll2_clkdm",
+        .pwrdm          = { .name = "dpll2_pwrdm" },
+};
+
+static struct clockdomain dpll3_clkdm = {
+        .name           = "dpll3_clkdm",
+        .pwrdm          = { .name = "dpll3_pwrdm" },
+};
+
+static struct clockdomain dpll4_clkdm = {
+        .name           = "dpll4_clkdm",
+        .pwrdm          = { .name = "dpll4_pwrdm" },
+};
+
+static struct clockdomain dpll5_clkdm = {
+        .name           = "dpll5_clkdm",
+        .pwrdm          = { .name = "dpll5_pwrdm" },
+};
+
+/*
+ * Clockdomain hwsup dependencies
+ */
+
+static struct clkdm_autodep clkdm_autodeps[] = {
+        {
+                .clkdm = { .name = "mpu_clkdm" },
+        },
+        {
+                .clkdm = { .name = "iva2_clkdm" },
+        },
+        {
+                .clkdm = { .name = NULL },
+        }
+};
+
+/*
+ *
+ */
+
+static struct clockdomain *clockdomains_omap3430_common[] __initdata = {
+        &wkup_common_clkdm,
+        &cm_common_clkdm,
+        &prm_common_clkdm,
+        &mpu_3xxx_clkdm,
+        &neon_clkdm,
+        &iva2_clkdm,
+        &d2d_clkdm,
+        &core_l3_3xxx_clkdm,
+        &core_l4_3xxx_clkdm,
+        &dss_3xxx_clkdm,
+        &cam_clkdm,
+        &per_clkdm,
+        &emu_clkdm,
+        &dpll1_clkdm,
+        &dpll2_clkdm,
+        &dpll3_clkdm,
+        &dpll4_clkdm,
+        NULL
+};
+
+static struct clockdomain *clockdomains_omap3430es1[] __initdata = {
+        &gfx_3430es1_clkdm,
+        NULL,
+};
+
+static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = {
+        &sgx_clkdm,
+        &dpll5_clkdm,
+        &usbhost_clkdm,
+        NULL,
+};
+
+void __init omap3xxx_clockdomains_init(void)
+{
+        struct clockdomain **sc;
+
+        if (!cpu_is_omap34xx())
+                return;
+
+        clkdm_register_platform_funcs(&omap3_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_omap3430_common);
+
+        sc = (omap_rev() == OMAP3430_REV_ES1_0) ? clockdomains_omap3430es1 :
+                clockdomains_omap3430es2plus;
+
+        clkdm_register_clkdms(sc);
+
+        clkdm_register_autodeps(clkdm_autodeps);
+        clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index dccc651fa0d0..9299ac291d28 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -34,350 +34,122 @@
 /* Static Dependencies for OMAP4 Clock Domains */
 
 static struct clkdm_dep d2d_wkup_sleep_deps[] = {
-        {
-                .clkdm_name      = "abe_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "ivahd_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_2_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_init_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "ivahd_clkdm" },
+        { .clkdm_name = "l3_1_clkdm" },
+        { .clkdm_name = "l3_2_clkdm" },
+        { .clkdm_name = "l3_emif_clkdm" },
+        { .clkdm_name = "l3_init_clkdm" },
+        { .clkdm_name = "l4_cfg_clkdm" },
+        { .clkdm_name = "l4_per_clkdm" },
         { NULL },
 };
 
 static struct clkdm_dep ducati_wkup_sleep_deps[] = {
-        {
-                .clkdm_name      = "abe_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "ivahd_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_2_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_dss_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_gfx_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_init_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_secure_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_wkup_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "tesla_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "ivahd_clkdm" },
+        { .clkdm_name = "l3_1_clkdm" },
+        { .clkdm_name = "l3_2_clkdm" },
+        { .clkdm_name = "l3_dss_clkdm" },
+        { .clkdm_name = "l3_emif_clkdm" },
+        { .clkdm_name = "l3_gfx_clkdm" },
+        { .clkdm_name = "l3_init_clkdm" },
+        { .clkdm_name = "l4_cfg_clkdm" },
+        { .clkdm_name = "l4_per_clkdm" },
+        { .clkdm_name = "l4_secure_clkdm" },
+        { .clkdm_name = "l4_wkup_clkdm" },
+        { .clkdm_name = "tesla_clkdm" },
         { NULL },
 };
 
 static struct clkdm_dep iss_wkup_sleep_deps[] = {
-        {
-                .clkdm_name      = "ivahd_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
+        { .clkdm_name = "ivahd_clkdm" },
+        { .clkdm_name = "l3_1_clkdm" },
+        { .clkdm_name = "l3_emif_clkdm" },
         { NULL },
 };
 
 static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
+        { .clkdm_name = "l3_1_clkdm" },
+        { .clkdm_name = "l3_emif_clkdm" },
         { NULL },
 };
 
 static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
-        {
-                .clkdm_name      = "abe_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "ducati_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "ivahd_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_dss_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_init_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_secure_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_wkup_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "ducati_clkdm" },
+        { .clkdm_name = "ivahd_clkdm" },
+        { .clkdm_name = "l3_1_clkdm" },
+        { .clkdm_name = "l3_dss_clkdm" },
+        { .clkdm_name = "l3_emif_clkdm" },
+        { .clkdm_name = "l3_init_clkdm" },
+        { .clkdm_name = "l4_cfg_clkdm" },
+        { .clkdm_name = "l4_per_clkdm" },
+        { .clkdm_name = "l4_secure_clkdm" },
+        { .clkdm_name = "l4_wkup_clkdm" },
         { NULL },
 };
 
 static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
-        {
-                .clkdm_name      = "ivahd_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_2_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
+        { .clkdm_name = "ivahd_clkdm" },
+        { .clkdm_name = "l3_2_clkdm" },
+        { .clkdm_name = "l3_emif_clkdm" },
         { NULL },
 };
 
 static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
-        {
-                .clkdm_name      = "ivahd_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
+        { .clkdm_name = "ivahd_clkdm" },
+        { .clkdm_name = "l3_1_clkdm" },
+        { .clkdm_name = "l3_emif_clkdm" },
         { NULL },
 };
 
 static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
-        {
-                .clkdm_name      = "abe_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "ivahd_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_secure_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_wkup_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "ivahd_clkdm" },
+        { .clkdm_name = "l3_emif_clkdm" },
+        { .clkdm_name = "l4_cfg_clkdm" },
+        { .clkdm_name = "l4_per_clkdm" },
+        { .clkdm_name = "l4_secure_clkdm" },
+        { .clkdm_name = "l4_wkup_clkdm" },
         { NULL },
 };
 
 static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
+        { .clkdm_name = "l3_1_clkdm" },
+        { .clkdm_name = "l3_emif_clkdm" },
+        { .clkdm_name = "l4_per_clkdm" },
         { NULL },
 };
 
 static struct clkdm_dep mpu_wkup_sleep_deps[] = {
-        {
-                .clkdm_name      = "abe_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "ducati_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "ivahd_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_2_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_dss_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_gfx_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_init_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_secure_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_wkup_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "tesla_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "ducati_clkdm" },
+        { .clkdm_name = "ivahd_clkdm" },
+        { .clkdm_name = "l3_1_clkdm" },
+        { .clkdm_name = "l3_2_clkdm" },
+        { .clkdm_name = "l3_dss_clkdm" },
+        { .clkdm_name = "l3_emif_clkdm" },
+        { .clkdm_name = "l3_gfx_clkdm" },
+        { .clkdm_name = "l3_init_clkdm" },
+        { .clkdm_name = "l4_cfg_clkdm" },
+        { .clkdm_name = "l4_per_clkdm" },
+        { .clkdm_name = "l4_secure_clkdm" },
+        { .clkdm_name = "l4_wkup_clkdm" },
+        { .clkdm_name = "tesla_clkdm" },
         { NULL },
 };
 
 static struct clkdm_dep tesla_wkup_sleep_deps[] = {
-        {
-                .clkdm_name      = "abe_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "ivahd_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_2_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_init_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_wkup_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "ivahd_clkdm" },
+        { .clkdm_name = "l3_1_clkdm" },
+        { .clkdm_name = "l3_2_clkdm" },
+        { .clkdm_name = "l3_emif_clkdm" },
+        { .clkdm_name = "l3_init_clkdm" },
+        { .clkdm_name = "l4_cfg_clkdm" },
+        { .clkdm_name = "l4_per_clkdm" },
+        { .clkdm_name = "l4_wkup_clkdm" },
         { NULL },
 };
 
@@ -388,7 +160,6 @@ static struct clockdomain l4_cefuse_44xx_clkdm = {
         .cm_inst          = OMAP4430_CM2_CEFUSE_INST,
         .clkdm_offs       = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain l4_cfg_44xx_clkdm = {
@@ -399,7 +170,6 @@ static struct clockdomain l4_cfg_44xx_clkdm = {
         .clkdm_offs       = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
         .dep_bit          = OMAP4430_L4CFG_STATDEP_SHIFT,
         .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain tesla_44xx_clkdm = {
@@ -412,7 +182,6 @@ static struct clockdomain tesla_44xx_clkdm = {
         .wkdep_srcs       = tesla_wkup_sleep_deps,
         .sleepdep_srcs    = tesla_wkup_sleep_deps,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain l3_gfx_44xx_clkdm = {
@@ -425,7 +194,6 @@ static struct clockdomain l3_gfx_44xx_clkdm = {
         .wkdep_srcs       = l3_gfx_wkup_sleep_deps,
         .sleepdep_srcs    = l3_gfx_wkup_sleep_deps,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain ivahd_44xx_clkdm = {
@@ -438,7 +206,6 @@ static struct clockdomain ivahd_44xx_clkdm = {
         .wkdep_srcs       = ivahd_wkup_sleep_deps,
         .sleepdep_srcs    = ivahd_wkup_sleep_deps,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain l4_secure_44xx_clkdm = {
@@ -451,7 +218,6 @@ static struct clockdomain l4_secure_44xx_clkdm = {
         .wkdep_srcs       = l4_secure_wkup_sleep_deps,
         .sleepdep_srcs    = l4_secure_wkup_sleep_deps,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain l4_per_44xx_clkdm = {
@@ -462,7 +228,6 @@ static struct clockdomain l4_per_44xx_clkdm = {
         .clkdm_offs       = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
         .dep_bit          = OMAP4430_L4PER_STATDEP_SHIFT,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain abe_44xx_clkdm = {
@@ -473,7 +238,6 @@ static struct clockdomain abe_44xx_clkdm = {
         .clkdm_offs       = OMAP4430_CM1_ABE_ABE_CDOFFS,
         .dep_bit          = OMAP4430_ABE_STATDEP_SHIFT,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain l3_instr_44xx_clkdm = {
@@ -482,7 +246,6 @@ static struct clockdomain l3_instr_44xx_clkdm = {
         .prcm_partition   = OMAP4430_CM2_PARTITION,
         .cm_inst          = OMAP4430_CM2_CORE_INST,
         .clkdm_offs       = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain l3_init_44xx_clkdm = {
@@ -495,7 +258,6 @@ static struct clockdomain l3_init_44xx_clkdm = {
         .wkdep_srcs       = l3_init_wkup_sleep_deps,
         .sleepdep_srcs    = l3_init_wkup_sleep_deps,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain d2d_44xx_clkdm = {
@@ -507,7 +269,6 @@ static struct clockdomain d2d_44xx_clkdm = {
         .wkdep_srcs       = d2d_wkup_sleep_deps,
         .sleepdep_srcs    = d2d_wkup_sleep_deps,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain mpu0_44xx_clkdm = {
@@ -517,7 +278,6 @@ static struct clockdomain mpu0_44xx_clkdm = {
         .cm_inst          = OMAP4430_PRCM_MPU_CPU0_INST,
         .clkdm_offs       = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain mpu1_44xx_clkdm = {
@@ -527,7 +287,6 @@ static struct clockdomain mpu1_44xx_clkdm = {
         .cm_inst          = OMAP4430_PRCM_MPU_CPU1_INST,
         .clkdm_offs       = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain l3_emif_44xx_clkdm = {
@@ -538,7 +297,6 @@ static struct clockdomain l3_emif_44xx_clkdm = {
         .clkdm_offs       = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
         .dep_bit          = OMAP4430_MEMIF_STATDEP_SHIFT,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain l4_ao_44xx_clkdm = {
@@ -548,7 +306,6 @@ static struct clockdomain l4_ao_44xx_clkdm = {
         .cm_inst          = OMAP4430_CM2_ALWAYS_ON_INST,
         .clkdm_offs       = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain ducati_44xx_clkdm = {
@@ -561,7 +318,6 @@ static struct clockdomain ducati_44xx_clkdm = {
         .wkdep_srcs       = ducati_wkup_sleep_deps,
         .sleepdep_srcs    = ducati_wkup_sleep_deps,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain mpu_44xx_clkdm = {
@@ -573,7 +329,6 @@ static struct clockdomain mpu_44xx_clkdm = {
         .wkdep_srcs       = mpu_wkup_sleep_deps,
         .sleepdep_srcs    = mpu_wkup_sleep_deps,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain l3_2_44xx_clkdm = {
@@ -584,7 +339,6 @@ static struct clockdomain l3_2_44xx_clkdm = {
         .clkdm_offs       = OMAP4430_CM2_CORE_L3_2_CDOFFS,
         .dep_bit          = OMAP4430_L3_2_STATDEP_SHIFT,
         .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain l3_1_44xx_clkdm = {
@@ -595,7 +349,6 @@ static struct clockdomain l3_1_44xx_clkdm = {
         .clkdm_offs       = OMAP4430_CM2_CORE_L3_1_CDOFFS,
         .dep_bit          = OMAP4430_L3_1_STATDEP_SHIFT,
         .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain iss_44xx_clkdm = {
@@ -607,7 +360,6 @@ static struct clockdomain iss_44xx_clkdm = {
         .wkdep_srcs       = iss_wkup_sleep_deps,
         .sleepdep_srcs    = iss_wkup_sleep_deps,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain l3_dss_44xx_clkdm = {
@@ -620,7 +372,6 @@ static struct clockdomain l3_dss_44xx_clkdm = {
         .wkdep_srcs       = l3_dss_wkup_sleep_deps,
         .sleepdep_srcs    = l3_dss_wkup_sleep_deps,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain l4_wkup_44xx_clkdm = {
@@ -631,7 +382,6 @@ static struct clockdomain l4_wkup_44xx_clkdm = {
         .clkdm_offs       = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
         .dep_bit          = OMAP4430_L4WKUP_STATDEP_SHIFT,
         .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain emu_sys_44xx_clkdm = {
@@ -641,7 +391,6 @@ static struct clockdomain emu_sys_44xx_clkdm = {
         .cm_inst          = OMAP4430_PRM_EMU_CM_INST,
         .clkdm_offs       = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
         .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain l3_dma_44xx_clkdm = {
@@ -653,7 +402,6 @@ static struct clockdomain l3_dma_44xx_clkdm = {
         .wkdep_srcs       = l3_dma_wkup_sleep_deps,
         .sleepdep_srcs    = l3_dma_wkup_sleep_deps,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* As clockdomains are added or removed above, this list must also be changed */
@@ -685,7 +433,10 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
         NULL
 };
 
+
 void __init omap44xx_clockdomains_init(void)
 {
-        clkdm_init(clockdomains_omap44xx, NULL, &omap4_clkdm_operations);
+        clkdm_register_platform_funcs(&omap4_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_omap44xx);
+        clkdm_complete_init();
 }
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 3f20cbb9967b..de61f15c48e2 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -56,6 +56,12 @@ void __init omap2_set_globals_242x(void)
 {
         __omap2_set_globals(&omap242x_globals);
 }
+
+void __init omap242x_map_io(void)
+{
+        omap2_set_globals_242x();
+        omap242x_map_common_io();
+}
 #endif
 
 #if defined(CONFIG_SOC_OMAP2430)
@@ -74,6 +80,12 @@ void __init omap2_set_globals_243x(void)
 {
         __omap2_set_globals(&omap243x_globals);
 }
+
+void __init omap243x_map_io(void)
+{
+        omap2_set_globals_243x();
+        omap243x_map_common_io();
+}
 #endif
 
 #if defined(CONFIG_ARCH_OMAP3)
@@ -138,5 +150,11 @@ void __init omap2_set_globals_443x(void)
         omap2_set_globals_control(&omap4_globals);
         omap2_set_globals_prcm(&omap4_globals);
 }
+
+void __init omap4_map_io(void)
+{
+        omap2_set_globals_443x();
+        omap44xx_map_common_io();
+}
 #endif
 
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 1077ad663f93..10adf66be7ba 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -44,7 +44,7 @@ static int __init omap3_l3_init(void)
 {
         int l;
         struct omap_hwmod *oh;
-        struct omap_device *od;
+        struct platform_device *pdev;
         char oh_name[L3_MODULES_MAX_LEN];
 
         /*
@@ -61,12 +61,12 @@ static int __init omap3_l3_init(void)
         if (!oh)
                 pr_err("could not look up %s\n", oh_name);
 
-        od = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
+        pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
                                                            NULL, 0, 0);
 
-        WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
+        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
 
-        return IS_ERR(od) ? PTR_ERR(od) : 0;
+        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
 }
 postcore_initcall(omap3_l3_init);
 
@@ -74,7 +74,7 @@ static int __init omap4_l3_init(void)
 {
         int l, i;
         struct omap_hwmod *oh[3];
-        struct omap_device *od;
+        struct platform_device *pdev;
         char oh_name[L3_MODULES_MAX_LEN];
 
         /*
@@ -92,12 +92,12 @@ static int __init omap4_l3_init(void)
                         pr_err("could not look up %s\n", oh_name);
         }
 
-        od = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
+        pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
                                                      0, NULL, 0, 0);
 
-        WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
+        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
 
-        return IS_ERR(od) ? PTR_ERR(od) : 0;
+        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
 }
 postcore_initcall(omap4_l3_init);
 
@@ -232,7 +232,7 @@ struct omap_device_pm_latency omap_keyboard_latency[] = {
 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
                         *sdp4430_keypad_data, struct omap_board_data *bdata)
 {
-        struct omap_device *od;
+        struct platform_device *pdev;
         struct omap_hwmod *oh;
         struct omap4_keypad_platform_data *keypad_data;
         unsigned int id = -1;
@@ -247,15 +247,15 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
 
         keypad_data = sdp4430_keypad_data;
 
-        od = omap_device_build(name, id, oh, keypad_data,
+        pdev = omap_device_build(name, id, oh, keypad_data,
                         sizeof(struct omap4_keypad_platform_data),
                         omap_keyboard_latency,
                         ARRAY_SIZE(omap_keyboard_latency), 0);
 
-        if (IS_ERR(od)) {
+        if (IS_ERR(pdev)) {
                 WARN(1, "Can't build omap_device for %s:%s.\n",
                                                 name, oh->name);
-                return PTR_ERR(od);
+                return PTR_ERR(pdev);
         }
         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
 
@@ -274,7 +274,7 @@ static struct omap_device_pm_latency mbox_latencies[] = {
 static inline void omap_init_mbox(void)
 {
         struct omap_hwmod *oh;
-        struct omap_device *od;
+        struct platform_device *pdev;
 
         oh = omap_hwmod_lookup("mailbox");
         if (!oh) {
@@ -282,10 +282,10 @@ static inline void omap_init_mbox(void)
                 return;
         }
 
-        od = omap_device_build("omap-mailbox", -1, oh, NULL, 0,
+        pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0,
                                 mbox_latencies, ARRAY_SIZE(mbox_latencies), 0);
-        WARN(IS_ERR(od), "%s: could not build device, err %ld\n",
-                                                __func__, PTR_ERR(od));
+        WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
+                                                __func__, PTR_ERR(pdev));
 }
 #else
 static inline void omap_init_mbox(void) { }
@@ -344,7 +344,7 @@ struct omap_device_pm_latency omap_mcspi_latency[] = {
 
 static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
 {
-        struct omap_device *od;
+        struct platform_device *pdev;
         char *name = "omap2_mcspi";
         struct omap2_mcspi_platform_config *pdata;
         static int spi_num;
@@ -371,10 +371,10 @@ static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
         }
 
         spi_num++;
-        od = omap_device_build(name, spi_num, oh, pdata,
+        pdev = omap_device_build(name, spi_num, oh, pdata,
                                 sizeof(*pdata), omap_mcspi_latency,
                                 ARRAY_SIZE(omap_mcspi_latency), 0);
-        WARN(IS_ERR(od), "Can't build omap_device for %s:%s\n",
+        WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
                                 name, oh->name);
         kfree(pdata);
         return 0;
@@ -709,7 +709,7 @@ static struct omap_device_pm_latency omap_wdt_latency[] = {
 static int __init omap_init_wdt(void)
 {
         int id = -1;
-        struct omap_device *od;
+        struct platform_device *pdev;
         struct omap_hwmod *oh;
         char *oh_name = "wd_timer2";
         char *dev_name = "omap_wdt";
@@ -723,10 +723,10 @@ static int __init omap_init_wdt(void)
                 return -EINVAL;
         }
 
-        od = omap_device_build(dev_name, id, oh, NULL, 0,
+        pdev = omap_device_build(dev_name, id, oh, NULL, 0,
                                 omap_wdt_latency,
                                 ARRAY_SIZE(omap_wdt_latency), 0);
-        WARN(IS_ERR(od), "Can't build omap_device for %s:%s.\n",
+        WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
                                 dev_name, oh->name);
         return 0;
 }
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index a5b7a236aa5b..18693f6de041 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -78,7 +78,7 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
 {
         int r = 0;
         struct omap_hwmod *oh;
-        struct omap_device *od;
+        struct platform_device *pdev;
         int i, oh_count;
         struct omap_display_platform_data pdata;
         const struct omap_dss_hwmod_data *curr_dss_hwmod;
@@ -108,13 +108,13 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
                         return -ENODEV;
                 }
 
-                od = omap_device_build(curr_dss_hwmod[i].dev_name,
+                pdev = omap_device_build(curr_dss_hwmod[i].dev_name,
                                 curr_dss_hwmod[i].id, oh, &pdata,
                                 sizeof(struct omap_display_platform_data),
                                 omap_dss_latency,
                                 ARRAY_SIZE(omap_dss_latency), 0);
 
-                if (WARN((IS_ERR(od)), "Could not build omap_device for %s\n",
+                if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n",
                                 curr_dss_hwmod[i].oh_name))
                         return -ENODEV;
         }
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index c9ff0e79703d..ae8cb3fb1830 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -228,7 +228,7 @@ static u32 configure_dma_errata(void)
 /* One time initializations */
 static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 {
-        struct omap_device                      *od;
+        struct platform_device                  *pdev;
         struct omap_system_dma_plat_info        *p;
         struct resource                         *mem;
         char                                    *name = "omap_dma_system";
@@ -258,23 +258,23 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 
         p->errata               = configure_dma_errata();
 
-        od = omap_device_build(name, 0, oh, p, sizeof(*p),
+        pdev = omap_device_build(name, 0, oh, p, sizeof(*p),
                         omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0);
         kfree(p);
-        if (IS_ERR(od)) {
+        if (IS_ERR(pdev)) {
                 pr_err("%s: Can't build omap_device for %s:%s.\n",
                         __func__, name, oh->name);
-                return PTR_ERR(od);
+                return PTR_ERR(pdev);
         }
 
-        mem = platform_get_resource(&od->pdev, IORESOURCE_MEM, 0);
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (!mem) {
-                dev_err(&od->pdev.dev, "%s: no mem resource\n", __func__);
+                dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
                 return -EINVAL;
         }
         dma_base = ioremap(mem->start, resource_size(mem));
         if (!dma_base) {
-                dev_err(&od->pdev.dev, "%s: ioremap fail\n", __func__);
+                dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
                 return -ENOMEM;
         }
 
@@ -283,7 +283,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
                                         (d->lch_count), GFP_KERNEL);
 
         if (!d->chan) {
-                dev_err(&od->pdev.dev, "%s: kzalloc fail\n", __func__);
+                dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
                 return -ENOMEM;
         }
         return 0;
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 2765cdc3152d..652ccc574196 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -34,7 +34,7 @@ static struct omap_device_pm_latency omap_gpio_latency[] = {
 
 static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 {
-        struct omap_device *od;
+        struct platform_device *pdev;
         struct omap_gpio_platform_data *pdata;
         struct omap_gpio_dev_attr *dev_attr;
         char *name = "omap_gpio";
@@ -107,19 +107,19 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
                 return -EINVAL;
         }
 
-        od = omap_device_build(name, id - 1, oh, pdata,
+        pdev = omap_device_build(name, id - 1, oh, pdata,
                                 sizeof(*pdata), omap_gpio_latency,
                                 ARRAY_SIZE(omap_gpio_latency),
                                 false);
         kfree(pdata);
 
-        if (IS_ERR(od)) {
+        if (IS_ERR(pdev)) {
                 WARN(1, "Can't build omap_device for %s:%s.\n",
                                         name, oh->name);
-                return PTR_ERR(od);
+                return PTR_ERR(pdev);
         }
 
-        omap_device_disable_idle_on_suspend(od);
+        omap_device_disable_idle_on_suspend(pdev);
 
         gpio_bank_count++;
         return 0;
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index a9b45c76e1d3..cc8791952a05 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -430,7 +430,7 @@ static struct omap_device_pm_latency omap_hsmmc_latency[] = {
 void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
 {
         struct omap_hwmod *oh;
-        struct omap_device *od;
+        struct platform_device *pdev;
         struct omap_device_pm_latency *ohl;
         char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
         struct omap_mmc_platform_data *mmc_data;
@@ -471,9 +471,9 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
                 mmc_data->controller_flags = mmc_dev_attr->flags;
         }
 
-        od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
+        pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
                 sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
-        if (IS_ERR(od)) {
+        if (IS_ERR(pdev)) {
                 WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
                 kfree(mmc_data->slots[0].name);
                 goto done;
@@ -482,7 +482,7 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
          * return device handle to board setup code
          * required to populate for regulator framework structure
          */
-        hsmmcinfo->dev = &od->pdev.dev;
+        hsmmcinfo->dev = &pdev->dev;
 
 done:
         kfree(mmc_data);
diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
index 06d4a80660a5..0b3ae9d9c3b3 100644
--- a/arch/arm/mach-omap2/hwspinlock.c
+++ b/arch/arm/mach-omap2/hwspinlock.c
@@ -35,7 +35,7 @@ int __init hwspinlocks_init(void)
 {
         int retval = 0;
         struct omap_hwmod *oh;
-        struct omap_device *od;
+        struct platform_device *pdev;
         const char *oh_name = "spinlock";
         const char *dev_name = "omap_hwspinlock";
 
@@ -48,13 +48,13 @@ int __init hwspinlocks_init(void)
         if (oh == NULL)
                 return -EINVAL;
 
-        od = omap_device_build(dev_name, 0, oh, NULL, 0,
+        pdev = omap_device_build(dev_name, 0, oh, NULL, 0,
                                 omap_spinlock_latency,
                                 ARRAY_SIZE(omap_spinlock_latency), false);
-        if (IS_ERR(od)) {
+        if (IS_ERR(pdev)) {
                 pr_err("Can't build omap_device for %s:%s\n", dev_name,
                                                                 oh_name);
-                retval = PTR_ERR(od);
+                retval = PTR_ERR(pdev);
         }
 
         return retval;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 37efb8696927..d27daf921c7e 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -28,7 +28,6 @@
 
 #include "control.h"
 
-static struct omap_chip_id omap_chip;
 static unsigned int omap_revision;
 
 u32 omap_features;
@@ -39,19 +38,6 @@ unsigned int omap_rev(void)
 }
 EXPORT_SYMBOL(omap_rev);
 
-/**
- * omap_chip_is - test whether currently running OMAP matches a chip type
- * @oc: omap_chip_t to test against
- *
- * Test whether the currently-running OMAP chip matches the supplied
- * chip type 'oc'.  Returns 1 upon a match; 0 upon failure.
- */
-int omap_chip_is(struct omap_chip_id oci)
-{
-        return (oci.oc & omap_chip.oc) ? 1 : 0;
-}
-EXPORT_SYMBOL(omap_chip_is);
-
 int omap_type(void)
 {
         u32 val = 0;
@@ -242,14 +228,12 @@ static void __init ti816x_check_features(void)
         omap_features = OMAP3_HAS_NEON;
 }
 
-static void __init omap3_check_revision(void)
+static void __init omap3_check_revision(const char **cpu_rev)
 {
         u32 cpuid, idcode;
         u16 hawkeye;
         u8 rev;
 
-        omap_chip.oc = CHIP_IS_OMAP3430;
-
         /*
          * We cannot access revision registers on ES1.0.
          * If the processor type is Cortex-A8 and the revision is 0x0
@@ -258,7 +242,7 @@ static void __init omap3_check_revision(void)
         cpuid = read_cpuid(CPUID_ID);
         if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
                 omap_revision = OMAP3430_REV_ES1_0;
-                omap_chip.oc |= CHIP_IS_OMAP3430ES1;
+                *cpu_rev = "1.0";
                 return;
         }
 
@@ -279,77 +263,85 @@ static void __init omap3_check_revision(void)
                 case 0: /* Take care of early samples */
                 case 1:
                         omap_revision = OMAP3430_REV_ES2_0;
-                        omap_chip.oc |= CHIP_IS_OMAP3430ES2;
+                        *cpu_rev = "2.0";
                         break;
                 case 2:
                         omap_revision = OMAP3430_REV_ES2_1;
-                        omap_chip.oc |= CHIP_IS_OMAP3430ES2;
+                        *cpu_rev = "2.1";
                         break;
                 case 3:
                         omap_revision = OMAP3430_REV_ES3_0;
-                        omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
+                        *cpu_rev = "3.0";
                         break;
                 case 4:
                         omap_revision = OMAP3430_REV_ES3_1;
-                        omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
+                        *cpu_rev = "3.1";
                         break;
                 case 7:
                 /* FALLTHROUGH */
                 default:
                         /* Use the latest known revision as default */
                         omap_revision = OMAP3430_REV_ES3_1_2;
-
-                        /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
-                        omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
+                        *cpu_rev = "3.1.2";
                 }
                 break;
         case 0xb868:
-                /* Handle OMAP35xx/AM35xx devices
+                /*
+                 * Handle OMAP/AM 3505/3517 devices
                  *
-                 * Set the device to be OMAP3505 here. Actual device
+                 * Set the device to be OMAP3517 here. Actual device
                  * is identified later based on the features.
-                 *
-                 * REVISIT: AM3505/AM3517 should have their own CHIP_IS
                  */
-                omap_revision = OMAP3505_REV(rev);
-                omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
+                switch (rev) {
+                case 0:
+                        omap_revision = OMAP3517_REV_ES1_0;
+                        *cpu_rev = "1.0";
+                        break;
+                case 1:
+                /* FALLTHROUGH */
+                default:
+                        omap_revision = OMAP3517_REV_ES1_1;
+                        *cpu_rev = "1.1";
+                }
                 break;
         case 0xb891:
                 /* Handle 36xx devices */
-                omap_chip.oc |= CHIP_IS_OMAP3630ES1;
 
                 switch(rev) {
                 case 0: /* Take care of early samples */
                         omap_revision = OMAP3630_REV_ES1_0;
+                        *cpu_rev = "1.0";
                         break;
                 case 1:
                         omap_revision = OMAP3630_REV_ES1_1;
-                        omap_chip.oc |= CHIP_IS_OMAP3630ES1_1;
+                        *cpu_rev = "1.1";
                         break;
                 case 2:
+                /* FALLTHROUGH */
                 default:
-                        omap_revision =  OMAP3630_REV_ES1_2;
-                        omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
+                        omap_revision = OMAP3630_REV_ES1_2;
+                        *cpu_rev = "1.2";
                 }
                 break;
         case 0xb81e:
-                omap_chip.oc = CHIP_IS_TI816X;
-
                 switch (rev) {
                 case 0:
                         omap_revision = TI8168_REV_ES1_0;
+                        *cpu_rev = "1.0";
                         break;
                 case 1:
+                /* FALLTHROUGH */
+                default:
                         omap_revision = TI8168_REV_ES1_1;
+                        *cpu_rev = "1.1";
                         break;
-                default:
-                        omap_revision =  TI8168_REV_ES1_1;
                 }
                 break;
         default:
-                /* Unknown default to latest silicon rev as default*/
-                omap_revision =  OMAP3630_REV_ES1_2;
-                omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
+                /* Unknown default to latest silicon rev as default */
+                omap_revision = OMAP3630_REV_ES1_2;
+                *cpu_rev = "1.2";
+                pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
         }
 }
 
@@ -382,24 +374,20 @@ static void __init omap4_check_revision(void)
                 switch (rev) {
                 case 0:
                         omap_revision = OMAP4430_REV_ES1_0;
-                        omap_chip.oc |= CHIP_IS_OMAP4430ES1;
                         break;
                 case 1:
                 default:
                         omap_revision = OMAP4430_REV_ES2_0;
-                        omap_chip.oc |= CHIP_IS_OMAP4430ES2;
                 }
                 break;
         case 0xb95c:
                 switch (rev) {
                 case 3:
                         omap_revision = OMAP4430_REV_ES2_1;
-                        omap_chip.oc |= CHIP_IS_OMAP4430ES2_1;
                         break;
                 case 4:
                 default:
                         omap_revision = OMAP4430_REV_ES2_2;
-                        omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
                 }
                 break;
         case 0xb94e:
@@ -407,14 +395,12 @@ static void __init omap4_check_revision(void)
                 case 0:
                 default:
                         omap_revision = OMAP4460_REV_ES1_0;
-                        omap_chip.oc |= CHIP_IS_OMAP4460ES1_0;
                         break;
                 }
                 break;
         default:
                 /* Unknown default to latest silicon rev as default */
                 omap_revision = OMAP4430_REV_ES2_2;
-                omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
         }
 
         pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
@@ -425,94 +411,33 @@ static void __init omap4_check_revision(void)
         if (omap3_has_ ##feat())                \
                 printk(#feat" ");
 
-static void __init omap3_cpuinfo(void)
+static void __init omap3_cpuinfo(const char *cpu_rev)
 {
-        u8 rev = GET_OMAP_REVISION();
-        char cpu_name[16], cpu_rev[16];
+        const char *cpu_name;
 
-        /* OMAP3430 and OMAP3530 are assumed to be same.
+        /*
+         * OMAP3430 and OMAP3530 are assumed to be same.
          *
          * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
          * on available features. Upon detection, update the CPU id
          * and CPU class bits.
          */
         if (cpu_is_omap3630()) {
-                strcpy(cpu_name, "OMAP3630");
-        } else if (cpu_is_omap3505()) {
-                /*
-                 * AM35xx devices
-                 */
-                if (omap3_has_sgx()) {
-                        omap_revision = OMAP3517_REV(rev);
-                        strcpy(cpu_name, "AM3517");
-                } else {
-                        /* Already set in omap3_check_revision() */
-                        strcpy(cpu_name, "AM3505");
-                }
+                cpu_name = "OMAP3630";
+        } else if (cpu_is_omap3517()) {
+                /* AM35xx devices */
+                cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
         } else if (cpu_is_ti816x()) {
-                strcpy(cpu_name, "TI816X");
+                cpu_name = "TI816X";
         } else if (omap3_has_iva() && omap3_has_sgx()) {
                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
-                strcpy(cpu_name, "OMAP3430/3530");
+                cpu_name = "OMAP3430/3530";
         } else if (omap3_has_iva()) {
-                omap_revision = OMAP3525_REV(rev);
-                strcpy(cpu_name, "OMAP3525");
+                cpu_name = "OMAP3525";
         } else if (omap3_has_sgx()) {
-                omap_revision = OMAP3515_REV(rev);
-                strcpy(cpu_name, "OMAP3515");
+                cpu_name = "OMAP3515";
         } else {
-                omap_revision = OMAP3503_REV(rev);
-                strcpy(cpu_name, "OMAP3503");
-        }
-
-        if (cpu_is_omap3630() || cpu_is_ti816x()) {
-                switch (rev) {
-                case OMAP_REVBITS_00:
-                        strcpy(cpu_rev, "1.0");
-                        break;
-                case OMAP_REVBITS_01:
-                        strcpy(cpu_rev, "1.1");
-                        break;
-                case OMAP_REVBITS_02:
-                        /* FALLTHROUGH */
-                default:
-                        /* Use the latest known revision as default */
-                        strcpy(cpu_rev, "1.2");
-                }
-        } else if (cpu_is_omap3505() || cpu_is_omap3517()) {
-                switch (rev) {
-                case OMAP_REVBITS_00:
-                        strcpy(cpu_rev, "1.0");
-                        break;
-                case OMAP_REVBITS_01:
-                        /* FALLTHROUGH */
-                default:
-                        /* Use the latest known revision as default */
-                        strcpy(cpu_rev, "1.1");
-                }
-        } else {
-                switch (rev) {
-                case OMAP_REVBITS_00:
-                        strcpy(cpu_rev, "1.0");
-                        break;
-                case OMAP_REVBITS_01:
-                        strcpy(cpu_rev, "2.0");
-                        break;
-                case OMAP_REVBITS_02:
-                        strcpy(cpu_rev, "2.1");
-                        break;
-                case OMAP_REVBITS_03:
-                        strcpy(cpu_rev, "3.0");
-                        break;
-                case OMAP_REVBITS_04:
-                        strcpy(cpu_rev, "3.1");
-                        break;
-                case OMAP_REVBITS_05:
-                        /* FALLTHROUGH */
-                default:
-                        /* Use the latest known revision as default */
-                        strcpy(cpu_rev, "3.1.2");
-                }
+                cpu_name = "OMAP3503";
         }
 
         /* Print verbose information */
@@ -533,6 +458,8 @@ static void __init omap3_cpuinfo(void)
  */
 void __init omap2_check_revision(void)
 {
+        const char *cpu_rev;
+
         /*
          * At this point we have an idea about the processor revision set
          * earlier with omap2_set_globals_tap().
@@ -540,7 +467,7 @@ void __init omap2_check_revision(void)
         if (cpu_is_omap24xx()) {
                 omap24xx_check_revision();
         } else if (cpu_is_omap34xx()) {
-                omap3_check_revision();
+                omap3_check_revision(&cpu_rev);
 
                 /* TI816X doesn't have feature register */
                 if (!cpu_is_ti816x())
@@ -548,7 +475,7 @@ void __init omap2_check_revision(void)
                 else
                         ti816x_check_features();
 
-                omap3_cpuinfo();
+                omap3_cpuinfo(cpu_rev);
                 return;
         } else if (cpu_is_omap44xx()) {
                 omap4_check_revision();
@@ -557,22 +484,6 @@ void __init omap2_check_revision(void)
         } else {
                 pr_err("OMAP revision unknown, please fix!\n");
         }
-
-        /*
-         * OK, now we know the exact revision. Initialize omap_chip bits
-         * for powerdowmain and clockdomain code.
-         */
-        if (cpu_is_omap243x()) {
-                /* Currently only supports 2430ES2.1 and 2430-all */
-                omap_chip.oc |= CHIP_IS_OMAP2430;
-                return;
-        } else if (cpu_is_omap242x()) {
-                /* Currently only supports 2420ES2.1.1 and 2420-all */
-                omap_chip.oc |= CHIP_IS_OMAP2420;
-                return;
-        }
-
-        pr_err("Uninitialized omap_chip, please fix!\n");
 }
 
 /*
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 2ce1ce6fb4db..c14308caf9d3 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -16,7 +16,6 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -250,6 +249,7 @@ static void __init _omap2_map_common_io(void)
 
         omap2_check_revision();
         omap_sram_init();
+        omap_init_consistent_dma_size();
 }
 
 #ifdef CONFIG_SOC_OMAP2420
@@ -341,12 +341,12 @@ void __init omap2_init_common_infrastructure(void)
         u8 postsetup_state;
 
         if (cpu_is_omap242x()) {
-                omap2xxx_powerdomains_init();
-                omap2xxx_clockdomains_init();
+                omap242x_powerdomains_init();
+                omap242x_clockdomains_init();
                 omap2420_hwmod_init();
         } else if (cpu_is_omap243x()) {
-                omap2xxx_powerdomains_init();
-                omap2xxx_clockdomains_init();
+                omap243x_powerdomains_init();
+                omap243x_clockdomains_init();
                 omap2430_hwmod_init();
         } else if (cpu_is_omap34xx()) {
                 omap3xxx_powerdomains_init();
@@ -376,7 +376,7 @@ void __init omap2_init_common_infrastructure(void)
          * omap_hwmod_late_init(), so boards that desire full watchdog
          * coverage of kernel initialization can reprogram the
          * postsetup_state between the calls to
-         * omap2_init_common_infra() and omap2_init_common_devices().
+         * omap2_init_common_infra() and omap_sdrc_init().
          *
          * XXX ideally we could detect whether the MPU WDT was currently
          * enabled here and make this conditional
@@ -400,7 +400,47 @@ void __init omap2_init_common_infrastructure(void)
                 pr_err("Could not init clock framework - unknown SoC\n");
 }
 
-void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
+void __init omap2420_init_early(void)
+{
+        omap2_init_common_infrastructure();
+}
+
+void __init omap2430_init_early(void)
+{
+        omap2_init_common_infrastructure();
+}
+
+void __init omap3430_init_early(void)
+{
+        omap2_init_common_infrastructure();
+}
+
+void __init omap35xx_init_early(void)
+{
+        omap2_init_common_infrastructure();
+}
+
+void __init omap3630_init_early(void)
+{
+        omap2_init_common_infrastructure();
+}
+
+void __init am35xx_init_early(void)
+{
+        omap2_init_common_infrastructure();
+}
+
+void __init ti816x_init_early(void)
+{
+        omap2_init_common_infrastructure();
+}
+
+void __init omap4430_init_early(void)
+{
+        omap2_init_common_infrastructure();
+}
+
+void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                                       struct omap_sdrc_params *sdrc_cs1)
 {
         if (cpu_is_omap24xx() || omap3_has_sdrc()) {
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 4a6ef6ab8458..5063f253c4b9 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -27,66 +27,69 @@
 
 #include "control.h"
 
-/* McBSP internal signal muxing functions */
+/*
+ * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
+ * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
+ */
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-34xx.h"
 
-void omap2_mcbsp1_mux_clkr_src(u8 mux)
+/* McBSP internal signal muxing function */
+static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
+                                   const char *src)
 {
         u32 v;
 
         v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-        if (mux == CLKR_SRC_CLKR)
-                v &= ~OMAP2_MCBSP1_CLKR_MASK;
-        else if (mux == CLKR_SRC_CLKX)
-                v |= OMAP2_MCBSP1_CLKR_MASK;
-        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
-}
-EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src);
 
-void omap2_mcbsp1_mux_fsr_src(u8 mux)
-{
-        u32 v;
+        if (!strcmp(signal, "clkr")) {
+                if (!strcmp(src, "clkr"))
+                        v &= ~OMAP2_MCBSP1_CLKR_MASK;
+                else if (!strcmp(src, "clkx"))
+                        v |= OMAP2_MCBSP1_CLKR_MASK;
+                else
+                        return -EINVAL;
+        } else if (!strcmp(signal, "fsr")) {
+                if (!strcmp(src, "fsr"))
+                        v &= ~OMAP2_MCBSP1_FSR_MASK;
+                else if (!strcmp(src, "fsx"))
+                        v |= OMAP2_MCBSP1_FSR_MASK;
+                else
+                        return -EINVAL;
+        } else {
+                return -EINVAL;
+        }
 
-        v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-        if (mux == FSR_SRC_FSR)
-                v &= ~OMAP2_MCBSP1_FSR_MASK;
-        else if (mux == FSR_SRC_FSX)
-                v |= OMAP2_MCBSP1_FSR_MASK;
         omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
+
+        return 0;
 }
-EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
 
 /* McBSP CLKS source switching function */
-
-int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
+static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
+                                   const char *src)
 {
-        struct omap_mcbsp *mcbsp;
         struct clk *fck_src;
         char *fck_src_name;
         int r;
 
-        if (!omap_mcbsp_check_valid_id(id)) {
-                pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
-                return -EINVAL;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        if (fck_src_id == MCBSP_CLKS_PAD_SRC)
+        if (!strcmp(src, "clks_ext"))
                 fck_src_name = "pad_fck";
-        else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
+        else if (!strcmp(src, "clks_fclk"))
                 fck_src_name = "prcm_fck";
         else
                 return -EINVAL;
 
-        fck_src = clk_get(mcbsp->dev, fck_src_name);
+        fck_src = clk_get(dev, fck_src_name);
         if (IS_ERR_OR_NULL(fck_src)) {
                 pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
                        fck_src_name);
                 return -EINVAL;
         }
 
-        pm_runtime_put_sync(mcbsp->dev);
+        pm_runtime_put_sync(dev);
 
-        r = clk_set_parent(mcbsp->fclk, fck_src);
+        r = clk_set_parent(clk, fck_src);
         if (IS_ERR_VALUE(r)) {
                 pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
                        "clks", fck_src_name);
@@ -94,13 +97,30 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
                 return -EINVAL;
         }
 
-        pm_runtime_get_sync(mcbsp->dev);
+        pm_runtime_get_sync(dev);
 
         clk_put(fck_src);
 
         return 0;
 }
-EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
+
+static int omap3_enable_st_clock(unsigned int id, bool enable)
+{
+        unsigned int w;
+
+        /*
+         * Sidetone uses McBSP ICLK - which must not idle when sidetones
+         * are enabled or sidetones start sounding ugly.
+         */
+        w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
+        if (enable)
+                w &= ~(1 << (id - 2));
+        else
+                w |= 1 << (id - 2);
+        omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
+
+        return 0;
+}
 
 struct omap_device_pm_latency omap2_mcbsp_latency[] = {
         {
@@ -116,7 +136,7 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
         char *name = "omap-mcbsp";
         struct omap_hwmod *oh_device[2];
         struct omap_mcbsp_platform_data *pdata = NULL;
-        struct omap_device *od;
+        struct platform_device *pdev;
 
         sscanf(oh->name, "mcbsp%d", &id);
 
@@ -126,7 +146,13 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
                 return -ENOMEM;
         }
 
-        pdata->mcbsp_config_type = oh->class->rev;
+        pdata->reg_step = 4;
+        if (oh->class->rev < MCBSP_CONFIG_TYPE2) {
+                pdata->reg_size = 2;
+        } else {
+                pdata->reg_size = 4;
+                pdata->has_ccr = true;
+        }
 
         if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
                 if (id == 2)
@@ -137,22 +163,29 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
                         pdata->buffer_size = 0x80;
         }
 
+        if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
+                pdata->has_wakeup = true;
+
         oh_device[0] = oh;
 
         if (oh->dev_attr) {
                 oh_device[1] = omap_hwmod_lookup((
                 (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
+                pdata->enable_st_clock = omap3_enable_st_clock;
                 count++;
         }
-        od = omap_device_build_ss(name, id, oh_device, count, pdata,
+        pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
                                 sizeof(*pdata), omap2_mcbsp_latency,
                                 ARRAY_SIZE(omap2_mcbsp_latency), false);
         kfree(pdata);
-        if (IS_ERR(od))  {
+        if (IS_ERR(pdev))  {
                 pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
                                         name, oh->name);
-                return PTR_ERR(od);
+                return PTR_ERR(pdev);
         }
+        pdata->set_clk_src = omap2_mcbsp_set_clk_src;
+        if (id == 1)
+                pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
         omap_mcbsp_count++;
         return 0;
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 84cc0bdda3ae..d71380705080 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1954,9 +1954,6 @@ int __init omap_hwmod_register(struct omap_hwmod **ohs)
 
         i = 0;
         do {
-                if (!omap_chip_is(ohs[i]->omap_chip))
-                        continue;
-
                 r = _register(ohs[i]);
                 WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
                      r);
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a015c69068f6..b6ea69a5c2f8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -100,7 +100,6 @@ static struct omap_hwmod omap2420_l3_main_hwmod = {
         .masters_cnt    = ARRAY_SIZE(omap2420_l3_main_masters),
         .slaves         = omap2420_l3_main_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_l3_main_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -206,7 +205,6 @@ static struct omap_hwmod omap2420_l4_core_hwmod = {
         .masters_cnt    = ARRAY_SIZE(omap2420_l4_core_masters),
         .slaves         = omap2420_l4_core_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_core_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -227,7 +225,6 @@ static struct omap_hwmod omap2420_l4_wkup_hwmod = {
         .masters_cnt    = ARRAY_SIZE(omap2420_l4_wkup_masters),
         .slaves         = omap2420_l4_wkup_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_wkup_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -243,7 +240,6 @@ static struct omap_hwmod omap2420_mpu_hwmod = {
         .main_clk       = "mpu_ck",
         .masters        = omap2420_mpu_masters,
         .masters_cnt    = ARRAY_SIZE(omap2420_mpu_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /*
@@ -271,7 +267,6 @@ static struct omap_hwmod omap2420_iva_hwmod = {
         .class          = &iva_hwmod_class,
         .masters        = omap2420_iva_masters,
         .masters_cnt    = ARRAY_SIZE(omap2420_iva_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer1 */
@@ -317,7 +312,6 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
         .slaves         = omap2420_timer1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer1_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer2 */
@@ -354,7 +348,6 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
         .slaves         = omap2420_timer2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer2_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer3 */
@@ -391,7 +384,6 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
         .slaves         = omap2420_timer3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer3_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer4 */
@@ -428,7 +420,6 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
         .slaves         = omap2420_timer4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer4_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer5 */
@@ -465,7 +456,6 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
         .slaves         = omap2420_timer5_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer5_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 
@@ -503,7 +493,6 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
         .slaves         = omap2420_timer6_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer6_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer7 */
@@ -540,7 +529,6 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
         .slaves         = omap2420_timer7_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer7_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer8 */
@@ -577,7 +565,6 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
         .slaves         = omap2420_timer8_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer8_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer9 */
@@ -614,7 +601,6 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
         .slaves         = omap2420_timer9_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer9_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer10 */
@@ -651,7 +637,6 @@ static struct omap_hwmod omap2420_timer10_hwmod = {
         .slaves         = omap2420_timer10_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer10_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer11 */
@@ -688,7 +673,6 @@ static struct omap_hwmod omap2420_timer11_hwmod = {
         .slaves         = omap2420_timer11_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer11_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer12 */
@@ -725,7 +709,6 @@ static struct omap_hwmod omap2420_timer12_hwmod = {
         .slaves         = omap2420_timer12_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer12_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* l4_wkup -> wd_timer2 */
@@ -766,7 +749,6 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = {
         },
         .slaves         = omap2420_wd_timer2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* UART1 */
@@ -792,7 +774,6 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
         .slaves         = omap2420_uart1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
         .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* UART2 */
@@ -818,7 +799,6 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
         .slaves         = omap2420_uart2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
         .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* UART3 */
@@ -844,7 +824,6 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
         .slaves         = omap2420_uart3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
         .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* dss */
@@ -898,7 +877,6 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_slaves),
         .masters        = omap2420_dss_masters,
         .masters_cnt    = ARRAY_SIZE(omap2420_dss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -938,7 +916,6 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
         },
         .slaves         = omap2420_dss_dispc_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_dispc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -975,7 +952,6 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
         },
         .slaves         = omap2420_dss_rfbi_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -1013,7 +989,6 @@ static struct omap_hwmod omap2420_dss_venc_hwmod = {
         },
         .slaves         = omap2420_dss_venc_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_venc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -1064,7 +1039,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c1_slaves),
         .class          = &i2c_class,
         .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
         .flags          = HWMOD_16BIT_REG,
 };
 
@@ -1092,7 +1066,6 @@ static struct omap_hwmod omap2420_i2c2_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c2_slaves),
         .class          = &i2c_class,
         .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
         .flags          = HWMOD_16BIT_REG,
 };
 
@@ -1197,7 +1170,6 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio1_slaves),
         .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* gpio2 */
@@ -1223,7 +1195,6 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio2_slaves),
         .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* gpio3 */
@@ -1249,7 +1220,6 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio3_slaves),
         .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* gpio4 */
@@ -1275,7 +1245,6 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio4_slaves),
         .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* dma attributes */
@@ -1322,7 +1291,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
         .masters        = omap2420_dma_system_masters,
         .masters_cnt    = ARRAY_SIZE(omap2420_dma_system_masters),
         .dev_attr       = &dma_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -1363,7 +1331,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
         },
         .slaves         = omap2420_mailbox_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_mailbox_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* mcspi1 */
@@ -1393,7 +1360,6 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi1_slaves),
         .class          = &omap2xxx_mcspi_class,
         .dev_attr       = &omap_mcspi1_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* mcspi2 */
@@ -1423,7 +1389,6 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi2_slaves),
         .class          = &omap2xxx_mcspi_class,
         .dev_attr       = &omap_mcspi2_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /*
@@ -1473,7 +1438,6 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
         },
         .slaves         = omap2420_mcbsp1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* mcbsp2 */
@@ -1514,7 +1478,6 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
         },
         .slaves         = omap2420_mcbsp2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 408193d8e044..56de8d616313 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -110,7 +110,6 @@ static struct omap_hwmod omap2430_l3_main_hwmod = {
         .masters_cnt    = ARRAY_SIZE(omap2430_l3_main_masters),
         .slaves         = omap2430_l3_main_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_l3_main_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -250,7 +249,6 @@ static struct omap_hwmod omap2430_l4_core_hwmod = {
         .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
         .slaves         = omap2430_l4_core_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -301,7 +299,6 @@ static struct omap_hwmod omap2430_l4_wkup_hwmod = {
         .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
         .slaves         = omap2430_l4_wkup_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -317,7 +314,6 @@ static struct omap_hwmod omap2430_mpu_hwmod = {
         .main_clk       = "mpu_ck",
         .masters        = omap2430_mpu_masters,
         .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /*
@@ -345,7 +341,6 @@ static struct omap_hwmod omap2430_iva_hwmod = {
         .class          = &iva_hwmod_class,
         .masters        = omap2430_iva_masters,
         .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer1 */
@@ -391,7 +386,6 @@ static struct omap_hwmod omap2430_timer1_hwmod = {
         .slaves         = omap2430_timer1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer2 */
@@ -428,7 +422,6 @@ static struct omap_hwmod omap2430_timer2_hwmod = {
         .slaves         = omap2430_timer2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer3 */
@@ -465,7 +458,6 @@ static struct omap_hwmod omap2430_timer3_hwmod = {
         .slaves         = omap2430_timer3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer4 */
@@ -502,7 +494,6 @@ static struct omap_hwmod omap2430_timer4_hwmod = {
         .slaves         = omap2430_timer4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer5 */
@@ -539,7 +530,6 @@ static struct omap_hwmod omap2430_timer5_hwmod = {
         .slaves         = omap2430_timer5_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer6 */
@@ -576,7 +566,6 @@ static struct omap_hwmod omap2430_timer6_hwmod = {
         .slaves         = omap2430_timer6_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer7 */
@@ -613,7 +602,6 @@ static struct omap_hwmod omap2430_timer7_hwmod = {
         .slaves         = omap2430_timer7_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer8 */
@@ -650,7 +638,6 @@ static struct omap_hwmod omap2430_timer8_hwmod = {
         .slaves         = omap2430_timer8_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer9 */
@@ -687,7 +674,6 @@ static struct omap_hwmod omap2430_timer9_hwmod = {
         .slaves         = omap2430_timer9_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer10 */
@@ -724,7 +710,6 @@ static struct omap_hwmod omap2430_timer10_hwmod = {
         .slaves         = omap2430_timer10_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer11 */
@@ -761,7 +746,6 @@ static struct omap_hwmod omap2430_timer11_hwmod = {
         .slaves         = omap2430_timer11_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer12 */
@@ -798,7 +782,6 @@ static struct omap_hwmod omap2430_timer12_hwmod = {
         .slaves         = omap2430_timer12_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
         .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* l4_wkup -> wd_timer2 */
@@ -839,7 +822,6 @@ static struct omap_hwmod omap2430_wd_timer2_hwmod = {
         },
         .slaves         = omap2430_wd_timer2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* UART1 */
@@ -865,7 +847,6 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
         .slaves         = omap2430_uart1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
         .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* UART2 */
@@ -891,7 +872,6 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
         .slaves         = omap2430_uart2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
         .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* UART3 */
@@ -917,7 +897,6 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
         .slaves         = omap2430_uart3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
         .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* dss */
@@ -965,7 +944,6 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
         .masters        = omap2430_dss_masters,
         .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -999,7 +977,6 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
         },
         .slaves         = omap2430_dss_dispc_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -1030,7 +1007,6 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
         },
         .slaves         = omap2430_dss_rfbi_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -1062,7 +1038,6 @@ static struct omap_hwmod omap2430_dss_venc_hwmod = {
         },
         .slaves         = omap2430_dss_venc_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_venc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -1123,7 +1098,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
         .class          = &i2c_class,
         .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* I2C2 */
@@ -1151,7 +1125,6 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
         .class          = &i2c_class,
         .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* l4_wkup -> gpio1 */
@@ -1273,7 +1246,6 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
         .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* gpio2 */
@@ -1299,7 +1271,6 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
         .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* gpio3 */
@@ -1325,7 +1296,6 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
         .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* gpio4 */
@@ -1351,7 +1321,6 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
         .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* gpio5 */
@@ -1382,7 +1351,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
         .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* dma attributes */
@@ -1429,7 +1397,6 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
         .masters        = omap2430_dma_system_masters,
         .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
         .dev_attr       = &dma_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -1469,7 +1436,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
         },
         .slaves         = omap2430_mailbox_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_mailbox_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* mcspi1 */
@@ -1499,7 +1465,6 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
         .class          = &omap2xxx_mcspi_class,
         .dev_attr       = &omap_mcspi1_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* mcspi2 */
@@ -1529,7 +1494,6 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
         .class          = &omap2xxx_mcspi_class,
         .dev_attr       = &omap_mcspi2_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* mcspi3 */
@@ -1572,7 +1536,6 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
         .class          = &omap2xxx_mcspi_class,
         .dev_attr       = &omap_mcspi3_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /*
@@ -1628,7 +1591,6 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = {
          */
         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
                                 | HWMOD_SWSUP_MSTANDBY,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /*
@@ -1689,7 +1651,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
         },
         .slaves         = omap2430_mcbsp1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* mcbsp2 */
@@ -1731,7 +1692,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
         },
         .slaves         = omap2430_mcbsp2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* mcbsp3 */
@@ -1783,7 +1743,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
         },
         .slaves         = omap2430_mcbsp3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* mcbsp4 */
@@ -1841,7 +1800,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
         },
         .slaves         = omap2430_mcbsp4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* mcbsp5 */
@@ -1899,7 +1857,6 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
         },
         .slaves         = omap2430_mcbsp5_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp5_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* MMC/SD/SDIO common */
@@ -1966,7 +1923,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
         .slaves         = omap2430_mmc1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_mmc1_slaves),
         .class          = &omap2430_mmc_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* MMC/SD/SDIO2 */
@@ -2010,7 +1966,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
         .slaves         = omap2430_mmc2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_mmc2_slaves),
         .class          = &omap2430_mmc_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 25bf43b5a4ec..ab35acbc2d1d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -156,7 +156,6 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = {
         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
         .slaves         = omap3xxx_l3_main_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -459,7 +458,6 @@ static struct omap_hwmod omap3xxx_l4_core_hwmod = {
         .class          = &l4_hwmod_class,
         .slaves         = omap3xxx_l4_core_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -474,7 +472,6 @@ static struct omap_hwmod omap3xxx_l4_per_hwmod = {
         .class          = &l4_hwmod_class,
         .slaves         = omap3xxx_l4_per_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -489,7 +486,6 @@ static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
         .class          = &l4_hwmod_class,
         .slaves         = omap3xxx_l4_wkup_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -505,7 +501,6 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
         .main_clk       = "arm_fck",
         .masters        = omap3xxx_mpu_masters,
         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /*
@@ -533,7 +528,6 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
         .class          = &iva_hwmod_class,
         .masters        = omap3xxx_iva_masters,
         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
 /* timer class */
@@ -613,7 +607,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
         .slaves         = omap3xxx_timer1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
         .class          = &omap3xxx_timer_1ms_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
 /* timer2 */
@@ -659,7 +652,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
         .slaves         = omap3xxx_timer2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
         .class          = &omap3xxx_timer_1ms_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
 /* timer3 */
@@ -705,7 +697,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
         .slaves         = omap3xxx_timer3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
 /* timer4 */
@@ -751,7 +742,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
         .slaves         = omap3xxx_timer4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
 /* timer5 */
@@ -797,7 +787,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
         .slaves         = omap3xxx_timer5_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
 /* timer6 */
@@ -843,7 +832,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
         .slaves         = omap3xxx_timer6_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
 /* timer7 */
@@ -889,7 +877,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
         .slaves         = omap3xxx_timer7_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
 /* timer8 */
@@ -935,7 +922,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
         .slaves         = omap3xxx_timer8_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
 /* timer9 */
@@ -981,7 +967,6 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
         .slaves         = omap3xxx_timer9_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
 /* timer10 */
@@ -1018,7 +1003,6 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
         .slaves         = omap3xxx_timer10_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
         .class          = &omap3xxx_timer_1ms_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
 /* timer11 */
@@ -1055,7 +1039,6 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
         .slaves         = omap3xxx_timer11_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
 /* timer12*/
@@ -1105,7 +1088,6 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
         .slaves         = omap3xxx_timer12_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
 /* l4_wkup -> wd_timer2 */
@@ -1182,7 +1164,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
         },
         .slaves         = omap3xxx_wd_timer2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         /*
          * XXX: Use software supervised mode, HW supervised smartidle seems to
          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
@@ -1213,7 +1194,6 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
         .slaves         = omap3xxx_uart1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
         .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* UART2 */
@@ -1239,7 +1219,6 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
         .slaves         = omap3xxx_uart2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
         .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* UART3 */
@@ -1265,7 +1244,6 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
         .slaves         = omap3xxx_uart3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
         .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* UART4 */
@@ -1302,7 +1280,6 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
         .slaves         = omap3xxx_uart4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
         .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 };
 
 static struct omap_hwmod_class i2c_class = {
@@ -1390,7 +1367,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
         .masters        = omap3xxx_dss_masters,
         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -1415,8 +1391,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
         .masters        = omap3xxx_dss_masters,
         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
-                                CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
 };
 
 /* l4_core -> dss_dispc */
@@ -1454,9 +1428,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
         },
         .slaves         = omap3xxx_dss_dispc_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
-                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
-                                CHIP_GE_OMAP3630ES1_1),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -1518,9 +1489,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
         },
         .slaves         = omap3xxx_dss_dsi1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
-                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
-                                CHIP_GE_OMAP3630ES1_1),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -1558,9 +1526,6 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
         },
         .slaves         = omap3xxx_dss_rfbi_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
-                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
-                                CHIP_GE_OMAP3630ES1_1),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -1599,9 +1564,6 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
         },
         .slaves         = omap3xxx_dss_venc_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
-                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
-                                CHIP_GE_OMAP3630ES1_1),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -1637,7 +1599,6 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
         .class          = &i2c_class,
         .dev_attr       = &i2c1_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* I2C2 */
@@ -1672,7 +1633,6 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
         .class          = &i2c_class,
         .dev_attr       = &i2c2_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* I2C3 */
@@ -1718,7 +1678,6 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
         .class          = &i2c_class,
         .dev_attr       = &i2c3_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* l4_wkup -> gpio1 */
@@ -1880,7 +1839,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
         .class          = &omap3xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* gpio2 */
@@ -1912,7 +1870,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
         .class          = &omap3xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* gpio3 */
@@ -1944,7 +1901,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
         .class          = &omap3xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* gpio4 */
@@ -1976,7 +1932,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
         .class          = &omap3xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* gpio5 */
@@ -2013,7 +1968,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
         .class          = &omap3xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* gpio6 */
@@ -2050,7 +2004,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
         .class          = &omap3xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* dma_system -> L3 */
@@ -2134,7 +2087,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
         .masters        = omap3xxx_dma_system_masters,
         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
         .dev_attr       = &dma_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .flags          = HWMOD_NO_IDLEST,
 };
 
@@ -2207,7 +2159,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
         },
         .slaves         = omap3xxx_mcbsp1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* mcbsp2 */
@@ -2264,7 +2215,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
         .slaves         = omap3xxx_mcbsp2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* mcbsp3 */
@@ -2321,7 +2271,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
         .slaves         = omap3xxx_mcbsp3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* mcbsp4 */
@@ -2379,7 +2328,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
         },
         .slaves         = omap3xxx_mcbsp4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* mcbsp5 */
@@ -2437,7 +2385,6 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
         },
         .slaves         = omap3xxx_mcbsp5_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* 'mcbsp sidetone' class */
 
@@ -2498,7 +2445,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
         },
         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* mcbsp3_sidetone */
@@ -2547,7 +2493,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
         },
         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 
@@ -2609,9 +2554,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
         },
         .slaves         = omap3_sr1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
-                                        CHIP_IS_OMAP3430ES3_0 |
-                                        CHIP_IS_OMAP3430ES3_1),
         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
@@ -2631,7 +2573,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
         },
         .slaves         = omap3_sr1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 };
 
 /* SR2 */
@@ -2655,9 +2596,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
         },
         .slaves         = omap3_sr2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
-                                        CHIP_IS_OMAP3430ES3_0 |
-                                        CHIP_IS_OMAP3430ES3_1),
         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
@@ -2677,7 +2615,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
         },
         .slaves         = omap3_sr2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 };
 
 /*
@@ -2745,7 +2682,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
         },
         .slaves         = omap3xxx_mailbox_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* l4 core -> mcspi1 interface */
@@ -2843,7 +2779,6 @@ static struct omap_hwmod omap34xx_mcspi1 = {
         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
         .class          = &omap34xx_mcspi_class,
         .dev_attr       = &omap_mcspi1_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* mcspi2 */
@@ -2873,7 +2808,6 @@ static struct omap_hwmod omap34xx_mcspi2 = {
         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
         .class          = &omap34xx_mcspi_class,
         .dev_attr       = &omap_mcspi2_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* mcspi3 */
@@ -2916,7 +2850,6 @@ static struct omap_hwmod omap34xx_mcspi3 = {
         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
         .class          = &omap34xx_mcspi_class,
         .dev_attr       = &omap_mcspi3_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* SPI4 */
@@ -2957,7 +2890,6 @@ static struct omap_hwmod omap34xx_mcspi4 = {
         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
         .class          = &omap34xx_mcspi_class,
         .dev_attr       = &omap_mcspi4_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /*
@@ -3014,7 +2946,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
          */
         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
                                 | HWMOD_SWSUP_MSTANDBY,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
 /* usb_otg_hs */
@@ -3042,7 +2973,6 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = {
         .slaves         = am35xx_usbhsotg_slaves,
         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
         .class          = &am35xx_usbotg_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
 };
 
 /* MMC/SD/SDIO common */
@@ -3108,7 +3038,6 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
         .slaves         = omap3xxx_mmc1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
         .class          = &omap34xx_mmc_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* MMC/SD/SDIO2 */
@@ -3151,7 +3080,6 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
         .slaves         = omap3xxx_mmc2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
         .class          = &omap34xx_mmc_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* MMC/SD/SDIO3 */
@@ -3193,7 +3121,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
         .slaves         = omap3xxx_mmc3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
         .class          = &omap34xx_mmc_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
@@ -3224,10 +3151,7 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap3xxx_uart1_hwmod,
         &omap3xxx_uart2_hwmod,
         &omap3xxx_uart3_hwmod,
-        &omap3xxx_uart4_hwmod,
         /* dss class */
-        &omap3430es1_dss_core_hwmod,
-        &omap3xxx_dss_core_hwmod,
         &omap3xxx_dss_dispc_hwmod,
         &omap3xxx_dss_dsi1_hwmod,
         &omap3xxx_dss_rfbi_hwmod,
@@ -3239,9 +3163,6 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap3xxx_i2c3_hwmod,
         &omap34xx_sr1_hwmod,
         &omap34xx_sr2_hwmod,
-        &omap36xx_sr1_hwmod,
-        &omap36xx_sr2_hwmod,
-
 
         /* gpio class */
         &omap3xxx_gpio1_hwmod,
@@ -3272,16 +3193,96 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap34xx_mcspi3,
         &omap34xx_mcspi4,
 
-        /* usbotg class */
+        NULL,
+};
+
+/* 3430ES1-only hwmods */
+static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
+        &omap3430es1_dss_core_hwmod,
+        NULL
+};
+
+/* 3430ES2+-only hwmods */
+static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
+        &omap3xxx_dss_core_hwmod,
         &omap3xxx_usbhsotg_hwmod,
+        NULL
+};
 
-        /* usbotg for am35x */
-        &am35xx_usbhsotg_hwmod,
+/* 34xx-only hwmods (all ES revisions) */
+static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
+        &omap34xx_sr1_hwmod,
+        &omap34xx_sr2_hwmod,
+        NULL
+};
 
-        NULL,
+/* 36xx-only hwmods (all ES revisions) */
+static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
+        &omap3xxx_uart4_hwmod,
+        &omap3xxx_dss_core_hwmod,
+        &omap36xx_sr1_hwmod,
+        &omap36xx_sr2_hwmod,
+        &omap3xxx_usbhsotg_hwmod,
+        NULL
+};
+
+static __initdata struct omap_hwmod *am35xx_hwmods[] = {
+        &omap3xxx_dss_core_hwmod, /* XXX ??? */
+        &am35xx_usbhsotg_hwmod,
+        NULL
 };
 
 int __init omap3xxx_hwmod_init(void)
 {
-        return omap_hwmod_register(omap3xxx_hwmods);
+        int r;
+        struct omap_hwmod **h = NULL;
+        unsigned int rev;
+
+        /* Register hwmods common to all OMAP3 */
+        r = omap_hwmod_register(omap3xxx_hwmods);
+        if (!r)
+                return r;
+
+        rev = omap_rev();
+
+        /*
+         * Register hwmods common to individual OMAP3 families, all
+         * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
+         * All possible revisions should be included in this conditional.
+         */
+        if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
+            rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
+            rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
+                h = omap34xx_hwmods;
+        } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
+                h = am35xx_hwmods;
+        } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
+                   rev == OMAP3630_REV_ES1_2) {
+                h = omap36xx_hwmods;
+        } else {
+                WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
+                return -EINVAL;
+        };
+
+        r = omap_hwmod_register(h);
+        if (!r)
+                return r;
+
+        /*
+         * Register hwmods specific to certain ES levels of a
+         * particular family of silicon (e.g., 34xx ES1.0)
+         */
+        h = NULL;
+        if (rev == OMAP3430_REV_ES1_0) {
+                h = omap3430es1_hwmods;
+        } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
+                   rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
+                   rev == OMAP3430_REV_ES3_1_2) {
+                h = omap3430es2plus_hwmods;
+        };
+
+        if (h)
+                r = omap_hwmod_register(h);
+
+        return r;
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 6201422c0606..caaf40911dd4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -133,7 +133,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
         .slaves         = omap44xx_dmm_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
         .mpu_irqs       = omap44xx_dmm_irqs,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -189,7 +188,6 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = {
         },
         .slaves         = omap44xx_emif_fw_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -236,7 +234,6 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
         },
         .slaves         = omap44xx_l3_instr_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* l3_main_1 */
@@ -336,7 +333,6 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
         },
         .slaves         = omap44xx_l3_main_1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* l3_main_2 */
@@ -438,7 +434,6 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
         },
         .slaves         = omap44xx_l3_main_2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* l3_main_3 */
@@ -496,7 +491,6 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
         },
         .slaves         = omap44xx_l3_main_3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -559,7 +553,6 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
         },
         .slaves         = omap44xx_l4_abe_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* l4_cfg */
@@ -588,7 +581,6 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
         },
         .slaves         = omap44xx_l4_cfg_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* l4_per */
@@ -617,7 +609,6 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = {
         },
         .slaves         = omap44xx_l4_per_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* l4_wkup */
@@ -646,7 +637,6 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
         },
         .slaves         = omap44xx_l4_wkup_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -677,7 +667,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
         .clkdm_name     = "mpuss_clkdm",
         .slaves         = omap44xx_mpu_private_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -828,7 +817,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
         .masters        = omap44xx_aess_masters,
         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -856,7 +844,6 @@ static struct omap_hwmod omap44xx_bandgap_hwmod = {
         },
         .opt_clks       = bandgap_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -917,7 +904,6 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
         },
         .slaves         = omap44xx_counter_32k_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -1005,7 +991,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
         .masters        = omap44xx_dma_system_masters,
         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -1098,7 +1083,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
         },
         .slaves         = omap44xx_dmic_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -1164,7 +1148,6 @@ static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
                 },
         },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct omap_hwmod omap44xx_dsp_hwmod = {
@@ -1187,7 +1170,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
         .masters        = omap44xx_dsp_masters,
         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -1278,7 +1260,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
         .masters        = omap44xx_dss_masters,
         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -1381,7 +1362,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
         .slaves         = omap44xx_dss_dispc_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -1480,7 +1460,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
         .slaves         = omap44xx_dss_dsi1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* dss_dsi2 */
@@ -1558,7 +1537,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
         .slaves         = omap44xx_dss_dsi2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -1656,7 +1634,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
         .slaves         = omap44xx_dss_hdmi_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -1748,7 +1725,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
         .slaves         = omap44xx_dss_rfbi_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -1817,7 +1793,6 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
         },
         .slaves         = omap44xx_dss_venc_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -1901,7 +1876,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
         .dev_attr       = &gpio_dev_attr,
         .slaves         = omap44xx_gpio1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* gpio2 */
@@ -1957,7 +1931,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
         .dev_attr       = &gpio_dev_attr,
         .slaves         = omap44xx_gpio2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* gpio3 */
@@ -2013,7 +1986,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
         .dev_attr       = &gpio_dev_attr,
         .slaves         = omap44xx_gpio3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* gpio4 */
@@ -2069,7 +2041,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
         .dev_attr       = &gpio_dev_attr,
         .slaves         = omap44xx_gpio4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* gpio5 */
@@ -2125,7 +2096,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
         .dev_attr       = &gpio_dev_attr,
         .slaves         = omap44xx_gpio5_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* gpio6 */
@@ -2181,7 +2151,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
         .dev_attr       = &gpio_dev_attr,
         .slaves         = omap44xx_gpio6_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -2261,7 +2230,6 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
         .masters        = omap44xx_hsi_masters,
         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -2345,7 +2313,6 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
         .slaves         = omap44xx_i2c1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
         .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* i2c2 */
@@ -2402,7 +2369,6 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
         .slaves         = omap44xx_i2c2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
         .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* i2c3 */
@@ -2459,7 +2425,6 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
         .slaves         = omap44xx_i2c3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
         .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* i2c4 */
@@ -2516,7 +2481,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
         .slaves         = omap44xx_i2c4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
         .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -2577,7 +2541,6 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
                 },
         },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* Pseudo hwmod for reset control purpose only */
@@ -2593,7 +2556,6 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
                 },
         },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct omap_hwmod omap44xx_ipu_hwmod = {
@@ -2616,7 +2578,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
         .masters        = omap44xx_ipu_masters,
         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -2706,7 +2667,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
         .masters        = omap44xx_iss_masters,
         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -2781,7 +2741,6 @@ static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
                 },
         },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* Pseudo hwmod for reset control purpose only */
@@ -2797,7 +2756,6 @@ static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
                 },
         },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct omap_hwmod omap44xx_iva_hwmod = {
@@ -2820,7 +2778,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
         .masters        = omap44xx_iva_masters,
         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -2890,7 +2847,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
         },
         .slaves         = omap44xx_kbd_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -2956,7 +2912,6 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
         },
         .slaves         = omap44xx_mailbox_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -3051,7 +3006,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
         },
         .slaves         = omap44xx_mcbsp1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* mcbsp2 */
@@ -3127,7 +3081,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
         },
         .slaves         = omap44xx_mcbsp2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* mcbsp3 */
@@ -3203,7 +3156,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
         },
         .slaves         = omap44xx_mcbsp3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* mcbsp4 */
@@ -3258,7 +3210,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
         },
         .slaves         = omap44xx_mcbsp4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -3353,7 +3304,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
         },
         .slaves         = omap44xx_mcpdm_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -3442,7 +3392,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
         .dev_attr       = &mcspi1_dev_attr,
         .slaves         = omap44xx_mcspi1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* mcspi2 */
@@ -3505,7 +3454,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
         .dev_attr       = &mcspi2_dev_attr,
         .slaves         = omap44xx_mcspi2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* mcspi3 */
@@ -3568,7 +3516,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
         .dev_attr       = &mcspi3_dev_attr,
         .slaves         = omap44xx_mcspi3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* mcspi4 */
@@ -3629,7 +3576,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
         .dev_attr       = &mcspi4_dev_attr,
         .slaves         = omap44xx_mcspi4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -3718,7 +3664,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
         .masters        = omap44xx_mmc1_masters,
         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* mmc2 */
@@ -3779,7 +3724,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
         .masters        = omap44xx_mmc2_masters,
         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* mmc3 */
@@ -3834,7 +3778,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
         },
         .slaves         = omap44xx_mmc3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* mmc4 */
@@ -3890,7 +3833,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
         },
         .slaves         = omap44xx_mmc4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* mmc5 */
@@ -3945,7 +3887,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
         },
         .slaves         = omap44xx_mmc5_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -3987,7 +3928,6 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
         },
         .masters        = omap44xx_mpu_masters,
         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -4063,7 +4003,6 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
         },
         .slaves         = omap44xx_smartreflex_core_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* smartreflex_iva */
@@ -4112,7 +4051,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
         },
         .slaves         = omap44xx_smartreflex_iva_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* smartreflex_mpu */
@@ -4161,7 +4099,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
         },
         .slaves         = omap44xx_smartreflex_mpu_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -4224,7 +4161,6 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = {
         },
         .slaves         = omap44xx_spinlock_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -4310,7 +4246,6 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
         },
         .slaves         = omap44xx_timer1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* timer2 */
@@ -4358,7 +4293,6 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
         },
         .slaves         = omap44xx_timer2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* timer3 */
@@ -4406,7 +4340,6 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
         },
         .slaves         = omap44xx_timer3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* timer4 */
@@ -4454,7 +4387,6 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
         },
         .slaves         = omap44xx_timer4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* timer5 */
@@ -4521,7 +4453,6 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
         },
         .slaves         = omap44xx_timer5_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* timer6 */
@@ -4589,7 +4520,6 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
         },
         .slaves         = omap44xx_timer6_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* timer7 */
@@ -4656,7 +4586,6 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
         },
         .slaves         = omap44xx_timer7_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* timer8 */
@@ -4723,7 +4652,6 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
         },
         .slaves         = omap44xx_timer8_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* timer9 */
@@ -4771,7 +4699,6 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
         },
         .slaves         = omap44xx_timer9_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* timer10 */
@@ -4819,7 +4746,6 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
         },
         .slaves         = omap44xx_timer10_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* timer11 */
@@ -4867,7 +4793,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
         },
         .slaves         = omap44xx_timer11_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -4944,7 +4869,6 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
         },
         .slaves         = omap44xx_uart1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* uart2 */
@@ -4999,7 +4923,6 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
         },
         .slaves         = omap44xx_uart2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* uart3 */
@@ -5055,7 +4978,6 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
         },
         .slaves         = omap44xx_uart3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* uart4 */
@@ -5110,7 +5032,6 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
         },
         .slaves         = omap44xx_uart4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -5195,7 +5116,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
         .masters        = omap44xx_usb_otg_hs_masters,
         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /*
@@ -5266,7 +5186,6 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
         },
         .slaves         = omap44xx_wd_timer2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 /* wd_timer3 */
@@ -5333,7 +5252,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
         },
         .slaves         = omap44xx_wd_timer3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
index ab8b35b780b5..9262a6b47702 100644
--- a/arch/arm/mach-omap2/opp.c
+++ b/arch/arm/mach-omap2/opp.c
@@ -69,7 +69,7 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
                                 opp_def->hwmod_name, i);
                         return -EINVAL;
                 }
-                dev = &oh->od->pdev.dev;
+                dev = &oh->od->pdev->dev;
 
                 r = opp_add(dev, opp_def->freq, opp_def->u_volt);
                 if (r) {
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 472bf22d5e84..25b8c7f43852 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -60,19 +60,19 @@ EXPORT_SYMBOL(omap4_get_dsp_device);
 static int _init_omap_device(char *name, struct device **new_dev)
 {
         struct omap_hwmod *oh;
-        struct omap_device *od;
+        struct platform_device *pdev;
 
         oh = omap_hwmod_lookup(name);
         if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
                  __func__, name))
                 return -ENODEV;
 
-        od = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false);
-        if (WARN(IS_ERR(od), "%s: could not build omap_device for %s\n",
+        pdev = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false);
+        if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n",
                  __func__, name))
                 return -ENODEV;
 
-        *new_dev = &od->pdev.dev;
+        *new_dev = &pdev->dev;
 
         return 0;
 }
@@ -136,8 +136,8 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 
         ret = pwrdm_set_next_pwrst(pwrdm, state);
         if (ret) {
-                printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
-                       pwrdm->name);
+                pr_err("%s: unable to set state of powerdomain: %s\n",
+                       __func__, pwrdm->name);
                 goto err;
         }
 
@@ -161,11 +161,11 @@ err:
 }
 
 /*
- * This API is to be called during init to put the various voltage
+ * This API is to be called during init to set the various voltage
  * domains to the voltage as per the opp table. Typically we boot up
  * at the nominal voltage. So this function finds out the rate of
  * the clock associated with the voltage domain, finds out the correct
- * opp entry and puts the voltage domain to the voltage specifies
+ * opp entry and sets the voltage domain to the voltage specified
  * in the opp entry
  */
 static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
@@ -177,21 +177,20 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
         unsigned long freq, bootup_volt;
 
         if (!vdd_name || !clk_name || !dev) {
-                printk(KERN_ERR "%s: Invalid parameters!\n", __func__);
+                pr_err("%s: invalid parameters\n", __func__);
                 goto exit;
         }
 
         voltdm = omap_voltage_domain_lookup(vdd_name);
         if (IS_ERR(voltdm)) {
-                printk(KERN_ERR "%s: Unable to get vdd pointer for vdd_%s\n",
+                pr_err("%s: unable to get vdd pointer for vdd_%s\n",
                         __func__, vdd_name);
                 goto exit;
         }
 
         clk =  clk_get(NULL, clk_name);
         if (IS_ERR(clk)) {
-                printk(KERN_ERR "%s: unable to get clk %s\n",
-                        __func__, clk_name);
+                pr_err("%s: unable to get clk %s\n", __func__, clk_name);
                 goto exit;
         }
 
@@ -200,14 +199,14 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
 
         opp = opp_find_freq_ceil(dev, &freq);
         if (IS_ERR(opp)) {
-                printk(KERN_ERR "%s: unable to find boot up OPP for vdd_%s\n",
+                pr_err("%s: unable to find boot up OPP for vdd_%s\n",
                         __func__, vdd_name);
                 goto exit;
         }
 
         bootup_volt = opp_get_voltage(opp);
         if (!bootup_volt) {
-                printk(KERN_ERR "%s: unable to find voltage corresponding"
+                pr_err("%s: unable to find voltage corresponding "
                         "to the bootup OPP for vdd_%s\n", __func__, vdd_name);
                 goto exit;
         }
@@ -216,8 +215,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
         return 0;
 
 exit:
-        printk(KERN_ERR "%s: Unable to put vdd_%s to its init voltage\n\n",
-                __func__, vdd_name);
+        pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name);
         return -EINVAL;
 }
 
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index bf089e743ed9..cf0c216132ab 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -53,8 +53,6 @@
 #include "powerdomain.h"
 #include "clockdomain.h"
 
-static int omap2_pm_debug;
-
 #ifdef CONFIG_SUSPEND
 static suspend_state_t suspend_state = PM_SUSPEND_ON;
 static inline bool is_suspending(void)
@@ -96,7 +94,6 @@ static int omap2_fclks_active(void)
 static void omap2_enter_full_retention(void)
 {
         u32 l;
-        struct timespec ts_preidle, ts_postidle, ts_idle;
 
         /* There is 1 reference hold for all children of the oscillator
          * clock, the following will remove it. If no one else uses the
@@ -124,10 +121,6 @@ static void omap2_enter_full_retention(void)
 
         omap2_gpio_prepare_for_idle(0);
 
-        if (omap2_pm_debug) {
-                getnstimeofday(&ts_preidle);
-        }
-
         /* One last check for pending IRQs to avoid extra latency due
          * to sleeping unnecessarily. */
         if (omap_irq_pending())
@@ -155,13 +148,6 @@ static void omap2_enter_full_retention(void)
                 console_unlock();
 
 no_sleep:
-        if (omap2_pm_debug) {
-                unsigned long long tmp;
-
-                getnstimeofday(&ts_postidle);
-                ts_idle = timespec_sub(ts_postidle, ts_preidle);
-                tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
-        }
         omap2_gpio_resume_after_idle();
 
         clk_enable(osc_ck);
@@ -219,7 +205,6 @@ static int omap2_allow_mpu_retention(void)
 static void omap2_enter_mpu_retention(void)
 {
         int only_idle = 0;
-        struct timespec ts_preidle, ts_postidle, ts_idle;
 
         /* Putting MPU into the WFI state while a transfer is active
          * seems to cause the I2C block to timeout. Why? Good question. */
@@ -246,19 +231,7 @@ static void omap2_enter_mpu_retention(void)
                 only_idle = 1;
         }
 
-        if (omap2_pm_debug) {
-                getnstimeofday(&ts_preidle);
-        }
-
         omap2_sram_idle();
-
-        if (omap2_pm_debug) {
-                unsigned long long tmp;
-
-                getnstimeofday(&ts_postidle);
-                ts_idle = timespec_sub(ts_postidle, ts_preidle);
-                tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
-        }
 }
 
 static int omap2_can_sleep(void)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7255d9bce868..c8cbd00a41af 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -55,7 +55,7 @@
 static suspend_state_t suspend_state = PM_SUSPEND_ON;
 static inline bool is_suspending(void)
 {
-        return (suspend_state != PM_SUSPEND_ON);
+        return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
 }
 #else
 static inline bool is_suspending(void)
diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c
index 171fccd208c7..f97afff68d6d 100644
--- a/arch/arm/mach-omap2/powerdomain-common.c
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -1,9 +1,8 @@
 /*
- *  linux/arch/arm/mach-omap2/powerdomain-common.c
- *  Contains common powerdomain framework functions
+ * Common powerdomain framework functions
  *
- *  Copyright (C) 2010 Texas Instruments, Inc.
- *  Copyright (C) 2010 Nokia Corporation
+ * Copyright (C) 2010-2011 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
  *
  * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
  *
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index ef71fdd40fc4..896cb4c5eb1a 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -1,7 +1,7 @@
 /*
  * OMAP powerdomain control
  *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
  * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Written by Paul Walmsley
@@ -81,9 +81,6 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
         if (!pwrdm || !pwrdm->name)
                 return -EINVAL;
 
-        if (!omap_chip_is(pwrdm->omap_chip))
-                return -EINVAL;
-
         if (cpu_is_omap44xx() &&
             pwrdm->prcm_partition == OMAP4430_INVALID_PRCM_PARTITION) {
                 pr_err("powerdomain: %s: missing OMAP4 PRCM partition ID\n",
@@ -194,36 +191,76 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
 /* Public functions */
 
 /**
- * pwrdm_init - set up the powerdomain layer
- * @pwrdms: array of struct powerdomain pointers to register
- * @custom_funcs: func pointers for arch specific implementations
+ * pwrdm_register_platform_funcs - register powerdomain implementation fns
+ * @po: func pointers for arch specific implementations
+ *
+ * Register the list of function pointers used to implement the
+ * powerdomain functions on different OMAP SoCs.  Should be called
+ * before any other pwrdm_register*() function.  Returns -EINVAL if
+ * @po is null, -EEXIST if platform functions have already been
+ * registered, or 0 upon success.
+ */
+int pwrdm_register_platform_funcs(struct pwrdm_ops *po)
+{
+        if (!po)
+                return -EINVAL;
+
+        if (arch_pwrdm)
+                return -EEXIST;
+
+        arch_pwrdm = po;
+
+        return 0;
+}
+
+/**
+ * pwrdm_register_pwrdms - register SoC powerdomains
+ * @ps: pointer to an array of struct powerdomain to register
  *
- * Loop through the array of powerdomains @pwrdms, registering all
- * that are available on the current CPU.  Also, program all
- * powerdomain target state as ON; this is to prevent domains from
- * hitting low power states (if bootloader has target states set to
- * something other than ON) and potentially even losing context while
- * PM is not fully initialized.  The PM late init code can then program
- * the desired target state for all the power domains.  No return
- * value.
+ * Register the powerdomains available on a particular OMAP SoC.  Must
+ * be called after pwrdm_register_platform_funcs().  May be called
+ * multiple times.  Returns -EACCES if called before
+ * pwrdm_register_platform_funcs(); -EINVAL if the argument @ps is
+ * null; or 0 upon success.
  */
-void pwrdm_init(struct powerdomain **pwrdms, struct pwrdm_ops *custom_funcs)
+int pwrdm_register_pwrdms(struct powerdomain **ps)
 {
         struct powerdomain **p = NULL;
-        struct powerdomain *temp_p;
 
-        if (!custom_funcs)
-                WARN(1, "powerdomain: No custom pwrdm functions registered\n");
-        else
-                arch_pwrdm = custom_funcs;
+        if (!arch_pwrdm)
+                return -EEXIST;
 
-        if (pwrdms) {
-                for (p = pwrdms; *p; p++)
-                        _pwrdm_register(*p);
-        }
+        if (!ps)
+                return -EINVAL;
+
+        for (p = ps; *p; p++)
+                _pwrdm_register(*p);
+
+        return 0;
+}
+
+/**
+ * pwrdm_complete_init - set up the powerdomain layer
+ *
+ * Do whatever is necessary to initialize registered powerdomains and
+ * powerdomain code.  Currently, this programs the next power state
+ * for each powerdomain to ON.  This prevents powerdomains from
+ * unexpectedly losing context or entering high wakeup latency modes
+ * with non-power-management-enabled kernels.  Must be called after
+ * pwrdm_register_pwrdms().  Returns -EACCES if called before
+ * pwrdm_register_pwrdms(), or 0 upon success.
+ */
+int pwrdm_complete_init(void)
+{
+        struct powerdomain *temp_p;
+
+        if (list_empty(&pwrdm_list))
+                return -EACCES;
 
         list_for_each_entry(temp_p, &pwrdm_list, node)
                 pwrdm_set_next_pwrst(temp_p, PWRDM_POWER_ON);
+
+        return 0;
 }
 
 /**
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index d23d979b9c34..8febd84e5e31 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -78,7 +78,6 @@ struct powerdomain;
 /**
  * struct powerdomain - OMAP powerdomain
  * @name: Powerdomain name
- * @omap_chip: represents the OMAP chip types containing this pwrdm
  * @prcm_offs: the address offset from CM_BASE/PRM_BASE
  * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
  * @pwrsts: Possible powerdomain power states
@@ -98,7 +97,6 @@ struct powerdomain;
  */
 struct powerdomain {
         const char *name;
-        const struct omap_chip_id omap_chip;
         const s16 prcm_offs;
         const u8 pwrsts;
         const u8 pwrsts_logic_ret;
@@ -162,7 +160,9 @@ struct pwrdm_ops {
         int     (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
 };
 
-void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs);
+int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
+int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
+int pwrdm_complete_init(void);
 
 struct powerdomain *pwrdm_lookup(const char *name);
 
@@ -210,7 +210,8 @@ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
 u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
 bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
 
-extern void omap2xxx_powerdomains_init(void);
+extern void omap242x_powerdomains_init(void);
+extern void omap243x_powerdomains_init(void);
 extern void omap3xxx_powerdomains_init(void);
 extern void omap44xx_powerdomains_init(void);
 
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
index 4210c3399769..bf30483d5cb0 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
@@ -1,7 +1,7 @@
 /*
  * OMAP2/3 common powerdomain definitions
  *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
  * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Paul Walmsley, Jouni Högander
@@ -12,20 +12,6 @@
  */
 
 /*
- * To Do List
- * -> Move the Sleep/Wakeup dependencies from Power Domain framework to
- *    Clock Domain Framework
- */
-
-/*
- * This file contains all of the powerdomains that have some element
- * of software control for the OMAP24xx and OMAP34xx chips.
- *
- * This is not an exhaustive listing of powerdomains on the chips; only
- * powerdomains that can be controlled in software.
- */
-
-/*
  * The names for the DSP/IVA2 powerdomains are confusing.
  *
  * Most OMAP chips have an on-board DSP.
@@ -59,8 +45,6 @@
 struct powerdomain gfx_omap2_pwrdm = {
         .name             = "gfx_pwrdm",
         .prcm_offs        = GFX_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
-                                           CHIP_IS_OMAP3430ES1),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
@@ -75,6 +59,5 @@ struct powerdomain gfx_omap2_pwrdm = {
 struct powerdomain wkup_omap2_pwrdm = {
         .name           = "wkup_pwrdm",
         .prcm_offs      = WKUP_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
         .pwrsts         = PWRSTS_ON,
 };
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index cc389fb2005d..bb4394e3b621 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -1,7 +1,7 @@
 /*
  * OMAP2XXX powerdomain definitions
  *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
  * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Paul Walmsley, Jouni Högander
@@ -28,7 +28,6 @@
 static struct powerdomain dsp_pwrdm = {
         .name             = "dsp_pwrdm",
         .prcm_offs        = OMAP24XX_DSP_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
@@ -43,7 +42,6 @@ static struct powerdomain dsp_pwrdm = {
 static struct powerdomain mpu_24xx_pwrdm = {
         .name             = "mpu_pwrdm",
         .prcm_offs        = MPU_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 1,
@@ -58,7 +56,6 @@ static struct powerdomain mpu_24xx_pwrdm = {
 static struct powerdomain core_24xx_pwrdm = {
         .name             = "core_pwrdm",
         .prcm_offs        = CORE_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .banks            = 3,
         .pwrsts_mem_ret   = {
@@ -78,14 +75,11 @@ static struct powerdomain core_24xx_pwrdm = {
  * 2430-specific powerdomains
  */
 
-#ifdef CONFIG_SOC_OMAP2430
-
 /* XXX 2430 KILLDOMAINWKUP bit?  No current users apparently */
 
 static struct powerdomain mdm_pwrdm = {
         .name             = "mdm_pwrdm",
         .prcm_offs        = OMAP2430_MDM_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
@@ -97,27 +91,41 @@ static struct powerdomain mdm_pwrdm = {
         },
 };
 
-#endif     /* CONFIG_SOC_OMAP2430 */
-
-/* As powerdomains are added or removed above, this list must also be changed */
-static struct powerdomain *powerdomains_omap2xxx[] __initdata = {
+/*
+ *
+ */
 
+static struct powerdomain *powerdomains_omap24xx[] __initdata = {
         &wkup_omap2_pwrdm,
         &gfx_omap2_pwrdm,
-
-#ifdef CONFIG_ARCH_OMAP2
         &dsp_pwrdm,
         &mpu_24xx_pwrdm,
         &core_24xx_pwrdm,
-#endif
+        NULL
+};
 
-#ifdef CONFIG_SOC_OMAP2430
+static struct powerdomain *powerdomains_omap2430[] __initdata = {
         &mdm_pwrdm,
-#endif
         NULL
 };
 
-void __init omap2xxx_powerdomains_init(void)
+void __init omap242x_powerdomains_init(void)
+{
+        if (!cpu_is_omap2420())
+                return;
+
+        pwrdm_register_platform_funcs(&omap2_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_omap24xx);
+        pwrdm_complete_init();
+}
+
+void __init omap243x_powerdomains_init(void)
 {
-        pwrdm_init(powerdomains_omap2xxx, &omap2_pwrdm_operations);
+        if (!cpu_is_omap2430())
+                return;
+
+        pwrdm_register_platform_funcs(&omap2_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_omap24xx);
+        pwrdm_register_pwrdms(powerdomains_omap2430);
+        pwrdm_complete_init();
 }
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index 469a920a74dc..e4f3a7d6ecfc 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -1,7 +1,7 @@
 /*
  * OMAP3 powerdomain definitions
  *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
  * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Paul Walmsley, Jouni Högander
@@ -14,6 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
+#include <plat/cpu.h>
+
 #include "powerdomain.h"
 #include "powerdomains2xxx_3xxx_data.h"
 
@@ -27,8 +29,6 @@
  * 34XX-specific powerdomains, dependencies
  */
 
-#ifdef CONFIG_ARCH_OMAP3
-
 /*
  * Powerdomains
  */
@@ -36,7 +36,6 @@
 static struct powerdomain iva2_pwrdm = {
         .name             = "iva2_pwrdm",
         .prcm_offs        = OMAP3430_IVA2_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 4,
@@ -57,7 +56,6 @@ static struct powerdomain iva2_pwrdm = {
 static struct powerdomain mpu_3xxx_pwrdm = {
         .name             = "mpu_pwrdm",
         .prcm_offs        = MPU_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .flags            = PWRDM_HAS_MPU_QUIRK,
@@ -83,10 +81,6 @@ static struct powerdomain mpu_3xxx_pwrdm = {
 static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
         .name             = "core_pwrdm",
         .prcm_offs        = CORE_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
-                                           CHIP_IS_OMAP3430ES2 |
-                                           CHIP_IS_OMAP3430ES3_0 |
-                                           CHIP_IS_OMAP3630ES1),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 2,
@@ -103,8 +97,6 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
 static struct powerdomain core_3xxx_es3_1_pwrdm = {
         .name             = "core_pwrdm",
         .prcm_offs        = CORE_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 |
-                                          CHIP_GE_OMAP3630ES1_1),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         /*
@@ -125,7 +117,6 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = {
 
 static struct powerdomain dss_pwrdm = {
         .name             = "dss_pwrdm",
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .prcm_offs        = OMAP3430_DSS_MOD,
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_RET,
@@ -146,7 +137,6 @@ static struct powerdomain dss_pwrdm = {
 static struct powerdomain sgx_pwrdm = {
         .name             = "sgx_pwrdm",
         .prcm_offs        = OMAP3430ES2_SGX_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
         /* XXX This is accurate for 3430 SGX, but what about GFX? */
         .pwrsts           = PWRSTS_OFF_ON,
         .pwrsts_logic_ret = PWRSTS_RET,
@@ -161,7 +151,6 @@ static struct powerdomain sgx_pwrdm = {
 
 static struct powerdomain cam_pwrdm = {
         .name             = "cam_pwrdm",
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .prcm_offs        = OMAP3430_CAM_MOD,
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_RET,
@@ -177,7 +166,6 @@ static struct powerdomain cam_pwrdm = {
 static struct powerdomain per_pwrdm = {
         .name             = "per_pwrdm",
         .prcm_offs        = OMAP3430_PER_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 1,
@@ -192,13 +180,11 @@ static struct powerdomain per_pwrdm = {
 static struct powerdomain emu_pwrdm = {
         .name           = "emu_pwrdm",
         .prcm_offs      = OMAP3430_EMU_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 static struct powerdomain neon_pwrdm = {
         .name             = "neon_pwrdm",
         .prcm_offs        = OMAP3430_NEON_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_RET,
 };
@@ -206,7 +192,6 @@ static struct powerdomain neon_pwrdm = {
 static struct powerdomain usbhost_pwrdm = {
         .name             = "usbhost_pwrdm",
         .prcm_offs        = OMAP3430ES2_USBHOST_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_RET,
         /*
@@ -228,60 +213,92 @@ static struct powerdomain usbhost_pwrdm = {
 static struct powerdomain dpll1_pwrdm = {
         .name           = "dpll1_pwrdm",
         .prcm_offs      = MPU_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 static struct powerdomain dpll2_pwrdm = {
         .name           = "dpll2_pwrdm",
         .prcm_offs      = OMAP3430_IVA2_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 static struct powerdomain dpll3_pwrdm = {
         .name           = "dpll3_pwrdm",
         .prcm_offs      = PLL_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 static struct powerdomain dpll4_pwrdm = {
         .name           = "dpll4_pwrdm",
         .prcm_offs      = PLL_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 static struct powerdomain dpll5_pwrdm = {
         .name           = "dpll5_pwrdm",
         .prcm_offs      = PLL_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 };
 
 /* As powerdomains are added or removed above, this list must also be changed */
-static struct powerdomain *powerdomains_omap3xxx[] __initdata = {
-
+static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
         &wkup_omap2_pwrdm,
-        &gfx_omap2_pwrdm,
         &iva2_pwrdm,
         &mpu_3xxx_pwrdm,
         &neon_pwrdm,
-        &core_3xxx_pre_es3_1_pwrdm,
-        &core_3xxx_es3_1_pwrdm,
         &cam_pwrdm,
         &dss_pwrdm,
         &per_pwrdm,
         &emu_pwrdm,
-        &sgx_pwrdm,
-        &usbhost_pwrdm,
         &dpll1_pwrdm,
         &dpll2_pwrdm,
         &dpll3_pwrdm,
         &dpll4_pwrdm,
+        NULL
+};
+
+static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
+        &gfx_omap2_pwrdm,
+        &core_3xxx_pre_es3_1_pwrdm,
+        NULL
+};
+
+/* also includes 3630ES1.0 */
+static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
+        &core_3xxx_pre_es3_1_pwrdm,
+        &sgx_pwrdm,
+        &usbhost_pwrdm,
         &dpll5_pwrdm,
-#endif
         NULL
 };
 
+/* also includes 3630ES1.1+ */
+static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
+        &core_3xxx_es3_1_pwrdm,
+        &sgx_pwrdm,
+        &usbhost_pwrdm,
+        &dpll5_pwrdm,
+        NULL
+};
 
 void __init omap3xxx_powerdomains_init(void)
 {
-        pwrdm_init(powerdomains_omap3xxx, &omap3_pwrdm_operations);
+        unsigned int rev;
+
+        if (!cpu_is_omap34xx())
+                return;
+
+        pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_omap3430_common);
+
+        rev = omap_rev();
+
+        if (rev == OMAP3430_REV_ES1_0)
+                pwrdm_register_pwrdms(powerdomains_omap3430es1);
+        else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
+                 rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0)
+                pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
+        else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 ||
+                 rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1 ||
+                 rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2)
+                pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
+        else
+                WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
+
+        pwrdm_complete_init();
 }
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index 247e79495115..cbce0c9069cd 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -35,7 +35,6 @@ static struct powerdomain core_44xx_pwrdm = {
         .name             = "core_pwrdm",
         .prcm_offs        = OMAP4430_PRM_CORE_INST,
         .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 5,
@@ -61,7 +60,6 @@ static struct powerdomain gfx_44xx_pwrdm = {
         .name             = "gfx_pwrdm",
         .prcm_offs        = OMAP4430_PRM_GFX_INST,
         .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_ON,
         .banks            = 1,
         .pwrsts_mem_ret = {
@@ -78,7 +76,6 @@ static struct powerdomain abe_44xx_pwrdm = {
         .name             = "abe_pwrdm",
         .prcm_offs        = OMAP4430_PRM_ABE_INST,
         .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF,
         .banks            = 2,
@@ -98,7 +95,6 @@ static struct powerdomain dss_44xx_pwrdm = {
         .name             = "dss_pwrdm",
         .prcm_offs        = OMAP4430_PRM_DSS_INST,
         .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF,
         .banks            = 1,
@@ -116,7 +112,6 @@ static struct powerdomain tesla_44xx_pwrdm = {
         .name             = "tesla_pwrdm",
         .prcm_offs        = OMAP4430_PRM_TESLA_INST,
         .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 3,
@@ -138,7 +133,6 @@ static struct powerdomain wkup_44xx_pwrdm = {
         .name             = "wkup_pwrdm",
         .prcm_offs        = OMAP4430_PRM_WKUP_INST,
         .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_ON,
         .banks            = 1,
         .pwrsts_mem_ret = {
@@ -154,7 +148,6 @@ static struct powerdomain cpu0_44xx_pwrdm = {
         .name             = "cpu0_pwrdm",
         .prcm_offs        = OMAP4430_PRCM_MPU_CPU0_INST,
         .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 1,
@@ -171,7 +164,6 @@ static struct powerdomain cpu1_44xx_pwrdm = {
         .name             = "cpu1_pwrdm",
         .prcm_offs        = OMAP4430_PRCM_MPU_CPU1_INST,
         .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 1,
@@ -188,7 +180,6 @@ static struct powerdomain emu_44xx_pwrdm = {
         .name             = "emu_pwrdm",
         .prcm_offs        = OMAP4430_PRM_EMU_INST,
         .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_ON,
         .banks            = 1,
         .pwrsts_mem_ret = {
@@ -204,7 +195,6 @@ static struct powerdomain mpu_44xx_pwrdm = {
         .name             = "mpu_pwrdm",
         .prcm_offs        = OMAP4430_PRM_MPU_INST,
         .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 3,
@@ -225,7 +215,6 @@ static struct powerdomain ivahd_44xx_pwrdm = {
         .name             = "ivahd_pwrdm",
         .prcm_offs        = OMAP4430_PRM_IVAHD_INST,
         .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF,
         .banks            = 4,
@@ -249,7 +238,6 @@ static struct powerdomain cam_44xx_pwrdm = {
         .name             = "cam_pwrdm",
         .prcm_offs        = OMAP4430_PRM_CAM_INST,
         .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_ON,
         .banks            = 1,
         .pwrsts_mem_ret = {
@@ -266,7 +254,6 @@ static struct powerdomain l3init_44xx_pwrdm = {
         .name             = "l3init_pwrdm",
         .prcm_offs        = OMAP4430_PRM_L3INIT_INST,
         .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 1,
@@ -284,7 +271,6 @@ static struct powerdomain l4per_44xx_pwrdm = {
         .name             = "l4per_pwrdm",
         .prcm_offs        = OMAP4430_PRM_L4PER_INST,
         .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 2,
@@ -307,7 +293,6 @@ static struct powerdomain always_on_core_44xx_pwrdm = {
         .name             = "always_on_core_pwrdm",
         .prcm_offs        = OMAP4430_PRM_ALWAYS_ON_INST,
         .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_ON,
 };
 
@@ -316,7 +301,6 @@ static struct powerdomain cefuse_44xx_pwrdm = {
         .name             = "cefuse_pwrdm",
         .prcm_offs        = OMAP4430_PRM_CEFUSE_INST,
         .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_ON,
         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -352,5 +336,7 @@ static struct powerdomain *powerdomains_omap44xx[] __initdata = {
 
 void __init omap44xx_powerdomains_init(void)
 {
-        pwrdm_init(powerdomains_omap44xx, &omap4_pwrdm_operations);
+        pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_omap44xx);
+        pwrdm_complete_init();
 }
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 466fc722fa0f..3d1c1d393f8f 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -711,7 +711,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
 {
         struct omap_uart_state *uart;
         struct omap_hwmod *oh;
-        struct omap_device *od;
+        struct platform_device *pdev;
         void *pdata = NULL;
         u32 pdata_size = 0;
         char *name;
@@ -799,20 +799,20 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
         if (WARN_ON(!oh))
                 return;
 
-        od = omap_device_build(name, uart->num, oh, pdata, pdata_size,
+        pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
                                omap_uart_latency,
                                ARRAY_SIZE(omap_uart_latency), false);
-        WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n",
+        WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
              name, oh->name);
 
-        omap_device_disable_idle_on_suspend(od);
+        omap_device_disable_idle_on_suspend(pdev);
         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
 
         uart->irq = oh->mpu_irqs[0].irq;
         uart->regshift = 2;
         uart->mapbase = oh->slaves[0]->addr->pa_start;
         uart->membase = omap_hwmod_get_mpu_rt_va(oh);
-        uart->pdev = &od->pdev;
+        uart->pdev = pdev;
 
         oh->dev_attr = uart;
 
@@ -846,8 +846,8 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
 
         if ((cpu_is_omap34xx() && uart->padconf) ||
             (uart->wk_en && uart->wk_mask)) {
-                device_init_wakeup(&od->pdev.dev, true);
-                DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout);
+                device_init_wakeup(&pdev->dev, true);
+                DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout);
         }
 
         /* Enable the MDR1 errata for OMAP3 */
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index 10d3c5ee8018..624264d8e1a5 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -80,7 +80,7 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
 static int sr_dev_init(struct omap_hwmod *oh, void *user)
 {
         struct omap_sr_data *sr_data;
-        struct omap_device *od;
+        struct platform_device *pdev;
         struct omap_volt_data *volt_data;
         char *name = "smartreflex";
         static int i;
@@ -120,10 +120,10 @@ static int sr_dev_init(struct omap_hwmod *oh, void *user)
 
         sr_data->enable_on_init = sr_enable_on_init;
 
-        od = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data),
+        pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data),
                                omap_sr_latency,
                                ARRAY_SIZE(omap_sr_latency), 0);
-        if (IS_ERR(od))
+        if (IS_ERR(pdev))
                 pr_warning("%s: Could not build omap_device for %s: %s.\n\n",
                         __func__, name, oh->name);
 exit:
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 19cf5bf99f1b..8c8300951f46 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -336,7 +336,7 @@ static void __init d2net_init(void)
 
 #ifdef CONFIG_MACH_D2NET
 MACHINE_START(D2NET, "LaCie d2 Network")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = d2net_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
@@ -348,7 +348,7 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_BIGDISK
 MACHINE_START(BIGDISK, "LaCie Big Disk Network")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = d2net_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index a3e3e9e5e328..88432aba972c 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -359,7 +359,7 @@ static void __init db88f5281_init(void)
 
 MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
         /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = db88f5281_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index c105556a0ee1..9e5c1663fc4f 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -730,7 +730,7 @@ static void __init dns323_init(void)
 /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
 MACHINE_START(DNS323, "D-Link DNS-323")
         /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = dns323_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index b67cff0d4cfe..70a4e9265f06 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -251,7 +251,7 @@ static void __init edmini_v2_init(void)
 /* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
 MACHINE_START(EDMINI_V2, "LaCie Ethernet Disk mini V2")
         /* Maintainer: Christopher Moore <moore@free.fr> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = edmini_v2_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 00381249d766..9115511dc035 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -380,7 +380,7 @@ static void __init kurobox_pro_init(void)
 #ifdef CONFIG_MACH_KUROBOX_PRO
 MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
         /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = kurobox_pro_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
@@ -393,7 +393,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_LINKSTATION_PRO
 MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
         /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = kurobox_pro_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 5065803ca82a..9503fff404e3 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -318,7 +318,7 @@ static void __init lschl_init(void)
 
 MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)")
         /* Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = lschl_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 8503d0a42d41..ed6d772f4a24 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -265,7 +265,7 @@ static void __init ls_hgl_init(void)
 
 MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL")
         /* Maintainer: Zhu Qingsen <zhuqs@cn.fujistu.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = ls_hgl_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 9c82723c05c0..743f7f1db181 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -267,7 +267,7 @@ static void __init lsmini_init(void)
 #ifdef CONFIG_MACH_LINKSTATION_MINI
 MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini")
         /* Maintainer: Alexey Kopytko <alexey@kopytko.ru> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = lsmini_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index ef3bb8e9a4c2..6020e26b1c71 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -261,7 +261,7 @@ static void __init mss2_init(void)
 
 MACHINE_START(MSS2, "Maxtor Shared Storage II")
         /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = mss2_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index 63ff10c3c464..b3356ada64b9 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -229,7 +229,7 @@ static void __init mv2120_init(void)
 /* Warning: HP uses a wrong mach-type (=526) in their bootloader */
 MACHINE_START(MV2120, "HP Media Vault mv2120")
         /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = mv2120_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index e43b39cc7fe9..6197c79a2ecb 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -419,7 +419,7 @@ static void __init net2big_init(void)
 
 /* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
 MACHINE_START(NET2BIG, "LaCie 2Big Network")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = net2big_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 291d22bf44c9..8c876664f494 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -169,7 +169,7 @@ subsys_initcall(rd88f5181l_fxo_pci_init);
 
 MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
         /* Maintainer: Nicolas Pitre <nico@marvell.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = rd88f5181l_fxo_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index 3f02362e1632..994644f59d8d 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -181,7 +181,7 @@ subsys_initcall(rd88f5181l_ge_pci_init);
 
 MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
         /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = rd88f5181l_ge_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 27fd38e658bd..1903d25ecae9 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -306,7 +306,7 @@ static void __init rd88f5182_init(void)
 
 MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
         /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = rd88f5182_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index ad2eba9286ad..e06fdae77f0a 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -122,7 +122,7 @@ subsys_initcall(rd88f6183ap_ge_pci_init);
 
 MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design")
         /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = rd88f6183ap_ge_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index a34e4fac72b0..306183273eb9 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -358,7 +358,7 @@ static void __init tsp2_init(void)
 
 MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live")
         /* Maintainer:  Sylver Bruneau <sylver.bruneau@googlemail.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = tsp2_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index c9831614e355..3dbcd5ed77ef 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -323,7 +323,7 @@ static void __init qnap_ts209_init(void)
 
 MACHINE_START(TS209, "QNAP TS-109/TS-209")
         /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = qnap_ts209_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index cc33b2222bad..23c9e2e5e550 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -312,7 +312,7 @@ static void __init qnap_ts409_init(void)
 
 MACHINE_START(TS409, "QNAP TS-409")
         /* Maintainer:  Sylver Bruneau <sylver.bruneau@gmail.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = qnap_ts409_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index 6b7b54116f30..6c75cd35c4c8 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -621,7 +621,7 @@ static void __init ts78xx_init(void)
 
 MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
         /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = ts78xx_init,
         .map_io         = ts78xx_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 2653595f901c..1c63a76f3ca3 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -173,7 +173,7 @@ subsys_initcall(wnr854t_pci_init);
 
 MACHINE_START(WNR854T, "Netgear WNR854T")
         /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = wnr854t_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index 251ef1543e53..4fd9f18c9d5d 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -261,7 +261,7 @@ subsys_initcall(wrt350n_v2_pci_init);
 
 MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
         /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_machine   = wrt350n_v2_init,
         .map_io         = orion5x_map_io,
         .init_early     = orion5x_init_early,
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
index 63399755f199..cdb95e726f5c 100644
--- a/arch/arm/mach-pnx4008/core.c
+++ b/arch/arm/mach-pnx4008/core.c
@@ -264,7 +264,7 @@ extern struct sys_timer pnx4008_timer;
 
 MACHINE_START(PNX4008, "Philips PNX4008")
         /* Maintainer: MontaVista Software Inc. */
-        .boot_params            = 0x80000100,
+        .atag_offset            = 0x100,
         .map_io                 = pnx4008_map_io,
         .init_irq               = pnx4008_init_irq,
         .init_machine           = pnx4008_init,
diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c
index 615a4e75ceab..aebad7e565cf 100644
--- a/arch/arm/mach-prima2/clock.c
+++ b/arch/arm/mach-prima2/clock.c
@@ -350,10 +350,10 @@ static struct clk_lookup onchip_clks[] = {
                 .clk = &clk_mem,
         }, {
                 .dev_id = "sys",
-                        .clk = &clk_sys,
+                .clk = &clk_sys,
         }, {
                 .dev_id = "io",
-                        .clk = &clk_io,
+                .clk = &clk_io,
         },
 };
 
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/prima2.c
index f57124bdd143..a3918d9994af 100644
--- a/arch/arm/mach-prima2/prima2.c
+++ b/arch/arm/mach-prima2/prima2.c
@@ -1,5 +1,5 @@
 /*
- * Defines machines for CSR SiRFprimaII 
+ * Defines machines for CSR SiRFprimaII
  *
  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
  *
@@ -31,7 +31,7 @@ static const char *prima2cb_dt_match[] __initdata = {
 
 MACHINE_START(PRIMA2_EVB, "prima2cb")
         /* Maintainer: Barry Song <baohua.song@csr.com> */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .init_early     = sirfsoc_of_clk_init,
         .map_io         = sirfsoc_map_lluart,
         .init_irq       = sirfsoc_of_irq_init,
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c
index ed7ec48d11da..26ab6fee5619 100644
--- a/arch/arm/mach-prima2/timer.c
+++ b/arch/arm/mach-prima2/timer.c
@@ -133,14 +133,14 @@ static struct irqaction sirfsoc_timer_irq = {
 /* Overwrite weak default sched_clock with more precise one */
 unsigned long long notrace sched_clock(void)
 {
-        static int is_mapped = 0;
+        static int is_mapped;
 
         /*
          * sched_clock is called earlier than .init of sys_timer
          * if we map timer memory in .init of sys_timer, system
          * will panic due to illegal memory access
          */
-        if(!is_mapped) {
+        if (!is_mapped) {
                 sirfsoc_of_timer_map();
                 is_mapped = 1;
         }
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index ef3e8b1e06c1..7765d677adbb 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -828,5 +828,5 @@ MACHINE_START(BALLOON3, "Balloon3")
         .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = balloon3_init,
-        .boot_params    = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset    = 0x100,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c
index 648b0ab2bf77..4efc16d39c79 100644
--- a/arch/arm/mach-pxa/capc7117.c
+++ b/arch/arm/mach-pxa/capc7117.c
@@ -148,7 +148,7 @@ static void __init capc7117_init(void)
 
 MACHINE_START(CAPC7117,
               "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM")
-        .boot_params = 0xa0000100,
+        .atag_offset = 0x100,
         .map_io = pxa3xx_map_io,
         .init_irq = pxa3xx_init_irq,
         .handle_irq = pxa3xx_handle_irq,
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index 13cf518bbbf8..349896c53abd 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -513,7 +513,7 @@ static void __init cmx2xx_map_io(void)
 #endif
 
 MACHINE_START(ARMCORE, "Compulab CM-X2XX")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = cmx2xx_map_io,
         .nr_irqs        = CMX2XX_NR_IRQS,
         .init_irq       = cmx2xx_init_irq,
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index b6a51340270b..9ac0225cd51b 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -852,7 +852,7 @@ static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags,
 }
 
 MACHINE_START(CM_X300, "CM-X300 module")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .handle_irq     = pxa3xx_handle_irq,
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c
index 870920934ecf..7db66465716f 100644
--- a/arch/arm/mach-pxa/colibri-pxa270.c
+++ b/arch/arm/mach-pxa/colibri-pxa270.c
@@ -306,7 +306,7 @@ static void __init colibri_pxa270_income_init(void)
 }
 
 MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
-        .boot_params    = COLIBRI_SDRAM_BASE + 0x100,
+        .atag_offset    = 0x100,
         .init_machine   = colibri_pxa270_init,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
@@ -315,7 +315,7 @@ MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
 MACHINE_END
 
 MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .init_machine   = colibri_pxa270_income_init,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index 60a6781e7a8e..c825e8bf2db1 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -183,7 +183,7 @@ void __init colibri_pxa300_init(void)
 }
 
 MACHINE_START(COLIBRI300, "Toradex Colibri PXA300")
-        .boot_params    = COLIBRI_SDRAM_BASE + 0x100,
+        .atag_offset    = 0x100,
         .init_machine   = colibri_pxa300_init,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index d2c6631915d4..692e1ffc5586 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -253,7 +253,7 @@ void __init colibri_pxa320_init(void)
 }
 
 MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
-        .boot_params    = COLIBRI_SDRAM_BASE + 0x100,
+        .atag_offset    = 0x100,
         .init_machine   = colibri_pxa320_init,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
index fe812eafb1f1..5e2cf39e9e4c 100644
--- a/arch/arm/mach-pxa/csb726.c
+++ b/arch/arm/mach-pxa/csb726.c
@@ -272,7 +272,7 @@ static void __init csb726_init(void)
 }
 
 MACHINE_START(CSB726, "Cogent CSB726")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .handle_irq       = pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 2e37ea52b372..94acc0b01dd6 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -1299,7 +1299,7 @@ static void __init em_x270_init(void)
 }
 
 MACHINE_START(EM_X270, "Compulab EM-X270")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .handle_irq     = pxa27x_handle_irq,
@@ -1308,7 +1308,7 @@ MACHINE_START(EM_X270, "Compulab EM-X270")
 MACHINE_END
 
 MACHINE_START(EXEDA, "Compulab eXeda")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .handle_irq     = pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index b4599ec9d619..e823c54057f3 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -189,7 +189,7 @@ static void __init e330_init(void)
 
 MACHINE_START(E330, "Toshiba e330")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
@@ -239,7 +239,7 @@ static void __init e350_init(void)
 
 MACHINE_START(E350, "Toshiba e350")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
@@ -362,7 +362,7 @@ static void __init e400_init(void)
 
 MACHINE_START(E400, "Toshiba e400")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
@@ -551,7 +551,7 @@ static void __init e740_init(void)
 
 MACHINE_START(E740, "Toshiba e740")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
@@ -743,7 +743,7 @@ static void __init e750_init(void)
 
 MACHINE_START(E750, "Toshiba e750")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
@@ -948,7 +948,7 @@ static void __init e800_init(void)
 
 MACHINE_START(E800, "Toshiba e800")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index b73eadb9f5dc..8308eee5a924 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -797,7 +797,7 @@ static void __init a780_init(void)
 }
 
 MACHINE_START(EZX_A780, "Motorola EZX A780")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
@@ -863,7 +863,7 @@ static void __init e680_init(void)
 }
 
 MACHINE_START(EZX_E680, "Motorola EZX E680")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
@@ -929,7 +929,7 @@ static void __init a1200_init(void)
 }
 
 MACHINE_START(EZX_A1200, "Motorola EZX A1200")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
@@ -1120,7 +1120,7 @@ static void __init a910_init(void)
 }
 
 MACHINE_START(EZX_A910, "Motorola EZX A910")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
@@ -1186,7 +1186,7 @@ static void __init e6_init(void)
 }
 
 MACHINE_START(EZX_E6, "Motorola EZX E6")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
@@ -1226,7 +1226,7 @@ static void __init e2_init(void)
 }
 
 MACHINE_START(EZX_E2, "Motorola EZX E2")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index deaa111c91f9..9c8208ca0415 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -233,7 +233,7 @@ static void __init gumstix_init(void)
 }
 
 MACHINE_START(GUMSTIX, "Gumstix")
-        .boot_params    = 0xa0000100, /* match u-boot bi_boot_params */
+        .atag_offset    = 0x100, /* match u-boot bi_boot_params */
         .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .handle_irq     = pxa25x_handle_irq,
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c
index 0a235128914d..4b5e110640b1 100644
--- a/arch/arm/mach-pxa/h5000.c
+++ b/arch/arm/mach-pxa/h5000.c
@@ -203,7 +203,7 @@ static void __init h5000_init(void)
 }
 
 MACHINE_START(H5400, "HP iPAQ H5000")
-        .boot_params = 0xa0000100,
+        .atag_offset = 0x100,
         .map_io = pxa25x_map_io,
         .init_irq = pxa25x_init_irq,
         .handle_irq = pxa25x_handle_irq,
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c
index a997d0ab2872..f2c324570844 100644
--- a/arch/arm/mach-pxa/himalaya.c
+++ b/arch/arm/mach-pxa/himalaya.c
@@ -158,7 +158,7 @@ static void __init himalaya_init(void)
 
 
 MACHINE_START(HIMALAYA, "HTC Himalaya")
-        .boot_params = 0xa0000100,
+        .atag_offset = 0x100,
         .map_io = pxa25x_map_io,
         .init_irq = pxa25x_init_irq,
         .handle_irq = pxa25x_handle_irq,
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index c748a473a2ff..6f6368ece9bd 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -838,7 +838,7 @@ static void __init hx4700_init(void)
 }
 
 MACHINE_START(H4700, "HP iPAQ HX4700")
-        .boot_params  = 0xa0000100,
+        .atag_offset  = 0x100,
         .map_io       = pxa27x_map_io,
         .nr_irqs      = HX4700_NR_IRQS,
         .init_irq     = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c
index d427429f1f34..f78d5db758da 100644
--- a/arch/arm/mach-pxa/icontrol.c
+++ b/arch/arm/mach-pxa/icontrol.c
@@ -191,7 +191,7 @@ static void __init icontrol_init(void)
 }
 
 MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .handle_irq     = pxa3xx_handle_irq,
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 8f97e15e86e5..0037e57e0cec 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -437,7 +437,7 @@ static void __init littleton_init(void)
 }
 
 MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa3xx_map_io,
         .nr_irqs        = LITTLETON_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index c171d6ebee49..16df0fc0879a 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -499,7 +499,7 @@ static void __init lpd270_map_io(void)
 
 MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
         /* Maintainer: Peter Barada */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = lpd270_map_io,
         .nr_irqs        = LPD270_NR_IRQS,
         .init_irq       = lpd270_init_irq,
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 5fe5bcd7c0a1..4b796c37af3e 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -753,7 +753,7 @@ static void __init magician_init(void)
 
 
 MACHINE_START(MAGICIAN, "HTC Magician")
-        .boot_params = 0xa0000100,
+        .atag_offset = 0x100,
         .map_io = pxa27x_map_io,
         .nr_irqs = MAGICIAN_NR_IRQS,
         .init_irq = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 4622eb78ef25..cc6e14f6d114 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -616,7 +616,7 @@ static void __init mainstone_map_io(void)
 
 MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
         /* Maintainer: MontaVista Software Inc. */
-        .boot_params    = 0xa0000100,   /* BLOB boot parameter setting */
+        .atag_offset    = 0x100,        /* BLOB boot parameter setting */
         .map_io         = mainstone_map_io,
         .nr_irqs        = MAINSTONE_NR_IRQS,
         .init_irq       = mainstone_init_irq,
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 64810f908e5b..b938fc2c316a 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -751,7 +751,7 @@ static void mioa701_machine_exit(void)
 }
 
 MACHINE_START(MIOA701, "MIO A701")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = &pxa27x_map_io,
         .init_irq       = &pxa27x_init_irq,
         .handle_irq     = &pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c
index fb408861dbcf..4af5d513c380 100644
--- a/arch/arm/mach-pxa/mp900.c
+++ b/arch/arm/mach-pxa/mp900.c
@@ -92,7 +92,7 @@ static void __init mp900c_init(void)
 
 /* Maintainer - Michael Petchkovsky <mkpetch@internode.on.net> */
 MACHINE_START(NEC_MP900, "MobilePro900/C")
-        .boot_params    = 0xa0220100,
+        .atag_offset    = 0x220100,
         .timer          = &pxa_timer,
         .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 6b77365ed938..3d4a2819cae1 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -342,7 +342,7 @@ static void __init palmld_init(void)
 }
 
 MACHINE_START(PALMLD, "Palm LifeDrive")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = palmld_map_io,
         .init_irq       = pxa27x_init_irq,
         .handle_irq     = pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 9bd3e47486fb..99d6bcf1f974 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -202,7 +202,7 @@ static void __init palmt5_init(void)
 }
 
 MACHINE_START(PALMT5, "Palm Tungsten|T5")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa27x_map_io,
         .reserve        = palmt5_reserve,
         .init_irq       = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index 6ad4a6c7bc96..6ec7caefb37c 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -537,7 +537,7 @@ static void __init palmtc_init(void)
 };
 
 MACHINE_START(PALMTC, "Palm Tungsten|C")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .handle_irq     = pxa25x_handle_irq,
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index 664232f3e62c..9376da06404c 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -356,7 +356,7 @@ static void __init palmte2_init(void)
 }
 
 MACHINE_START(PALMTE2, "Palm Tungsten|E2")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .handle_irq     = pxa25x_handle_irq,
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index bb27d4b688d8..7346fbfa8101 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -440,7 +440,7 @@ static void __init centro_init(void)
 }
 
 MACHINE_START(TREO680, "Palm Treo 680")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa27x_map_io,
         .reserve        = treo_reserve,
         .init_irq       = pxa27x_init_irq,
@@ -450,7 +450,7 @@ MACHINE_START(TREO680, "Palm Treo 680")
 MACHINE_END
 
 MACHINE_START(CENTRO, "Palm Centro 685")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa27x_map_io,
         .reserve        = treo_reserve,
         .init_irq       = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index fc4285589c1f..2b9e76fc2c90 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -364,7 +364,7 @@ static void __init palmtx_init(void)
 }
 
 MACHINE_START(PALMTX, "Palm T|X")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = palmtx_map_io,
         .init_irq       = pxa27x_init_irq,
         .handle_irq     = pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index e61c1cc05519..68e18baf8e07 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -399,7 +399,7 @@ static void __init palmz72_init(void)
 }
 
 MACHINE_START(PALMZ72, "Palm Zire72")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .handle_irq     = pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index ffa65dfb8c6f..0b825a353537 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -258,7 +258,7 @@ static void __init pcm027_map_io(void)
 
 MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270")
         /* Maintainer: Pengutronix */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pcm027_map_io,
         .nr_irqs        = PCM027_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index bbcd90562ebe..6810cddec927 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -1086,7 +1086,7 @@ static void __init raumfeld_speaker_init(void)
 
 #ifdef CONFIG_MACH_RAUMFELD_RC
 MACHINE_START(RAUMFELD_RC, "Raumfeld Controller")
-        .boot_params    = RAUMFELD_SDRAM_BASE + 0x100,
+        .atag_offset    = 0x100,
         .init_machine   = raumfeld_controller_init,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
@@ -1097,7 +1097,7 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_RAUMFELD_CONNECTOR
 MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector")
-        .boot_params    = RAUMFELD_SDRAM_BASE + 0x100,
+        .atag_offset    = 0x100,
         .init_machine   = raumfeld_connector_init,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
@@ -1108,7 +1108,7 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_RAUMFELD_SPEAKER
 MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker")
-        .boot_params    = RAUMFELD_SDRAM_BASE + 0x100,
+        .atag_offset    = 0x100,
         .init_machine   = raumfeld_speaker_init,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index df4356e8acae..602d70b50f81 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -596,7 +596,7 @@ static void __init saar_init(void)
 
 MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
         /* Maintainer: Eric Miao <eric.miao@marvell.com> */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .handle_irq       = pxa3xx_handle_irq,
diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c
index ebd6379c4969..5ce340320ab9 100644
--- a/arch/arm/mach-pxa/saarb.c
+++ b/arch/arm/mach-pxa/saarb.c
@@ -103,7 +103,7 @@ static void __init saarb_init(void)
 }
 
 MACHINE_START(SAARB, "PXA955 Handheld Platform (aka SAARB)")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa3xx_map_io,
         .nr_irqs        = SAARB_NR_IRQS,
         .init_irq       = pxa95x_init_irq,
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index 3f8d0af9e2f7..4c9a48bef569 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -1004,7 +1004,7 @@ MACHINE_START(INTELMOTE2, "IMOTE 2")
         .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = imote2_init,
-        .boot_params    = 0xA0000100,
+        .atag_offset    = 0x100,
 MACHINE_END
 #endif
 
@@ -1016,6 +1016,6 @@ MACHINE_START(STARGATE2, "Stargate 2")
         .handle_irq = pxa27x_handle_irq,
         .timer = &pxa_timer,
         .init_machine = stargate2_init,
-        .boot_params = 0xA0000100,
+        .atag_offset = 0x100,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index 32fb58e01b10..ad47bb98f30d 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -489,7 +489,7 @@ static void __init tavorevb_init(void)
 
 MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)")
         /* Maintainer: Eric Miao <eric.miao@marvell.com> */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .handle_irq       = pxa3xx_handle_irq,
diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c
index fd5a8eae0a87..fd569167302a 100644
--- a/arch/arm/mach-pxa/tavorevb3.c
+++ b/arch/arm/mach-pxa/tavorevb3.c
@@ -125,7 +125,7 @@ static void __init evb3_init(void)
 }
 
 MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa3xx_map_io,
         .nr_irqs        = TAVOREVB3_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index c0417508f39d..35bbf13724b9 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -554,7 +554,7 @@ static void __init trizeps4_map_io(void)
 
 MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
         /* MAINTAINER("Jürgen Schindele") */
-        .boot_params    = TRIZEPS4_SDRAM_BASE + 0x100,
+        .atag_offset    = 0x100,
         .init_machine   = trizeps4_init,
         .map_io         = trizeps4_map_io,
         .init_irq       = pxa27x_init_irq,
@@ -564,7 +564,7 @@ MACHINE_END
 
 MACHINE_START(TRIZEPS4WL, "Keith und Koep Trizeps IV-WL module")
         /* MAINTAINER("Jürgen Schindele") */
-        .boot_params    = TRIZEPS4_SDRAM_BASE + 0x100,
+        .atag_offset    = 0x100,
         .init_machine   = trizeps4_init,
         .map_io         = trizeps4_map_io,
         .init_irq       = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index d4a3dc74e84a..242ddae332d3 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -992,7 +992,7 @@ static void __init viper_map_io(void)
 
 MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC")
         /* Maintainer: Marc Zyngier <maz@misterjones.org> */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = viper_map_io,
         .init_irq       = viper_init_irq,
         .handle_irq     = pxa25x_handle_irq,
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index 5f8490ab07cb..a7539a6ed1ff 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -716,7 +716,7 @@ static void __init vpac270_init(void)
 }
 
 MACHINE_START(VPAC270, "Voipac PXA270")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .handle_irq     = pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c
index acc600f5e72f..54930cccbe54 100644
--- a/arch/arm/mach-pxa/xcep.c
+++ b/arch/arm/mach-pxa/xcep.c
@@ -180,7 +180,7 @@ static void __init xcep_init(void)
 }
 
 MACHINE_START(XCEP, "Iskratel XCEP")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .init_machine   = xcep_init,
         .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index 6c9275a20c91..65fed3753fa2 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -718,7 +718,7 @@ static void __init z2_init(void)
 }
 
 MACHINE_START(ZIPIT2, "Zipit Z2")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .handle_irq     = pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 99c49bcd9f70..c424e7d85ce3 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -904,7 +904,7 @@ static void __init zeus_map_io(void)
 
 MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
         /* Maintainer: Marc Zyngier <maz@misterjones.org> */
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = zeus_map_io,
         .nr_irqs        = ZEUS_NR_IRQS,
         .init_irq       = zeus_init_irq,
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 15ec66b3471a..31d496891891 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -422,7 +422,7 @@ static void __init zylonite_init(void)
 }
 
 MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
-        .boot_params    = 0xa0000100,
+        .atag_offset    = 0x100,
         .map_io         = pxa3xx_map_io,
         .nr_irqs        = ZYLONITE_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 7a4e3b18cb3e..026c66ad7ec2 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -463,7 +463,7 @@ static void __init realview_eb_init(void)
 
 MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
+        .atag_offset    = 0x100,
         .fixup          = realview_fixup,
         .map_io         = realview_eb_map_io,
         .init_early     = realview_init_early,
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index ad5671acb66a..7263dea77779 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -358,7 +358,7 @@ static void __init realview_pb1176_init(void)
 
 MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
+        .atag_offset    = 0x100,
         .fixup          = realview_pb1176_fixup,
         .map_io         = realview_pb1176_map_io,
         .init_early     = realview_init_early,
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index b43644b3685e..671ad6d6ff00 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -360,7 +360,7 @@ static void __init realview_pb11mp_init(void)
 
 MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
+        .atag_offset    = 0x100,
         .fixup          = realview_fixup,
         .map_io         = realview_pb11mp_map_io,
         .init_early     = realview_init_early,
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 763e8f38c15d..cbf22df4ad5b 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -310,7 +310,7 @@ static void __init realview_pba8_init(void)
 
 MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
+        .atag_offset    = 0x100,
         .fixup          = realview_fixup,
         .map_io         = realview_pba8_map_io,
         .init_early     = realview_init_early,
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 363b0ab56150..8ec7e52618b4 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -393,7 +393,7 @@ static void __init realview_pbx_init(void)
 
 MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
+        .atag_offset    = 0x100,
         .fixup          = realview_pbx_fixup,
         .map_io         = realview_pbx_map_io,
         .init_early     = realview_init_early,
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index 580b3c73d2c7..a9241eb87724 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -218,7 +218,7 @@ extern struct sys_timer ioc_timer;
 
 MACHINE_START(RISCPC, "Acorn-RiscPC")
         /* Maintainer: Russell King */
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .reserve_lp0    = 1,
         .reserve_lp1    = 1,
         .map_io         = rpc_map_io,
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 7245a55795dc..3700cf32af0f 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -8,7 +8,6 @@ config CPU_S3C2410
         select CPU_ARM920T
         select S3C_GPIO_PULL_UP
         select S3C2410_CLOCK
-        select S3C2410_GPIO
         select CPU_LLSERIAL_S3C2410
         select S3C2410_PM if PM
         select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
@@ -28,11 +27,6 @@ config S3C2410_PM
         help
           Power Management code common to S3C2410 and better
 
-config S3C2410_GPIO
-        bool
-        help
-          GPIO code for S3C2410 and similar processors
-
 config SIMTEC_NOR
         bool
         help
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 81695353d8f4..782fd81144e9 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -13,7 +13,6 @@ obj-$(CONFIG_CPU_S3C2410)	+= s3c2410.o
 obj-$(CONFIG_CPU_S3C2410_DMA)   += dma.o
 obj-$(CONFIG_CPU_S3C2410_DMA)   += dma.o
 obj-$(CONFIG_S3C2410_PM)        += pm.o sleep.o
-obj-$(CONFIG_S3C2410_GPIO)      += gpio.o
 obj-$(CONFIG_S3C2410_CPUFREQ)   += cpu-freq.o
 obj-$(CONFIG_S3C2410_PLLTABLE)  += pll.o
 
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 0d8e043804c2..dbe43df8cfec 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -47,38 +47,26 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
                 .channels[0]    = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
                 .channels[2]    = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
                 .channels[3]    = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_SPI0] = {
                 .name           = "spi0",
                 .channels[1]    = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
         },
         [DMACH_SPI1] = {
                 .name           = "spi1",
                 .channels[3]    = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
         },
         [DMACH_UART0] = {
                 .name           = "uart0",
                 .channels[0]    = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
         },
         [DMACH_UART1] = {
                 .name           = "uart1",
                 .channels[1]    = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
         },
         [DMACH_UART2] = {
                 .name           = "uart2",
                 .channels[3]    = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
         },
         [DMACH_TIMER] = {
                 .name           = "timer",
@@ -90,12 +78,10 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
                 .name           = "i2s-sdi",
                 .channels[1]    = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
                 .channels[2]    = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_I2S_OUT] = {
                 .name           = "i2s-sdo",
                 .channels[2]    = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_USB_EP1] = {
                 .name           = "usb-ep1",
diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
deleted file mode 100644
index 9664e011dae2..000000000000
--- a/arch/arm/mach-s3c2410/gpio.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* linux/arch/arm/mach-s3c2410/gpio.c
- *
- * Copyright (c) 2004-2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 GPIO support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/gpio-fns.h>
-#include <asm/irq.h>
-
-#include <mach/regs-gpio.h>
-
-int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
-                           unsigned int config)
-{
-        void __iomem *reg = S3C24XX_EINFLT0;
-        unsigned long flags;
-        unsigned long val;
-
-        if (pin < S3C2410_GPG(8) || pin > S3C2410_GPG(15))
-                return -EINVAL;
-
-        config &= 0xff;
-
-        pin -= S3C2410_GPG(8);
-        reg += pin & ~3;
-
-        local_irq_save(flags);
-
-        /* update filter width and clock source */
-
-        val = __raw_readl(reg);
-        val &= ~(0xff << ((pin & 3) * 8));
-        val |= config << ((pin & 3) * 8);
-        __raw_writel(val, reg);
-
-        /* update filter enable */
-
-        val = __raw_readl(S3C24XX_EXTINT2);
-        val &= ~(1 << ((pin * 4) + 3));
-        val |= on << ((pin * 4) + 3);
-        __raw_writel(val, S3C24XX_EXTINT2);
-
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-EXPORT_SYMBOL(s3c2410_gpio_irqfilter);
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index 425552d84b60..4cf495f813a7 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -14,9 +14,53 @@
 #define __ASM_ARCH_MAP_H
 
 #include <plat/map-base.h>
-#include <plat/map.h>
 
-#define S3C2410_ADDR(x)         S3C_ADDR(x)
+/*
+ * S3C2410 UART offset is 0x4000 but the other SoCs are 0x400.
+ * So need to define it, and here is to avoid redefinition warning.
+ */
+#define S3C_UART_OFFSET         (0x4000)
+
+#include <plat/map-s3c.h>
+
+/*
+ * interrupt controller is the first thing we put in, to make
+ * the assembly code for the irq detection easier
+ */
+#define S3C2410_PA_IRQ          (0x4A000000)
+#define S3C24XX_SZ_IRQ          SZ_1M
+
+/* memory controller registers */
+#define S3C2410_PA_MEMCTRL      (0x48000000)
+#define S3C24XX_SZ_MEMCTRL      SZ_1M
+
+/* UARTs */
+#define S3C_VA_UARTx(uart)      (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
+
+/* Timers */
+#define S3C2410_PA_TIMER        (0x51000000)
+#define S3C24XX_SZ_TIMER        SZ_1M
+
+/* Clock and Power management */
+#define S3C24XX_SZ_CLKPWR       SZ_1M
+
+/* USB Device port */
+#define S3C2410_PA_USBDEV       (0x52000000)
+#define S3C24XX_SZ_USBDEV       SZ_1M
+
+/* Watchdog */
+#define S3C2410_PA_WATCHDOG     (0x53000000)
+#define S3C24XX_SZ_WATCHDOG     SZ_1M
+
+/* Standard size definitions for peripheral blocks. */
+
+#define S3C24XX_SZ_UART         SZ_1M
+#define S3C24XX_SZ_IIS          SZ_1M
+#define S3C24XX_SZ_ADC          SZ_1M
+#define S3C24XX_SZ_SPI          SZ_1M
+#define S3C24XX_SZ_SDI          SZ_1M
+#define S3C24XX_SZ_NAND         SZ_1M
+#define S3C24XX_SZ_GPIO         SZ_1M
 
 /* USB host controller */
 #define S3C2410_PA_USBHOST (0x49000000)
@@ -75,10 +119,8 @@
 
 /* S3C2412 memory and IO controls */
 #define S3C2412_PA_SSMC (0x4F000000)
-#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
 
 #define S3C2412_PA_EBI  (0x48800000)
-#define S3C2412_VA_EBI  S3C_ADDR_CPU(0x00010000)
 
 /* physical addresses of all the chip-select areas */
 
@@ -100,12 +142,10 @@
 #define S3C24XX_PA_DMA      S3C2410_PA_DMA
 #define S3C24XX_PA_CLKPWR   S3C2410_PA_CLKPWR
 #define S3C24XX_PA_LCD      S3C2410_PA_LCD
-#define S3C24XX_PA_UART     S3C2410_PA_UART
 #define S3C24XX_PA_TIMER    S3C2410_PA_TIMER
 #define S3C24XX_PA_USBDEV   S3C2410_PA_USBDEV
 #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
 #define S3C24XX_PA_IIS      S3C2410_PA_IIS
-#define S3C24XX_PA_GPIO     S3C2410_PA_GPIO
 #define S3C24XX_PA_RTC      S3C2410_PA_RTC
 #define S3C24XX_PA_ADC      S3C2410_PA_ADC
 #define S3C24XX_PA_SPI      S3C2410_PA_SPI
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index dabc141243f3..79838942b0ac 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -236,7 +236,7 @@ static void __init amlm5900_init(void)
 }
 
 MACHINE_START(AML_M5900, "AML_M5900")
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = amlm5900_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = amlm5900_init,
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 1e2d536adda9..a20ae1ad4062 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -657,7 +657,7 @@ static void __init bast_init(void)
 
 MACHINE_START(BAST, "Simtec-BAST")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = bast_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = bast_init,
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 2a2fa0620133..556c535829f0 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -744,7 +744,7 @@ static void __init h1940_init(void)
 
 MACHINE_START(H1940, "IPAQ-H1940")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = h1940_map_io,
         .reserve        = h1940_reserve,
         .init_irq       = h1940_init_irq,
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 079dcaa602d3..1dc3e3234417 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -586,7 +586,7 @@ MACHINE_START(N30, "Acer-N30")
         /* Maintainer: Christer Weinigel <christer@weinigel.se>,
                                 Ben Dooks <ben-linux@fluff.org>
         */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .timer          = &s3c24xx_timer,
         .init_machine   = n30_init,
         .init_irq       = s3c24xx_init_irq,
@@ -596,7 +596,7 @@ MACHINE_END
 MACHINE_START(N35, "Acer-N35")
         /* Maintainer: Christer Weinigel <christer@weinigel.se>
         */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .timer          = &s3c24xx_timer,
         .init_machine   = n30_init,
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c
index 0aa16cd5acbc..f03f3fd9cec9 100644
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c2410/mach-otom.c
@@ -116,7 +116,7 @@ static void __init otom11_init(void)
 
 MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
         /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = otom11_map_io,
         .init_machine   = otom11_init,
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index f44f77531b1e..367d376deb96 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -344,7 +344,7 @@ static void __init qt2410_machine_init(void)
 }
 
 MACHINE_START(QT2410, "QT2410")
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = qt2410_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = qt2410_machine_init,
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c
index e17f03387aba..99c9dfdb71c7 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
@@ -111,7 +111,7 @@ static void __init smdk2410_init(void)
 MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switch
                                     * to SMDK2410 */
         /* Maintainer: Jonas Dietsche */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = smdk2410_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = smdk2410_init,
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c
index 43c2b831b9e8..e0d0b6fb2800 100644
--- a/arch/arm/mach-s3c2410/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c
@@ -146,7 +146,7 @@ static void __init tct_hammer_init(void)
 }
 
 MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = tct_hammer_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = tct_hammer_init,
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 6ccce5a761b4..df47e8e90065 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -400,7 +400,7 @@ static void __init vr1000_init(void)
 
 MACHINE_START(VR1000, "Thorcom-VR1000")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = vr1000_map_io,
         .init_machine   = vr1000_init,
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index c2cf4e569989..b8b9029e9f2d 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -9,7 +9,6 @@ config CPU_S3C2412
         select CPU_LLSERIAL_S3C2440
         select S3C2412_PM if PM
         select S3C2412_DMA if S3C2410_DMA
-        select S3C2410_GPIO
         help
           Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
 
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 6c48a91ea39e..7e4d95fa8a97 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -12,7 +12,6 @@ obj-				:=
 obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o
 obj-$(CONFIG_CPU_S3C2412)       += irq.o
 obj-$(CONFIG_CPU_S3C2412)       += clock.o
-obj-$(CONFIG_CPU_S3C2412)       += gpio.o
 obj-$(CONFIG_S3C2412_DMA)       += dma.o
 obj-$(CONFIG_S3C2412_PM)        += pm.o
 obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep.o
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 7abecfca0b7e..c61e3261615d 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -50,64 +50,46 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
                 .name           = "sdi",
                 .channels       = MAP(S3C2412_DMAREQSEL_SDI),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_SDI),
-                .hw_addr.to     = S3C2410_PA_SDI + S3C2410_SDIDATA,
-                .hw_addr.from   = S3C2410_PA_SDI + S3C2410_SDIDATA,
         },
         [DMACH_SPI0] = {
                 .name           = "spi0",
                 .channels       = MAP(S3C2412_DMAREQSEL_SPI0TX),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_SPI0RX),
-                .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
         },
         [DMACH_SPI1] = {
                 .name           = "spi1",
                 .channels       = MAP(S3C2412_DMAREQSEL_SPI1TX),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_SPI1RX),
-                .hw_addr.to     = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + S3C2412_SPI1  + S3C2410_SPRDAT,
         },
         [DMACH_UART0] = {
                 .name           = "uart0",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART0_0),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_UART0_0),
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
         },
         [DMACH_UART1] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART1_0),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_UART1_0),
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
         },
         [DMACH_UART2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART2_0),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_UART2_0),
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
         },
         [DMACH_UART0_SRC2] = {
                 .name           = "uart0",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART0_1),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_UART0_1),
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
         },
         [DMACH_UART1_SRC2] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART1_1),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_UART1_1),
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
         },
         [DMACH_UART2_SRC2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART2_1),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_UART2_1),
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
         },
         [DMACH_TIMER] = {
                 .name           = "timer",
diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c
deleted file mode 100644
index 3404a876b33e..000000000000
--- a/arch/arm/mach-s3c2412/gpio.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* linux/arch/arm/mach-s3c2412/gpio.c
- *
- * Copyright (c) 2007 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * http://armlinux.simtec.co.uk/.
- *
- * S3C2412/S3C2413 specific GPIO support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/regs-gpio.h>
-#include <mach/hardware.h>
-
-#include <plat/gpio-core.h>
-
-int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
-{
-        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
-        unsigned long offs = pin - chip->chip.base;
-        unsigned long flags;
-        unsigned long slpcon;
-
-        offs *= 2;
-
-        if (pin < S3C2410_GPB(0))
-                return -EINVAL;
-
-        if (pin >= S3C2410_GPF(0) &&
-            pin <= S3C2410_GPG(16))
-                return -EINVAL;
-
-        if (pin > S3C2410_GPH(16))
-                return -EINVAL;
-
-        local_irq_save(flags);
-
-        slpcon = __raw_readl(chip->base + 0x0C);
-
-        slpcon &= ~(3 << offs);
-        slpcon |= state << offs;
-
-        __raw_writel(slpcon, chip->base + 0x0C);
-
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-EXPORT_SYMBOL(s3c2412_gpio_set_sleepcfg);
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 5eeb47580b0c..286ef1738c61 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -655,7 +655,7 @@ static void __init jive_machine_init(void)
 
 MACHINE_START(JIVE, "JIVE")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
 
         .init_irq       = s3c24xx_init_irq,
         .map_io         = jive_map_io,
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index 834cfb61bcfe..d6325ede9f29 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -128,7 +128,7 @@ static void __init smdk2413_machine_init(void)
 
 MACHINE_START(S3C2413, "S3C2413")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
 
         .fixup          = smdk2413_fixup,
         .init_irq       = s3c24xx_init_irq,
@@ -139,7 +139,7 @@ MACHINE_END
 
 MACHINE_START(SMDK2412, "SMDK2412")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
 
         .fixup          = smdk2413_fixup,
         .init_irq       = s3c24xx_init_irq,
@@ -150,7 +150,7 @@ MACHINE_END
 
 MACHINE_START(SMDK2413, "SMDK2413")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
 
         .fixup          = smdk2413_fixup,
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index 83544ebe20ac..5955c15018b4 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -156,7 +156,7 @@ static void __init vstms_init(void)
 }
 
 MACHINE_START(VSTMS, "VSTMS")
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
 
         .fixup          = vstms_fixup,
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
index ac27ebb31c9b..a9eee531ca76 100644
--- a/arch/arm/mach-s3c2416/mach-smdk2416.c
+++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
@@ -245,7 +245,7 @@ static void __init smdk2416_machine_init(void)
 
 MACHINE_START(SMDK2416, "SMDK2416")
         /* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
 
         .init_irq       = s3c24xx_init_irq,
         .map_io         = smdk2416_map_io,
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index 50825a3f91cc..c461fb8e15c0 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -8,7 +8,6 @@ config CPU_S3C2440
         select S3C_GPIO_PULL_UP
         select S3C2410_CLOCK
         select S3C2410_PM if PM
-        select S3C2410_GPIO
         select S3C2440_DMA if S3C2410_DMA
         select CPU_S3C244X
         select CPU_LLSERIAL_S3C2440
@@ -20,7 +19,6 @@ config CPU_S3C2442
         select CPU_ARM920T
         select S3C_GPIO_PULL_DOWN
         select S3C2410_CLOCK
-        select S3C2410_GPIO
         select S3C2410_PM if PM
         select CPU_S3C244X
         select CPU_LLSERIAL_S3C2440
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index 3b0529f54e9c..0e73f8f9d132 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -48,38 +48,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
                 .channels[1]    = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
                 .channels[2]    = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
                 .channels[3]    = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_SPI0] = {
                 .name           = "spi0",
                 .channels[1]    = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
         },
         [DMACH_SPI1] = {
                 .name           = "spi1",
                 .channels[3]    = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
         },
         [DMACH_UART0] = {
                 .name           = "uart0",
                 .channels[0]    = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
         },
         [DMACH_UART1] = {
                 .name           = "uart1",
                 .channels[1]    = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
         },
         [DMACH_UART2] = {
                 .name           = "uart2",
                 .channels[3]    = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
         },
         [DMACH_TIMER] = {
                 .name           = "timer",
@@ -91,31 +79,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
                 .name           = "i2s-sdi",
                 .channels[1]    = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
                 .channels[2]    = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_I2S_OUT] = {
                 .name           = "i2s-sdo",
                 .channels[0]    = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
                 .channels[2]    = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_PCM_IN] = {
                 .name           = "pcm-in",
                 .channels[0]    = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
                 .channels[2]    = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
-                .hw_addr.from   = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
         },
         [DMACH_PCM_OUT] = {
                 .name           = "pcm-out",
                 .channels[1]    = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
                 .channels[3]    = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
-                .hw_addr.to     = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
         },
         [DMACH_MIC_IN] = {
                 .name           = "mic-in",
                 .channels[2]    = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
                 .channels[3]    = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
-                .hw_addr.from   = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
         },
         [DMACH_USB_EP1] = {
                 .name           = "usb-ep1",
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index d7086788b1ff..74f92fc3fd04 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -498,7 +498,7 @@ static void __init anubis_init(void)
 
 MACHINE_START(ANUBIS, "Simtec-Anubis")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = anubis_map_io,
         .init_machine   = anubis_init,
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 6c98b789b8c6..38887ee0c784 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -233,7 +233,7 @@ static void __init at2440evb_init(void)
 
 
 MACHINE_START(AT2440EVB, "AT2440EVB")
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = at2440evb_map_io,
         .init_machine   = at2440evb_init,
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
index c10ddf4ed7f1..de1e0ff46cec 100644
--- a/arch/arm/mach-s3c2440/mach-gta02.c
+++ b/arch/arm/mach-s3c2440/mach-gta02.c
@@ -595,7 +595,7 @@ static void __init gta02_machine_init(void)
 
 MACHINE_START(NEO1973_GTA02, "GTA02")
         /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = gta02_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = gta02_machine_init,
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index fc2dc0b3d4fe..91fe0b4c95f1 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -676,7 +676,7 @@ static void __init mini2440_init(void)
 
 MACHINE_START(MINI2440, "MINI2440")
         /* Maintainer: Michel Pollet <buserror@gmail.com> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = mini2440_map_io,
         .init_machine   = mini2440_init,
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 37dd306fb7dc..61c0bf148165 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -151,7 +151,7 @@ static void __init nexcoder_init(void)
 
 MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
         /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = nexcoder_map_io,
         .init_machine   = nexcoder_init,
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index d88536393310..dc142ebf8cba 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -447,7 +447,7 @@ static void __init osiris_init(void)
 
 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = osiris_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = osiris_init,
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 27ea95096fe1..684dbb3567f5 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -825,7 +825,7 @@ static void __init rx1950_reserve(void)
 
 MACHINE_START(RX1950, "HP iPAQ RX1950")
     /* Maintainers: Vasily Khoruzhick */
-        .boot_params = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset = 0x100,
         .map_io = rx1950_map_io,
         .reserve        = rx1950_reserve,
         .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index 1472b1a5b2fb..e19499c2f909 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -218,7 +218,7 @@ static void __init rx3715_init_machine(void)
 
 MACHINE_START(RX3715, "IPAQ-RX3715")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = rx3715_map_io,
         .reserve        = rx3715_reserve,
         .init_irq       = rx3715_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index eedfe0f11643..36eeb4197a84 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -175,7 +175,7 @@ static void __init smdk2440_machine_init(void)
 
 MACHINE_START(S3C2440, "SMDK2440")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
 
         .init_irq       = s3c24xx_init_irq,
         .map_io         = smdk2440_map_io,
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index 3f658685ec16..fe52151d2e84 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -54,68 +54,46 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
         [DMACH_SDI] = {
                 .name           = "sdi",
                 .channels       = MAP(S3C2443_DMAREQSEL_SDI),
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_SPI0] = {
                 .name           = "spi0",
                 .channels       = MAP(S3C2443_DMAREQSEL_SPI0TX),
-                .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
         },
         [DMACH_SPI1] = {
                 .name           = "spi1",
                 .channels       = MAP(S3C2443_DMAREQSEL_SPI1TX),
-                .hw_addr.to     = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
         },
         [DMACH_UART0] = {
                 .name           = "uart0",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART0_0),
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
         },
         [DMACH_UART1] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART1_0),
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
         },
         [DMACH_UART2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART2_0),
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
         },
         [DMACH_UART3] = {
                 .name           = "uart3",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART3_0),
-                .hw_addr.to     = S3C2443_PA_UART3 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2443_PA_UART3 + S3C2410_URXH,
         },
         [DMACH_UART0_SRC2] = {
                 .name           = "uart0",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART0_1),
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
         },
         [DMACH_UART1_SRC2] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART1_1),
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
         },
         [DMACH_UART2_SRC2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART2_1),
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
         },
         [DMACH_UART3_SRC2] = {
                 .name           = "uart3",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART3_1),
-                .hw_addr.to     = S3C2443_PA_UART3 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2443_PA_UART3 + S3C2410_URXH,
         },
         [DMACH_TIMER] = {
                 .name           = "timer",
@@ -124,27 +102,22 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
         [DMACH_I2S_IN] = {
                 .name           = "i2s-sdi",
                 .channels       = MAP(S3C2443_DMAREQSEL_I2SRX),
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_I2S_OUT] = {
                 .name           = "i2s-sdo",
                 .channels       = MAP(S3C2443_DMAREQSEL_I2STX),
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_PCM_IN] = {
                 .name           = "pcm-in",
                 .channels       = MAP(S3C2443_DMAREQSEL_PCMIN),
-                .hw_addr.from   = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
         },
         [DMACH_PCM_OUT] = {
                 .name           = "pcm-out",
                 .channels       = MAP(S3C2443_DMAREQSEL_PCMOUT),
-                .hw_addr.to     = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
         },
         [DMACH_MIC_IN] = {
                 .name           = "mic-in",
                 .channels       = MAP(S3C2443_DMAREQSEL_MICIN),
-                .hw_addr.from   = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
         },
 };
 
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index 514275e43ca0..bec107e00441 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -139,7 +139,7 @@ static void __init smdk2443_machine_init(void)
 
 MACHINE_START(SMDK2443, "SMDK2443")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .atag_offset    = 0x100,
 
         .init_irq       = s3c24xx_init_irq,
         .map_io         = smdk2443_map_io,
diff --git a/arch/arm/mach-s3c64xx/cpu.c b/arch/arm/mach-s3c64xx/cpu.c
index 374e45e566b8..8dc05763a7eb 100644
--- a/arch/arm/mach-s3c64xx/cpu.c
+++ b/arch/arm/mach-s3c64xx/cpu.c
@@ -20,6 +20,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/dma-mapping.h>
 
 #include <mach/hardware.h>
 #include <mach/map.h>
@@ -145,6 +146,7 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
         /* initialise the io descriptors we need for initialisation */
         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
         iotable_init(mach_desc, size);
+        init_consistent_dma_size(SZ_8M);
 
         idcode = __raw_readl(S3C_VA_SYS + 0x118);
         if (!idcode) {
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index a1f13f02c841..23a1d71e4d53 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -16,6 +16,7 @@
 #define __ASM_ARCH_MAP_H __FILE__
 
 #include <plat/map-base.h>
+#include <plat/map-s3c.h>
 
 /*
  * Post-mux Chip Select Regions Xm0CSn_
@@ -83,7 +84,6 @@
 #define S3C64XX_PA_IIC1         (0x7F00F000)
 
 #define S3C64XX_PA_GPIO         (0x7F008000)
-#define S3C64XX_VA_GPIO         S3C_ADDR_CPU(0x00000000)
 #define S3C64XX_SZ_GPIO         SZ_4K
 
 #define S3C64XX_PA_SDRAM        (0x50000000)
@@ -94,16 +94,10 @@
 #define S3C64XX_PA_VIC1         (0x71300000)
 
 #define S3C64XX_PA_MODEM        (0x74108000)
-#define S3C64XX_VA_MODEM        S3C_ADDR_CPU(0x00100000)
 
 #define S3C64XX_PA_USBHOST      (0x74300000)
 
 #define S3C64XX_PA_USB_HSPHY    (0x7C100000)
-#define S3C64XX_VA_USB_HSPHY    S3C_ADDR_CPU(0x00200000)
-
-/* place VICs close together */
-#define VA_VIC0                 (S3C_VA_IRQ + 0x00)
-#define VA_VIC1                 (S3C_VA_IRQ + 0x10000)
 
 /* compatibiltiy defines. */
 #define S3C_PA_TIMER            S3C64XX_PA_TIMER
@@ -119,7 +113,6 @@
 #define S3C_PA_FB               S3C64XX_PA_FB
 #define S3C_PA_USBHOST          S3C64XX_PA_USBHOST
 #define S3C_PA_USB_HSOTG        S3C64XX_PA_USB_HSOTG
-#define S3C_VA_USB_HSPHY        S3C64XX_VA_USB_HSPHY
 #define S3C_PA_RTC              S3C64XX_PA_RTC
 #define S3C_PA_WDT              S3C64XX_PA_WATCHDOG
 
diff --git a/arch/arm/mach-s3c64xx/include/mach/memory.h b/arch/arm/mach-s3c64xx/include/mach/memory.h
index 4760cdae1eb6..b704669f95ff 100644
--- a/arch/arm/mach-s3c64xx/include/mach/memory.h
+++ b/arch/arm/mach-s3c64xx/include/mach/memory.h
@@ -15,6 +15,4 @@
 
 #define PLAT_PHYS_OFFSET     UL(0x50000000)
 
-#define CONSISTENT_DMA_SIZE     SZ_8M
-
 #endif
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index cb8864327ac4..d164a282bfb4 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -233,7 +233,7 @@ static void __init anw6410_machine_init(void)
 
 MACHINE_START(ANW6410, "A&W6410")
         /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
-        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
 
         .init_irq       = s3c6410_init_irq,
         .map_io         = anw6410_map_io,
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index af0c2fe1ea37..806580388f30 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -329,9 +329,6 @@ static struct platform_device *crag6410_devices[] __initdata = {
         &s3c_device_fb,
         &s3c_device_ohci,
         &s3c_device_usb_hsotg,
-        &s3c_device_adc,
-        &s3c_device_rtc,
-        &s3c_device_ts,
         &s3c_device_timer[0],
         &s3c64xx_device_iis0,
         &s3c64xx_device_iis1,
@@ -766,7 +763,7 @@ static void __init crag6410_machine_init(void)
 
 MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
         /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */
-        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
         .init_irq       = s3c6410_init_irq,
         .map_io         = crag6410_map_io,
         .init_machine   = crag6410_machine_init,
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index b3d93cc8dde0..19a0887e1c1e 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -265,7 +265,7 @@ static void __init hmt_machine_init(void)
 
 MACHINE_START(HMT, "Airgoo-HMT")
         /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */
-        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
         .init_irq       = s3c6410_init_irq,
         .map_io         = hmt_map_io,
         .init_machine   = hmt_machine_init,
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 527f49bd1b57..fb8969aa412e 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -205,12 +205,6 @@ static struct platform_device mini6410_lcd_powerdev = {
         .dev.platform_data      = &mini6410_lcd_power_data,
 };
 
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
-
 static struct platform_device *mini6410_devices[] __initdata = {
         &mini6410_device_eth,
         &s3c_device_hsmmc0,
@@ -319,7 +313,7 @@ static void __init mini6410_machine_init(void)
 
         s3c_nand_set_platdata(&mini6410_nand_info);
         s3c_fb_set_platdata(&mini6410_lcd_pdata);
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
 
         /* configure nCS1 width to 16 bits */
 
@@ -349,7 +343,7 @@ static void __init mini6410_machine_init(void)
 
 MACHINE_START(MINI6410, "MINI6410")
         /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
-        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
         .init_irq       = s3c6410_init_irq,
         .map_io         = mini6410_map_io,
         .init_machine   = mini6410_machine_init,
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index 01c6857c5b63..c30f2e5e0d85 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -97,7 +97,7 @@ static void __init ncp_machine_init(void)
 
 MACHINE_START(NCP, "NCP")
         /* Maintainer: Samsung Electronics */
-        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
         .init_irq       = s3c6410_init_irq,
         .map_io         = ncp_map_io,
         .init_machine   = ncp_machine_init,
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 95b04b1729e3..93170d4834e7 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -198,12 +198,6 @@ static struct platform_device *real6410_devices[] __initdata = {
         &s3c_device_ohci,
 };
 
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
-
 static void __init real6410_map_io(void)
 {
         u32 tmp;
@@ -300,7 +294,7 @@ static void __init real6410_machine_init(void)
 
         s3c_fb_set_platdata(&real6410_lcd_pdata);
         s3c_nand_set_platdata(&real6410_nand_info);
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
 
         /* configure nCS1 width to 16 bits */
 
@@ -329,7 +323,7 @@ static void __init real6410_machine_init(void)
 
 MACHINE_START(REAL6410, "REAL6410")
         /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
-        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
 
         .init_irq       = s3c6410_init_irq,
         .map_io         = real6410_map_io,
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index 342e8dfddf8b..cbb57ded3d95 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -146,7 +146,7 @@ static void __init smartq5_machine_init(void)
 
 MACHINE_START(SMARTQ5, "SmartQ 5")
         /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
-        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
         .init_irq       = s3c6410_init_irq,
         .map_io         = smartq_map_io,
         .init_machine   = smartq5_machine_init,
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index 57963977da8e..04f914b85fdf 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -162,7 +162,7 @@ static void __init smartq7_machine_init(void)
 
 MACHINE_START(SMARTQ7, "SmartQ 7")
         /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
-        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
         .init_irq       = s3c6410_init_irq,
         .map_io         = smartq_map_io,
         .init_machine   = smartq7_machine_init,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index 3cca642f1e6d..6fd5e95f8f75 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -85,7 +85,7 @@ static void __init smdk6400_machine_init(void)
 
 MACHINE_START(SMDK6400, "SMDK6400")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
 
         .init_irq       = s3c6400_init_irq,
         .map_io         = smdk6400_map_io,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index a9f3183e0290..5f147c33edad 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -619,12 +619,6 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
         { I2C_BOARD_INFO("24c128", 0x57), },    /* Samsung S524AD0XD1 */
 };
 
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
-
 /* LCD Backlight data */
 static struct samsung_bl_gpio_info smdk6410_bl_gpio_info = {
         .no = S3C64XX_GPF(15),
@@ -666,7 +660,7 @@ static void __init smdk6410_machine_init(void)
 
         samsung_keypad_set_platdata(&smdk6410_keypad_data);
 
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
 
         /* configure nCS1 width to 16 bits */
 
@@ -703,7 +697,7 @@ static void __init smdk6410_machine_init(void)
 
 MACHINE_START(SMDK6410, "SMDK6410")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
 
         .init_irq       = s3c6410_init_irq,
         .map_io         = smdk6410_map_io,
diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
index a5c00952ea35..8a938542c54d 100644
--- a/arch/arm/mach-s5p64x0/cpu.c
+++ b/arch/arm/mach-s5p64x0/cpu.c
@@ -20,6 +20,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
+#include <linux/dma-mapping.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -111,6 +112,7 @@ void __init s5p6440_map_io(void)
 
         iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
         iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
+        init_consistent_dma_size(SZ_8M);
 }
 
 void __init s5p6450_map_io(void)
@@ -120,6 +122,7 @@ void __init s5p6450_map_io(void)
 
         iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
         iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
+        init_consistent_dma_size(SZ_8M);
 }
 
 /*
diff --git a/arch/arm/mach-s5p64x0/include/mach/memory.h b/arch/arm/mach-s5p64x0/include/mach/memory.h
index 365a6eb4b88f..b14cbc3f521b 100644
--- a/arch/arm/mach-s5p64x0/include/mach/memory.h
+++ b/arch/arm/mach-s5p64x0/include/mach/memory.h
@@ -14,6 +14,5 @@
 #define __ASM_ARCH_MEMORY_H __FILE__
 
 #define PLAT_PHYS_OFFSET                UL(0x20000000)
-#define CONSISTENT_DMA_SIZE     SZ_8M
 
 #endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 346f8dfa6f35..88857f5a49f7 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -129,12 +129,6 @@ static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = {
         /* To be populated */
 };
 
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
-
 /* LCD Backlight data */
 static struct samsung_bl_gpio_info smdk6440_bl_gpio_info = {
         .no = S5P6440_GPF(15),
@@ -155,7 +149,7 @@ static void __init smdk6440_map_io(void)
 
 static void __init smdk6440_machine_init(void)
 {
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
 
         s3c_i2c0_set_platdata(&s5p6440_i2c0_data);
         s3c_i2c1_set_platdata(&s5p6440_i2c1_data);
@@ -171,7 +165,7 @@ static void __init smdk6440_machine_init(void)
 
 MACHINE_START(SMDK6440, "SMDK6440")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .boot_params    = S5P64X0_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
 
         .init_irq       = s5p6440_init_irq,
         .map_io         = smdk6440_map_io,
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 33f2adf8f3fe..e1b277b94610 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -148,12 +148,6 @@ static struct i2c_board_info smdk6450_i2c_devs1[] __initdata = {
         { I2C_BOARD_INFO("24c128", 0x57), },/* Samsung S524AD0XD1 EEPROM */
 };
 
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
-
 /* LCD Backlight data */
 static struct samsung_bl_gpio_info smdk6450_bl_gpio_info = {
         .no = S5P6450_GPF(15),
@@ -174,7 +168,7 @@ static void __init smdk6450_map_io(void)
 
 static void __init smdk6450_machine_init(void)
 {
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
 
         s3c_i2c0_set_platdata(&s5p6450_i2c0_data);
         s3c_i2c1_set_platdata(&s5p6450_i2c1_data);
@@ -190,7 +184,7 @@ static void __init smdk6450_machine_init(void)
 
 MACHINE_START(SMDK6450, "SMDK6450")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .boot_params    = S5P64X0_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
 
         .init_irq       = s5p6450_init_irq,
         .map_io         = smdk6450_map_io,
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 227d8908aab6..26f5c91c9427 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -203,12 +203,6 @@ static struct platform_device *smdkc100_devices[] __initdata = {
         &s5pc100_device_spdif,
 };
 
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
-
 /* LCD Backlight data */
 static struct samsung_bl_gpio_info smdkc100_bl_gpio_info = {
         .no = S5PC100_GPD(0),
@@ -228,7 +222,7 @@ static void __init smdkc100_map_io(void)
 
 static void __init smdkc100_machine_init(void)
 {
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
 
         /* I2C */
         s3c_i2c0_set_platdata(NULL);
@@ -254,7 +248,7 @@ static void __init smdkc100_machine_init(void)
 
 MACHINE_START(SMDKC100, "SMDKC100")
         /* Maintainer: Byungho Min <bhmin@samsung.com> */
-        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
         .init_irq       = s5pc100_init_irq,
         .map_io         = smdkc100_map_io,
         .init_machine   = smdkc100_machine_init,
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 69dd87cd8e22..aaeb44a73716 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -14,7 +14,6 @@ config CPU_S5PV210
         select S3C_PL330_DMA
         select S5P_EXT_INT
         select S5P_HRT
-        select S5PV210_PM if PM
         help
           Enable S5PV210 CPU support
 
@@ -169,9 +168,4 @@ config MACH_TORBRECK
 
 endmenu
 
-config S5PV210_PM
-        bool
-        help
-          Power Management code common to S5PV210
-
 endif
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 599a3c0e8f6c..ef7e4668d670 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -14,7 +14,7 @@ obj-				:=
 
 obj-$(CONFIG_CPU_S5PV210)       += cpu.o init.o clock.o dma.o
 obj-$(CONFIG_CPU_S5PV210)       += setup-i2c0.o
-obj-$(CONFIG_S5PV210_PM)        += pm.o sleep.o
+obj-$(CONFIG_PM)                += pm.o sleep.o
 
 # machine support
 
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 79907ec78d43..91145720822c 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -20,6 +20,7 @@
 #include <linux/sysdev.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
+#include <linux/dma-mapping.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -119,6 +120,7 @@ static void s5pv210_sw_reset(void)
 void __init s5pv210_map_io(void)
 {
         iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
+        init_consistent_dma_size(14 << 20);
 
         /* initialise device information early */
         s5pv210_default_sdhci0();
diff --git a/arch/arm/mach-s5pv210/include/mach/memory.h b/arch/arm/mach-s5pv210/include/mach/memory.h
index 7b5fcf0da0c4..2d3cfa221d5f 100644
--- a/arch/arm/mach-s5pv210/include/mach/memory.h
+++ b/arch/arm/mach-s5pv210/include/mach/memory.h
@@ -14,7 +14,6 @@
 #define __ASM_ARCH_MEMORY_H
 
 #define PLAT_PHYS_OFFSET                UL(0x20000000)
-#define CONSISTENT_DMA_SIZE     (SZ_8M + SZ_4M + SZ_2M)
 
 /*
  * Sparsemem support
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 509627f25111..5811a96125f0 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -678,7 +678,7 @@ MACHINE_START(AQUILA, "Aquila")
         /* Maintainers:
            Marek Szyprowski <m.szyprowski@samsung.com>
            Kyungmin Park <kyungmin.park@samsung.com> */
-        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
         .init_irq       = s5pv210_init_irq,
         .map_io         = aquila_map_io,
         .init_machine   = aquila_machine_init,
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 85c2d51a0956..061cc7e4f48c 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -897,7 +897,7 @@ static void __init goni_machine_init(void)
 
 MACHINE_START(GONI, "GONI")
         /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */
-        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
         .init_irq       = s5pv210_init_irq,
         .map_io         = goni_map_io,
         .init_machine   = goni_machine_init,
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 6c412c8ceccc..f7266bb0cac8 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -136,7 +136,7 @@ static void __init smdkc110_machine_init(void)
 
 MACHINE_START(SMDKC110, "SMDKC110")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
         .init_irq       = s5pv210_init_irq,
         .map_io         = smdkc110_map_io,
         .init_machine   = smdkc110_machine_init,
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 5e011fc6720d..a9106c392398 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -265,12 +265,6 @@ static struct i2c_board_info smdkv210_i2c_devs2[] __initdata = {
         /* To Be Updated */
 };
 
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
-
 /* LCD Backlight data */
 static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = {
         .no = S5PV210_GPD0(3),
@@ -296,7 +290,7 @@ static void __init smdkv210_machine_init(void)
         smdkv210_dm9000_init();
 
         samsung_keypad_set_platdata(&smdkv210_keypad_data);
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
 
         s3c_i2c0_set_platdata(NULL);
         s3c_i2c1_set_platdata(NULL);
@@ -319,7 +313,7 @@ static void __init smdkv210_machine_init(void)
 
 MACHINE_START(SMDKV210, "SMDKV210")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
         .init_irq       = s5pv210_init_irq,
         .map_io         = smdkv210_map_io,
         .init_machine   = smdkv210_machine_init,
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
index 925fc0dc6252..97cc066c5369 100644
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
@@ -125,7 +125,7 @@ static void __init torbreck_machine_init(void)
 
 MACHINE_START(TORBRECK, "TORBRECK")
         /* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
-        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
         .init_irq       = s5pv210_init_irq,
         .map_io         = torbreck_map_io,
         .init_machine   = torbreck_machine_init,
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index 26257df19b63..d40da5f1f37b 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -447,7 +447,7 @@ static void __init assabet_map_io(void)
 
 
 MACHINE_START(ASSABET, "Intel-Assabet")
-        .boot_params    = 0xc0000100,
+        .atag_offset    = 0x100,
         .fixup          = fixup_assabet,
         .map_io         = assabet_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index b4311b0a4395..bda83e1ab078 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -302,7 +302,7 @@ static void __init badge4_map_io(void)
 }
 
 MACHINE_START(BADGE4, "Hewlett-Packard Laboratories BadgePAD 4")
-        .boot_params    = 0xc0000100,
+        .atag_offset    = 0x100,
         .map_io         = badge4_map_io,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c
index 03d7376cf8a0..b30733a2b82e 100644
--- a/arch/arm/mach-sa1100/h3100.c
+++ b/arch/arm/mach-sa1100/h3100.c
@@ -84,7 +84,7 @@ static void __init h3100_mach_init(void)
 }
 
 MACHINE_START(H3100, "Compaq iPAQ H3100")
-        .boot_params    = 0xc0000100,
+        .atag_offset    = 0x100,
         .map_io         = h3100_map_io,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index 965f64a836f8..6fd324d92389 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -125,7 +125,7 @@ static void __init h3600_mach_init(void)
 }
 
 MACHINE_START(H3600, "Compaq iPAQ H3600")
-        .boot_params    = 0xc0000100,
+        .atag_offset    = 0x100,
         .map_io         = h3600_map_io,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index db5e434a17db..30f4a551b8e5 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -195,7 +195,7 @@ static void __init hackkit_init(void)
  */
 
 MACHINE_START(HACKKIT, "HackKit Cpu Board")
-        .boot_params    = 0xc0000100,
+        .atag_offset    = 0x100,
         .map_io         = hackkit_map_io,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index 176c066aec7e..0bb520d48ed0 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -364,7 +364,7 @@ static void __init jornada720_mach_init(void)
 
 MACHINE_START(JORNADA720, "HP Jornada 720")
         /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */
-        .boot_params    = 0xc0000100,
+        .atag_offset    = 0x100,
         .map_io         = jornada720_map_io,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index 7b9556b59057..5bc59d0947ba 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -61,7 +61,7 @@ static void __init lart_map_io(void)
 }
 
 MACHINE_START(LART, "LART")
-        .boot_params    = 0xc0000100,
+        .atag_offset    = 0x100,
         .map_io         = lart_map_io,
         .init_irq       = sa1100_init_irq,
         .init_machine   = lart_init,
diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c
index 72087f0658b7..032f3881d145 100644
--- a/arch/arm/mach-sa1100/nanoengine.c
+++ b/arch/arm/mach-sa1100/nanoengine.c
@@ -111,7 +111,7 @@ static void __init nanoengine_init(void)
 }
 
 MACHINE_START(NANOENGINE, "BSE nanoEngine")
-        .boot_params    = 0xc0000000,
+        .atag_offset    = 0x100,
         .map_io         = nanoengine_map_io,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index 7917b2405579..1cccbf5b9e9a 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -82,7 +82,7 @@ static void __init shannon_map_io(void)
 }
 
 MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)")
-        .boot_params    = 0xc0000100,
+        .atag_offset    = 0x100,
         .map_io         = shannon_map_io,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index cfb76077bd25..a1c2427655da 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -229,7 +229,7 @@ arch_initcall(simpad_init);
 
 MACHINE_START(SIMPAD, "Simpad")
         /* Maintainer: Holger Freyther */
-        .boot_params    = 0xc0000100,
+        .atag_offset    = 0x100,
         .map_io         = simpad_map_io,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index ac2873c8014b..feda3ca7fc95 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -152,7 +152,7 @@ static struct sys_timer shark_timer = {
 
 MACHINE_START(SHARK, "Shark")
         /* Maintainer: Alexander Schulz */
-        .boot_params    = 0x08003000,
+        .atag_offset    = 0x3000,
         .map_io         = shark_map_io,
         .init_irq       = shark_init_irq,
         .timer          = &shark_timer,
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index cdfdd624d21d..5fde49da399a 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -37,6 +37,7 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
 #include <linux/sh_clk.h>
+#include <linux/dma-mapping.h>
 #include <video/sh_mobile_lcdc.h>
 #include <video/sh_mipi_dsi.h>
 #include <sound/sh_fsi.h>
@@ -447,6 +448,8 @@ static struct map_desc ag5evm_io_desc[] __initdata = {
 static void __init ag5evm_map_io(void)
 {
         iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc));
+        /* DMA memory at 0xf6000000 - 0xffdfffff */
+        init_consistent_dma_size(158 << 20);
 
         /* setup early devices and console here as well */
         sh73a0_add_early_devices();
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 523f608eb8cf..b622d8d3ab72 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -42,6 +42,7 @@
 #include <linux/leds.h>
 #include <linux/input/sh_keysc.h>
 #include <linux/usb/r8a66597.h>
+#include <linux/dma-mapping.h>
 
 #include <media/sh_mobile_ceu.h>
 #include <media/sh_mobile_csi2.h>
@@ -1170,6 +1171,8 @@ static struct map_desc ap4evb_io_desc[] __initdata = {
 static void __init ap4evb_map_io(void)
 {
         iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc));
+        /* DMA memory at 0xf6000000 - 0xffdfffff */
+        init_consistent_dma_size(158 << 20);
 
         /* setup early devices and console here as well */
         sh7372_add_early_devices();
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
index ef4613b993a2..8b620bf06221 100644
--- a/arch/arm/mach-shmobile/board-g3evm.c
+++ b/arch/arm/mach-shmobile/board-g3evm.c
@@ -32,6 +32,7 @@
 #include <linux/gpio.h>
 #include <linux/input.h>
 #include <linux/input/sh_keysc.h>
+#include <linux/dma-mapping.h>
 #include <mach/sh7367.h>
 #include <mach/common.h>
 #include <asm/mach-types.h>
@@ -260,6 +261,8 @@ static struct map_desc g3evm_io_desc[] __initdata = {
 static void __init g3evm_map_io(void)
 {
         iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc));
+        /* DMA memory at 0xf6000000 - 0xffdfffff */
+        init_consistent_dma_size(158 << 20);
 
         /* setup early devices and console here as well */
         sh7367_add_early_devices();
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index 8e3c5559f27f..7719ddc5f591 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -33,6 +33,7 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/gpio.h>
+#include <linux/dma-mapping.h>
 #include <mach/sh7377.h>
 #include <mach/common.h>
 #include <asm/mach-types.h>
@@ -274,6 +275,8 @@ static struct map_desc g4evm_io_desc[] __initdata = {
 static void __init g4evm_map_io(void)
 {
         iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc));
+        /* DMA memory at 0xf6000000 - 0xffdfffff */
+        init_consistent_dma_size(158 << 20);
 
         /* setup early devices and console here as well */
         sh7377_add_early_devices();
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 17c19dc25604..de2253d7f157 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -45,6 +45,7 @@
 #include <linux/tca6416_keypad.h>
 #include <linux/usb/r8a66597.h>
 #include <linux/usb/renesas_usbhs.h>
+#include <linux/dma-mapping.h>
 
 #include <video/sh_mobile_hdmi.h>
 #include <video/sh_mobile_lcdc.h>
@@ -1381,6 +1382,8 @@ static struct map_desc mackerel_io_desc[] __initdata = {
 static void __init mackerel_map_io(void)
 {
         iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc));
+        /* DMA memory at 0xf6000000 - 0xffdfffff */
+        init_consistent_dma_size(158 << 20);
 
         /* setup early devices and console here as well */
         sh7372_add_early_devices();
diff --git a/arch/arm/mach-shmobile/include/mach/memory.h b/arch/arm/mach-shmobile/include/mach/memory.h
index ad00c3c258f4..0ffbe8155c76 100644
--- a/arch/arm/mach-shmobile/include/mach/memory.h
+++ b/arch/arm/mach-shmobile/include/mach/memory.h
@@ -4,7 +4,4 @@
 #define PLAT_PHYS_OFFSET        UL(CONFIG_MEMORY_START)
 #define MEM_SIZE        UL(CONFIG_MEMORY_SIZE)
 
-/* DMA memory at 0xf6000000 - 0xffdfffff */
-#define CONSISTENT_DMA_SIZE (158 << 20)
-
 #endif /* __ASM_MACH_MEMORY_H */
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 69006f694220..a5ff98eed1db 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -64,7 +64,7 @@ static void __init spear300_evb_init(void)
 }
 
 MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
-        .boot_params    =       0x00000100,
+        .atag_offset    =       0x100,
         .map_io         =       spear3xx_map_io,
         .init_irq       =       spear3xx_init_irq,
         .timer          =       &spear3xx_timer,
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index c8684ce1f9b3..45d180d59362 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -70,7 +70,7 @@ static void __init spear310_evb_init(void)
 }
 
 MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
-        .boot_params    =       0x00000100,
+        .atag_offset    =       0x100,
         .map_io         =       spear3xx_map_io,
         .init_irq       =       spear3xx_init_irq,
         .timer          =       &spear3xx_timer,
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index a12b353940d6..22879848d73a 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -68,7 +68,7 @@ static void __init spear320_evb_init(void)
 }
 
 MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
-        .boot_params    =       0x00000100,
+        .atag_offset    =       0x100,
         .map_io         =       spear3xx_map_io,
         .init_irq       =       spear3xx_init_irq,
         .timer          =       &spear3xx_timer,
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
index f19cefe91a2b..8238fe38e713 100644
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ b/arch/arm/mach-spear6xx/spear600_evb.c
@@ -43,7 +43,7 @@ static void __init spear600_evb_init(void)
 }
 
 MACHINE_START(SPEAR600, "ST-SPEAR600-EVB")
-        .boot_params    =       0x00000100,
+        .atag_offset    =       0x100,
         .map_io         =       spear6xx_map_io,
         .init_irq       =       spear6xx_init_irq,
         .timer          =       &spear6xx_timer,
diff --git a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
index 4cb3c2dd905c..777a5bb9eed2 100644
--- a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
+++ b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
@@ -73,7 +73,7 @@ static void __init tcc8k_map_io(void)
 }
 
 MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board")
-        .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = tcc8k_map_io,
         .init_irq       = tcc8k_init_irq,
         .init_machine   = tcc8k_init,
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index 846cd7d69e3e..a4d1980e697a 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -179,7 +179,7 @@ static void __init tegra_harmony_init(void)
 }
 
 MACHINE_START(HARMONY, "harmony")
-        .boot_params  = 0x00000100,
+        .atag_offset    = 0x100,
         .fixup          = tegra_harmony_fixup,
         .map_io         = tegra_map_common_io,
         .init_early     = tegra_init_early,
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index ea2f79c9879b..3197c4cbaa71 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -127,7 +127,7 @@ static void __init tegra_paz00_init(void)
 }
 
 MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .fixup          = tegra_paz00_fixup,
         .map_io         = tegra_map_common_io,
         .init_early     = tegra_init_early,
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index 56cbabf6aa68..9e98ac706f40 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -201,7 +201,7 @@ static void __init tegra_wario_init(void)
 
 
 MACHINE_START(SEABOARD, "seaboard")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = tegra_map_common_io,
         .init_early     = tegra_init_early,
         .init_irq       = tegra_init_irq,
@@ -210,7 +210,7 @@ MACHINE_START(SEABOARD, "seaboard")
 MACHINE_END
 
 MACHINE_START(KAEN, "kaen")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = tegra_map_common_io,
         .init_early     = tegra_init_early,
         .init_irq       = tegra_init_irq,
@@ -219,7 +219,7 @@ MACHINE_START(KAEN, "kaen")
 MACHINE_END
 
 MACHINE_START(WARIO, "wario")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = tegra_map_common_io,
         .init_early     = tegra_init_early,
         .init_irq       = tegra_init_irq,
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index 89a6d2adc1de..8489aa8f5154 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -171,7 +171,7 @@ static void __init tegra_trimslice_init(void)
 }
 
 MACHINE_START(TRIMSLICE, "trimslice")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .fixup          = tegra_trimslice_fixup,
         .map_io         = tegra_map_common_io,
         .init_early     = tegra_init_early,
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 32a7b0f7e9f7..966a5a06a58c 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -48,39 +48,12 @@ config MACH_U300_BS365
 
 endchoice
 
-choice
-        prompt "Memory configuration"
-        default MACH_U300_SINGLE_RAM
-        ---help---
-        You have to config the kernel according to the physical memory
-        configuration.
-
-config MACH_U300_SINGLE_RAM
-        bool "Single RAM"
-        help
-                Select this if you want support for Single RAM phones.
-
-config MACH_U300_DUAL_RAM
-        bool "Dual RAM"
-        help
-                Select this if you want support for Dual RAM phones.
-                This is two RAM memories on different EMIFs.
-endchoice
-
 config U300_DEBUG
         bool "Debug support for U300"
         depends on PM
         help
                 Debug support for U300 in sysfs, procfs etc.
 
-config MACH_U300_SEMI_IS_SHARED
-        bool "The SEMI is used by both the access and application side"
-        depends on MACH_U300
-        help
-                This makes it possible to use the SEMI (Shared External
-                Memory Interface) from both from access and application
-                side.
-
 config MACH_U300_SPIDUMMY
         bool "SSP/SPI dummy chip"
         select SPI
@@ -93,25 +66,6 @@ config MACH_U300_SPIDUMMY
                 you don't need it. Selecting this will activate the
                 SPI framework and ARM PL022 support.
 
-comment "All the settings below must match the bootloader's settings"
-
-config MACH_U300_ACCESS_MEM_SIZE
-       int "Access CPU memory allocation"
-       range 7 25
-       depends on MACH_U300_SINGLE_RAM
-       default 13
-       help
-                How much memory in MiB that the Access side CPU has allocated
-
-config MACH_U300_2MB_ALIGNMENT_FIX
-       bool "2MiB alignment fix"
-       depends on MACH_U300_SINGLE_RAM
-       default y
-       help
-                If yes and the Access side CPU has allocated an odd size in
-                MiB, this fix gives you one MiB extra that would otherwise be
-                lost due to Linux 2 MiB alignment policy.
-
 endmenu
 
 endif
diff --git a/arch/arm/mach-u300/Makefile.boot b/arch/arm/mach-u300/Makefile.boot
index 6fbfc6ea2d35..a06bb0deadfe 100644
--- a/arch/arm/mach-u300/Makefile.boot
+++ b/arch/arm/mach-u300/Makefile.boot
@@ -1,15 +1,4 @@
-# Note: the following conditions must always be true:
-#   ZRELADDR == virt_to_phys(TEXTADDR)
-#   PARAMS_PHYS must be within 4MB of ZRELADDR
-#   INITRD_PHYS must be in RAM
-
-ifdef CONFIG_MACH_U300_SINGLE_RAM
-     zreladdr-y := 0x28E08000
-  params_phys-y := 0x28E00100
-else
-     zreladdr-y := 0x48008000
-  params_phys-y := 0x48000100
-endif
-
+   zreladdr-y   := 0x48008000
+params_phys-y   := 0x48000100
 # This isn't used.
-#initrd_phys-y  := 0x29800000
+#initrd_phys-y  := 0x48800000
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 399c89f14dfb..724037e2de3d 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -25,6 +25,7 @@
 #include <linux/err.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/fsmc.h>
+#include <linux/dma-mapping.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -68,30 +69,13 @@ static struct map_desc u300_io_desc[] __initdata = {
                 .length         = SZ_32K,
                 .type           = MT_DEVICE,
         },
-        {
-                .virtual        = 0xffff2000, /* TCM memory */
-                .pfn            = __phys_to_pfn(0xffff2000),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        },
-
-        /*
-         * This overlaps with the IRQ vectors etc at 0xffff0000, so these
-         * may have to be moved to 0x00000000 in order to use the ROM.
-         */
-        /*
-        {
-                .virtual        = U300_BOOTROM_VIRT_BASE,
-                .pfn            = __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
-                .length         = SZ_64K,
-                .type           = MT_ROM,
-        },
-        */
 };
 
 void __init u300_map_io(void)
 {
         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
+        /* We enable a real big DMA buffer if need be. */
+        init_consistent_dma_size(SZ_4M);
 }
 
 /*
@@ -361,51 +345,6 @@ static struct resource wdog_resources[] = {
         }
 };
 
-/* TODO: These should be protected by suitable #ifdef's */
-static struct resource ave_resources[] = {
-        {
-                .name  = "AVE3e I/O Area",
-                .start = U300_VIDEOENC_BASE,
-                .end   = U300_VIDEOENC_BASE + SZ_512K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "AVE3e IRQ0",
-                .start = IRQ_U300_VIDEO_ENC_0,
-                .end   = IRQ_U300_VIDEO_ENC_0,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "AVE3e IRQ1",
-                .start = IRQ_U300_VIDEO_ENC_1,
-                .end   = IRQ_U300_VIDEO_ENC_1,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "AVE3e Physmem Area",
-                .start = 0, /* 0 will be remapped to reserved memory */
-                .end   = SZ_1M - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        /*
-         * The AVE3e requires two regions of 256MB that it considers
-         * "invisible". The hardware will not be able to access these
-         * addresses, so they should never point to system RAM.
-         */
-        {
-                .name  = "AVE3e Reserved 0",
-                .start = 0xd0000000,
-                .end   = 0xd0000000 + SZ_256M - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "AVE3e Reserved 1",
-                .start = 0xe0000000,
-                .end   = 0xe0000000 + SZ_256M - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
 static struct resource dma_resource[] = {
         {
                 .start = U300_DMAC_BASE,
@@ -1612,13 +1551,6 @@ static struct platform_device nand_device = {
         },
 };
 
-static struct platform_device ave_device = {
-        .name = "video_enc",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(ave_resources),
-        .resource = ave_resources,
-};
-
 static struct platform_device dma_device = {
         .name           = "coh901318",
         .id             = -1,
@@ -1643,10 +1575,8 @@ static struct platform_device *platform_devs[] __initdata = {
         &gpio_device,
         &nand_device,
         &wdog_device,
-        &ave_device
 };
 
-
 /*
  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
  * together so some interrupts are connected to the first one and some
@@ -1837,17 +1767,10 @@ void __init u300_init_devices(void)
         /* Register subdevices on the SPI bus */
         u300_spi_register_board_devices();
 
-#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
-        /*
-         * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
-         * both subsystems are requesting this mode.
-         * If we not share the Acc SDRAM, this is never the case. Therefore
-         * enable it here from the App side.
-         */
+        /* Enable SEMI self refresh */
         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
-#endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
 }
 
 static int core_module_init(void)
diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h
index 888e2e351ee1..c808f347a081 100644
--- a/arch/arm/mach-u300/include/mach/memory.h
+++ b/arch/arm/mach-u300/include/mach/memory.h
@@ -13,30 +13,7 @@
 #ifndef __MACH_MEMORY_H
 #define __MACH_MEMORY_H
 
-#ifdef CONFIG_MACH_U300_DUAL_RAM
-
-#define PLAT_PHYS_OFFSET                UL(0x48000000)
-#define BOOT_PARAMS_OFFSET      (PHYS_OFFSET + 0x100)
-
-#else
-
-#ifdef CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
-#define PLAT_PHYS_OFFSET (0x28000000 + \
-             (CONFIG_MACH_U300_ACCESS_MEM_SIZE - \
-             (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024)
-#else
-#define PLAT_PHYS_OFFSET (0x28000000 + \
-             (CONFIG_MACH_U300_ACCESS_MEM_SIZE +        \
-             (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024)
-#endif
-#define BOOT_PARAMS_OFFSET (0x28000000 + \
-            (CONFIG_MACH_U300_ACCESS_MEM_SIZE +         \
-            (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024 + 0x100)
-#endif
-
-/*
- * We enable a real big DMA buffer if need be.
- */
-#define CONSISTENT_DMA_SIZE SZ_4M
+#define PLAT_PHYS_OFFSET        UL(0x48000000)
+#define BOOT_PARAMS_OFFSET      0x100
 
 #endif
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
index 48b3b7f39966..89422ee7f3a8 100644
--- a/arch/arm/mach-u300/u300.c
+++ b/arch/arm/mach-u300/u300.c
@@ -23,21 +23,6 @@
 #include <asm/mach/arch.h>
 #include <asm/memory.h>
 
-static void __init u300_reserve(void)
-{
-        /*
-         * U300 - This platform family can share physical memory
-         * between two ARM cpus, one running Linux and the other
-         * running another OS.
-         */
-#ifdef CONFIG_MACH_U300_SINGLE_RAM
-#if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) && \
-        CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
-        memblock_reserve(PHYS_OFFSET, 0x00100000);
-#endif
-#endif
-}
-
 static void __init u300_init_machine(void)
 {
         u300_init_devices();
@@ -61,9 +46,8 @@ static void __init u300_init_machine(void)
 
 MACHINE_START(U300, MACH_U300_STRING)
         /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
-        .boot_params    = BOOT_PARAMS_OFFSET,
+        .atag_offset    = BOOT_PARAMS_OFFSET,
         .map_io         = u300_map_io,
-        .reserve        = u300_reserve,
         .init_irq       = u300_init_irq,
         .timer          = &u300_timer,
         .init_machine   = u300_init_machine,
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 4210cb434dbc..a3e0c8692f0d 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -6,6 +6,7 @@ config UX500_SOC_COMMON
         select ARM_GIC
         select HAS_MTU
         select ARM_ERRATA_753970
+        select ARM_ERRATA_754322
 
 menu "Ux500 SoC"
 
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 1694916e6822..9fd00a6d4248 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -4,6 +4,7 @@
 
 obj-y                           := clock.o cpu.o devices.o devices-common.o \
                                    id.o usb.o
+obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
 obj-$(CONFIG_UX500_SOC_DB5500)  += cpu-db5500.o dma-db5500.o
 obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o
 obj-$(CONFIG_MACH_U8500)        += board-mop500.o board-mop500-sdi.o \
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index f26fd76f72b4..4108c7bf324e 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -153,7 +153,7 @@ static pin_cfg_t mop500_pins_default[] = {
         GPIO7_U1_RTSn   | PIN_OUTPUT_HIGH,
 };
 
-static pin_cfg_t mop500_pins_hrefv60[] = {
+static pin_cfg_t hrefv60_pins[] = {
         /* WLAN */
         GPIO4_GPIO              | PIN_INPUT_PULLUP,/* WLAN_IRQ */
         GPIO85_GPIO             | PIN_OUTPUT_LOW,/* WLAN_ENA */
@@ -279,14 +279,26 @@ static pin_cfg_t snowball_pins[] = {
 void __init mop500_pins_init(void)
 {
         nmk_config_pins(mop500_pins_common,
-                                ARRAY_SIZE(mop500_pins_common));
-        if (machine_is_hrefv60())
-                nmk_config_pins(mop500_pins_hrefv60,
-                                ARRAY_SIZE(mop500_pins_hrefv60));
-        else if (machine_is_snowball())
-                nmk_config_pins(snowball_pins,
-                                ARRAY_SIZE(snowball_pins));
-        else
-                nmk_config_pins(mop500_pins_default,
-                                ARRAY_SIZE(mop500_pins_default));
+                        ARRAY_SIZE(mop500_pins_common));
+
+        nmk_config_pins(mop500_pins_default,
+                        ARRAY_SIZE(mop500_pins_default));
+}
+
+void __init snowball_pins_init(void)
+{
+        nmk_config_pins(mop500_pins_common,
+                        ARRAY_SIZE(mop500_pins_common));
+
+        nmk_config_pins(snowball_pins,
+                        ARRAY_SIZE(snowball_pins));
+}
+
+void __init hrefv60_pins_init(void)
+{
+        nmk_config_pins(mop500_pins_common,
+                        ARRAY_SIZE(mop500_pins_common));
+
+        nmk_config_pins(hrefv60_pins,
+                        ARRAY_SIZE(hrefv60_pins));
 }
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index d0cb9e5eb87c..6826faeecc68 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -216,30 +216,48 @@ void __init mop500_sdi_init(void)
         /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
         if (!cpu_is_u8500v10())
                 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
-        /* sdi2 on snowball is in ATL_B mode for FSMC (LAN) */
-        if (!machine_is_snowball())
-                db8500_add_sdi2(&mop500_sdi2_data, periphid);
+
+        db8500_add_sdi2(&mop500_sdi2_data, periphid);
 
         /* On-board eMMC */
         db8500_add_sdi4(&mop500_sdi4_data, periphid);
 
-        if (machine_is_hrefv60() || machine_is_snowball()) {
-                if (machine_is_hrefv60()) {
-                        mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
-                        sdi0_en = HREFV60_SDMMC_EN_GPIO;
-                        sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
-                } else if (machine_is_snowball()) {
-                        mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
-                        mop500_sdi0_data.cd_invert = true;
-                        sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
-                        sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO;
-                }
-                sdi0_configure();
-        }
-
         /*
          * On boards with the TC35892 GPIO expander, sdi0 will finally
          * be added when the TC35892 initializes and calls
          * mop500_sdi_tc35892_init() above.
          */
 }
+
+void __init snowball_sdi_init(void)
+{
+        u32 periphid = 0x10480180;
+
+        mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
+
+        /* On-board eMMC */
+        db8500_add_sdi4(&mop500_sdi4_data, periphid);
+
+        mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
+        mop500_sdi0_data.cd_invert = true;
+        sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
+        sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO;
+        sdi0_configure();
+}
+
+void __init hrefv60_sdi_init(void)
+{
+        u32 periphid = 0x10480180;
+
+        mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
+
+        db8500_add_sdi2(&mop500_sdi2_data, periphid);
+
+        /* On-board eMMC */
+        db8500_add_sdi4(&mop500_sdi4_data, periphid);
+
+        mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
+        sdi0_en = HREFV60_SDMMC_EN_GPIO;
+        sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
+        sdi0_configure();
+}
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index cd54abaccd96..4810968b672c 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -603,28 +603,72 @@ static void __init mop500_init_machine(void)
 {
         int i2c0_devs;
 
+        mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
+
+        u8500_init_devices();
+
+        mop500_pins_init();
+
+        platform_add_devices(mop500_platform_devs,
+                        ARRAY_SIZE(mop500_platform_devs));
+
+        mop500_i2c_init();
+        mop500_sdi_init();
+        mop500_spi_init();
+        mop500_uart_init();
+
+        i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
+
+        i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
+        i2c_register_board_info(2, mop500_i2c2_devices,
+                                ARRAY_SIZE(mop500_i2c2_devices));
+
+        /* This board has full regulator constraints */
+        regulator_has_full_constraints();
+}
+
+static void __init snowball_init_machine(void)
+{
+        int i2c0_devs;
+
+        u8500_init_devices();
+
+        snowball_pins_init();
+
+        platform_add_devices(snowball_platform_devs,
+                        ARRAY_SIZE(snowball_platform_devs));
+
+        mop500_i2c_init();
+        snowball_sdi_init();
+        mop500_spi_init();
+        mop500_uart_init();
+
+        i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
+        i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
+        i2c_register_board_info(2, mop500_i2c2_devices,
+                                ARRAY_SIZE(mop500_i2c2_devices));
+
+        /* This board has full regulator constraints */
+        regulator_has_full_constraints();
+}
+
+static void __init hrefv60_init_machine(void)
+{
+        int i2c0_devs;
+
         /*
          * The HREFv60 board removed a GPIO expander and routed
          * all these GPIO pins to the internal GPIO controller
          * instead.
          */
-        if (!machine_is_snowball()) {
-                if (machine_is_hrefv60())
-                        mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
-                else
-                        mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
-        }
+        mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
 
         u8500_init_devices();
 
-        mop500_pins_init();
+        hrefv60_pins_init();
 
-        if (machine_is_snowball())
-                platform_add_devices(snowball_platform_devs,
-                                        ARRAY_SIZE(snowball_platform_devs));
-        else
-                platform_add_devices(mop500_platform_devs,
-                                        ARRAY_SIZE(mop500_platform_devs));
+        platform_add_devices(mop500_platform_devs,
+                        ARRAY_SIZE(mop500_platform_devs));
 
         mop500_i2c_init();
         mop500_sdi_init();
@@ -632,8 +676,8 @@ static void __init mop500_init_machine(void)
         mop500_uart_init();
 
         i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
-        if (machine_is_hrefv60())
-                i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
+
+        i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
 
         i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
         i2c_register_board_info(2, mop500_i2c2_devices,
@@ -645,7 +689,7 @@ static void __init mop500_init_machine(void)
 
 MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
         /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */
-        .boot_params    = 0x100,
+        .atag_offset    = 0x100,
         .map_io         = u8500_map_io,
         .init_irq       = ux500_init_irq,
         /* we re-use nomadik timer here */
@@ -654,18 +698,18 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
 MACHINE_END
 
 MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
-        .boot_params    = 0x100,
+        .atag_offset    = 0x100,
         .map_io         = u8500_map_io,
         .init_irq       = ux500_init_irq,
         .timer          = &ux500_timer,
-        .init_machine   = mop500_init_machine,
+        .init_machine   = hrefv60_init_machine,
 MACHINE_END
 
 MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
-        .boot_params    = 0x100,
+        .atag_offset    = 0x100,
         .map_io         = u8500_map_io,
         .init_irq       = ux500_init_irq,
         /* we re-use nomadik timer here */
         .timer          = &ux500_timer,
-        .init_machine   = mop500_init_machine,
+        .init_machine   = snowball_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index ee77a8970c33..de18a2a23e6e 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -40,10 +40,13 @@
 struct i2c_board_info;
 
 extern void mop500_sdi_init(void);
+extern void snowball_sdi_init(void);
 extern void mop500_sdi_tc35892_init(void);
 void __init mop500_u8500uib_init(void);
 void __init mop500_stuib_init(void);
 void __init mop500_pins_init(void);
+void __init hrefv60_pins_init(void);
+void __init snowball_pins_init(void);
 
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
                 unsigned n);
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
index e58f0f562426..166d47a5f4f3 100644
--- a/arch/arm/mach-ux500/board-u5500.c
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -118,7 +118,7 @@ static void __init u5500_init_machine(void)
 }
 
 MACHINE_START(U5500, "ST-Ericsson U5500 Platform")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = u5500_map_io,
         .init_irq       = ux500_init_irq,
         .timer          = &ux500_timer,
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
new file mode 100644
index 000000000000..122ddde00ba7
--- /dev/null
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2011
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/io.h>
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <mach/hardware.h>
+#include <mach/id.h>
+
+static void __iomem *l2x0_base;
+
+static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
+{
+        /* wait for the operation to complete */
+        while (readl_relaxed(reg) & mask)
+                cpu_relax();
+}
+
+static inline void ux500_cache_sync(void)
+{
+        writel_relaxed(0, l2x0_base + L2X0_CACHE_SYNC);
+        ux500_cache_wait(l2x0_base + L2X0_CACHE_SYNC, 1);
+}
+
+/*
+ * The L2 cache cannot be turned off in the non-secure world.
+ * Dummy until a secure service is in place.
+ */
+static void ux500_l2x0_disable(void)
+{
+}
+
+/*
+ * This is only called when doing a kexec, just after turning off the L2
+ * and L1 cache, and it is surrounded by a spinlock in the generic version.
+ * However, we're not really turning off the L2 cache right now and the
+ * PL310 does not support exclusive accesses (used to implement the spinlock).
+ * So, the invalidation needs to be done without the spinlock.
+ */
+static void ux500_l2x0_inv_all(void)
+{
+        uint32_t l2x0_way_mask = (1<<16) - 1;   /* Bitmask of active ways */
+
+        /* invalidate all ways */
+        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
+        ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
+        ux500_cache_sync();
+}
+
+static int __init ux500_l2x0_unlock(void)
+{
+        int i;
+
+        /*
+         * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
+         * apparently locks both caches before jumping to the kernel. The
+         * l2x0 core will not touch the unlock registers if the l2x0 is
+         * already enabled, so we do it right here instead. The PL310 has
+         * 8 sets of registers, one per possible CPU.
+         */
+        for (i = 0; i < 8; i++) {
+                writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
+                               i * L2X0_LOCKDOWN_STRIDE);
+                writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
+                               i * L2X0_LOCKDOWN_STRIDE);
+        }
+        return 0;
+}
+
+static int __init ux500_l2x0_init(void)
+{
+        if (cpu_is_u5500())
+                l2x0_base = __io_address(U5500_L2CC_BASE);
+        else if (cpu_is_u8500())
+                l2x0_base = __io_address(U8500_L2CC_BASE);
+        else
+                ux500_unknown_soc();
+
+        /* Unlock before init */
+        ux500_l2x0_unlock();
+
+        /* 64KB way size, 8 way associativity, force WA */
+        l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
+
+        /* Override invalidate function */
+        outer_cache.disable = ux500_l2x0_disable;
+        outer_cache.inv_all = ux500_l2x0_inv_all;
+
+        return 0;
+}
+
+early_initcall(ux500_l2x0_init);
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 1da23bb87c16..252e8b3c5706 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -11,8 +11,6 @@
 #include <linux/mfd/db8500-prcmu.h>
 #include <linux/mfd/db5500-prcmu.h>
 
-#include <asm/cacheflush.h>
-#include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
 #include <asm/localtimer.h>
@@ -26,10 +24,6 @@
 
 void __iomem *_PRCMU_BASE;
 
-#ifdef CONFIG_CACHE_L2X0
-static void __iomem *l2x0_base;
-#endif
-
 void __init ux500_init_irq(void)
 {
         void __iomem *dist_base;
@@ -57,69 +51,6 @@ void __init ux500_init_irq(void)
         clk_init();
 }
 
-#ifdef CONFIG_CACHE_L2X0
-static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
-{
-        /* wait for the operation to complete */
-        while (readl_relaxed(reg) & mask)
-                ;
-}
-
-static inline void ux500_cache_sync(void)
-{
-        void __iomem *base = l2x0_base;
-
-        writel_relaxed(0, base + L2X0_CACHE_SYNC);
-        ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
-}
-
-/*
- * The L2 cache cannot be turned off in the non-secure world.
- * Dummy until a secure service is in place.
- */
-static void ux500_l2x0_disable(void)
-{
-}
-
-/*
- * This is only called when doing a kexec, just after turning off the L2
- * and L1 cache, and it is surrounded by a spinlock in the generic version.
- * However, we're not really turning off the L2 cache right now and the
- * PL310 does not support exclusive accesses (used to implement the spinlock).
- * So, the invalidation needs to be done without the spinlock.
- */
-static void ux500_l2x0_inv_all(void)
-{
-        void __iomem *base = l2x0_base;
-        uint32_t l2x0_way_mask = (1<<16) - 1;   /* Bitmask of active ways */
-
-        /* invalidate all ways */
-        writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY);
-        ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask);
-        ux500_cache_sync();
-}
-
-static int ux500_l2x0_init(void)
-{
-        if (cpu_is_u5500())
-                l2x0_base = __io_address(U5500_L2CC_BASE);
-        else if (cpu_is_u8500())
-                l2x0_base = __io_address(U8500_L2CC_BASE);
-        else
-                ux500_unknown_soc();
-
-        /* 64KB way size, 8 way associativity, force WA */
-        l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
-
-        /* Override invalidate function */
-        outer_cache.disable = ux500_l2x0_disable;
-        outer_cache.inv_all = ux500_l2x0_inv_all;
-
-        return 0;
-}
-early_initcall(ux500_l2x0_init);
-#endif
-
 static void __init ux500_timer_init(void)
 {
 #ifdef CONFIG_LOCAL_TIMERS
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 7dd08074c37b..6fb3c4b0105d 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -51,15 +51,9 @@ static void flush(void)
 static inline void arch_decomp_setup(void)
 {
         /* Check in run time if we run on an U8500 or U5500 */
-        if (machine_is_u8500() ||
-            machine_is_svp8500v1() ||
-            machine_is_svp8500v2() ||
-            machine_is_hrefv60()   ||
-            machine_is_snowball())
-                ux500_uart_base = U8500_UART2_BASE;
-        else if (machine_is_u5500())
+        if (machine_is_u5500())
                 ux500_uart_base = U5500_UART0_BASE;
-        else /* not much can be done to help here */
+        else
                 ux500_uart_base = U8500_UART2_BASE;
 }
 
diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h
index f923764ee16c..8b1d1a7a679e 100644
--- a/arch/arm/mach-ux500/pins-db8500.h
+++ b/arch/arm/mach-ux500/pins-db8500.h
@@ -35,40 +35,40 @@
 
 #define GPIO4_GPIO              PIN_CFG(4, GPIO)
 #define GPIO4_U1_RXD            PIN_CFG(4, ALT_A)
-#define GPIO4_I2C4_SCL          PIN_CFG_PULL(4, ALT_B, UP)
+#define GPIO4_I2C4_SCL          PIN_CFG_INPUT(4, ALT_B, PULLUP)
 #define GPIO4_IP_TRSTn          PIN_CFG(4, ALT_C)
 
 #define GPIO5_GPIO              PIN_CFG(5, GPIO)
 #define GPIO5_U1_TXD            PIN_CFG(5, ALT_A)
-#define GPIO5_I2C4_SDA          PIN_CFG_PULL(5, ALT_B, UP)
+#define GPIO5_I2C4_SDA          PIN_CFG_INPUT(5, ALT_B, PULLUP)
 #define GPIO5_IP_GPIO6          PIN_CFG(5, ALT_C)
 
 #define GPIO6_GPIO              PIN_CFG(6, GPIO)
 #define GPIO6_U1_CTSn           PIN_CFG(6, ALT_A)
-#define GPIO6_I2C1_SCL          PIN_CFG_PULL(6, ALT_B, UP)
+#define GPIO6_I2C1_SCL          PIN_CFG_INPUT(6, ALT_B, PULLUP)
 #define GPIO6_IP_GPIO0          PIN_CFG(6, ALT_C)
 
 #define GPIO7_GPIO              PIN_CFG(7, GPIO)
 #define GPIO7_U1_RTSn           PIN_CFG(7, ALT_A)
-#define GPIO7_I2C1_SDA          PIN_CFG_PULL(7, ALT_B, UP)
+#define GPIO7_I2C1_SDA          PIN_CFG_INPUT(7, ALT_B, PULLUP)
 #define GPIO7_IP_GPIO1          PIN_CFG(7, ALT_C)
 
 #define GPIO8_GPIO              PIN_CFG(8, GPIO)
-#define GPIO8_IPI2C_SDA         PIN_CFG_PULL(8, ALT_A, UP)
-#define GPIO8_I2C2_SDA          PIN_CFG_PULL(8, ALT_B, UP)
+#define GPIO8_IPI2C_SDA         PIN_CFG_INPUT(8, ALT_A, PULLUP)
+#define GPIO8_I2C2_SDA          PIN_CFG_INPUT(8, ALT_B, PULLUP)
 
 #define GPIO9_GPIO              PIN_CFG(9, GPIO)
-#define GPIO9_IPI2C_SCL         PIN_CFG_PULL(9, ALT_A, UP)
-#define GPIO9_I2C2_SCL          PIN_CFG_PULL(9, ALT_B, UP)
+#define GPIO9_IPI2C_SCL         PIN_CFG_INPUT(9, ALT_A, PULLUP)
+#define GPIO9_I2C2_SCL          PIN_CFG_INPUT(9, ALT_B, PULLUP)
 
 #define GPIO10_GPIO             PIN_CFG(10, GPIO)
-#define GPIO10_IPI2C_SDA        PIN_CFG_PULL(10, ALT_A, UP)
-#define GPIO10_I2C2_SDA         PIN_CFG_PULL(10, ALT_B, UP)
+#define GPIO10_IPI2C_SDA        PIN_CFG_INPUT(10, ALT_A, PULLUP)
+#define GPIO10_I2C2_SDA         PIN_CFG_INPUT(10, ALT_B, PULLUP)
 #define GPIO10_IP_GPIO3         PIN_CFG(10, ALT_C)
 
 #define GPIO11_GPIO             PIN_CFG(11, GPIO)
-#define GPIO11_IPI2C_SCL        PIN_CFG_PULL(11, ALT_A, UP)
-#define GPIO11_I2C2_SCL         PIN_CFG_PULL(11, ALT_B, UP)
+#define GPIO11_IPI2C_SCL        PIN_CFG_INPUT(11, ALT_A, PULLUP)
+#define GPIO11_I2C2_SCL         PIN_CFG_INPUT(11, ALT_B, PULLUP)
 #define GPIO11_IP_GPIO2         PIN_CFG(11, ALT_C)
 
 #define GPIO12_GPIO             PIN_CFG(12, GPIO)
@@ -87,66 +87,66 @@
 
 #define GPIO16_GPIO             PIN_CFG(16, GPIO)
 #define GPIO16_MSP0_RFS         PIN_CFG(16, ALT_A)
-#define GPIO16_I2C1_SCL         PIN_CFG_PULL(16, ALT_B, UP)
+#define GPIO16_I2C1_SCL         PIN_CFG_INPUT(16, ALT_B, PULLUP)
 #define GPIO16_SLIM0_DAT        PIN_CFG(16, ALT_C)
 
 #define GPIO17_GPIO             PIN_CFG(17, GPIO)
 #define GPIO17_MSP0_RCK         PIN_CFG(17, ALT_A)
-#define GPIO17_I2C1_SDA         PIN_CFG_PULL(17, ALT_B, UP)
+#define GPIO17_I2C1_SDA         PIN_CFG_INPUT(17, ALT_B, PULLUP)
 #define GPIO17_SLIM0_CLK        PIN_CFG(17, ALT_C)
 
 #define GPIO18_GPIO             PIN_CFG(18, GPIO)
-#define GPIO18_MC0_CMDDIR       PIN_CFG_PULL(18, ALT_A, UP)
+#define GPIO18_MC0_CMDDIR       PIN_CFG_INPUT(18, ALT_A, PULLUP)
 #define GPIO18_U2_RXD           PIN_CFG(18, ALT_B)
 #define GPIO18_MS_IEP           PIN_CFG(18, ALT_C)
 
 #define GPIO19_GPIO             PIN_CFG(19, GPIO)
-#define GPIO19_MC0_DAT0DIR      PIN_CFG_PULL(19, ALT_A, UP)
+#define GPIO19_MC0_DAT0DIR      PIN_CFG_INPUT(19, ALT_A, PULLUP)
 #define GPIO19_U2_TXD           PIN_CFG(19, ALT_B)
 #define GPIO19_MS_DAT0DIR       PIN_CFG(19, ALT_C)
 
 #define GPIO20_GPIO             PIN_CFG(20, GPIO)
-#define GPIO20_MC0_DAT2DIR      PIN_CFG_PULL(20, ALT_A, UP)
+#define GPIO20_MC0_DAT2DIR      PIN_CFG_INPUT(20, ALT_A, PULLUP)
 #define GPIO20_UARTMOD_TXD      PIN_CFG(20, ALT_B)
 #define GPIO20_IP_TRIGOUT       PIN_CFG(20, ALT_C)
 
 #define GPIO21_GPIO             PIN_CFG(21, GPIO)
-#define GPIO21_MC0_DAT31DIR     PIN_CFG_PULL(21, ALT_A, UP)
+#define GPIO21_MC0_DAT31DIR     PIN_CFG_INPUT(21, ALT_A, PULLUP)
 #define GPIO21_MSP0_SCK         PIN_CFG(21, ALT_B)
 #define GPIO21_MS_DAT31DIR      PIN_CFG(21, ALT_C)
 
 #define GPIO22_GPIO             PIN_CFG(22, GPIO)
-#define GPIO22_MC0_FBCLK        PIN_CFG_PULL(22, ALT_A, UP)
+#define GPIO22_MC0_FBCLK        PIN_CFG_INPUT(22, ALT_A, PULLUP)
 #define GPIO22_UARTMOD_RXD      PIN_CFG(22, ALT_B)
 #define GPIO22_MS_FBCLK         PIN_CFG(22, ALT_C)
 
 #define GPIO23_GPIO             PIN_CFG(23, GPIO)
-#define GPIO23_MC0_CLK          PIN_CFG_PULL(23, ALT_A, UP)
+#define GPIO23_MC0_CLK          PIN_CFG_INPUT(23, ALT_A, PULLUP)
 #define GPIO23_STMMOD_CLK       PIN_CFG(23, ALT_B)
 #define GPIO23_MS_CLK           PIN_CFG(23, ALT_C)
 
 #define GPIO24_GPIO             PIN_CFG(24, GPIO)
-#define GPIO24_MC0_CMD          PIN_CFG_PULL(24, ALT_A, UP)
+#define GPIO24_MC0_CMD          PIN_CFG_INPUT(24, ALT_A, PULLUP)
 #define GPIO24_UARTMOD_RXD      PIN_CFG(24, ALT_B)
 #define GPIO24_MS_BS            PIN_CFG(24, ALT_C)
 
 #define GPIO25_GPIO             PIN_CFG(25, GPIO)
-#define GPIO25_MC0_DAT0         PIN_CFG_PULL(25, ALT_A, UP)
+#define GPIO25_MC0_DAT0         PIN_CFG_INPUT(25, ALT_A, PULLUP)
 #define GPIO25_STMMOD_DAT0      PIN_CFG(25, ALT_B)
 #define GPIO25_MS_DAT0          PIN_CFG(25, ALT_C)
 
 #define GPIO26_GPIO             PIN_CFG(26, GPIO)
-#define GPIO26_MC0_DAT1         PIN_CFG_PULL(26, ALT_A, UP)
+#define GPIO26_MC0_DAT1         PIN_CFG_INPUT(26, ALT_A, PULLUP)
 #define GPIO26_STMMOD_DAT1      PIN_CFG(26, ALT_B)
 #define GPIO26_MS_DAT1          PIN_CFG(26, ALT_C)
 
 #define GPIO27_GPIO             PIN_CFG(27, GPIO)
-#define GPIO27_MC0_DAT2         PIN_CFG_PULL(27, ALT_A, UP)
+#define GPIO27_MC0_DAT2         PIN_CFG_INPUT(27, ALT_A, PULLUP)
 #define GPIO27_STMMOD_DAT2      PIN_CFG(27, ALT_B)
 #define GPIO27_MS_DAT2          PIN_CFG(27, ALT_C)
 
 #define GPIO28_GPIO             PIN_CFG(28, GPIO)
-#define GPIO28_MC0_DAT3         PIN_CFG_PULL(28, ALT_A, UP)
+#define GPIO28_MC0_DAT3         PIN_CFG_INPUT(28, ALT_A, PULLUP)
 #define GPIO28_STMMOD_DAT3      PIN_CFG(28, ALT_B)
 #define GPIO28_MS_DAT3          PIN_CFG(28, ALT_C)
 
@@ -357,48 +357,48 @@
 #define GPIO97_MC5_DAT7         PIN_CFG(97, ALT_C)
 
 #define GPIO128_GPIO            PIN_CFG(128, GPIO)
-#define GPIO128_MC2_CLK         PIN_CFG_PULL(128, ALT_A, UP)
+#define GPIO128_MC2_CLK         PIN_CFG_INPUT(128, ALT_A, PULLUP)
 #define GPIO128_SM_CKO          PIN_CFG(128, ALT_B)
 
 #define GPIO129_GPIO            PIN_CFG(129, GPIO)
-#define GPIO129_MC2_CMD         PIN_CFG_PULL(129, ALT_A, UP)
+#define GPIO129_MC2_CMD         PIN_CFG_INPUT(129, ALT_A, PULLUP)
 #define GPIO129_SM_WAIT0n       PIN_CFG(129, ALT_B)
 
 #define GPIO130_GPIO            PIN_CFG(130, GPIO)
-#define GPIO130_MC2_FBCLK       PIN_CFG_PULL(130, ALT_A, UP)
+#define GPIO130_MC2_FBCLK       PIN_CFG_INPUT(130, ALT_A, PULLUP)
 #define GPIO130_SM_FBCLK        PIN_CFG(130, ALT_B)
 #define GPIO130_MC2_RSTN        PIN_CFG(130, ALT_C)
 
 #define GPIO131_GPIO            PIN_CFG(131, GPIO)
-#define GPIO131_MC2_DAT0        PIN_CFG_PULL(131, ALT_A, UP)
+#define GPIO131_MC2_DAT0        PIN_CFG_INPUT(131, ALT_A, PULLUP)
 #define GPIO131_SM_ADQ8         PIN_CFG(131, ALT_B)
 
 #define GPIO132_GPIO            PIN_CFG(132, GPIO)
-#define GPIO132_MC2_DAT1        PIN_CFG_PULL(132, ALT_A, UP)
+#define GPIO132_MC2_DAT1        PIN_CFG_INPUT(132, ALT_A, PULLUP)
 #define GPIO132_SM_ADQ9         PIN_CFG(132, ALT_B)
 
 #define GPIO133_GPIO            PIN_CFG(133, GPIO)
-#define GPIO133_MC2_DAT2        PIN_CFG_PULL(133, ALT_A, UP)
+#define GPIO133_MC2_DAT2        PIN_CFG_INPUT(133, ALT_A, PULLUP)
 #define GPIO133_SM_ADQ10        PIN_CFG(133, ALT_B)
 
 #define GPIO134_GPIO            PIN_CFG(134, GPIO)
-#define GPIO134_MC2_DAT3        PIN_CFG_PULL(134, ALT_A, UP)
+#define GPIO134_MC2_DAT3        PIN_CFG_INPUT(134, ALT_A, PULLUP)
 #define GPIO134_SM_ADQ11        PIN_CFG(134, ALT_B)
 
 #define GPIO135_GPIO            PIN_CFG(135, GPIO)
-#define GPIO135_MC2_DAT4        PIN_CFG_PULL(135, ALT_A, UP)
+#define GPIO135_MC2_DAT4        PIN_CFG_INPUT(135, ALT_A, PULLUP)
 #define GPIO135_SM_ADQ12        PIN_CFG(135, ALT_B)
 
 #define GPIO136_GPIO            PIN_CFG(136, GPIO)
-#define GPIO136_MC2_DAT5        PIN_CFG_PULL(136, ALT_A, UP)
+#define GPIO136_MC2_DAT5        PIN_CFG_INPUT(136, ALT_A, PULLUP)
 #define GPIO136_SM_ADQ13        PIN_CFG(136, ALT_B)
 
 #define GPIO137_GPIO            PIN_CFG(137, GPIO)
-#define GPIO137_MC2_DAT6        PIN_CFG_PULL(137, ALT_A, UP)
+#define GPIO137_MC2_DAT6        PIN_CFG_INPUT(137, ALT_A, PULLUP)
 #define GPIO137_SM_ADQ14        PIN_CFG(137, ALT_B)
 
 #define GPIO138_GPIO            PIN_CFG(138, GPIO)
-#define GPIO138_MC2_DAT7        PIN_CFG_PULL(138, ALT_A, UP)
+#define GPIO138_MC2_DAT7        PIN_CFG_INPUT(138, ALT_A, PULLUP)
 #define GPIO138_SM_ADQ15        PIN_CFG(138, ALT_B)
 
 #define GPIO139_GPIO            PIN_CFG(139, GPIO)
@@ -434,10 +434,10 @@
 #define GPIO146_SSP0_TXD        PIN_CFG(146, ALT_A)
 
 #define GPIO147_GPIO            PIN_CFG(147, GPIO)
-#define GPIO147_I2C0_SCL        PIN_CFG_PULL(147, ALT_A, UP)
+#define GPIO147_I2C0_SCL        PIN_CFG_INPUT(147, ALT_A, PULLUP)
 
 #define GPIO148_GPIO            PIN_CFG(148, GPIO)
-#define GPIO148_I2C0_SDA        PIN_CFG_PULL(148, ALT_A, UP)
+#define GPIO148_I2C0_SDA        PIN_CFG_INPUT(148, ALT_A, PULLUP)
 
 #define GPIO149_GPIO            PIN_CFG(149, GPIO)
 #define GPIO149_IP_GPIO0        PIN_CFG(149, ALT_A)
@@ -459,82 +459,82 @@
 #define GPIO152_KP_O9           PIN_CFG(152, ALT_C)
 
 #define GPIO153_GPIO            PIN_CFG(153, GPIO)
-#define GPIO153_KP_I7           PIN_CFG_PULL(153, ALT_A, DOWN)
+#define GPIO153_KP_I7           PIN_CFG_INPUT(153, ALT_A, PULLDOWN)
 #define GPIO153_LCD_D24         PIN_CFG(153, ALT_B)
 #define GPIO153_U2_RXD          PIN_CFG(153, ALT_C)
 
 #define GPIO154_GPIO            PIN_CFG(154, GPIO)
-#define GPIO154_KP_I6           PIN_CFG_PULL(154, ALT_A, DOWN)
+#define GPIO154_KP_I6           PIN_CFG_INPUT(154, ALT_A, PULLDOWN)
 #define GPIO154_LCD_D25         PIN_CFG(154, ALT_B)
 #define GPIO154_U2_TXD          PIN_CFG(154, ALT_C)
 
 #define GPIO155_GPIO            PIN_CFG(155, GPIO)
-#define GPIO155_KP_I5           PIN_CFG_PULL(155, ALT_A, DOWN)
+#define GPIO155_KP_I5           PIN_CFG_INPUT(155, ALT_A, PULLDOWN)
 #define GPIO155_LCD_D26         PIN_CFG(155, ALT_B)
 #define GPIO155_STMAPE_CLK      PIN_CFG(155, ALT_C)
 
 #define GPIO156_GPIO            PIN_CFG(156, GPIO)
-#define GPIO156_KP_I4           PIN_CFG_PULL(156, ALT_A, DOWN)
+#define GPIO156_KP_I4           PIN_CFG_INPUT(156, ALT_A, PULLDOWN)
 #define GPIO156_LCD_D27         PIN_CFG(156, ALT_B)
 #define GPIO156_STMAPE_DAT3     PIN_CFG(156, ALT_C)
 
 #define GPIO157_GPIO            PIN_CFG(157, GPIO)
-#define GPIO157_KP_O7           PIN_CFG_PULL(157, ALT_A, UP)
+#define GPIO157_KP_O7           PIN_CFG_INPUT(157, ALT_A, PULLUP)
 #define GPIO157_LCD_D28         PIN_CFG(157, ALT_B)
 #define GPIO157_STMAPE_DAT2     PIN_CFG(157, ALT_C)
 
 #define GPIO158_GPIO            PIN_CFG(158, GPIO)
-#define GPIO158_KP_O6           PIN_CFG_PULL(158, ALT_A, UP)
+#define GPIO158_KP_O6           PIN_CFG_INPUT(158, ALT_A, PULLUP)
 #define GPIO158_LCD_D29         PIN_CFG(158, ALT_B)
 #define GPIO158_STMAPE_DAT1     PIN_CFG(158, ALT_C)
 
 #define GPIO159_GPIO            PIN_CFG(159, GPIO)
-#define GPIO159_KP_O5           PIN_CFG_PULL(159, ALT_A, UP)
+#define GPIO159_KP_O5           PIN_CFG_INPUT(159, ALT_A, PULLUP)
 #define GPIO159_LCD_D30         PIN_CFG(159, ALT_B)
 #define GPIO159_STMAPE_DAT0     PIN_CFG(159, ALT_C)
 
 #define GPIO160_GPIO            PIN_CFG(160, GPIO)
-#define GPIO160_KP_O4           PIN_CFG_PULL(160, ALT_A, UP)
+#define GPIO160_KP_O4           PIN_CFG_INPUT(160, ALT_A, PULLUP)
 #define GPIO160_LCD_D31         PIN_CFG(160, ALT_B)
 #define GPIO160_NONE            PIN_CFG(160, ALT_C)
 
 #define GPIO161_GPIO            PIN_CFG(161, GPIO)
-#define GPIO161_KP_I3           PIN_CFG_PULL(161, ALT_A, DOWN)
+#define GPIO161_KP_I3           PIN_CFG_INPUT(161, ALT_A, PULLDOWN)
 #define GPIO161_LCD_D32         PIN_CFG(161, ALT_B)
 #define GPIO161_UARTMOD_RXD     PIN_CFG(161, ALT_C)
 
 #define GPIO162_GPIO            PIN_CFG(162, GPIO)
-#define GPIO162_KP_I2           PIN_CFG_PULL(162, ALT_A, DOWN)
+#define GPIO162_KP_I2           PIN_CFG_INPUT(162, ALT_A, PULLDOWN)
 #define GPIO162_LCD_D33         PIN_CFG(162, ALT_B)
 #define GPIO162_UARTMOD_TXD     PIN_CFG(162, ALT_C)
 
 #define GPIO163_GPIO            PIN_CFG(163, GPIO)
-#define GPIO163_KP_I1           PIN_CFG_PULL(163, ALT_A, DOWN)
+#define GPIO163_KP_I1           PIN_CFG_INPUT(163, ALT_A, PULLDOWN)
 #define GPIO163_LCD_D34         PIN_CFG(163, ALT_B)
 #define GPIO163_STMMOD_CLK      PIN_CFG(163, ALT_C)
 
 #define GPIO164_GPIO            PIN_CFG(164, GPIO)
-#define GPIO164_KP_I0           PIN_CFG_PULL(164, ALT_A, UP)
+#define GPIO164_KP_I0           PIN_CFG_INPUT(164, ALT_A, PULLUP)
 #define GPIO164_LCD_D35         PIN_CFG(164, ALT_B)
 #define GPIO164_STMMOD_DAT3     PIN_CFG(164, ALT_C)
 
 #define GPIO165_GPIO            PIN_CFG(165, GPIO)
-#define GPIO165_KP_O3           PIN_CFG_PULL(165, ALT_A, UP)
+#define GPIO165_KP_O3           PIN_CFG_INPUT(165, ALT_A, PULLUP)
 #define GPIO165_LCD_D36         PIN_CFG(165, ALT_B)
 #define GPIO165_STMMOD_DAT2     PIN_CFG(165, ALT_C)
 
 #define GPIO166_GPIO            PIN_CFG(166, GPIO)
-#define GPIO166_KP_O2           PIN_CFG_PULL(166, ALT_A, UP)
+#define GPIO166_KP_O2           PIN_CFG_INPUT(166, ALT_A, PULLUP)
 #define GPIO166_LCD_D37         PIN_CFG(166, ALT_B)
 #define GPIO166_STMMOD_DAT1     PIN_CFG(166, ALT_C)
 
 #define GPIO167_GPIO            PIN_CFG(167, GPIO)
-#define GPIO167_KP_O1           PIN_CFG_PULL(167, ALT_A, UP)
+#define GPIO167_KP_O1           PIN_CFG_INPUT(167, ALT_A, PULLUP)
 #define GPIO167_LCD_D38         PIN_CFG(167, ALT_B)
 #define GPIO167_STMMOD_DAT0     PIN_CFG(167, ALT_C)
 
 #define GPIO168_GPIO            PIN_CFG(168, GPIO)
-#define GPIO168_KP_O0           PIN_CFG_PULL(168, ALT_A, UP)
+#define GPIO168_KP_O0           PIN_CFG_INPUT(168, ALT_A, PULLUP)
 #define GPIO168_LCD_D39         PIN_CFG(168, ALT_B)
 #define GPIO168_NONE            PIN_CFG(168, ALT_C)
 
@@ -569,39 +569,39 @@
 #define GPIO196_MSP2_RXD        PIN_CFG(196, ALT_A)
 
 #define GPIO197_GPIO            PIN_CFG(197, GPIO)
-#define GPIO197_MC4_DAT3        PIN_CFG_PULL(197, ALT_A, UP)
+#define GPIO197_MC4_DAT3        PIN_CFG_INPUT(197, ALT_A, PULLUP)
 
 #define GPIO198_GPIO            PIN_CFG(198, GPIO)
-#define GPIO198_MC4_DAT2        PIN_CFG_PULL(198, ALT_A, UP)
+#define GPIO198_MC4_DAT2        PIN_CFG_INPUT(198, ALT_A, PULLUP)
 
 #define GPIO199_GPIO            PIN_CFG(199, GPIO)
-#define GPIO199_MC4_DAT1        PIN_CFG_PULL(199, ALT_A, UP)
+#define GPIO199_MC4_DAT1        PIN_CFG_INPUT(199, ALT_A, PULLUP)
 
 #define GPIO200_GPIO            PIN_CFG(200, GPIO)
-#define GPIO200_MC4_DAT0        PIN_CFG_PULL(200, ALT_A, UP)
+#define GPIO200_MC4_DAT0        PIN_CFG_INPUT(200, ALT_A, PULLUP)
 
 #define GPIO201_GPIO            PIN_CFG(201, GPIO)
-#define GPIO201_MC4_CMD         PIN_CFG_PULL(201, ALT_A, UP)
+#define GPIO201_MC4_CMD         PIN_CFG_INPUT(201, ALT_A, PULLUP)
 
 #define GPIO202_GPIO            PIN_CFG(202, GPIO)
-#define GPIO202_MC4_FBCLK       PIN_CFG_PULL(202, ALT_A, UP)
+#define GPIO202_MC4_FBCLK       PIN_CFG_INPUT(202, ALT_A, PULLUP)
 #define GPIO202_PWL             PIN_CFG(202, ALT_B)
 #define GPIO202_MC4_RSTN        PIN_CFG(202, ALT_C)
 
 #define GPIO203_GPIO            PIN_CFG(203, GPIO)
-#define GPIO203_MC4_CLK         PIN_CFG_PULL(203, ALT_A, UP)
+#define GPIO203_MC4_CLK         PIN_CFG_INPUT(203, ALT_A, PULLUP)
 
 #define GPIO204_GPIO            PIN_CFG(204, GPIO)
-#define GPIO204_MC4_DAT7        PIN_CFG_PULL(204, ALT_A, UP)
+#define GPIO204_MC4_DAT7        PIN_CFG_INPUT(204, ALT_A, PULLUP)
 
 #define GPIO205_GPIO            PIN_CFG(205, GPIO)
-#define GPIO205_MC4_DAT6        PIN_CFG_PULL(205, ALT_A, UP)
+#define GPIO205_MC4_DAT6        PIN_CFG_INPUT(205, ALT_A, PULLUP)
 
 #define GPIO206_GPIO            PIN_CFG(206, GPIO)
-#define GPIO206_MC4_DAT5        PIN_CFG_PULL(206, ALT_A, UP)
+#define GPIO206_MC4_DAT5        PIN_CFG_INPUT(206, ALT_A, PULLUP)
 
 #define GPIO207_GPIO            PIN_CFG(207, GPIO)
-#define GPIO207_MC4_DAT4        PIN_CFG_PULL(207, ALT_A, UP)
+#define GPIO207_MC4_DAT4        PIN_CFG_INPUT(207, ALT_A, PULLUP)
 
 #define GPIO208_GPIO            PIN_CFG(208, GPIO)
 #define GPIO208_MC1_CLK         PIN_CFG(208, ALT_A)
@@ -632,21 +632,25 @@
 #define GPIO215_MC1_CMDDIR      PIN_CFG(215, ALT_A)
 #define GPIO215_MC3_DAT2DIR     PIN_CFG(215, ALT_B)
 #define GPIO215_CLKOUT1         PIN_CFG(215, ALT_C)
+#define GPIO215_SPI2_TXD        PIN_CFG(215, ALT_C)
 
 #define GPIO216_GPIO            PIN_CFG(216, GPIO)
 #define GPIO216_MC1_DAT2DIR     PIN_CFG(216, ALT_A)
 #define GPIO216_MC3_CMDDIR      PIN_CFG(216, ALT_B)
-#define GPIO216_I2C3_SDA        PIN_CFG_PULL(216, ALT_C, UP)
+#define GPIO216_I2C3_SDA        PIN_CFG_INPUT(216, ALT_C, PULLUP)
+#define GPIO216_SPI2_FRM        PIN_CFG(216, ALT_C)
 
 #define GPIO217_GPIO            PIN_CFG(217, GPIO)
 #define GPIO217_MC1_DAT0DIR     PIN_CFG(217, ALT_A)
 #define GPIO217_MC3_DAT31DIR    PIN_CFG(217, ALT_B)
 #define GPIO217_CLKOUT2         PIN_CFG(217, ALT_C)
+#define GPIO217_SPI2_CLK        PIN_CFG(217, ALT_C)
 
 #define GPIO218_GPIO            PIN_CFG(218, GPIO)
 #define GPIO218_MC1_DAT31DIR    PIN_CFG(218, ALT_A)
 #define GPIO218_MC3_DAT0DIR     PIN_CFG(218, ALT_B)
-#define GPIO218_I2C3_SCL        PIN_CFG_PULL(218, ALT_C, UP)
+#define GPIO218_I2C3_SCL        PIN_CFG_INPUT(218, ALT_C, PULLUP)
+#define GPIO218_SPI2_RXD        PIN_CFG(218, ALT_C)
 
 #define GPIO219_GPIO            PIN_CFG(219, GPIO)
 #define GPIO219_HSIR_FLA0       PIN_CFG(219, ALT_A)
@@ -694,12 +698,12 @@
 #define GPIO229_GPIO            PIN_CFG(229, GPIO)
 #define GPIO229_CLKOUT1         PIN_CFG(229, ALT_A)
 #define GPIO229_PWL             PIN_CFG(229, ALT_B)
-#define GPIO229_I2C3_SDA        PIN_CFG_PULL(229, ALT_C, UP)
+#define GPIO229_I2C3_SDA        PIN_CFG_INPUT(229, ALT_C, PULLUP)
 
 #define GPIO230_GPIO            PIN_CFG(230, GPIO)
 #define GPIO230_CLKOUT2         PIN_CFG(230, ALT_A)
 #define GPIO230_PWL             PIN_CFG(230, ALT_B)
-#define GPIO230_I2C3_SCL        PIN_CFG_PULL(230, ALT_C, UP)
+#define GPIO230_I2C3_SCL        PIN_CFG_INPUT(230, ALT_C, PULLUP)
 
 #define GPIO256_GPIO            PIN_CFG(256, GPIO)
 #define GPIO256_USB_NXT         PIN_CFG(256, ALT_A)
diff --git a/arch/arm/mach-versatile/versatile_ab.c b/arch/arm/mach-versatile/versatile_ab.c
index f8ae64b3eed0..fda4866703cd 100644
--- a/arch/arm/mach-versatile/versatile_ab.c
+++ b/arch/arm/mach-versatile/versatile_ab.c
@@ -35,7 +35,7 @@
 
 MACHINE_START(VERSATILE_AB, "ARM-Versatile AB")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = versatile_map_io,
         .init_early     = versatile_init_early,
         .init_irq       = versatile_init_irq,
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 37c23dfeefb7..feaf9cbe60f6 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -103,7 +103,7 @@ static void __init versatile_pb_init(void)
 
 MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = versatile_map_io,
         .init_early     = versatile_init_early,
         .init_irq       = versatile_init_irq,
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index d0d267a8d3f9..1fafc3244607 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -443,7 +443,7 @@ static void __init v2m_init(void)
 }
 
 MACHINE_START(VEXPRESS, "ARM-Versatile Express")
-        .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
+        .atag_offset    = 0x100,
         .map_io         = v2m_map_io,
         .init_early     = v2m_init_early,
         .init_irq       = v2m_init_irq,
diff --git a/arch/arm/mach-vt8500/bv07.c b/arch/arm/mach-vt8500/bv07.c
index 94a261d86bf0..a464c7584411 100644
--- a/arch/arm/mach-vt8500/bv07.c
+++ b/arch/arm/mach-vt8500/bv07.c
@@ -68,7 +68,7 @@ void __init bv07_init(void)
 }
 
 MACHINE_START(BV07, "Benign BV07 Mini Netbook")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .reserve        = vt8500_reserve_mem,
         .map_io         = vt8500_map_io,
         .init_irq       = vt8500_init_irq,
diff --git a/arch/arm/mach-vt8500/wm8505_7in.c b/arch/arm/mach-vt8500/wm8505_7in.c
index e73aadbcafd6..cf910a956080 100644
--- a/arch/arm/mach-vt8500/wm8505_7in.c
+++ b/arch/arm/mach-vt8500/wm8505_7in.c
@@ -68,7 +68,7 @@ void __init wm8505_7in_init(void)
 }
 
 MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook")
-        .boot_params    = 0x00000100,
+        .atag_offset    = 0x100,
         .reserve        = wm8505_reserve_mem,
         .map_io         = wm8505_map_io,
         .init_irq       = wm8505_init_irq,
diff --git a/arch/arm/mach-w90x900/mach-nuc910evb.c b/arch/arm/mach-w90x900/mach-nuc910evb.c
index 30fccde94fb8..31c109018228 100644
--- a/arch/arm/mach-w90x900/mach-nuc910evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc910evb.c
@@ -34,7 +34,6 @@ static void __init nuc910evb_init(void)
 
 MACHINE_START(W90P910EVB, "W90P910EVB")
         /* Maintainer: Wan ZongShun */
-        .boot_params    = 0,
         .map_io         = nuc910evb_map_io,
         .init_irq       = nuc900_init_irq,
         .init_machine   = nuc910evb_init,
diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c
index 590c99b96dc1..4062e55a57d8 100644
--- a/arch/arm/mach-w90x900/mach-nuc950evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc950evb.c
@@ -37,7 +37,6 @@ static void __init nuc950evb_init(void)
 
 MACHINE_START(W90P950EVB, "W90P950EVB")
         /* Maintainer: Wan ZongShun */
-        .boot_params    = 0,
         .map_io         = nuc950evb_map_io,
         .init_irq       = nuc900_init_irq,
         .init_machine   = nuc950evb_init,
diff --git a/arch/arm/mach-w90x900/mach-nuc960evb.c b/arch/arm/mach-w90x900/mach-nuc960evb.c
index e09c645d61b6..0ab9995d5b58 100644
--- a/arch/arm/mach-w90x900/mach-nuc960evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc960evb.c
@@ -34,7 +34,6 @@ static void __init nuc960evb_init(void)
 
 MACHINE_START(W90N960EVB, "W90N960EVB")
         /* Maintainer: Wan ZongShun */
-        .boot_params    = 0,
         .map_io         = nuc960evb_map_io,
         .init_irq       = nuc900_init_irq,
         .init_machine   = nuc960evb_init,
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index c3ff82f92d9c..01f5987eb1ad 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -18,12 +18,14 @@
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
 #include <linux/highmem.h>
+#include <linux/slab.h>
 
 #include <asm/memory.h>
 #include <asm/highmem.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
 #include <asm/sizes.h>
+#include <asm/mach/arch.h>
 
 #include "mm.h"
 
@@ -117,26 +119,37 @@ static void __dma_free_buffer(struct page *page, size_t size)
 }
 
 #ifdef CONFIG_MMU
-/* Sanity check size */
-#if (CONSISTENT_DMA_SIZE % SZ_2M)
-#error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
-#endif
 
-#define CONSISTENT_OFFSET(x)    (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
-#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
-#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
+
+#define CONSISTENT_OFFSET(x)    (((unsigned long)(x) - consistent_base) >> PAGE_SHIFT)
+#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - consistent_base) >> PGDIR_SHIFT)
 
 /*
  * These are the page tables (2MB each) covering uncached, DMA consistent allocations
  */
-static pte_t *consistent_pte[NUM_CONSISTENT_PTES];
+static pte_t **consistent_pte;
+
+#define DEFAULT_CONSISTENT_DMA_SIZE SZ_2M
+
+unsigned long consistent_base = CONSISTENT_END - DEFAULT_CONSISTENT_DMA_SIZE;
+
+void __init init_consistent_dma_size(unsigned long size)
+{
+        unsigned long base = CONSISTENT_END - ALIGN(size, SZ_2M);
+
+        BUG_ON(consistent_pte); /* Check we're called before DMA region init */
+        BUG_ON(base < VMALLOC_END);
+
+        /* Grow region to accommodate specified size  */
+        if (base < consistent_base)
+                consistent_base = base;
+}
 
 #include "vmregion.h"
 
 static struct arm_vmregion_head consistent_head = {
         .vm_lock        = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock),
         .vm_list        = LIST_HEAD_INIT(consistent_head.vm_list),
-        .vm_start       = CONSISTENT_BASE,
         .vm_end         = CONSISTENT_END,
 };
 
@@ -155,7 +168,17 @@ static int __init consistent_init(void)
         pmd_t *pmd;
         pte_t *pte;
         int i = 0;
-        u32 base = CONSISTENT_BASE;
+        unsigned long base = consistent_base;
+        unsigned long num_ptes = (CONSISTENT_END - base) >> PGDIR_SHIFT;
+
+        consistent_pte = kmalloc(num_ptes * sizeof(pte_t), GFP_KERNEL);
+        if (!consistent_pte) {
+                pr_err("%s: no memory\n", __func__);
+                return -ENOMEM;
+        }
+
+        pr_debug("DMA memory: 0x%08lx - 0x%08lx:\n", base, CONSISTENT_END);
+        consistent_head.vm_start = base;
 
         do {
                 pgd = pgd_offset(&init_mm, base);
@@ -198,7 +221,7 @@ __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot)
         size_t align;
         int bit;
 
-        if (!consistent_pte[0]) {
+        if (!consistent_pte) {
                 printk(KERN_ERR "%s: not initialised\n", __func__);
                 dump_stack();
                 return NULL;
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index cc7e2d8be9aa..34409a08ba0d 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -653,9 +653,6 @@ void __init mem_init(void)
                         "    ITCM    : 0x%08lx - 0x%08lx   (%4ld kB)\n"
 #endif
                         "    fixmap  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
-#ifdef CONFIG_MMU
-                        "    DMA     : 0x%08lx - 0x%08lx   (%4ld MB)\n"
-#endif
                         "    vmalloc : 0x%08lx - 0x%08lx   (%4ld MB)\n"
                         "    lowmem  : 0x%08lx - 0x%08lx   (%4ld MB)\n"
 #ifdef CONFIG_HIGHMEM
@@ -674,9 +671,6 @@ void __init mem_init(void)
                         MLK(ITCM_OFFSET, (unsigned long) itcm_end),
 #endif
                         MLK(FIXADDR_START, FIXADDR_TOP),
-#ifdef CONFIG_MMU
-                        MLM(CONSISTENT_BASE, CONSISTENT_END),
-#endif
                         MLM(VMALLOC_START, VMALLOC_END),
                         MLM(PAGE_OFFSET, (unsigned long)high_memory),
 #ifdef CONFIG_HIGHMEM
@@ -699,9 +693,6 @@ void __init mem_init(void)
          * be detected at build time already.
          */
 #ifdef CONFIG_MMU
-        BUILD_BUG_ON(VMALLOC_END                        > CONSISTENT_BASE);
-        BUG_ON(VMALLOC_END                              > CONSISTENT_BASE);
-
         BUILD_BUG_ON(TASK_SIZE                          > MODULES_VADDR);
         BUG_ON(TASK_SIZE                                > MODULES_VADDR);
 #endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 594d677b92c8..ea9c9f3e48bf 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -273,6 +273,14 @@ static struct mem_type mem_types[] = {
                 .prot_l1   = PMD_TYPE_TABLE,
                 .domain    = DOMAIN_KERNEL,
         },
+        [MT_MEMORY_SO] = {
+                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+                                L_PTE_MT_UNCACHED,
+                .prot_l1   = PMD_TYPE_TABLE,
+                .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
+                                PMD_SECT_UNCACHED | PMD_SECT_XN,
+                .domain    = DOMAIN_KERNEL,
+        },
 };
 
 const struct mem_type *get_mem_type(unsigned int type)
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 2e6849b41f66..88fb3d9e0640 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -379,31 +379,26 @@ ENTRY(cpu_arm920_set_pte_ext)
 
 /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
 .globl  cpu_arm920_suspend_size
-.equ    cpu_arm920_suspend_size, 4 * 4
+.equ    cpu_arm920_suspend_size, 4 * 3
 #ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_arm920_do_suspend)
-        stmfd   sp!, {r4 - r7, lr}
+        stmfd   sp!, {r4 - r6, lr}
         mrc     p15, 0, r4, c13, c0, 0  @ PID
         mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
-        mrc     p15, 0, r6, c2, c0, 0   @ TTB address
-        mrc     p15, 0, r7, c1, c0, 0   @ Control register
-        stmia   r0, {r4 - r7}
-        ldmfd   sp!, {r4 - r7, pc}
+        mrc     p15, 0, r6, c1, c0, 0   @ Control register
+        stmia   r0, {r4 - r6}
+        ldmfd   sp!, {r4 - r6, pc}
 ENDPROC(cpu_arm920_do_suspend)
 
 ENTRY(cpu_arm920_do_resume)
         mov     ip, #0
         mcr     p15, 0, ip, c8, c7, 0   @ invalidate I+D TLBs
         mcr     p15, 0, ip, c7, c7, 0   @ invalidate I+D caches
-        ldmia   r0, {r4 - r7}
+        ldmia   r0, {r4 - r6}
         mcr     p15, 0, r4, c13, c0, 0  @ PID
         mcr     p15, 0, r5, c3, c0, 0   @ Domain ID
-        mcr     p15, 0, r6, c2, c0, 0   @ TTB address
-        mov     r0, r7                  @ control register
-        mov     r2, r6, lsr #14         @ get TTB0 base
-        mov     r2, r2, lsl #14
-        ldr     r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
-                     PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE
+        mcr     p15, 0, r1, c2, c0, 0   @ TTB address
+        mov     r0, r6                  @ control register
         b       cpu_resume_mmu
 ENDPROC(cpu_arm920_do_resume)
 #endif
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index cd8f79c3a282..9f8fd91f918a 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -394,31 +394,26 @@ ENTRY(cpu_arm926_set_pte_ext)
 
 /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
 .globl  cpu_arm926_suspend_size
-.equ    cpu_arm926_suspend_size, 4 * 4
+.equ    cpu_arm926_suspend_size, 4 * 3
 #ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_arm926_do_suspend)
-        stmfd   sp!, {r4 - r7, lr}
+        stmfd   sp!, {r4 - r6, lr}
         mrc     p15, 0, r4, c13, c0, 0  @ PID
         mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
-        mrc     p15, 0, r6, c2, c0, 0   @ TTB address
-        mrc     p15, 0, r7, c1, c0, 0   @ Control register
-        stmia   r0, {r4 - r7}
-        ldmfd   sp!, {r4 - r7, pc}
+        mrc     p15, 0, r6, c1, c0, 0   @ Control register
+        stmia   r0, {r4 - r6}
+        ldmfd   sp!, {r4 - r6, pc}
 ENDPROC(cpu_arm926_do_suspend)
 
 ENTRY(cpu_arm926_do_resume)
         mov     ip, #0
         mcr     p15, 0, ip, c8, c7, 0   @ invalidate I+D TLBs
         mcr     p15, 0, ip, c7, c7, 0   @ invalidate I+D caches
-        ldmia   r0, {r4 - r7}
+        ldmia   r0, {r4 - r6}
         mcr     p15, 0, r4, c13, c0, 0  @ PID
         mcr     p15, 0, r5, c3, c0, 0   @ Domain ID
-        mcr     p15, 0, r6, c2, c0, 0   @ TTB address
-        mov     r0, r7                  @ control register
-        mov     r2, r6, lsr #14         @ get TTB0 base
-        mov     r2, r2, lsl #14
-        ldr     r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
-                     PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE
+        mcr     p15, 0, r1, c2, c0, 0   @ TTB address
+        mov     r0, r6                  @ control register
         b       cpu_resume_mmu
 ENDPROC(cpu_arm926_do_resume)
 #endif
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 69e7f2ef7384..7d91545d089b 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -168,20 +168,19 @@ ENTRY(cpu_sa1100_set_pte_ext)
         mov     pc, lr
 
 .globl  cpu_sa1100_suspend_size
-.equ    cpu_sa1100_suspend_size, 4*4
+.equ    cpu_sa1100_suspend_size, 4 * 3
 #ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_sa1100_do_suspend)
-        stmfd   sp!, {r4 - r7, lr}
+        stmfd   sp!, {r4 - r6, lr}
         mrc     p15, 0, r4, c3, c0, 0           @ domain ID
-        mrc     p15, 0, r5, c2, c0, 0           @ translation table base addr
-        mrc     p15, 0, r6, c13, c0, 0          @ PID
-        mrc     p15, 0, r7, c1, c0, 0           @ control reg
-        stmia   r0, {r4 - r7}                   @ store cp regs
-        ldmfd   sp!, {r4 - r7, pc}
+        mrc     p15, 0, r5, c13, c0, 0          @ PID
+        mrc     p15, 0, r6, c1, c0, 0           @ control reg
+        stmia   r0, {r4 - r6}                   @ store cp regs
+        ldmfd   sp!, {r4 - r6, pc}
 ENDPROC(cpu_sa1100_do_suspend)
 
 ENTRY(cpu_sa1100_do_resume)
-        ldmia   r0, {r4 - r7}                   @ load cp regs
+        ldmia   r0, {r4 - r6}                   @ load cp regs
         mov     ip, #0
         mcr     p15, 0, ip, c8, c7, 0           @ flush I+D TLBs
         mcr     p15, 0, ip, c7, c7, 0           @ flush I&D cache
@@ -189,13 +188,9 @@ ENTRY(cpu_sa1100_do_resume)
         mcr     p15, 0, ip, c9, c0, 5           @ allow user space to use RB
 
         mcr     p15, 0, r4, c3, c0, 0           @ domain ID
-        mcr     p15, 0, r5, c2, c0, 0           @ translation table base addr
-        mcr     p15, 0, r6, c13, c0, 0          @ PID
-        mov     r0, r7                          @ control register
-        mov     r2, r5, lsr #14                 @ get TTB0 base
-        mov     r2, r2, lsl #14
-        ldr     r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
-                     PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE
+        mcr     p15, 0, r1, c2, c0, 0           @ translation table base addr
+        mcr     p15, 0, r5, c13, c0, 0          @ PID
+        mov     r0, r6                          @ control register
         b       cpu_resume_mmu
 ENDPROC(cpu_sa1100_do_resume)
 #endif
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index a923aa0fd00d..d061d2fa5506 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -128,20 +128,18 @@ ENTRY(cpu_v6_set_pte_ext)
 
 /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
 .globl  cpu_v6_suspend_size
-.equ    cpu_v6_suspend_size, 4 * 8
+.equ    cpu_v6_suspend_size, 4 * 6
 #ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_v6_do_suspend)
-        stmfd   sp!, {r4 - r11, lr}
+        stmfd   sp!, {r4 - r9, lr}
         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
-        mrc     p15, 0, r5, c13, c0, 1  @ Context ID
-        mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
-        mrc     p15, 0, r7, c2, c0, 0   @ Translation table base 0
-        mrc     p15, 0, r8, c2, c0, 1   @ Translation table base 1
-        mrc     p15, 0, r9, c1, c0, 1   @ auxiliary control register
-        mrc     p15, 0, r10, c1, c0, 2  @ co-processor access control
-        mrc     p15, 0, r11, c1, c0, 0  @ control register
-        stmia   r0, {r4 - r11}
-        ldmfd   sp!, {r4- r11, pc}
+        mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
+        mrc     p15, 0, r6, c2, c0, 1   @ Translation table base 1
+        mrc     p15, 0, r7, c1, c0, 1   @ auxiliary control register
+        mrc     p15, 0, r8, c1, c0, 2   @ co-processor access control
+        mrc     p15, 0, r9, c1, c0, 0   @ control register
+        stmia   r0, {r4 - r9}
+        ldmfd   sp!, {r4- r9, pc}
 ENDPROC(cpu_v6_do_suspend)
 
 ENTRY(cpu_v6_do_resume)
@@ -150,25 +148,21 @@ ENTRY(cpu_v6_do_resume)
         mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
         mcr     p15, 0, ip, c7, c15, 0  @ clean+invalidate cache
         mcr     p15, 0, ip, c7, c10, 4  @ drain write buffer
-        ldmia   r0, {r4 - r11}
+        mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
+        ldmia   r0, {r4 - r9}
         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
-        mcr     p15, 0, r5, c13, c0, 1  @ Context ID
-        mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
-        mcr     p15, 0, r7, c2, c0, 0   @ Translation table base 0
-        mcr     p15, 0, r8, c2, c0, 1   @ Translation table base 1
-        mcr     p15, 0, r9, c1, c0, 1   @ auxiliary control register
-        mcr     p15, 0, r10, c1, c0, 2  @ co-processor access control
+        mcr     p15, 0, r5, c3, c0, 0   @ Domain ID
+        ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
+        ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
+        mcr     p15, 0, r1, c2, c0, 0   @ Translation table base 0
+        mcr     p15, 0, r6, c2, c0, 1   @ Translation table base 1
+        mcr     p15, 0, r7, c1, c0, 1   @ auxiliary control register
+        mcr     p15, 0, r8, c1, c0, 2   @ co-processor access control
         mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
         mcr     p15, 0, ip, c7, c5, 4   @ ISB
-        mov     r0, r11                 @ control register
-        mov     r2, r7, lsr #14         @ get TTB0 base
-        mov     r2, r2, lsl #14
-        ldr     r3, cpu_resume_l1_flags
+        mov     r0, r9                  @ control register
         b       cpu_resume_mmu
 ENDPROC(cpu_v6_do_resume)
-cpu_resume_l1_flags:
-        ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
-        ALT_UP(.long  PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
 #endif
 
         string  cpu_v6_name, "ARMv6-compatible processor"
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 9049c0764db2..6af366ce0165 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -217,56 +217,50 @@ ENDPROC(cpu_v7_set_pte_ext)
 
 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
 .globl  cpu_v7_suspend_size
-.equ    cpu_v7_suspend_size, 4 * 9
+.equ    cpu_v7_suspend_size, 4 * 7
 #ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_v7_do_suspend)
-        stmfd   sp!, {r4 - r11, lr}
+        stmfd   sp!, {r4 - r10, lr}
         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
-        mrc     p15, 0, r5, c13, c0, 1  @ Context ID
-        mrc     p15, 0, r6, c13, c0, 3  @ User r/o thread ID
-        stmia   r0!, {r4 - r6}
+        mrc     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
+        stmia   r0!, {r4 - r5}
         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
-        mrc     p15, 0, r7, c2, c0, 0   @ TTB 0
-        mrc     p15, 0, r8, c2, c0, 1   @ TTB 1
-        mrc     p15, 0, r9, c1, c0, 0   @ Control register
-        mrc     p15, 0, r10, c1, c0, 1  @ Auxiliary control register
-        mrc     p15, 0, r11, c1, c0, 2  @ Co-processor access control
-        stmia   r0, {r6 - r11}
-        ldmfd   sp!, {r4 - r11, pc}
+        mrc     p15, 0, r7, c2, c0, 1   @ TTB 1
+        mrc     p15, 0, r8, c1, c0, 0   @ Control register
+        mrc     p15, 0, r9, c1, c0, 1   @ Auxiliary control register
+        mrc     p15, 0, r10, c1, c0, 2  @ Co-processor access control
+        stmia   r0, {r6 - r10}
+        ldmfd   sp!, {r4 - r10, pc}
 ENDPROC(cpu_v7_do_suspend)
 
 ENTRY(cpu_v7_do_resume)
         mov     ip, #0
         mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
         mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
-        ldmia   r0!, {r4 - r6}
+        mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
+        ldmia   r0!, {r4 - r5}
         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
-        mcr     p15, 0, r5, c13, c0, 1  @ Context ID
-        mcr     p15, 0, r6, c13, c0, 3  @ User r/o thread ID
-        ldmia   r0, {r6 - r11}
+        mcr     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
+        ldmia   r0, {r6 - r10}
         mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
-        mcr     p15, 0, r7, c2, c0, 0   @ TTB 0
-        mcr     p15, 0, r8, c2, c0, 1   @ TTB 1
+        ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
+        ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
+        mcr     p15, 0, r1, c2, c0, 0   @ TTB 0
+        mcr     p15, 0, r7, c2, c0, 1   @ TTB 1
         mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
         mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
-        teq     r4, r10                 @ Is it already set?
-        mcrne   p15, 0, r10, c1, c0, 1  @ No, so write it
-        mcr     p15, 0, r11, c1, c0, 2  @ Co-processor access control
+        teq     r4, r9                  @ Is it already set?
+        mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
+        mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
         ldr     r4, =PRRR               @ PRRR
         ldr     r5, =NMRR               @ NMRR
         mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
         mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
         isb
         dsb
-        mov     r0, r9                  @ control register
-        mov     r2, r7, lsr #14         @ get TTB0 base
-        mov     r2, r2, lsl #14
-        ldr     r3, cpu_resume_l1_flags
+        mov     r0, r8                  @ control register
         b       cpu_resume_mmu
 ENDPROC(cpu_v7_do_resume)
-cpu_resume_l1_flags:
-        ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
-        ALT_UP(.long  PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
 #endif
 
         __CPUINIT
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 755e1bf22681..abf0507a08ae 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -406,24 +406,23 @@ ENTRY(cpu_xsc3_set_pte_ext)
         .align
 
 .globl  cpu_xsc3_suspend_size
-.equ    cpu_xsc3_suspend_size, 4 * 7
+.equ    cpu_xsc3_suspend_size, 4 * 6
 #ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_xsc3_do_suspend)
-        stmfd   sp!, {r4 - r10, lr}
+        stmfd   sp!, {r4 - r9, lr}
         mrc     p14, 0, r4, c6, c0, 0   @ clock configuration, for turbo mode
         mrc     p15, 0, r5, c15, c1, 0  @ CP access reg
         mrc     p15, 0, r6, c13, c0, 0  @ PID
         mrc     p15, 0, r7, c3, c0, 0   @ domain ID
-        mrc     p15, 0, r8, c2, c0, 0   @ translation table base addr
-        mrc     p15, 0, r9, c1, c0, 1   @ auxiliary control reg
-        mrc     p15, 0, r10, c1, c0, 0  @ control reg
+        mrc     p15, 0, r8, c1, c0, 1   @ auxiliary control reg
+        mrc     p15, 0, r9, c1, c0, 0   @ control reg
         bic     r4, r4, #2              @ clear frequency change bit
-        stmia   r0, {r4 - r10}          @ store cp regs
-        ldmia   sp!, {r4 - r10, pc}
+        stmia   r0, {r4 - r9}           @ store cp regs
+        ldmia   sp!, {r4 - r9, pc}
 ENDPROC(cpu_xsc3_do_suspend)
 
 ENTRY(cpu_xsc3_do_resume)
-        ldmia   r0, {r4 - r10}          @ load cp regs
+        ldmia   r0, {r4 - r9}           @ load cp regs
         mov     ip, #0
         mcr     p15, 0, ip, c7, c7, 0   @ invalidate I & D caches, BTB
         mcr     p15, 0, ip, c7, c10, 4  @ drain write (&fill) buffer
@@ -433,15 +432,10 @@ ENTRY(cpu_xsc3_do_resume)
         mcr     p15, 0, r5, c15, c1, 0  @ CP access reg
         mcr     p15, 0, r6, c13, c0, 0  @ PID
         mcr     p15, 0, r7, c3, c0, 0   @ domain ID
-        mcr     p15, 0, r8, c2, c0, 0   @ translation table base addr
-        mcr     p15, 0, r9, c1, c0, 1   @ auxiliary control reg
-
-        @ temporarily map resume_turn_on_mmu into the page table,
-        @ otherwise prefetch abort occurs after MMU is turned on
-        mov     r0, r10                 @ control register
-        mov     r2, r8, lsr #14         @ get TTB0 base
-        mov     r2, r2, lsl #14
-        ldr     r3, =0x542e             @ section flags
+        orr     r1, r1, #0x18           @ cache the page table in L2
+        mcr     p15, 0, r1, c2, c0, 0   @ translation table base addr
+        mcr     p15, 0, r8, c1, c0, 1   @ auxiliary control reg
+        mov     r0, r9                  @ control register
         b       cpu_resume_mmu
 ENDPROC(cpu_xsc3_do_resume)
 #endif
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index fbc06e55b87a..3277904bebaf 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -520,24 +520,23 @@ ENTRY(cpu_xscale_set_pte_ext)
         .align
 
 .globl  cpu_xscale_suspend_size
-.equ    cpu_xscale_suspend_size, 4 * 7
+.equ    cpu_xscale_suspend_size, 4 * 6
 #ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_xscale_do_suspend)
-        stmfd   sp!, {r4 - r10, lr}
+        stmfd   sp!, {r4 - r9, lr}
         mrc     p14, 0, r4, c6, c0, 0   @ clock configuration, for turbo mode
         mrc     p15, 0, r5, c15, c1, 0  @ CP access reg
         mrc     p15, 0, r6, c13, c0, 0  @ PID
         mrc     p15, 0, r7, c3, c0, 0   @ domain ID
-        mrc     p15, 0, r8, c2, c0, 0   @ translation table base addr
-        mrc     p15, 0, r9, c1, c1, 0   @ auxiliary control reg
-        mrc     p15, 0, r10, c1, c0, 0  @ control reg
+        mrc     p15, 0, r8, c1, c1, 0   @ auxiliary control reg
+        mrc     p15, 0, r9, c1, c0, 0   @ control reg
         bic     r4, r4, #2              @ clear frequency change bit
-        stmia   r0, {r4 - r10}          @ store cp regs
-        ldmfd   sp!, {r4 - r10, pc}
+        stmia   r0, {r4 - r9}           @ store cp regs
+        ldmfd   sp!, {r4 - r9, pc}
 ENDPROC(cpu_xscale_do_suspend)
 
 ENTRY(cpu_xscale_do_resume)
-        ldmia   r0, {r4 - r10}          @ load cp regs
+        ldmia   r0, {r4 - r9}           @ load cp regs
         mov     ip, #0
         mcr     p15, 0, ip, c8, c7, 0   @ invalidate I & D TLBs
         mcr     p15, 0, ip, c7, c7, 0   @ invalidate I & D caches, BTB
@@ -545,13 +544,9 @@ ENTRY(cpu_xscale_do_resume)
         mcr     p15, 0, r5, c15, c1, 0  @ CP access reg
         mcr     p15, 0, r6, c13, c0, 0  @ PID
         mcr     p15, 0, r7, c3, c0, 0   @ domain ID
-        mcr     p15, 0, r8, c2, c0, 0   @ translation table base addr
-        mcr     p15, 0, r9, c1, c1, 0   @ auxiliary control reg
-        mov     r0, r10                 @ control register
-        mov     r2, r8, lsr #14         @ get TTB0 base
-        mov     r2, r2, lsl #14
-        ldr     r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
-                     PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE
+        mcr     p15, 0, r1, c2, c0, 0   @ translation table base addr
+        mcr     p15, 0, r8, c1, c1, 0   @ auxiliary control reg
+        mov     r0, r9                  @ control register
         b       cpu_resume_mmu
 ENDPROC(cpu_xscale_do_resume)
 #endif
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index 175e3647bb27..8cced35009bd 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -187,18 +187,11 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
 static int mxc_audmux_v2_init(void)
 {
         int ret;
-#if defined(CONFIG_ARCH_MX5)
         if (cpu_is_mx51()) {
                 audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR);
-                ret = 0;
-                return ret;
-        }
-#endif
-#if defined(CONFIG_ARCH_MX3)
-        if (cpu_is_mx31())
+        } else if (cpu_is_mx31()) {
                 audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
-
-        else if (cpu_is_mx35()) {
+        } else if (cpu_is_mx35()) {
                 audmux_clk = clk_get(NULL, "audmux");
                 if (IS_ERR(audmux_clk)) {
                         ret = PTR_ERR(audmux_clk);
@@ -207,10 +200,7 @@ static int mxc_audmux_v2_init(void)
                         return ret;
                 }
                 audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
-        }
-#endif
-#if defined(CONFIG_SOC_IMX25)
-        if (cpu_is_mx25()) {
+        } else if (cpu_is_mx25()) {
                 audmux_clk = clk_get(NULL, "audmux");
                 if (IS_ERR(audmux_clk)) {
                         ret = PTR_ERR(audmux_clk);
@@ -220,7 +210,7 @@ static int mxc_audmux_v2_init(void)
                 }
                 audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
         }
-#endif /* if defined(CONFIG_SOC_IMX25) */
+
         audmux_debugfs_init();
 
         return 0;
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index 0d6ed31bdbf2..5aaa8c5f3420 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -23,20 +23,6 @@
 #include <linux/platform_device.h>
 #include <mach/common.h>
 
-int __init mxc_register_device(struct platform_device *pdev, void *data)
-{
-        int ret;
-
-        pdev->dev.platform_data = data;
-
-        ret = platform_device_register(pdev);
-        if (ret)
-                pr_debug("Unable to register platform device '%s': %d\n",
-                         pdev->name, ret);
-
-        return ret;
-}
-
 struct platform_device *__init imx_add_platform_device_dmamask(
                 const char *name, int id,
                 const struct resource *res, unsigned int num_resources,
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index bd294add932c..39b08957e8ad 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -1,6 +1,6 @@
 config IMX_HAVE_PLATFORM_FEC
         bool
-        default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53
+        default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX50 || SOC_IMX51 || SOC_IMX53
 
 config IMX_HAVE_PLATFORM_FLEXCAN
         select HAVE_CAN_FLEXCAN if CAN
diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
index 23ce08e6ffd2..848038f301fd 100644
--- a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
+++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
@@ -36,6 +36,11 @@ const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst =
         imx_fsl_usb2_udc_data_entry_single(MX35);
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
+#ifdef CONFIG_SOC_IMX51
+const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data __initconst =
+        imx_fsl_usb2_udc_data_entry_single(MX51);
+#endif
+
 struct platform_device *__init imx_add_fsl_usb2_udc(
                 const struct imx_fsl_usb2_udc_data *data,
                 const struct fsl_usb2_platform_data *pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index afe60f7244a8..19ad580c0be3 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -85,6 +85,12 @@ const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
         imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K)
         imx51_imx_i2c_data_entry(0, 1),
         imx51_imx_i2c_data_entry(1, 2),
+        {
+                .id = 2,
+                .iobase = MX51_HSI2C_DMA_BASE_ADDR,
+                .iosize = SZ_16K,
+                .irq = MX51_INT_HS_I2C,
+        },
 };
 #endif /* ifdef CONFIG_SOC_IMX51 */
 
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
index e1763e03e7cb..35851d889aca 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
@@ -49,6 +49,15 @@ const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst =
         imx_mxc_ehci_data_entry_single(MX35, 1, HS);
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
+#ifdef CONFIG_SOC_IMX51
+const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data __initconst =
+        imx_mxc_ehci_data_entry_single(MX51, 0, OTG);
+const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[] __initconst = {
+        imx_mxc_ehci_data_entry_single(MX51, 1, HS1),
+        imx_mxc_ehci_data_entry_single(MX51, 2, HS2),
+};
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
 struct platform_device *__init imx_add_mxc_ehci(
                 const struct imx_mxc_ehci_data *data,
                 const struct mxc_usbh_platform_data *pdata)
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 4e3d97890d69..d7149d1bd32c 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -66,10 +66,20 @@ extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
                         unsigned long ckih1, unsigned long ckih2);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
         resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
-extern int mxc_register_device(struct platform_device *pdev, void *data);
 extern void mxc_set_cpu_type(unsigned int type);
 extern void mxc_arch_reset_init(void __iomem *);
 extern void mx51_efikamx_reset(void);
 extern int mx53_revision(void);
 extern int mx53_display_revision(void);
+
+enum mxc_cpu_pwr_mode {
+        WAIT_CLOCKED,           /* wfi only */
+        WAIT_UNCLOCKED,         /* WAIT */
+        WAIT_UNCLOCKED_POWER_OFF,       /* WAIT + SRPG */
+        STOP_POWER_ON,          /* just STOP */
+        STOP_POWER_OFF,         /* STOP + SRPG */
+};
+
+extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
+extern void (*imx_idle)(void);
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index 31c820c1b796..44af0064ba1a 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -23,17 +23,10 @@
 #include <mach/hardware.h>
 #include <asm-generic/gpio.h>
 
-
-/* There's a off-by-one betweem the gpio bank number and the gpiochip */
-/* range e.g. GPIO_1_5 is gpio 5 under linux */
-#define IMX_GPIO_NR(bank, nr)           (((bank) - 1) * 32 + (nr))
-
 /* use gpiolib dispatchers */
 #define gpio_get_value          __gpio_get_value
 #define gpio_set_value          __gpio_set_value
 #define gpio_cansleep           __gpio_cansleep
-
-#define gpio_to_irq(gpio)       (MXC_GPIO_IRQ_START + (gpio))
-#define irq_to_gpio(irq)        ((irq) - MXC_GPIO_IRQ_START)
+#define gpio_to_irq             __gpio_to_irq
 
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index a8bfd565dcad..eba3118adfbb 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -81,11 +81,16 @@
  *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
  *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
  * mx51:
+ *      TZIC    0xe0000000+0x004000     ->      0xf5000000+0x004000
  *      IRAM    0x1ffe0000+0x020000     ->      0xf4fe0000+0x020000
- *      DEBUG   0x60000000+0x100000     ->      0xf5000000+0x100000
  *      SPBA0   0x70000000+0x100000     ->      0xf5400000+0x100000
  *      AIPS1   0x73f00000+0x100000     ->      0xf5700000+0x100000
  *      AIPS2   0x83f00000+0x100000     ->      0xf4300000+0x100000
+ * mx53:
+ *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
+ *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
+ *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
+ *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
  */
 #define IMX_IO_P2V(x)   (                                               \
                         0xf4000000 +                                    \
@@ -116,4 +121,10 @@
         .type = _type,                                                  \
 }
 
+/* There's a off-by-one betweem the gpio bank number and the gpiochip */
+/* range e.g. GPIO_1_5 is gpio 5 under linux */
+#define IMX_GPIO_NR(bank, nr)           (((bank) - 1) * 32 + (nr))
+
+#define IMX_GPIO_TO_IRQ(gpio)   (MXC_GPIO_IRQ_START + (gpio))
+
 #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
index 4347a87d2bb0..338300b18b00 100644
--- a/arch/arm/plat-mxc/include/mach/io.h
+++ b/arch/arm/plat-mxc/include/mach/io.h
@@ -14,32 +14,22 @@
 /* Allow IO space to be anywhere in the memory */
 #define IO_SPACE_LIMIT 0xffffffff
 
-#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35)
-#include <mach/hardware.h>
-
 #define __arch_ioremap __imx_ioremap
 #define __arch_iounmap __iounmap
 
 #define addr_in_module(addr, mod) \
         ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
 
+extern void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int);
+
 static inline void __iomem *
 __imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
 {
-        if (mtype == MT_DEVICE && (cpu_is_mx31() || cpu_is_mx35())) {
-                /*
-                 * Access all peripherals below 0x80000000 as nonshared device
-                 * on mx3, but leave l2cc alone.  Otherwise cache corruptions
-                 * can occur.
-                 */
-                if (phys_addr < 0x80000000 &&
-                                !addr_in_module(phys_addr, MX3x_L2CC))
-                        mtype = MT_DEVICE_NONSHARED;
-        }
-
-        return __arm_ioremap(phys_addr, size, mtype);
+        if (imx_ioremap != NULL)
+                return imx_ioremap(phys_addr, size, mtype);
+        else
+                return __arm_ioremap(phys_addr, size, mtype);
 }
-#endif
 
 /* io address mapping macro */
 #define __io(a)         __typesafe_io(a)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index df6acc066fb1..c7f5169a6a54 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -14,6 +14,8 @@
 #define __MACH_IOMUX_MX51_H__
 
 #include <mach/iomux-v3.h>
+#define __NA_   0x000
+
 
 /* Pad control groupings */
 #define MX51_UART_PAD_CTRL      (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
@@ -47,1521 +49,765 @@
 
 /* Raw pin modes without pad control */
 /*                                                        PAD    MUX ALT INPSE PATH PADCTRL */
-#define _MX51_PAD_EIM_D16__AUD4_RXFS            IOMUX_PAD(0x3f0, 0x5c, 5, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D16__AUD5_TXD             IOMUX_PAD(0x3f0, 0x5c, 7, 0x08d8, 0, 0)
-#define _MX51_PAD_EIM_D16__EIM_D16              IOMUX_PAD(0x3f0, 0x5c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D16__GPIO2_0              IOMUX_PAD(0x3f0, 0x5c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D16__I2C1_SDA             IOMUX_PAD(0x3f0, 0x5c, 0x14, 0x09b4, 0, 0)
-#define _MX51_PAD_EIM_D16__UART2_CTS            IOMUX_PAD(0x3f0, 0x5c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D16__USBH2_DATA0          IOMUX_PAD(0x3f0, 0x5c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D17__AUD5_RXD             IOMUX_PAD(0x3f4, 0x60, 7, 0x08d4, 0, 0)
-#define _MX51_PAD_EIM_D17__EIM_D17              IOMUX_PAD(0x3f4, 0x60, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D17__GPIO2_1              IOMUX_PAD(0x3f4, 0x60, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D17__UART2_RXD            IOMUX_PAD(0x3f4, 0x60, 3, 0x09ec, 0, 0)
-#define _MX51_PAD_EIM_D17__UART3_CTS            IOMUX_PAD(0x3f4, 0x60, 4, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D17__USBH2_DATA1          IOMUX_PAD(0x3f4, 0x60, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D18__AUD5_TXC             IOMUX_PAD(0x3f8, 0x64, 7, 0x08e4, 0, 0)
-#define _MX51_PAD_EIM_D18__EIM_D18              IOMUX_PAD(0x3f8, 0x64, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D18__GPIO2_2              IOMUX_PAD(0x3f8, 0x64, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D18__UART2_TXD            IOMUX_PAD(0x3f8, 0x64, 3, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D18__UART3_RTS            IOMUX_PAD(0x3f8, 0x64, 4, 0x09f0, 1, 0)
-#define _MX51_PAD_EIM_D18__USBH2_DATA2          IOMUX_PAD(0x3f8, 0x64, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D19__AUD4_RXC             IOMUX_PAD(0x3fc, 0x68, 5, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D19__AUD5_TXFS            IOMUX_PAD(0x3fc, 0x68, 7, 0x08e8, 0, 0)
-#define _MX51_PAD_EIM_D19__EIM_D19              IOMUX_PAD(0x3fc, 0x68, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D19__GPIO2_3              IOMUX_PAD(0x3fc, 0x68, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D19__I2C1_SCL             IOMUX_PAD(0x3fc, 0x68, 0x14, 0x09b0, 0, 0)
-#define _MX51_PAD_EIM_D19__UART2_RTS            IOMUX_PAD(0x3fc, 0x68, 3, 0x09e8, 1, 0)
-#define _MX51_PAD_EIM_D19__USBH2_DATA3          IOMUX_PAD(0x3fc, 0x68, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D20__AUD4_TXD             IOMUX_PAD(0x400, 0x6c, 5, 0x08c8, 0, 0)
-#define _MX51_PAD_EIM_D20__EIM_D20              IOMUX_PAD(0x400, 0x6c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D20__GPIO2_4              IOMUX_PAD(0x400, 0x6c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D20__SRTC_ALARM_DEB       IOMUX_PAD(0x400, 0x6c, 4, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D20__USBH2_DATA4          IOMUX_PAD(0x400, 0x6c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D21__AUD4_RXD             IOMUX_PAD(0x404, 0x70, 5, 0x08c4, 0, 0)
-#define _MX51_PAD_EIM_D21__EIM_D21              IOMUX_PAD(0x404, 0x70, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D21__GPIO2_5              IOMUX_PAD(0x404, 0x70, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D21__SRTC_ALARM_DEB       IOMUX_PAD(0x404, 0x70, 3, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D21__USBH2_DATA5          IOMUX_PAD(0x404, 0x70, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D22__AUD4_TXC             IOMUX_PAD(0x408, 0x74, 5, 0x08cc, 0, 0)
-#define _MX51_PAD_EIM_D22__EIM_D22              IOMUX_PAD(0x408, 0x74, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D22__GPIO2_6              IOMUX_PAD(0x408, 0x74, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D22__USBH2_DATA6          IOMUX_PAD(0x408, 0x74, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D23__AUD4_TXFS            IOMUX_PAD(0x40c, 0x78, 5, 0x08d0, 0, 0)
-#define _MX51_PAD_EIM_D23__EIM_D23              IOMUX_PAD(0x40c, 0x78, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D23__GPIO2_7              IOMUX_PAD(0x40c, 0x78, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D23__SPDIF_OUT1           IOMUX_PAD(0x40c, 0x78, 4, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D23__USBH2_DATA7          IOMUX_PAD(0x40c, 0x78, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D24__AUD6_RXFS            IOMUX_PAD(0x410, 0x7c, 5, 0x08f8, 0, 0)
-#define _MX51_PAD_EIM_D24__EIM_D24              IOMUX_PAD(0x410, 0x7c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D24__GPIO2_8              IOMUX_PAD(0x410, 0x7c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D24__I2C2_SDA             IOMUX_PAD(0x410, 0x7c, 0x14, 0x09bc, 0, 0)
-#define _MX51_PAD_EIM_D24__UART3_CTS            IOMUX_PAD(0x410, 0x7c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D24__USBOTG_DATA0         IOMUX_PAD(0x410, 0x7c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D25__EIM_D25              IOMUX_PAD(0x414, 0x80, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D25__KEY_COL6             IOMUX_PAD(0x414, 0x80, 1, 0x09c8, 0, 0)
-#define _MX51_PAD_EIM_D25__UART2_CTS            IOMUX_PAD(0x414, 0x80, 4, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D25__UART3_RXD            IOMUX_PAD(0x414, 0x80, 3, 0x09f4, 0, 0)
-#define _MX51_PAD_EIM_D25__USBOTG_DATA1         IOMUX_PAD(0x414, 0x80, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D26__EIM_D26              IOMUX_PAD(0x418, 0x84, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D26__KEY_COL7             IOMUX_PAD(0x418, 0x84, 1, 0x09cc, 0, 0)
-#define _MX51_PAD_EIM_D26__UART2_RTS            IOMUX_PAD(0x418, 0x84, 4, 0x09e8, 3, 0)
-#define _MX51_PAD_EIM_D26__UART3_TXD            IOMUX_PAD(0x418, 0x84, 3, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D26__USBOTG_DATA2         IOMUX_PAD(0x418, 0x84, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D27__AUD6_RXC             IOMUX_PAD(0x41c, 0x88, 5, 0x08f4, 0, 0)
-#define _MX51_PAD_EIM_D27__EIM_D27              IOMUX_PAD(0x41c, 0x88, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D27__GPIO2_9              IOMUX_PAD(0x41c, 0x88, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D27__I2C2_SCL             IOMUX_PAD(0x41c, 0x88, 0x14, 0x09b8, 0, 0)
-#define _MX51_PAD_EIM_D27__UART3_RTS            IOMUX_PAD(0x41c, 0x88, 3, 0x09f0, 3, 0)
-#define _MX51_PAD_EIM_D27__USBOTG_DATA3         IOMUX_PAD(0x41c, 0x88, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D28__AUD6_TXD             IOMUX_PAD(0x420, 0x8c, 5, 0x08f0, 0, 0)
-#define _MX51_PAD_EIM_D28__EIM_D28              IOMUX_PAD(0x420, 0x8c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D28__KEY_ROW4             IOMUX_PAD(0x420, 0x8c, 1, 0x09d0, 0, 0)
-#define _MX51_PAD_EIM_D28__USBOTG_DATA4         IOMUX_PAD(0x420, 0x8c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D29__AUD6_RXD             IOMUX_PAD(0x424, 0x90, 5, 0x08ec, 0, 0)
-#define _MX51_PAD_EIM_D29__EIM_D29              IOMUX_PAD(0x424, 0x90, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D29__KEY_ROW5             IOMUX_PAD(0x424, 0x90, 1, 0x09d4, 0, 0)
-#define _MX51_PAD_EIM_D29__USBOTG_DATA5         IOMUX_PAD(0x424, 0x90, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D30__AUD6_TXC             IOMUX_PAD(0x428, 0x94, 5, 0x08fc, 0, 0)
-#define _MX51_PAD_EIM_D30__EIM_D30              IOMUX_PAD(0x428, 0x94, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D30__KEY_ROW6             IOMUX_PAD(0x428, 0x94, 1, 0x09d8, 0, 0)
-#define _MX51_PAD_EIM_D30__USBOTG_DATA6         IOMUX_PAD(0x428, 0x94, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D31__AUD6_TXFS            IOMUX_PAD(0x42c, 0x98, 5, 0x0900, 0, 0)
-#define _MX51_PAD_EIM_D31__EIM_D31              IOMUX_PAD(0x42c, 0x98, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D31__KEY_ROW7             IOMUX_PAD(0x42c, 0x98, 1, 0x09dc, 0, 0)
-#define _MX51_PAD_EIM_D31__USBOTG_DATA7         IOMUX_PAD(0x42c, 0x98, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A16__EIM_A16              IOMUX_PAD(0x430, 0x9c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A16__GPIO2_10             IOMUX_PAD(0x430, 0x9c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A16__OSC_FREQ_SEL0        IOMUX_PAD(0x430, 0x9c, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A17__EIM_A17              IOMUX_PAD(0x434, 0xa0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A17__GPIO2_11             IOMUX_PAD(0x434, 0xa0, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A17__OSC_FREQ_SEL1        IOMUX_PAD(0x434, 0xa0, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A18__BOOT_LPB0            IOMUX_PAD(0x438, 0xa4, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A18__EIM_A18              IOMUX_PAD(0x438, 0xa4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A18__GPIO2_12             IOMUX_PAD(0x438, 0xa4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A19__BOOT_LPB1            IOMUX_PAD(0x43c, 0xa8, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A19__EIM_A19              IOMUX_PAD(0x43c, 0xa8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A19__GPIO2_13             IOMUX_PAD(0x43c, 0xa8, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A20__BOOT_UART_SRC0       IOMUX_PAD(0x440, 0xac, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A20__EIM_A20              IOMUX_PAD(0x440, 0xac, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A20__GPIO2_14             IOMUX_PAD(0x440, 0xac, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A21__BOOT_UART_SRC1       IOMUX_PAD(0x444, 0xb0, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A21__EIM_A21              IOMUX_PAD(0x444, 0xb0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A21__GPIO2_15             IOMUX_PAD(0x444, 0xb0, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A22__EIM_A22              IOMUX_PAD(0x448, 0xb4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A22__GPIO2_16             IOMUX_PAD(0x448, 0xb4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A23__BOOT_HPN_EN          IOMUX_PAD(0x44c, 0xb8, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A23__EIM_A23              IOMUX_PAD(0x44c, 0xb8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A23__GPIO2_17             IOMUX_PAD(0x44c, 0xb8, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A24__EIM_A24              IOMUX_PAD(0x450, 0xbc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A24__GPIO2_18             IOMUX_PAD(0x450, 0xbc, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A24__USBH2_CLK            IOMUX_PAD(0x450, 0xbc, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A25__DISP1_PIN4           IOMUX_PAD(0x454, 0xc0, 6, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A25__EIM_A25              IOMUX_PAD(0x454, 0xc0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A25__GPIO2_19             IOMUX_PAD(0x454, 0xc0, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A25__USBH2_DIR            IOMUX_PAD(0x454, 0xc0, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A26__CSI1_DATA_EN         IOMUX_PAD(0x458, 0xc4, 5, 0x09a0, 0, 0)
-#define _MX51_PAD_EIM_A26__DISP2_EXT_CLK        IOMUX_PAD(0x458, 0xc4, 6, 0x0908, 0, 0)
-#define _MX51_PAD_EIM_A26__EIM_A26              IOMUX_PAD(0x458, 0xc4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A26__GPIO2_20             IOMUX_PAD(0x458, 0xc4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A26__USBH2_STP            IOMUX_PAD(0x458, 0xc4, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A27__CSI2_DATA_EN         IOMUX_PAD(0x45c, 0xc8, 5, 0x099c, 0, 0)
-#define _MX51_PAD_EIM_A27__DISP1_PIN1           IOMUX_PAD(0x45c, 0xc8, 6, 0x09a4, 0, 0)
-#define _MX51_PAD_EIM_A27__EIM_A27              IOMUX_PAD(0x45c, 0xc8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A27__GPIO2_21             IOMUX_PAD(0x45c, 0xc8, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A27__USBH2_NXT            IOMUX_PAD(0x45c, 0xc8, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB0__EIM_EB0              IOMUX_PAD(0x460, 0xcc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB1__EIM_EB1              IOMUX_PAD(0x464, 0xd0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB2__AUD5_RXFS            IOMUX_PAD(0x468, 0xd4, 6, 0x08e0, 0, 0)
-#define _MX51_PAD_EIM_EB2__CSI1_D2              IOMUX_PAD(0x468, 0xd4, 5, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB2__EIM_EB2              IOMUX_PAD(0x468, 0xd4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB2__FEC_MDIO             IOMUX_PAD(0x468, 0xd4, 3, 0x0954, 0, 0)
-#define _MX51_PAD_EIM_EB2__GPIO2_22             IOMUX_PAD(0x468, 0xd4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB2__GPT_CMPOUT1          IOMUX_PAD(0x468, 0xd4, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB3__AUD5_RXC             IOMUX_PAD(0x46c, 0xd8, 6, 0x08dc, 0, 0)
-#define _MX51_PAD_EIM_EB3__CSI1_D3              IOMUX_PAD(0x46c, 0xd8, 5, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB3__EIM_EB3              IOMUX_PAD(0x46c, 0xd8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB3__FEC_RDATA1           IOMUX_PAD(0x46c, 0xd8, 3, 0x095c, 0, 0)
-#define _MX51_PAD_EIM_EB3__GPIO2_23             IOMUX_PAD(0x46c, 0xd8, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB3__GPT_CMPOUT2          IOMUX_PAD(0x46c, 0xd8, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_OE__EIM_OE                IOMUX_PAD(0x470, 0xdc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_OE__GPIO2_24              IOMUX_PAD(0x470, 0xdc, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS0__EIM_CS0              IOMUX_PAD(0x474, 0xe0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS0__GPIO2_25             IOMUX_PAD(0x474, 0xe0, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS1__EIM_CS1              IOMUX_PAD(0x478, 0xe4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS1__GPIO2_26             IOMUX_PAD(0x478, 0xe4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS2__AUD5_TXD             IOMUX_PAD(0x47c, 0xe8, 6, 0x08d8, 1, 0)
-#define _MX51_PAD_EIM_CS2__CSI1_D4              IOMUX_PAD(0x47c, 0xe8, 5, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS2__EIM_CS2              IOMUX_PAD(0x47c, 0xe8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS2__FEC_RDATA2           IOMUX_PAD(0x47c, 0xe8, 3, 0x0960, 0, 0)
-#define _MX51_PAD_EIM_CS2__GPIO2_27             IOMUX_PAD(0x47c, 0xe8, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS2__USBOTG_STP           IOMUX_PAD(0x47c, 0xe8, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS3__AUD5_RXD             IOMUX_PAD(0x480, 0xec, 6, 0x08d4, 1, 0)
-#define _MX51_PAD_EIM_CS3__CSI1_D5              IOMUX_PAD(0x480, 0xec, 5, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS3__EIM_CS3              IOMUX_PAD(0x480, 0xec, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS3__FEC_RDATA3           IOMUX_PAD(0x480, 0xec, 3, 0x0964, 0, 0)
-#define _MX51_PAD_EIM_CS3__GPIO2_28             IOMUX_PAD(0x480, 0xec, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS3__USBOTG_NXT           IOMUX_PAD(0x480, 0xec, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS4__AUD5_TXC             IOMUX_PAD(0x484, 0xf0, 6, 0x08e4, 1, 0)
-#define _MX51_PAD_EIM_CS4__CSI1_D6              IOMUX_PAD(0x484, 0xf0, 5, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS4__EIM_CS4              IOMUX_PAD(0x484, 0xf0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS4__FEC_RX_ER            IOMUX_PAD(0x484, 0xf0, 3, 0x0970, 0, 0)
-#define _MX51_PAD_EIM_CS4__GPIO2_29             IOMUX_PAD(0x484, 0xf0, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS4__USBOTG_CLK           IOMUX_PAD(0x484, 0xf0, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS5__AUD5_TXFS            IOMUX_PAD(0x488, 0xf4, 6, 0x08e8, 1, 0)
-#define _MX51_PAD_EIM_CS5__CSI1_D7              IOMUX_PAD(0x488, 0xf4, 5, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS5__DISP1_EXT_CLK        IOMUX_PAD(0x488, 0xf4, 4, 0x0904, 0, 0)
-#define _MX51_PAD_EIM_CS5__EIM_CS5              IOMUX_PAD(0x488, 0xf4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS5__FEC_CRS              IOMUX_PAD(0x488, 0xf4, 3, 0x0950, 0, 0)
-#define _MX51_PAD_EIM_CS5__GPIO2_30             IOMUX_PAD(0x488, 0xf4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS5__USBOTG_DIR           IOMUX_PAD(0x488, 0xf4, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DTACK__EIM_DTACK          IOMUX_PAD(0x48c, 0xf8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DTACK__GPIO2_31           IOMUX_PAD(0x48c, 0xf8, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_LBA__EIM_LBA              IOMUX_PAD(0x494, 0xfc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_LBA__GPIO3_1              IOMUX_PAD(0x494, 0xfc, 1, 0x0978, 0, 0)
-#define _MX51_PAD_EIM_CRE__EIM_CRE              IOMUX_PAD(0x4a0, 0x100, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CRE__GPIO3_2              IOMUX_PAD(0x4a0, 0x100, 1, 0x097c, 0, 0)
-#define _MX51_PAD_DRAM_CS1__DRAM_CS1            IOMUX_PAD(0x4d0, 0x104, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_WE_B__GPIO3_3           IOMUX_PAD(0x4e4, 0x108, 3, 0x0980, 0, 0)
-#define _MX51_PAD_NANDF_WE_B__NANDF_WE_B        IOMUX_PAD(0x4e4, 0x108, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_WE_B__PATA_DIOW         IOMUX_PAD(0x4e4, 0x108, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_WE_B__SD3_DATA0         IOMUX_PAD(0x4e4, 0x108, 2, 0x093c, 0, 0)
-#define _MX51_PAD_NANDF_RE_B__GPIO3_4           IOMUX_PAD(0x4e8, 0x10c, 3, 0x0984, 0, 0)
-#define _MX51_PAD_NANDF_RE_B__NANDF_RE_B        IOMUX_PAD(0x4e8, 0x10c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RE_B__PATA_DIOR         IOMUX_PAD(0x4e8, 0x10c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RE_B__SD3_DATA1         IOMUX_PAD(0x4e8, 0x10c, 2, 0x0940, 0, 0)
-#define _MX51_PAD_NANDF_ALE__GPIO3_5            IOMUX_PAD(0x4ec, 0x110, 3, 0x0988, 0, 0)
-#define _MX51_PAD_NANDF_ALE__NANDF_ALE          IOMUX_PAD(0x4ec, 0x110, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_ALE__PATA_BUFFER_EN     IOMUX_PAD(0x4ec, 0x110, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CLE__GPIO3_6            IOMUX_PAD(0x4f0, 0x114, 3, 0x098c, 0, 0)
-#define _MX51_PAD_NANDF_CLE__NANDF_CLE          IOMUX_PAD(0x4f0, 0x114, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CLE__PATA_RESET_B       IOMUX_PAD(0x4f0, 0x114, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_WP_B__GPIO3_7           IOMUX_PAD(0x4f4, 0x118, 3, 0x0990, 0, 0)
-#define _MX51_PAD_NANDF_WP_B__NANDF_WP_B        IOMUX_PAD(0x4f4, 0x118, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_WP_B__PATA_DMACK        IOMUX_PAD(0x4f4, 0x118, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_WP_B__SD3_DATA2         IOMUX_PAD(0x4f4, 0x118, 2, 0x0944, 0, 0)
-#define _MX51_PAD_NANDF_RB0__ECSPI2_SS1         IOMUX_PAD(0x4f8, 0x11c, 5, 0x0930, 0, 0)
-#define _MX51_PAD_NANDF_RB0__GPIO3_8            IOMUX_PAD(0x4f8, 0x11c, 3, 0x0994, 0, 0)
-#define _MX51_PAD_NANDF_RB0__NANDF_RB0          IOMUX_PAD(0x4f8, 0x11c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB0__PATA_DMARQ         IOMUX_PAD(0x4f8, 0x11c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB0__SD3_DATA3          IOMUX_PAD(0x4f8, 0x11c, 2, 0x0948, 0, 0)
-#define _MX51_PAD_NANDF_RB1__CSPI_MOSI          IOMUX_PAD(0x4fc, 0x120, 6, 0x091c, 0, 0)
-#define _MX51_PAD_NANDF_RB1__ECSPI2_RDY         IOMUX_PAD(0x4fc, 0x120, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB1__GPIO3_9            IOMUX_PAD(0x4fc, 0x120, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB1__NANDF_RB1          IOMUX_PAD(0x4fc, 0x120, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB1__PATA_IORDY         IOMUX_PAD(0x4fc, 0x120, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB1__SD4_CMD            IOMUX_PAD(0x4fc, 0x120, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB2__DISP2_WAIT         IOMUX_PAD(0x500, 0x124, 5, 0x09a8, 0, 0)
-#define _MX51_PAD_NANDF_RB2__ECSPI2_SCLK        IOMUX_PAD(0x500, 0x124, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB2__FEC_COL            IOMUX_PAD(0x500, 0x124, 1, 0x094c, 0, 0)
-#define _MX51_PAD_NANDF_RB2__GPIO3_10           IOMUX_PAD(0x500, 0x124, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB2__NANDF_RB2          IOMUX_PAD(0x500, 0x124, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB2__USBH3_H3_DP        IOMUX_PAD(0x500, 0x124, 7, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB2__USBH3_NXT          IOMUX_PAD(0x500, 0x124, 6, 0x0a20, 0, 0)
-#define _MX51_PAD_NANDF_RB3__DISP1_WAIT         IOMUX_PAD(0x504, 0x128, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB3__ECSPI2_MISO        IOMUX_PAD(0x504, 0x128, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB3__FEC_RX_CLK         IOMUX_PAD(0x504, 0x128, 1, 0x0968, 0, 0)
-#define _MX51_PAD_NANDF_RB3__GPIO3_11           IOMUX_PAD(0x504, 0x128, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB3__NANDF_RB3          IOMUX_PAD(0x504, 0x128, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB3__USBH3_CLK          IOMUX_PAD(0x504, 0x128, 6, 0x09f8, 0, 0)
-#define _MX51_PAD_NANDF_RB3__USBH3_H3_DM        IOMUX_PAD(0x504, 0x128, 7, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO_NAND__GPIO_NAND          IOMUX_PAD(0x514, 0x12c, 0, 0x0998, 0, 0)
-#define _MX51_PAD_GPIO_NAND__PATA_INTRQ         IOMUX_PAD(0x514, 0x12c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS0__GPIO3_16           IOMUX_PAD(0x518, 0x130, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS0__NANDF_CS0          IOMUX_PAD(0x518, 0x130, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS1__GPIO3_17           IOMUX_PAD(0x51c, 0x134, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS1__NANDF_CS1          IOMUX_PAD(0x51c, 0x134, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS2__CSPI_SCLK          IOMUX_PAD(0x520, 0x138, 6, 0x0914, 0, 0)
-#define _MX51_PAD_NANDF_CS2__FEC_TX_ER          IOMUX_PAD(0x520, 0x138, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS2__GPIO3_18           IOMUX_PAD(0x520, 0x138, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS2__NANDF_CS2          IOMUX_PAD(0x520, 0x138, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS2__PATA_CS_0          IOMUX_PAD(0x520, 0x138, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS2__SD4_CLK            IOMUX_PAD(0x520, 0x138, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS2__USBH3_H1_DP        IOMUX_PAD(0x520, 0x138, 7, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS3__FEC_MDC            IOMUX_PAD(0x524, 0x13c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS3__GPIO3_19           IOMUX_PAD(0x524, 0x13c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS3__NANDF_CS3          IOMUX_PAD(0x524, 0x13c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS3__PATA_CS_1          IOMUX_PAD(0x524, 0x13c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS3__SD4_DAT0           IOMUX_PAD(0x524, 0x13c, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS3__USBH3_H1_DM        IOMUX_PAD(0x524, 0x13c, 7, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS4__FEC_TDATA1         IOMUX_PAD(0x528, 0x140, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS4__GPIO3_20           IOMUX_PAD(0x528, 0x140, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS4__NANDF_CS4          IOMUX_PAD(0x528, 0x140, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS4__PATA_DA_0          IOMUX_PAD(0x528, 0x140, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS4__SD4_DAT1           IOMUX_PAD(0x528, 0x140, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS4__USBH3_STP          IOMUX_PAD(0x528, 0x140, 7, 0x0a24, 0, 0)
-#define _MX51_PAD_NANDF_CS5__FEC_TDATA2         IOMUX_PAD(0x52c, 0x144, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS5__GPIO3_21           IOMUX_PAD(0x52c, 0x144, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS5__NANDF_CS5          IOMUX_PAD(0x52c, 0x144, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS5__PATA_DA_1          IOMUX_PAD(0x52c, 0x144, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS5__SD4_DAT2           IOMUX_PAD(0x52c, 0x144, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS5__USBH3_DIR          IOMUX_PAD(0x52c, 0x144, 7, 0x0a1c, 0, 0)
-#define _MX51_PAD_NANDF_CS6__CSPI_SS3           IOMUX_PAD(0x530, 0x148, 7, 0x0928, 0, 0)
-#define _MX51_PAD_NANDF_CS6__FEC_TDATA3         IOMUX_PAD(0x530, 0x148, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS6__GPIO3_22           IOMUX_PAD(0x530, 0x148, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS6__NANDF_CS6          IOMUX_PAD(0x530, 0x148, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS6__PATA_DA_2          IOMUX_PAD(0x530, 0x148, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS6__SD4_DAT3           IOMUX_PAD(0x530, 0x148, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS7__FEC_TX_EN          IOMUX_PAD(0x534, 0x14c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS7__GPIO3_23           IOMUX_PAD(0x534, 0x14c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS7__NANDF_CS7          IOMUX_PAD(0x534, 0x14c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS7__SD3_CLK            IOMUX_PAD(0x534, 0x14c, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0     IOMUX_PAD(0x538, 0x150, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK     IOMUX_PAD(0x538, 0x150, 1, 0x0974, 0, 0)
-#define _MX51_PAD_NANDF_RDY_INT__GPIO3_24       IOMUX_PAD(0x538, 0x150, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT  IOMUX_PAD(0x538, 0x150, 0, 0x0938, 0, 0)
-#define _MX51_PAD_NANDF_RDY_INT__SD3_CMD        IOMUX_PAD(0x538, 0x150, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D15__ECSPI2_MOSI        IOMUX_PAD(0x53c, 0x154, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D15__GPIO3_25           IOMUX_PAD(0x53c, 0x154, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D15__NANDF_D15          IOMUX_PAD(0x53c, 0x154, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D15__PATA_DATA15        IOMUX_PAD(0x53c, 0x154, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D15__SD3_DAT7           IOMUX_PAD(0x53c, 0x154, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D14__ECSPI2_SS3         IOMUX_PAD(0x540, 0x158, 2, 0x0934, 0, 0)
-#define _MX51_PAD_NANDF_D14__GPIO3_26           IOMUX_PAD(0x540, 0x158, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D14__NANDF_D14          IOMUX_PAD(0x540, 0x158, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D14__PATA_DATA14        IOMUX_PAD(0x540, 0x158, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D14__SD3_DAT6           IOMUX_PAD(0x540, 0x158, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D13__ECSPI2_SS2         IOMUX_PAD(0x544, 0x15c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D13__GPIO3_27           IOMUX_PAD(0x544, 0x15c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D13__NANDF_D13          IOMUX_PAD(0x544, 0x15c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D13__PATA_DATA13        IOMUX_PAD(0x544, 0x15c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D13__SD3_DAT5           IOMUX_PAD(0x544, 0x15c, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D12__ECSPI2_SS1         IOMUX_PAD(0x548, 0x160, 2, 0x0930, 1, 0)
-#define _MX51_PAD_NANDF_D12__GPIO3_28           IOMUX_PAD(0x548, 0x160, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D12__NANDF_D12          IOMUX_PAD(0x548, 0x160, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D12__PATA_DATA12        IOMUX_PAD(0x548, 0x160, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D12__SD3_DAT4           IOMUX_PAD(0x548, 0x160, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D11__FEC_RX_DV          IOMUX_PAD(0x54c, 0x164, 2, 0x096c, 0, 0)
-#define _MX51_PAD_NANDF_D11__GPIO3_29           IOMUX_PAD(0x54c, 0x164, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D11__NANDF_D11          IOMUX_PAD(0x54c, 0x164, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D11__PATA_DATA11        IOMUX_PAD(0x54c, 0x164, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D11__SD3_DATA3          IOMUX_PAD(0x54c, 0x164, 5, 0x0948, 1, 0)
-#define _MX51_PAD_NANDF_D10__GPIO3_30           IOMUX_PAD(0x550, 0x168, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D10__NANDF_D10          IOMUX_PAD(0x550, 0x168, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D10__PATA_DATA10        IOMUX_PAD(0x550, 0x168, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D10__SD3_DATA2          IOMUX_PAD(0x550, 0x168, 5, 0x0944, 1, 0)
-#define _MX51_PAD_NANDF_D9__FEC_RDATA0          IOMUX_PAD(0x554, 0x16c, 0x12, 0x0958, 0, 0)
-#define _MX51_PAD_NANDF_D9__GPIO3_31            IOMUX_PAD(0x554, 0x16c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D9__NANDF_D9            IOMUX_PAD(0x554, 0x16c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D9__PATA_DATA9          IOMUX_PAD(0x554, 0x16c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D9__SD3_DATA1           IOMUX_PAD(0x554, 0x16c, 5, 0x0940, 1, 0)
-#define _MX51_PAD_NANDF_D8__FEC_TDATA0          IOMUX_PAD(0x558, 0x170, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D8__GPIO4_0             IOMUX_PAD(0x558, 0x170, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D8__NANDF_D8            IOMUX_PAD(0x558, 0x170, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D8__PATA_DATA8          IOMUX_PAD(0x558, 0x170, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D8__SD3_DATA0           IOMUX_PAD(0x558, 0x170, 5, 0x093c, 1, 0)
-#define _MX51_PAD_NANDF_D7__GPIO4_1             IOMUX_PAD(0x55c, 0x174, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D7__NANDF_D7            IOMUX_PAD(0x55c, 0x174, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D7__PATA_DATA7          IOMUX_PAD(0x55c, 0x174, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D7__USBH3_DATA0         IOMUX_PAD(0x55c, 0x174, 5, 0x09fc, 0, 0)
-#define _MX51_PAD_NANDF_D6__GPIO4_2             IOMUX_PAD(0x560, 0x178, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D6__NANDF_D6            IOMUX_PAD(0x560, 0x178, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D6__PATA_DATA6          IOMUX_PAD(0x560, 0x178, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D6__SD4_LCTL            IOMUX_PAD(0x560, 0x178, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D6__USBH3_DATA1         IOMUX_PAD(0x560, 0x178, 5, 0x0a00, 0, 0)
-#define _MX51_PAD_NANDF_D5__GPIO4_3             IOMUX_PAD(0x564, 0x17c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D5__NANDF_D5            IOMUX_PAD(0x564, 0x17c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D5__PATA_DATA5          IOMUX_PAD(0x564, 0x17c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D5__SD4_WP              IOMUX_PAD(0x564, 0x17c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D5__USBH3_DATA2         IOMUX_PAD(0x564, 0x17c, 5, 0x0a04, 0, 0)
-#define _MX51_PAD_NANDF_D4__GPIO4_4             IOMUX_PAD(0x568, 0x180, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D4__NANDF_D4            IOMUX_PAD(0x568, 0x180, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D4__PATA_DATA4          IOMUX_PAD(0x568, 0x180, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D4__SD4_CD              IOMUX_PAD(0x568, 0x180, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D4__USBH3_DATA3         IOMUX_PAD(0x568, 0x180, 5, 0x0a08, 0, 0)
-#define _MX51_PAD_NANDF_D3__GPIO4_5             IOMUX_PAD(0x56c, 0x184, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D3__NANDF_D3            IOMUX_PAD(0x56c, 0x184, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D3__PATA_DATA3          IOMUX_PAD(0x56c, 0x184, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D3__SD4_DAT4            IOMUX_PAD(0x56c, 0x184, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D3__USBH3_DATA4         IOMUX_PAD(0x56c, 0x184, 5, 0x0a0c, 0, 0)
-#define _MX51_PAD_NANDF_D2__GPIO4_6             IOMUX_PAD(0x570, 0x188, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D2__NANDF_D2            IOMUX_PAD(0x570, 0x188, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D2__PATA_DATA2          IOMUX_PAD(0x570, 0x188, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D2__SD4_DAT5            IOMUX_PAD(0x570, 0x188, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D2__USBH3_DATA5         IOMUX_PAD(0x570, 0x188, 5, 0x0a10, 0, 0)
-#define _MX51_PAD_NANDF_D1__GPIO4_7             IOMUX_PAD(0x574, 0x18c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D1__NANDF_D1            IOMUX_PAD(0x574, 0x18c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D1__PATA_DATA1          IOMUX_PAD(0x574, 0x18c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D1__SD4_DAT6            IOMUX_PAD(0x574, 0x18c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D1__USBH3_DATA6         IOMUX_PAD(0x574, 0x18c, 5, 0x0a14, 0, 0)
-#define _MX51_PAD_NANDF_D0__GPIO4_8             IOMUX_PAD(0x578, 0x190, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D0__NANDF_D0            IOMUX_PAD(0x578, 0x190, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D0__PATA_DATA0          IOMUX_PAD(0x578, 0x190, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D0__SD4_DAT7            IOMUX_PAD(0x578, 0x190, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D0__USBH3_DATA7         IOMUX_PAD(0x578, 0x190, 5, 0x0a18, 0, 0)
-#define _MX51_PAD_CSI1_D8__CSI1_D8              IOMUX_PAD(0x57c, 0x194, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D8__GPIO3_12             IOMUX_PAD(0x57c, 0x194, 3, 0x0998, 1, 0)
-#define _MX51_PAD_CSI1_D9__CSI1_D9              IOMUX_PAD(0x580, 0x198, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D9__GPIO3_13             IOMUX_PAD(0x580, 0x198, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D10__CSI1_D10            IOMUX_PAD(0x584, 0x19c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D11__CSI1_D11            IOMUX_PAD(0x588, 0x1a0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D12__CSI1_D12            IOMUX_PAD(0x58c, 0x1a4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D13__CSI1_D13            IOMUX_PAD(0x590, 0x1a8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D14__CSI1_D14            IOMUX_PAD(0x594, 0x1ac, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D15__CSI1_D15            IOMUX_PAD(0x598, 0x1b0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D16__CSI1_D16            IOMUX_PAD(0x59c, 0x1b4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D17__CSI1_D17            IOMUX_PAD(0x5a0, 0x1b8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D18__CSI1_D18            IOMUX_PAD(0x5a4, 0x1bc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D19__CSI1_D19            IOMUX_PAD(0x5a8, 0x1c0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_VSYNC__CSI1_VSYNC        IOMUX_PAD(0x5ac, 0x1c4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_VSYNC__GPIO3_14          IOMUX_PAD(0x5ac, 0x1c4, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_HSYNC__CSI1_HSYNC        IOMUX_PAD(0x5b0, 0x1c8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_HSYNC__GPIO3_15          IOMUX_PAD(0x5b0, 0x1c8, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK      IOMUX_PAD(0x5b4, 0x000, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_MCLK__CSI1_MCLK          IOMUX_PAD(0x5b8, 0x000, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D12__CSI2_D12            IOMUX_PAD(0x5bc, 0x1cc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D12__GPIO4_9             IOMUX_PAD(0x5bc, 0x1cc, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D13__CSI2_D13            IOMUX_PAD(0x5c0, 0x1d0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D13__GPIO4_10            IOMUX_PAD(0x5c0, 0x1d0, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D14__CSI2_D14            IOMUX_PAD(0x5c4, 0x1d4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D15__CSI2_D15            IOMUX_PAD(0x5c8, 0x1d8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D16__CSI2_D16            IOMUX_PAD(0x5cc, 0x1dc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D17__CSI2_D17            IOMUX_PAD(0x5d0, 0x1e0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D18__CSI2_D18            IOMUX_PAD(0x5d4, 0x1e4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D18__GPIO4_11            IOMUX_PAD(0x5d4, 0x1e4, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D19__CSI2_D19            IOMUX_PAD(0x5d8, 0x1e8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D19__GPIO4_12            IOMUX_PAD(0x5d8, 0x1e8, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_VSYNC__CSI2_VSYNC        IOMUX_PAD(0x5dc, 0x1ec, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_VSYNC__GPIO4_13          IOMUX_PAD(0x5dc, 0x1ec, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_HSYNC__CSI2_HSYNC        IOMUX_PAD(0x5e0, 0x1f0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_HSYNC__GPIO4_14          IOMUX_PAD(0x5e0, 0x1f0, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK      IOMUX_PAD(0x5e4, 0x1f4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_PIXCLK__GPIO4_15         IOMUX_PAD(0x5e4, 0x1f4, 3, 0x0000, 0, 0)
-#define _MX51_PAD_I2C1_CLK__GPIO4_16            IOMUX_PAD(0x5e8, 0x1f8, 3, 0x0000, 0, 0)
-#define _MX51_PAD_I2C1_CLK__I2C1_CLK            IOMUX_PAD(0x5e8, 0x1f8, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_I2C1_DAT__GPIO4_17            IOMUX_PAD(0x5ec, 0x1fc, 3, 0x0000, 0, 0)
-#define _MX51_PAD_I2C1_DAT__I2C1_DAT            IOMUX_PAD(0x5ec, 0x1fc, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_TXD__AUD3_TXD         IOMUX_PAD(0x5f0, 0x200, 0, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_TXD__GPIO4_18         IOMUX_PAD(0x5f0, 0x200, 3, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_RXD__AUD3_RXD         IOMUX_PAD(0x5f4, 0x204, 0, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_RXD__GPIO4_19         IOMUX_PAD(0x5f4, 0x204, 3, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_RXD__UART3_RXD        IOMUX_PAD(0x5f4, 0x204, 1, 0x09f4, 2, 0)
-#define _MX51_PAD_AUD3_BB_CK__AUD3_TXC          IOMUX_PAD(0x5f8, 0x208, 0, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_CK__GPIO4_20          IOMUX_PAD(0x5f8, 0x208, 3, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_FS__AUD3_TXFS         IOMUX_PAD(0x5fc, 0x20c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_FS__GPIO4_21          IOMUX_PAD(0x5fc, 0x20c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_FS__UART3_TXD         IOMUX_PAD(0x5fc, 0x20c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI       IOMUX_PAD(0x600, 0x210, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_MOSI__GPIO4_22          IOMUX_PAD(0x600, 0x210, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_MOSI__I2C1_SDA          IOMUX_PAD(0x600, 0x210, 0x11, 0x09b4, 1, 0)
-#define _MX51_PAD_CSPI1_MISO__AUD4_RXD          IOMUX_PAD(0x604, 0x214, 1, 0x08c4, 1, 0)
-#define _MX51_PAD_CSPI1_MISO__ECSPI1_MISO       IOMUX_PAD(0x604, 0x214, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_MISO__GPIO4_23          IOMUX_PAD(0x604, 0x214, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_SS0__AUD4_TXC           IOMUX_PAD(0x608, 0x218, 1, 0x08cc, 1, 0)
-#define _MX51_PAD_CSPI1_SS0__ECSPI1_SS0         IOMUX_PAD(0x608, 0x218, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_SS0__GPIO4_24           IOMUX_PAD(0x608, 0x218, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_SS1__AUD4_TXD           IOMUX_PAD(0x60c, 0x21c, 1, 0x08c8, 1, 0)
-#define _MX51_PAD_CSPI1_SS1__ECSPI1_SS1         IOMUX_PAD(0x60c, 0x21c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_SS1__GPIO4_25           IOMUX_PAD(0x60c, 0x21c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_RDY__AUD4_TXFS          IOMUX_PAD(0x610, 0x220, 1, 0x08d0, 1, 0)
-#define _MX51_PAD_CSPI1_RDY__ECSPI1_RDY         IOMUX_PAD(0x610, 0x220, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_RDY__GPIO4_26           IOMUX_PAD(0x610, 0x220, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK       IOMUX_PAD(0x614, 0x224, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_SCLK__GPIO4_27          IOMUX_PAD(0x614, 0x224, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_SCLK__I2C1_SCL          IOMUX_PAD(0x614, 0x224, 0x11, 0x09b0, 1, 0)
-#define _MX51_PAD_UART1_RXD__GPIO4_28           IOMUX_PAD(0x618, 0x228, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART1_RXD__UART1_RXD          IOMUX_PAD(0x618, 0x228, 0, 0x09e4, 0, 0)
-#define _MX51_PAD_UART1_TXD__GPIO4_29           IOMUX_PAD(0x61c, 0x22c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART1_TXD__PWM2_PWMO          IOMUX_PAD(0x61c, 0x22c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_UART1_TXD__UART1_TXD          IOMUX_PAD(0x61c, 0x22c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_UART1_RTS__GPIO4_30           IOMUX_PAD(0x620, 0x230, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART1_RTS__UART1_RTS          IOMUX_PAD(0x620, 0x230, 0, 0x09e0, 0, 0)
-#define _MX51_PAD_UART1_CTS__GPIO4_31           IOMUX_PAD(0x624, 0x234, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART1_CTS__UART1_CTS          IOMUX_PAD(0x624, 0x234, 0, 0x0000, 0, 0)
-#define _MX51_PAD_UART2_RXD__FIRI_TXD           IOMUX_PAD(0x628, 0x238, 1, 0x0000, 0, 0)
-#define _MX51_PAD_UART2_RXD__GPIO1_20           IOMUX_PAD(0x628, 0x238, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART2_RXD__UART2_RXD          IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0)
-#define _MX51_PAD_UART2_TXD__FIRI_RXD           IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_UART2_TXD__GPIO1_21           IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART2_TXD__UART2_TXD          IOMUX_PAD(0x62c, 0x23c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_UART3_RXD__CSI1_D0            IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0)
-#define _MX51_PAD_UART3_RXD__GPIO1_22           IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART3_RXD__UART1_DTR          IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0)
-#define _MX51_PAD_UART3_RXD__UART3_RXD          IOMUX_PAD(0x630, 0x240, 1, 0x09f4, 4, 0)
-#define _MX51_PAD_UART3_TXD__CSI1_D1            IOMUX_PAD(0x634, 0x244, 2, 0x0000, 0, 0)
-#define _MX51_PAD_UART3_TXD__GPIO1_23           IOMUX_PAD(0x634, 0x244, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART3_TXD__UART1_DSR          IOMUX_PAD(0x634, 0x244, 0, 0x0000, 0, 0)
-#define _MX51_PAD_UART3_TXD__UART3_TXD          IOMUX_PAD(0x634, 0x244, 1, 0x0000, 0, 0)
-#define _MX51_PAD_OWIRE_LINE__GPIO1_24          IOMUX_PAD(0x638, 0x248, 3, 0x0000, 0, 0)
-#define _MX51_PAD_OWIRE_LINE__OWIRE_LINE        IOMUX_PAD(0x638, 0x248, 0, 0x0000, 0, 0)
-#define _MX51_PAD_OWIRE_LINE__SPDIF_OUT         IOMUX_PAD(0x638, 0x248, 6, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_ROW0__KEY_ROW0            IOMUX_PAD(0x63c, 0x24c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_ROW1__KEY_ROW1            IOMUX_PAD(0x640, 0x250, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_ROW2__KEY_ROW2            IOMUX_PAD(0x644, 0x254, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_ROW3__KEY_ROW3            IOMUX_PAD(0x648, 0x258, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL0__KEY_COL0            IOMUX_PAD(0x64c, 0x25c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL0__PLL1_BYP            IOMUX_PAD(0x64c, 0x25c, 7, 0x090c, 0, 0)
-#define _MX51_PAD_KEY_COL1__KEY_COL1            IOMUX_PAD(0x650, 0x260, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL1__PLL2_BYP            IOMUX_PAD(0x650, 0x260, 7, 0x0910, 0, 0)
-#define _MX51_PAD_KEY_COL2__KEY_COL2            IOMUX_PAD(0x654, 0x264, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL2__PLL3_BYP            IOMUX_PAD(0x654, 0x264, 7, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL3__KEY_COL3            IOMUX_PAD(0x658, 0x268, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL4__I2C2_SCL            IOMUX_PAD(0x65c, 0x26c, 0x13, 0x09b8, 1, 0)
-#define _MX51_PAD_KEY_COL4__KEY_COL4            IOMUX_PAD(0x65c, 0x26c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL4__SPDIF_OUT1          IOMUX_PAD(0x65c, 0x26c, 6, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL4__UART1_RI            IOMUX_PAD(0x65c, 0x26c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL4__UART3_RTS           IOMUX_PAD(0x65c, 0x26c, 2, 0x09f0, 4, 0)
-#define _MX51_PAD_KEY_COL5__I2C2_SDA            IOMUX_PAD(0x660, 0x270, 0x13, 0x09bc, 1, 0)
-#define _MX51_PAD_KEY_COL5__KEY_COL5            IOMUX_PAD(0x660, 0x270, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL5__UART1_DCD           IOMUX_PAD(0x660, 0x270, 1, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL5__UART3_CTS           IOMUX_PAD(0x660, 0x270, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_CLK__CSPI_SCLK          IOMUX_PAD(0x678, 0x278, 1, 0x0914, 1, 0)
-#define _MX51_PAD_USBH1_CLK__GPIO1_25           IOMUX_PAD(0x678, 0x278, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_CLK__I2C2_SCL           IOMUX_PAD(0x678, 0x278, 0x15, 0x09b8, 2, 0)
-#define _MX51_PAD_USBH1_CLK__USBH1_CLK          IOMUX_PAD(0x678, 0x278, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DIR__CSPI_MOSI          IOMUX_PAD(0x67c, 0x27c, 1, 0x091c, 1, 0)
-#define _MX51_PAD_USBH1_DIR__GPIO1_26           IOMUX_PAD(0x67c, 0x27c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DIR__I2C2_SDA           IOMUX_PAD(0x67c, 0x27c, 0x15, 0x09bc, 2, 0)
-#define _MX51_PAD_USBH1_DIR__USBH1_DIR          IOMUX_PAD(0x67c, 0x27c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_STP__CSPI_RDY           IOMUX_PAD(0x680, 0x280, 1, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_STP__GPIO1_27           IOMUX_PAD(0x680, 0x280, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_STP__UART3_RXD          IOMUX_PAD(0x680, 0x280, 5, 0x09f4, 6, 0)
-#define _MX51_PAD_USBH1_STP__USBH1_STP          IOMUX_PAD(0x680, 0x280, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_NXT__CSPI_MISO          IOMUX_PAD(0x684, 0x284, 1, 0x0918, 0, 0)
-#define _MX51_PAD_USBH1_NXT__GPIO1_28           IOMUX_PAD(0x684, 0x284, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_NXT__UART3_TXD          IOMUX_PAD(0x684, 0x284, 5, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_NXT__USBH1_NXT          IOMUX_PAD(0x684, 0x284, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA0__GPIO1_11         IOMUX_PAD(0x688, 0x288, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA0__UART2_CTS        IOMUX_PAD(0x688, 0x288, 1, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA0__USBH1_DATA0      IOMUX_PAD(0x688, 0x288, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA1__GPIO1_12         IOMUX_PAD(0x68c, 0x28c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA1__UART2_RXD        IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0)
-#define _MX51_PAD_USBH1_DATA1__USBH1_DATA1      IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA2__GPIO1_13         IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA2__UART2_TXD        IOMUX_PAD(0x690, 0x290, 1, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA2__USBH1_DATA2      IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA3__GPIO1_14         IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA3__UART2_RTS        IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0)
-#define _MX51_PAD_USBH1_DATA3__USBH1_DATA3      IOMUX_PAD(0x694, 0x294, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA4__CSPI_SS0         IOMUX_PAD(0x698, 0x298, 1, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA4__GPIO1_15         IOMUX_PAD(0x698, 0x298, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA4__USBH1_DATA4      IOMUX_PAD(0x698, 0x298, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA5__CSPI_SS1         IOMUX_PAD(0x69c, 0x29c, 1, 0x0920, 0, 0)
-#define _MX51_PAD_USBH1_DATA5__GPIO1_16         IOMUX_PAD(0x69c, 0x29c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA5__USBH1_DATA5      IOMUX_PAD(0x69c, 0x29c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA6__CSPI_SS3         IOMUX_PAD(0x6a0, 0x2a0, 1, 0x0928, 1, 0)
-#define _MX51_PAD_USBH1_DATA6__GPIO1_17         IOMUX_PAD(0x6a0, 0x2a0, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA6__USBH1_DATA6      IOMUX_PAD(0x6a0, 0x2a0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA7__ECSPI1_SS3       IOMUX_PAD(0x6a4, 0x2a4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA7__ECSPI2_SS3       IOMUX_PAD(0x6a4, 0x2a4, 5, 0x0934, 1, 0)
-#define _MX51_PAD_USBH1_DATA7__GPIO1_18         IOMUX_PAD(0x6a4, 0x2a4, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA7__USBH1_DATA7      IOMUX_PAD(0x6a4, 0x2a4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_PIN11__DI1_PIN11          IOMUX_PAD(0x6a8, 0x2a8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_PIN11__ECSPI1_SS2         IOMUX_PAD(0x6a8, 0x2a8, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_PIN11__GPIO3_0            IOMUX_PAD(0x6a8, 0x2a8, 4, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_PIN12__DI1_PIN12          IOMUX_PAD(0x6ac, 0x2ac, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_PIN12__GPIO3_1            IOMUX_PAD(0x6ac, 0x2ac, 4, 0x0978, 1, 0)
-#define _MX51_PAD_DI1_PIN13__DI1_PIN13          IOMUX_PAD(0x6b0, 0x2b0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_PIN13__GPIO3_2            IOMUX_PAD(0x6b0, 0x2b0, 4, 0x097c, 1, 0)
-#define _MX51_PAD_DI1_D0_CS__DI1_D0_CS          IOMUX_PAD(0x6b4, 0x2b4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_D0_CS__GPIO3_3            IOMUX_PAD(0x6b4, 0x2b4, 4, 0x0980, 1, 0)
-#define _MX51_PAD_DI1_D1_CS__DI1_D1_CS          IOMUX_PAD(0x6b8, 0x2b8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_D1_CS__DISP1_PIN14        IOMUX_PAD(0x6b8, 0x2b8, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_D1_CS__DISP1_PIN5         IOMUX_PAD(0x6b8, 0x2b8, 3, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_D1_CS__GPIO3_4            IOMUX_PAD(0x6b8, 0x2b8, 4, 0x0984, 1, 0)
-#define _MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1    IOMUX_PAD(0x6bc, 0x2bc, 2, 0x09a4, 1, 0)
-#define _MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN        IOMUX_PAD(0x6bc, 0x2bc, 0, 0x09c4, 0, 0)
-#define _MX51_PAD_DISPB2_SER_DIN__GPIO3_5       IOMUX_PAD(0x6bc, 0x2bc, 4, 0x0988, 1, 0)
-#define _MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6    IOMUX_PAD(0x6c0, 0x2c0, 3, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO        IOMUX_PAD(0x6c0, 0x2c0, 0, 0x09c4, 1, 0)
-#define _MX51_PAD_DISPB2_SER_DIO__GPIO3_6       IOMUX_PAD(0x6c0, 0x2c0, 4, 0x098c, 1, 0)
-#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17   IOMUX_PAD(0x6c4, 0x2c4, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7    IOMUX_PAD(0x6c4, 0x2c4, 3, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK        IOMUX_PAD(0x6c4, 0x2c4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_CLK__GPIO3_7       IOMUX_PAD(0x6c4, 0x2c4, 4, 0x0990, 1, 0)
-#define _MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK  IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN16    IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN8     IOMUX_PAD(0x6c8, 0x2c8, 3, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS  IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS  IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_RS__GPIO3_8        IOMUX_PAD(0x6c8, 0x2c8, 4, 0x0994, 1, 0)
-#define _MX51_PAD_DISP1_DAT0__DISP1_DAT0        IOMUX_PAD(0x6cc, 0x2cc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT1__DISP1_DAT1        IOMUX_PAD(0x6d0, 0x2d0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT2__DISP1_DAT2        IOMUX_PAD(0x6d4, 0x2d4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT3__DISP1_DAT3        IOMUX_PAD(0x6d8, 0x2d8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT4__DISP1_DAT4        IOMUX_PAD(0x6dc, 0x2dc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT5__DISP1_DAT5        IOMUX_PAD(0x6e0, 0x2e0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT6__BOOT_USB_SRC      IOMUX_PAD(0x6e4, 0x2e4, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT6__DISP1_DAT6        IOMUX_PAD(0x6e4, 0x2e4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG   IOMUX_PAD(0x6e8, 0x2e8, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT7__DISP1_DAT7        IOMUX_PAD(0x6e8, 0x2e8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT8__BOOT_SRC0         IOMUX_PAD(0x6ec, 0x2ec, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT8__DISP1_DAT8        IOMUX_PAD(0x6ec, 0x2ec, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT9__BOOT_SRC1         IOMUX_PAD(0x6f0, 0x2f0, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT9__DISP1_DAT9        IOMUX_PAD(0x6f0, 0x2f0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE  IOMUX_PAD(0x6f4, 0x2f4, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT10__DISP1_DAT10      IOMUX_PAD(0x6f4, 0x2f4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2   IOMUX_PAD(0x6f8, 0x2f8, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT11__DISP1_DAT11      IOMUX_PAD(0x6f8, 0x2f8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL     IOMUX_PAD(0x6fc, 0x2fc, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT12__DISP1_DAT12      IOMUX_PAD(0x6fc, 0x2fc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0    IOMUX_PAD(0x700, 0x300, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT13__DISP1_DAT13      IOMUX_PAD(0x700, 0x300, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1    IOMUX_PAD(0x704, 0x304, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT14__DISP1_DAT14      IOMUX_PAD(0x704, 0x304, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH   IOMUX_PAD(0x708, 0x308, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT15__DISP1_DAT15      IOMUX_PAD(0x708, 0x308, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0  IOMUX_PAD(0x70c, 0x30c, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT16__DISP1_DAT16      IOMUX_PAD(0x70c, 0x30c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1  IOMUX_PAD(0x710, 0x310, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT17__DISP1_DAT17      IOMUX_PAD(0x710, 0x310, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT18__DISP1_DAT18      IOMUX_PAD(0x714, 0x314, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT18__DISP2_PIN11      IOMUX_PAD(0x714, 0x314, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT18__DISP2_PIN5       IOMUX_PAD(0x714, 0x314, 4, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT19__DISP1_DAT19      IOMUX_PAD(0x718, 0x318, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT19__DISP2_PIN12      IOMUX_PAD(0x718, 0x318, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT19__DISP2_PIN6       IOMUX_PAD(0x718, 0x318, 4, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0   IOMUX_PAD(0x71c, 0x31c, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT20__DISP1_DAT20      IOMUX_PAD(0x71c, 0x31c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT20__DISP2_PIN13      IOMUX_PAD(0x71c, 0x31c, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT20__DISP2_PIN7       IOMUX_PAD(0x71c, 0x31c, 4, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1   IOMUX_PAD(0x720, 0x320, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT21__DISP1_DAT21      IOMUX_PAD(0x720, 0x320, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT21__DISP2_PIN14      IOMUX_PAD(0x720, 0x320, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT21__DISP2_PIN8       IOMUX_PAD(0x720, 0x320, 4, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0   IOMUX_PAD(0x724, 0x324, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT22__DISP1_DAT22      IOMUX_PAD(0x724, 0x324, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT22__DISP2_D0_CS      IOMUX_PAD(0x724, 0x324, 6, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT22__DISP2_DAT16      IOMUX_PAD(0x724, 0x324, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1   IOMUX_PAD(0x728, 0x328, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT23__DISP1_DAT23      IOMUX_PAD(0x728, 0x328, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT23__DISP2_D1_CS      IOMUX_PAD(0x728, 0x328, 6, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT23__DISP2_DAT17      IOMUX_PAD(0x728, 0x328, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT23__DISP2_SER_CS     IOMUX_PAD(0x728, 0x328, 4, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_PIN3__DI1_PIN3            IOMUX_PAD(0x72c, 0x32c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_PIN2__DI1_PIN2            IOMUX_PAD(0x734, 0x330, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI_GP2__DISP1_SER_CLK         IOMUX_PAD(0x740, 0x338, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI_GP2__DISP2_WAIT            IOMUX_PAD(0x740, 0x338, 2, 0x09a8, 1, 0)
-#define _MX51_PAD_DI_GP3__CSI1_DATA_EN          IOMUX_PAD(0x744, 0x33c, 3, 0x09a0, 1, 0)
-#define _MX51_PAD_DI_GP3__DISP1_SER_DIO         IOMUX_PAD(0x744, 0x33c, 0, 0x09c0, 0, 0)
-#define _MX51_PAD_DI_GP3__FEC_TX_ER             IOMUX_PAD(0x744, 0x33c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DI2_PIN4__CSI2_DATA_EN        IOMUX_PAD(0x748, 0x340, 3, 0x099c, 1, 0)
-#define _MX51_PAD_DI2_PIN4__DI2_PIN4            IOMUX_PAD(0x748, 0x340, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI2_PIN4__FEC_CRS             IOMUX_PAD(0x748, 0x340, 2, 0x0950, 1, 0)
-#define _MX51_PAD_DI2_PIN2__DI2_PIN2            IOMUX_PAD(0x74c, 0x344, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI2_PIN2__FEC_MDC             IOMUX_PAD(0x74c, 0x344, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DI2_PIN3__DI2_PIN3            IOMUX_PAD(0x750, 0x348, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI2_PIN3__FEC_MDIO            IOMUX_PAD(0x750, 0x348, 2, 0x0954, 1, 0)
-#define _MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK    IOMUX_PAD(0x754, 0x34c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI2_DISP_CLK__FEC_RDATA1      IOMUX_PAD(0x754, 0x34c, 2, 0x095c, 1, 0)
-#define _MX51_PAD_DI_GP4__DI2_PIN15             IOMUX_PAD(0x758, 0x350, 4, 0x0000, 0, 0)
-#define _MX51_PAD_DI_GP4__DISP1_SER_DIN         IOMUX_PAD(0x758, 0x350, 0, 0x09c0, 1, 0)
-#define _MX51_PAD_DI_GP4__DISP2_PIN1            IOMUX_PAD(0x758, 0x350, 3, 0x0000, 0, 0)
-#define _MX51_PAD_DI_GP4__FEC_RDATA2            IOMUX_PAD(0x758, 0x350, 2, 0x0960, 1, 0)
-#define _MX51_PAD_DISP2_DAT0__DISP2_DAT0        IOMUX_PAD(0x75c, 0x354, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT0__FEC_RDATA3        IOMUX_PAD(0x75c, 0x354, 2, 0x0964, 1, 0)
-#define _MX51_PAD_DISP2_DAT0__KEY_COL6          IOMUX_PAD(0x75c, 0x354, 4, 0x09c8, 1, 0)
-#define _MX51_PAD_DISP2_DAT0__UART3_RXD         IOMUX_PAD(0x75c, 0x354, 5, 0x09f4, 8, 0)
-#define _MX51_PAD_DISP2_DAT0__USBH3_CLK         IOMUX_PAD(0x75c, 0x354, 3, 0x09f8, 1, 0)
-#define _MX51_PAD_DISP2_DAT1__DISP2_DAT1        IOMUX_PAD(0x760, 0x358, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT1__FEC_RX_ER         IOMUX_PAD(0x760, 0x358, 2, 0x0970, 1, 0)
-#define _MX51_PAD_DISP2_DAT1__KEY_COL7          IOMUX_PAD(0x760, 0x358, 4, 0x09cc, 1, 0)
-#define _MX51_PAD_DISP2_DAT1__UART3_TXD         IOMUX_PAD(0x760, 0x358, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT1__USBH3_DIR         IOMUX_PAD(0x760, 0x358, 3, 0x0a1c, 1, 0)
-#define _MX51_PAD_DISP2_DAT2__DISP2_DAT2        IOMUX_PAD(0x764, 0x35c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT3__DISP2_DAT3        IOMUX_PAD(0x768, 0x360, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT4__DISP2_DAT4        IOMUX_PAD(0x76c, 0x364, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT5__DISP2_DAT5        IOMUX_PAD(0x770, 0x368, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT6__DISP2_DAT6        IOMUX_PAD(0x774, 0x36c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT6__FEC_TDATA1        IOMUX_PAD(0x774, 0x36c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT6__GPIO1_19          IOMUX_PAD(0x774, 0x36c, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT6__KEY_ROW4          IOMUX_PAD(0x774, 0x36c, 4, 0x09d0, 1, 0)
-#define _MX51_PAD_DISP2_DAT6__USBH3_STP         IOMUX_PAD(0x774, 0x36c, 3, 0x0a24, 1, 0)
-#define _MX51_PAD_DISP2_DAT7__DISP2_DAT7        IOMUX_PAD(0x778, 0x370, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT7__FEC_TDATA2        IOMUX_PAD(0x778, 0x370, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT7__GPIO1_29          IOMUX_PAD(0x778, 0x370, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT7__KEY_ROW5          IOMUX_PAD(0x778, 0x370, 4, 0x09d4, 1, 0)
-#define _MX51_PAD_DISP2_DAT7__USBH3_NXT         IOMUX_PAD(0x778, 0x370, 3, 0x0a20, 1, 0)
-#define _MX51_PAD_DISP2_DAT8__DISP2_DAT8        IOMUX_PAD(0x77c, 0x374, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT8__FEC_TDATA3        IOMUX_PAD(0x77c, 0x374, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT8__GPIO1_30          IOMUX_PAD(0x77c, 0x374, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT8__KEY_ROW6          IOMUX_PAD(0x77c, 0x374, 4, 0x09d8, 1, 0)
-#define _MX51_PAD_DISP2_DAT8__USBH3_DATA0       IOMUX_PAD(0x77c, 0x374, 3, 0x09fc, 1, 0)
-#define _MX51_PAD_DISP2_DAT9__AUD6_RXC          IOMUX_PAD(0x780, 0x378, 4, 0x08f4, 1, 0)
-#define _MX51_PAD_DISP2_DAT9__DISP2_DAT9        IOMUX_PAD(0x780, 0x378, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT9__FEC_TX_EN         IOMUX_PAD(0x780, 0x378, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT9__GPIO1_31          IOMUX_PAD(0x780, 0x378, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT9__USBH3_DATA1       IOMUX_PAD(0x780, 0x378, 3, 0x0a00, 1, 0)
-#define _MX51_PAD_DISP2_DAT10__DISP2_DAT10      IOMUX_PAD(0x784, 0x37c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT10__DISP2_SER_CS     IOMUX_PAD(0x784, 0x37c, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT10__FEC_COL          IOMUX_PAD(0x784, 0x37c, 2, 0x094c, 1, 0)
-#define _MX51_PAD_DISP2_DAT10__KEY_ROW7         IOMUX_PAD(0x784, 0x37c, 4, 0x09dc, 1, 0)
-#define _MX51_PAD_DISP2_DAT10__USBH3_DATA2      IOMUX_PAD(0x784, 0x37c, 3, 0x0a04, 1, 0)
-#define _MX51_PAD_DISP2_DAT11__AUD6_TXD         IOMUX_PAD(0x788, 0x380, 4, 0x08f0, 1, 0)
-#define _MX51_PAD_DISP2_DAT11__DISP2_DAT11      IOMUX_PAD(0x788, 0x380, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT11__FEC_RX_CLK       IOMUX_PAD(0x788, 0x380, 2, 0x0968, 1, 0)
-#define _MX51_PAD_DISP2_DAT11__GPIO1_10         IOMUX_PAD(0x788, 0x380, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT11__USBH3_DATA3      IOMUX_PAD(0x788, 0x380, 3, 0x0a08, 1, 0)
-#define _MX51_PAD_DISP2_DAT12__AUD6_RXD         IOMUX_PAD(0x78c, 0x384, 4, 0x08ec, 1, 0)
-#define _MX51_PAD_DISP2_DAT12__DISP2_DAT12      IOMUX_PAD(0x78c, 0x384, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT12__FEC_RX_DV        IOMUX_PAD(0x78c, 0x384, 2, 0x096c, 1, 0)
-#define _MX51_PAD_DISP2_DAT12__USBH3_DATA4      IOMUX_PAD(0x78c, 0x384, 3, 0x0a0c, 1, 0)
-#define _MX51_PAD_DISP2_DAT13__AUD6_TXC         IOMUX_PAD(0x790, 0x388, 4, 0x08fc, 1, 0)
-#define _MX51_PAD_DISP2_DAT13__DISP2_DAT13      IOMUX_PAD(0x790, 0x388, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT13__FEC_TX_CLK       IOMUX_PAD(0x790, 0x388, 2, 0x0974, 1, 0)
-#define _MX51_PAD_DISP2_DAT13__USBH3_DATA5      IOMUX_PAD(0x790, 0x388, 3, 0x0a10, 1, 0)
-#define _MX51_PAD_DISP2_DAT14__AUD6_TXFS        IOMUX_PAD(0x794, 0x38c, 4, 0x0900, 1, 0)
-#define _MX51_PAD_DISP2_DAT14__DISP2_DAT14      IOMUX_PAD(0x794, 0x38c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT14__FEC_RDATA0       IOMUX_PAD(0x794, 0x38c, 2, 0x0958, 1, 0)
-#define _MX51_PAD_DISP2_DAT14__USBH3_DATA6      IOMUX_PAD(0x794, 0x38c, 3, 0x0a14, 1, 0)
-#define _MX51_PAD_DISP2_DAT15__AUD6_RXFS        IOMUX_PAD(0x798, 0x390, 4, 0x08f8, 1, 0)
-#define _MX51_PAD_DISP2_DAT15__DISP1_SER_CS     IOMUX_PAD(0x798, 0x390, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT15__DISP2_DAT15      IOMUX_PAD(0x798, 0x390, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT15__FEC_TDATA0       IOMUX_PAD(0x798, 0x390, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT15__USBH3_DATA7      IOMUX_PAD(0x798, 0x390, 3, 0x0a18, 1, 0)
-#define _MX51_PAD_SD1_CMD__AUD5_RXFS            IOMUX_PAD(0x79c, 0x394, 1, 0x08e0, 1, 0)
-#define _MX51_PAD_SD1_CMD__CSPI_MOSI            IOMUX_PAD(0x79c, 0x394, 2, 0x091c, 2, 0)
-#define _MX51_PAD_SD1_CMD__SD1_CMD              IOMUX_PAD(0x79c, 0x394, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_SD1_CLK__AUD5_RXC             IOMUX_PAD(0x7a0, 0x398, 1, 0x08dc, 1, 0)
-#define _MX51_PAD_SD1_CLK__CSPI_SCLK            IOMUX_PAD(0x7a0, 0x398, 2, 0x0914, 2, 0)
-#define _MX51_PAD_SD1_CLK__SD1_CLK              IOMUX_PAD(0x7a0, 0x398, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_SD1_DATA0__AUD5_TXD           IOMUX_PAD(0x7a4, 0x39c, 1, 0x08d8, 2, 0)
-#define _MX51_PAD_SD1_DATA0__CSPI_MISO          IOMUX_PAD(0x7a4, 0x39c, 2, 0x0918, 1, 0)
-#define _MX51_PAD_SD1_DATA0__SD1_DATA0          IOMUX_PAD(0x7a4, 0x39c, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA0__EIM_DA0              IOMUX_PAD(0x000, 0x01c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA1__EIM_DA1              IOMUX_PAD(0x000, 0x020, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA2__EIM_DA2              IOMUX_PAD(0x000, 0x024, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA3__EIM_DA3              IOMUX_PAD(0x000, 0x028, 0, 0x0000, 0, 0)
-#define _MX51_PAD_SD1_DATA1__AUD5_RXD           IOMUX_PAD(0x7a8, 0x3a0, 1, 0x08d4, 2, 0)
-#define _MX51_PAD_SD1_DATA1__SD1_DATA1          IOMUX_PAD(0x7a8, 0x3a0, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA4__EIM_DA4              IOMUX_PAD(0x000, 0x02c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA5__EIM_DA5              IOMUX_PAD(0x000, 0x030, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA6__EIM_DA6              IOMUX_PAD(0x000, 0x034, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA7__EIM_DA7              IOMUX_PAD(0x000, 0x038, 0, 0x0000, 0, 0)
-#define _MX51_PAD_SD1_DATA2__AUD5_TXC           IOMUX_PAD(0x7ac, 0x3a4, 1, 0x08e4, 2, 0)
-#define _MX51_PAD_SD1_DATA2__SD1_DATA2          IOMUX_PAD(0x7ac, 0x3a4, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA10__EIM_DA10            IOMUX_PAD(0x000, 0x044, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA11__EIM_DA11            IOMUX_PAD(0x000, 0x048, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA8__EIM_DA8              IOMUX_PAD(0x000, 0x03c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA9__EIM_DA9              IOMUX_PAD(0x000, 0x040, 0, 0x0000, 0, 0)
-#define _MX51_PAD_SD1_DATA3__AUD5_TXFS          IOMUX_PAD(0x7b0, 0x3a8, 1, 0x08e8, 2, 0)
-#define _MX51_PAD_SD1_DATA3__CSPI_SS1           IOMUX_PAD(0x7b0, 0x3a8, 2, 0x0920, 1, 0)
-#define _MX51_PAD_SD1_DATA3__SD1_DATA3          IOMUX_PAD(0x7b0, 0x3a8, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_0__CSPI_SS2             IOMUX_PAD(0x7b4, 0x3ac, 2, 0x0924, 0, 0)
-#define _MX51_PAD_GPIO1_0__GPIO1_0              IOMUX_PAD(0x7b4, 0x3ac, 1, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_0__SD1_CD               IOMUX_PAD(0x7b4, 0x3ac, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_1__CSPI_MISO            IOMUX_PAD(0x7b8, 0x3b0, 2, 0x0918, 2, 0)
-#define _MX51_PAD_GPIO1_1__GPIO1_1              IOMUX_PAD(0x7b8, 0x3b0, 1, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_1__SD1_WP               IOMUX_PAD(0x7b8, 0x3b0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA12__EIM_DA12            IOMUX_PAD(0x000, 0x04c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA13__EIM_DA13            IOMUX_PAD(0x000, 0x050, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA14__EIM_DA14            IOMUX_PAD(0x000, 0x054, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA15__EIM_DA15            IOMUX_PAD(0x000, 0x058, 0, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_CMD__CSPI_MOSI            IOMUX_PAD(0x000, 0x3b4, 2, 0x091c, 3, 0)
-#define _MX51_PAD_SD2_CMD__I2C1_SCL             IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x09b0, 2, 0)
-#define _MX51_PAD_SD2_CMD__SD2_CMD              IOMUX_PAD(0x7bc, 0x3b4, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_CLK__CSPI_SCLK            IOMUX_PAD(0x7c0, 0x3b8, 2, 0x0914, 3, 0)
-#define _MX51_PAD_SD2_CLK__I2C1_SDA             IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x09b4, 2, 0)
-#define _MX51_PAD_SD2_CLK__SD2_CLK              IOMUX_PAD(0x7c0, 0x3b8, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA0__CSPI_MISO          IOMUX_PAD(0x7c4, 0x3bc, 2, 0x0918, 3, 0)
-#define _MX51_PAD_SD2_DATA0__SD1_DAT4           IOMUX_PAD(0x7c4, 0x3bc, 1, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA0__SD2_DATA0          IOMUX_PAD(0x7c4, 0x3bc, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA1__SD1_DAT5           IOMUX_PAD(0x7c8, 0x3c0, 1, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA1__SD2_DATA1          IOMUX_PAD(0x7c8, 0x3c0, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA1__USBH3_H2_DP        IOMUX_PAD(0x7c8, 0x3c0, 2, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA2__SD1_DAT6           IOMUX_PAD(0x7cc, 0x3c4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA2__SD2_DATA2          IOMUX_PAD(0x7cc, 0x3c4, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA2__USBH3_H2_DM        IOMUX_PAD(0x7cc, 0x3c4, 2, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA3__CSPI_SS2           IOMUX_PAD(0x7d0, 0x3c8, 2, 0x0924, 1, 0)
-#define _MX51_PAD_SD2_DATA3__SD1_DAT7           IOMUX_PAD(0x7d0, 0x3c8, 1, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA3__SD2_DATA3          IOMUX_PAD(0x7d0, 0x3c8, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_2__CCM_OUT_2            IOMUX_PAD(0x7d4, 0x3cc, 5, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_2__GPIO1_2              IOMUX_PAD(0x7d4, 0x3cc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_2__I2C2_SCL             IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x09b8, 3, 0)
-#define _MX51_PAD_GPIO1_2__PLL1_BYP             IOMUX_PAD(0x7d4, 0x3cc, 7, 0x090c, 1, 0)
-#define _MX51_PAD_GPIO1_2__PWM1_PWMO            IOMUX_PAD(0x7d4, 0x3cc, 1, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_3__GPIO1_3              IOMUX_PAD(0x7d8, 0x3d0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_3__I2C2_SDA             IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x09bc, 3, 0)
-#define _MX51_PAD_GPIO1_3__PLL2_BYP             IOMUX_PAD(0x7d8, 0x3d0, 7, 0x0910, 1, 0)
-#define _MX51_PAD_GPIO1_3__PWM2_PWMO            IOMUX_PAD(0x7d8, 0x3d0, 1, 0x0000, 0, 0)
-#define _MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ    IOMUX_PAD(0x7fc, 0x3d4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B  IOMUX_PAD(0x7fc, 0x3d4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_4__DISP2_EXT_CLK        IOMUX_PAD(0x804, 0x3d8, 4, 0x0908, 1, 0)
-#define _MX51_PAD_GPIO1_4__EIM_RDY              IOMUX_PAD(0x804, 0x3d8, 3, 0x0938, 1, 0)
-#define _MX51_PAD_GPIO1_4__GPIO1_4              IOMUX_PAD(0x804, 0x3d8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_4__WDOG1_WDOG_B         IOMUX_PAD(0x804, 0x3d8, 2, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_5__CSI2_MCLK            IOMUX_PAD(0x808, 0x3dc, 6, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_5__DISP2_PIN16          IOMUX_PAD(0x808, 0x3dc, 3, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_5__GPIO1_5              IOMUX_PAD(0x808, 0x3dc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_5__WDOG2_WDOG_B         IOMUX_PAD(0x808, 0x3dc, 2, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_6__DISP2_PIN17          IOMUX_PAD(0x80c, 0x3e0, 4, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_6__GPIO1_6              IOMUX_PAD(0x80c, 0x3e0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_6__REF_EN_B             IOMUX_PAD(0x80c, 0x3e0, 3, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_7__CCM_OUT_0            IOMUX_PAD(0x810, 0x3e4, 3, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_7__GPIO1_7              IOMUX_PAD(0x810, 0x3e4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_7__SD2_WP               IOMUX_PAD(0x810, 0x3e4, 6, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_7__SPDIF_OUT1           IOMUX_PAD(0x810, 0x3e4, 2, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_8__CSI2_DATA_EN         IOMUX_PAD(0x814, 0x3e8, 2, 0x099c, 2, 0)
-#define _MX51_PAD_GPIO1_8__GPIO1_8              IOMUX_PAD(0x814, 0x3e8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_8__SD2_CD               IOMUX_PAD(0x814, 0x3e8, 6, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_8__USBH3_PWR            IOMUX_PAD(0x814, 0x3e8, 1, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_9__CCM_OUT_1            IOMUX_PAD(0x818, 0x3ec, 3, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_9__DISP2_D1_CS          IOMUX_PAD(0x818, 0x3ec, 2, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_9__DISP2_SER_CS         IOMUX_PAD(0x818, 0x3ec, 7, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_9__GPIO1_9              IOMUX_PAD(0x818, 0x3ec, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_9__SD2_LCTL             IOMUX_PAD(0x818, 0x3ec, 6, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_9__USBH3_OC             IOMUX_PAD(0x818, 0x3ec, 1, 0x0000, 0, 0)
 
 /* The same pins as above but with the default pad control values applied */
-#define MX51_PAD_EIM_D16__AUD4_RXFS             (_MX51_PAD_EIM_D16__AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D16__AUD5_TXD              (_MX51_PAD_EIM_D16__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D16__EIM_D16               (_MX51_PAD_EIM_D16__EIM_D16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D16__GPIO2_0               (_MX51_PAD_EIM_D16__GPIO2_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_D16__I2C1_SDA              (_MX51_PAD_EIM_D16__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
-#define MX51_PAD_EIM_D16__UART2_CTS             (_MX51_PAD_EIM_D16__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_EIM_D16__USBH2_DATA0           (_MX51_PAD_EIM_D16__USBH2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D17__AUD5_RXD              (_MX51_PAD_EIM_D17__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D17__EIM_D17               (_MX51_PAD_EIM_D17__EIM_D17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D17__GPIO2_1               (_MX51_PAD_EIM_D17__GPIO2_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_D17__UART2_RXD             (_MX51_PAD_EIM_D17__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_EIM_D17__UART3_CTS             (_MX51_PAD_EIM_D17__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_EIM_D17__USBH2_DATA1           (_MX51_PAD_EIM_D17__USBH2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D18__AUD5_TXC              (_MX51_PAD_EIM_D18__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D18__EIM_D18               (_MX51_PAD_EIM_D18__EIM_D18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D18__GPIO2_2               (_MX51_PAD_EIM_D18__GPIO2_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_D18__UART2_TXD             (_MX51_PAD_EIM_D18__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_EIM_D18__UART3_RTS             (_MX51_PAD_EIM_D18__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_EIM_D18__USBH2_DATA2           (_MX51_PAD_EIM_D18__USBH2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D19__AUD4_RXC              (_MX51_PAD_EIM_D19__AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D19__AUD5_TXFS             (_MX51_PAD_EIM_D19__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D19__EIM_D19               (_MX51_PAD_EIM_D19__EIM_D19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D19__GPIO2_3               (_MX51_PAD_EIM_D19__GPIO2_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_D19__I2C1_SCL              (_MX51_PAD_EIM_D19__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
-#define MX51_PAD_EIM_D19__UART2_RTS             (_MX51_PAD_EIM_D19__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_EIM_D19__USBH2_DATA3           (_MX51_PAD_EIM_D19__USBH2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D20__AUD4_TXD              (_MX51_PAD_EIM_D20__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D20__EIM_D20               (_MX51_PAD_EIM_D20__EIM_D20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D20__GPIO2_4               (_MX51_PAD_EIM_D20__GPIO2_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB        (_MX51_PAD_EIM_D20__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D20__USBH2_DATA4           (_MX51_PAD_EIM_D20__USBH2_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D21__AUD4_RXD              (_MX51_PAD_EIM_D21__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D21__EIM_D21               (_MX51_PAD_EIM_D21__EIM_D21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D21__GPIO2_5               (_MX51_PAD_EIM_D21__GPIO2_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB        (_MX51_PAD_EIM_D21__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D21__USBH2_DATA5           (_MX51_PAD_EIM_D21__USBH2_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D22__AUD4_TXC              (_MX51_PAD_EIM_D22__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D22__EIM_D22               (_MX51_PAD_EIM_D22__EIM_D22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D22__GPIO2_6               (_MX51_PAD_EIM_D22__GPIO2_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_D22__USBH2_DATA6           (_MX51_PAD_EIM_D22__USBH2_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D23__AUD4_TXFS             (_MX51_PAD_EIM_D23__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D23__EIM_D23               (_MX51_PAD_EIM_D23__EIM_D23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D23__GPIO2_7               (_MX51_PAD_EIM_D23__GPIO2_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_D23__SPDIF_OUT1            (_MX51_PAD_EIM_D23__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D23__USBH2_DATA7           (_MX51_PAD_EIM_D23__USBH2_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D24__AUD6_RXFS             (_MX51_PAD_EIM_D24__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D24__EIM_D24               (_MX51_PAD_EIM_D24__EIM_D24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D24__GPIO2_8               (_MX51_PAD_EIM_D24__GPIO2_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_D24__I2C2_SDA              (_MX51_PAD_EIM_D24__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
-#define MX51_PAD_EIM_D24__UART3_CTS             (_MX51_PAD_EIM_D24__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_EIM_D24__USBOTG_DATA0          (_MX51_PAD_EIM_D24__USBOTG_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D25__EIM_D25               (_MX51_PAD_EIM_D25__EIM_D25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D25__KEY_COL6              (_MX51_PAD_EIM_D25__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D25__UART2_CTS             (_MX51_PAD_EIM_D25__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_EIM_D25__UART3_RXD             (_MX51_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_EIM_D25__USBOTG_DATA1          (_MX51_PAD_EIM_D25__USBOTG_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D26__EIM_D26               (_MX51_PAD_EIM_D26__EIM_D26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D26__KEY_COL7              (_MX51_PAD_EIM_D26__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D26__UART2_RTS             (_MX51_PAD_EIM_D26__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_EIM_D26__UART3_TXD             (_MX51_PAD_EIM_D26__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_EIM_D26__USBOTG_DATA2          (_MX51_PAD_EIM_D26__USBOTG_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D27__AUD6_RXC              (_MX51_PAD_EIM_D27__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D27__EIM_D27               (_MX51_PAD_EIM_D27__EIM_D27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D27__GPIO2_9               (_MX51_PAD_EIM_D27__GPIO2_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_D27__I2C2_SCL              (_MX51_PAD_EIM_D27__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
-#define MX51_PAD_EIM_D27__UART3_RTS             (_MX51_PAD_EIM_D27__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_EIM_D27__USBOTG_DATA3          (_MX51_PAD_EIM_D27__USBOTG_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D28__AUD6_TXD              (_MX51_PAD_EIM_D28__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D28__EIM_D28               (_MX51_PAD_EIM_D28__EIM_D28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D28__KEY_ROW4              (_MX51_PAD_EIM_D28__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D28__USBOTG_DATA4          (_MX51_PAD_EIM_D28__USBOTG_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D29__AUD6_RXD              (_MX51_PAD_EIM_D29__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D29__EIM_D29               (_MX51_PAD_EIM_D29__EIM_D29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D29__KEY_ROW5              (_MX51_PAD_EIM_D29__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D29__USBOTG_DATA5          (_MX51_PAD_EIM_D29__USBOTG_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D30__AUD6_TXC              (_MX51_PAD_EIM_D30__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D30__EIM_D30               (_MX51_PAD_EIM_D30__EIM_D30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D30__KEY_ROW6              (_MX51_PAD_EIM_D30__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D30__USBOTG_DATA6          (_MX51_PAD_EIM_D30__USBOTG_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D31__AUD6_TXFS             (_MX51_PAD_EIM_D31__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D31__EIM_D31               (_MX51_PAD_EIM_D31__EIM_D31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D31__KEY_ROW7              (_MX51_PAD_EIM_D31__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_D31__USBOTG_DATA7          (_MX51_PAD_EIM_D31__USBOTG_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A16__EIM_A16               (_MX51_PAD_EIM_A16__EIM_A16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A16__GPIO2_10              (_MX51_PAD_EIM_A16__GPIO2_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0         (_MX51_PAD_EIM_A16__OSC_FREQ_SEL0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A17__EIM_A17               (_MX51_PAD_EIM_A17__EIM_A17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A17__GPIO2_11              (_MX51_PAD_EIM_A17__GPIO2_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1         (_MX51_PAD_EIM_A17__OSC_FREQ_SEL1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A18__BOOT_LPB0             (_MX51_PAD_EIM_A18__BOOT_LPB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A18__EIM_A18               (_MX51_PAD_EIM_A18__EIM_A18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A18__GPIO2_12              (_MX51_PAD_EIM_A18__GPIO2_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_A19__BOOT_LPB1             (_MX51_PAD_EIM_A19__BOOT_LPB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A19__EIM_A19               (_MX51_PAD_EIM_A19__EIM_A19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A19__GPIO2_13              (_MX51_PAD_EIM_A19__GPIO2_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_A20__BOOT_UART_SRC0        (_MX51_PAD_EIM_A20__BOOT_UART_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A20__EIM_A20               (_MX51_PAD_EIM_A20__EIM_A20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A20__GPIO2_14              (_MX51_PAD_EIM_A20__GPIO2_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_A21__BOOT_UART_SRC1        (_MX51_PAD_EIM_A21__BOOT_UART_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A21__EIM_A21               (_MX51_PAD_EIM_A21__EIM_A21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A21__GPIO2_15              (_MX51_PAD_EIM_A21__GPIO2_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_A22__EIM_A22               (_MX51_PAD_EIM_A22__EIM_A22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A22__GPIO2_16              (_MX51_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_A23__BOOT_HPN_EN           (_MX51_PAD_EIM_A23__BOOT_HPN_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A23__EIM_A23               (_MX51_PAD_EIM_A23__EIM_A23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A23__GPIO2_17              (_MX51_PAD_EIM_A23__GPIO2_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_A24__EIM_A24               (_MX51_PAD_EIM_A24__EIM_A24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A24__GPIO2_18              (_MX51_PAD_EIM_A24__GPIO2_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_A24__USBH2_CLK             (_MX51_PAD_EIM_A24__USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A25__DISP1_PIN4            (_MX51_PAD_EIM_A25__DISP1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A25__EIM_A25               (_MX51_PAD_EIM_A25__EIM_A25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A25__GPIO2_19              (_MX51_PAD_EIM_A25__GPIO2_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_A25__USBH2_DIR             (_MX51_PAD_EIM_A25__USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A26__CSI1_DATA_EN          (_MX51_PAD_EIM_A26__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A26__DISP2_EXT_CLK         (_MX51_PAD_EIM_A26__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A26__EIM_A26               (_MX51_PAD_EIM_A26__EIM_A26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A26__GPIO2_20              (_MX51_PAD_EIM_A26__GPIO2_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_A26__USBH2_STP             (_MX51_PAD_EIM_A26__USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A27__CSI2_DATA_EN          (_MX51_PAD_EIM_A27__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A27__DISP1_PIN1            (_MX51_PAD_EIM_A27__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A27__EIM_A27               (_MX51_PAD_EIM_A27__EIM_A27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_A27__GPIO2_21              (_MX51_PAD_EIM_A27__GPIO2_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_A27__USBH2_NXT             (_MX51_PAD_EIM_A27__USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_EB0__EIM_EB0               (_MX51_PAD_EIM_EB0__EIM_EB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_EB1__EIM_EB1               (_MX51_PAD_EIM_EB1__EIM_EB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_EB2__AUD5_RXFS             (_MX51_PAD_EIM_EB2__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_EB2__CSI1_D2               (_MX51_PAD_EIM_EB2__CSI1_D2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_EB2__EIM_EB2               (_MX51_PAD_EIM_EB2__EIM_EB2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_EB2__FEC_MDIO              (_MX51_PAD_EIM_EB2__FEC_MDIO | \
+#define MX51_PAD_EIM_D16__AUD4_RXFS             IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__AUD5_TXD              IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__EIM_D16               IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__GPIO2_0               IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__I2C1_SDA              IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D16__UART2_CTS             IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D16__USBH2_DATA0           IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__AUD5_RXD              IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__EIM_D17               IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__GPIO2_1               IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__UART2_RXD             IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D17__UART3_CTS             IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D17__USBH2_DATA1           IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__AUD5_TXC              IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__EIM_D18               IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__GPIO2_2               IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__UART2_TXD             IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D18__UART3_RTS             IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D18__USBH2_DATA2           IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__AUD4_RXC              IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__AUD5_TXFS             IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__EIM_D19               IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__GPIO2_3               IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__I2C1_SCL              IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D19__UART2_RTS             IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D19__USBH2_DATA3           IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__AUD4_TXD              IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__EIM_D20               IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__GPIO2_4               IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB        IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__USBH2_DATA4           IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__AUD4_RXD              IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__EIM_D21               IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__GPIO2_5               IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB        IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__USBH2_DATA5           IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__AUD4_TXC              IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__EIM_D22               IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__GPIO2_6               IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__USBH2_DATA6           IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__AUD4_TXFS             IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__EIM_D23               IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__GPIO2_7               IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__SPDIF_OUT1            IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__USBH2_DATA7           IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__AUD6_RXFS             IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__EIM_D24               IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__GPIO2_8               IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__I2C2_SDA              IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D24__UART3_CTS             IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D24__USBOTG_DATA0          IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D25__EIM_D25               IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D25__KEY_COL6              IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART2_CTS             IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D25__USBOTG_DATA1          IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D26__EIM_D26               IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D26__KEY_COL7              IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART2_RTS             IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D26__USBOTG_DATA2          IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D27__AUD6_RXC              IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D27__EIM_D27               IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D27__GPIO2_9               IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D27__I2C2_SCL              IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D27__USBOTG_DATA3          IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D28__AUD6_TXD              IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D28__EIM_D28               IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D28__KEY_ROW4              IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D28__USBOTG_DATA4          IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__AUD6_RXD              IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__EIM_D29               IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__KEY_ROW5              IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__USBOTG_DATA5          IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__AUD6_TXC              IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__EIM_D30               IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__KEY_ROW6              IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__USBOTG_DATA6          IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__AUD6_TXFS             IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__EIM_D31               IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__KEY_ROW7              IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__USBOTG_DATA7          IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__EIM_A16               IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__GPIO2_10              IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0         IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__EIM_A17               IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__GPIO2_11              IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1         IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__BOOT_LPB0             IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__EIM_A18               IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__GPIO2_12              IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__BOOT_LPB1             IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__EIM_A19               IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__GPIO2_13              IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__BOOT_UART_SRC0        IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__EIM_A20               IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__GPIO2_14              IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__BOOT_UART_SRC1        IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__EIM_A21               IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__GPIO2_15              IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A22__EIM_A22               IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A22__GPIO2_16              IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__BOOT_HPN_EN           IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__EIM_A23               IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__GPIO2_17              IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__EIM_A24               IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__GPIO2_18              IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__USBH2_CLK             IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__DISP1_PIN4            IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__EIM_A25               IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__GPIO2_19              IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__USBH2_DIR             IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__CSI1_DATA_EN          IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__DISP2_EXT_CLK         IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__EIM_A26               IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__GPIO2_20              IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__USBH2_STP             IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__CSI2_DATA_EN          IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__DISP1_PIN1            IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__EIM_A27               IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__GPIO2_21              IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__USBH2_NXT             IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB0__EIM_EB0               IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB1__EIM_EB1               IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__AUD5_RXFS             IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__CSI1_D2               IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__EIM_EB2               IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__FEC_MDIO              (IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, 0) | \
                 MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
                 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS))
-#define MX51_PAD_EIM_EB2__GPIO2_22              (_MX51_PAD_EIM_EB2__GPIO2_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_EB2__GPT_CMPOUT1           (_MX51_PAD_EIM_EB2__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_EB3__AUD5_RXC              (_MX51_PAD_EIM_EB3__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_EB3__CSI1_D3               (_MX51_PAD_EIM_EB3__CSI1_D3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_EB3__EIM_EB3               (_MX51_PAD_EIM_EB3__EIM_EB3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_EB3__FEC_RDATA1            (_MX51_PAD_EIM_EB3__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_EB3__GPIO2_23              (_MX51_PAD_EIM_EB3__GPIO2_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_EB3__GPT_CMPOUT2           (_MX51_PAD_EIM_EB3__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_OE__EIM_OE                 (_MX51_PAD_EIM_OE__EIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_OE__GPIO2_24               (_MX51_PAD_EIM_OE__GPIO2_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_CS0__EIM_CS0               (_MX51_PAD_EIM_CS0__EIM_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS0__GPIO2_25              (_MX51_PAD_EIM_CS0__GPIO2_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_CS1__EIM_CS1               (_MX51_PAD_EIM_CS1__EIM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS1__GPIO2_26              (_MX51_PAD_EIM_CS1__GPIO2_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_CS2__AUD5_TXD              (_MX51_PAD_EIM_CS2__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS2__CSI1_D4               (_MX51_PAD_EIM_CS2__CSI1_D4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS2__EIM_CS2               (_MX51_PAD_EIM_CS2__EIM_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS2__FEC_RDATA2            (_MX51_PAD_EIM_CS2__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS2__GPIO2_27              (_MX51_PAD_EIM_CS2__GPIO2_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_CS2__USBOTG_STP            (_MX51_PAD_EIM_CS2__USBOTG_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS3__AUD5_RXD              (_MX51_PAD_EIM_CS3__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS3__CSI1_D5               (_MX51_PAD_EIM_CS3__CSI1_D5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS3__EIM_CS3               (_MX51_PAD_EIM_CS3__EIM_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS3__FEC_RDATA3            (_MX51_PAD_EIM_CS3__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS3__GPIO2_28              (_MX51_PAD_EIM_CS3__GPIO2_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_CS3__USBOTG_NXT            (_MX51_PAD_EIM_CS3__USBOTG_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS4__AUD5_TXC              (_MX51_PAD_EIM_CS4__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS4__CSI1_D6               (_MX51_PAD_EIM_CS4__CSI1_D6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS4__EIM_CS4               (_MX51_PAD_EIM_CS4__EIM_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS4__FEC_RX_ER             (_MX51_PAD_EIM_CS4__FEC_RX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
-#define MX51_PAD_EIM_CS4__GPIO2_29              (_MX51_PAD_EIM_CS4__GPIO2_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_CS4__USBOTG_CLK            (_MX51_PAD_EIM_CS4__USBOTG_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS5__AUD5_TXFS             (_MX51_PAD_EIM_CS5__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS5__CSI1_D7               (_MX51_PAD_EIM_CS5__CSI1_D7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK         (_MX51_PAD_EIM_CS5__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS5__EIM_CS5               (_MX51_PAD_EIM_CS5__EIM_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CS5__FEC_CRS               (_MX51_PAD_EIM_CS5__FEC_CRS | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
-#define MX51_PAD_EIM_CS5__GPIO2_30              (_MX51_PAD_EIM_CS5__GPIO2_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_CS5__USBOTG_DIR            (_MX51_PAD_EIM_CS5__USBOTG_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_DTACK__EIM_DTACK           (_MX51_PAD_EIM_DTACK__EIM_DTACK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_DTACK__GPIO2_31            (_MX51_PAD_EIM_DTACK__GPIO2_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_LBA__EIM_LBA               (_MX51_PAD_EIM_LBA__EIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_LBA__GPIO3_1               (_MX51_PAD_EIM_LBA__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_EIM_CRE__EIM_CRE               (_MX51_PAD_EIM_CRE__EIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_CRE__GPIO3_2               (_MX51_PAD_EIM_CRE__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_DRAM_CS1__DRAM_CS1             (_MX51_PAD_DRAM_CS1__DRAM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_WE_B__GPIO3_3            (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_WE_B__NANDF_WE_B         (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_WE_B__PATA_DIOW          (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_WE_B__SD3_DATA0          (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_NANDF_RE_B__GPIO3_4            (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_RE_B__NANDF_RE_B         (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RE_B__PATA_DIOR          (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RE_B__SD3_DATA1          (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_NANDF_ALE__GPIO3_5             (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_ALE__NANDF_ALE           (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN      (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CLE__GPIO3_6             (_MX51_PAD_NANDF_CLE__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_CLE__NANDF_CLE           (_MX51_PAD_NANDF_CLE__NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CLE__PATA_RESET_B        (_MX51_PAD_NANDF_CLE__PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_WP_B__GPIO3_7            (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_WP_B__NANDF_WP_B         (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_WP_B__PATA_DMACK         (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_WP_B__SD3_DATA2          (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_NANDF_RB0__ECSPI2_SS1          (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_NANDF_RB0__GPIO3_8             (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB0__NANDF_RB0           (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB0__PATA_DMARQ          (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB0__SD3_DATA3           (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_NANDF_RB1__CSPI_MOSI           (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_NANDF_RB1__ECSPI2_RDY          (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_NANDF_RB1__GPIO3_9             (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB1__NANDF_RB1           (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB1__PATA_IORDY          (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB1__SD4_CMD             (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_NANDF_RB2__DISP2_WAIT          (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_NANDF_RB2__FEC_COL             (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
-#define MX51_PAD_NANDF_RB2__GPIO3_10            (_MX51_PAD_NANDF_RB2__GPIO3_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB2__NANDF_RB2           (_MX51_PAD_NANDF_RB2__NANDF_RB2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB2__USBH3_H3_DP         (_MX51_PAD_NANDF_RB2__USBH3_H3_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB2__USBH3_NXT           (_MX51_PAD_NANDF_RB2__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB3__DISP1_WAIT          (_MX51_PAD_NANDF_RB3__DISP1_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB3__ECSPI2_MISO         (_MX51_PAD_NANDF_RB3__ECSPI2_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_NANDF_RB3__FEC_RX_CLK          (_MX51_PAD_NANDF_RB3__FEC_RX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
-#define MX51_PAD_NANDF_RB3__GPIO3_11            (_MX51_PAD_NANDF_RB3__GPIO3_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB3__NANDF_RB3           (_MX51_PAD_NANDF_RB3__NANDF_RB3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB3__USBH3_CLK           (_MX51_PAD_NANDF_RB3__USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB3__USBH3_H3_DM         (_MX51_PAD_NANDF_RB3__USBH3_H3_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO_NAND__GPIO_NAND           (_MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_GPIO_NAND__PATA_INTRQ          (_MX51_PAD_GPIO_NAND__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS0__GPIO3_16            (_MX51_PAD_NANDF_CS0__GPIO3_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS0__NANDF_CS0           (_MX51_PAD_NANDF_CS0__NANDF_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS1__GPIO3_17            (_MX51_PAD_NANDF_CS1__GPIO3_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS1__NANDF_CS1           (_MX51_PAD_NANDF_CS1__NANDF_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS2__CSPI_SCLK           (_MX51_PAD_NANDF_CS2__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_NANDF_CS2__FEC_TX_ER           (_MX51_PAD_NANDF_CS2__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
-#define MX51_PAD_NANDF_CS2__GPIO3_18            (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS2__NANDF_CS2           (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS2__PATA_CS_0           (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS2__SD4_CLK             (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
-#define MX51_PAD_NANDF_CS2__USBH3_H1_DP         (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS3__FEC_MDC             (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
-#define MX51_PAD_NANDF_CS3__GPIO3_19            (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS3__NANDF_CS3           (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS3__PATA_CS_1           (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS3__SD4_DAT0            (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_NANDF_CS3__USBH3_H1_DM         (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS4__FEC_TDATA1          (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
-#define MX51_PAD_NANDF_CS4__GPIO3_20            (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS4__NANDF_CS4           (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS4__PATA_DA_0           (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS4__SD4_DAT1            (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_NANDF_CS4__USBH3_STP           (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS5__FEC_TDATA2          (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
-#define MX51_PAD_NANDF_CS5__GPIO3_21            (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS5__NANDF_CS5           (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS5__PATA_DA_1           (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS5__SD4_DAT2            (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_NANDF_CS5__USBH3_DIR           (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS6__CSPI_SS3            (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_NANDF_CS6__FEC_TDATA3          (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
-#define MX51_PAD_NANDF_CS6__GPIO3_22            (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS6__NANDF_CS6           (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS6__PATA_DA_2           (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS6__SD4_DAT3            (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_NANDF_CS7__FEC_TX_EN           (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
-#define MX51_PAD_NANDF_CS7__GPIO3_23            (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS7__NANDF_CS7           (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS7__SD3_CLK             (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
-#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0      (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
-#define MX51_PAD_NANDF_RDY_INT__GPIO3_24        (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT   (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RDY_INT__SD3_CMD         (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_NANDF_D15__ECSPI2_MOSI         (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_NANDF_D15__GPIO3_25            (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_D15__NANDF_D15           (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D15__PATA_DATA15         (_MX51_PAD_NANDF_D15__PATA_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D15__SD3_DAT7            (_MX51_PAD_NANDF_D15__SD3_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D14__ECSPI2_SS3          (_MX51_PAD_NANDF_D14__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_NANDF_D14__GPIO3_26            (_MX51_PAD_NANDF_D14__GPIO3_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_D14__NANDF_D14           (_MX51_PAD_NANDF_D14__NANDF_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D14__PATA_DATA14         (_MX51_PAD_NANDF_D14__PATA_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D14__SD3_DAT6            (_MX51_PAD_NANDF_D14__SD3_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D13__ECSPI2_SS2          (_MX51_PAD_NANDF_D13__ECSPI2_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_NANDF_D13__GPIO3_27            (_MX51_PAD_NANDF_D13__GPIO3_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_D13__NANDF_D13           (_MX51_PAD_NANDF_D13__NANDF_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D13__PATA_DATA13         (_MX51_PAD_NANDF_D13__PATA_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D13__SD3_DAT5            (_MX51_PAD_NANDF_D13__SD3_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D12__ECSPI2_SS1          (_MX51_PAD_NANDF_D12__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_NANDF_D12__GPIO3_28            (_MX51_PAD_NANDF_D12__GPIO3_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_D12__NANDF_D12           (_MX51_PAD_NANDF_D12__NANDF_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D12__PATA_DATA12         (_MX51_PAD_NANDF_D12__PATA_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D12__SD3_DAT4            (_MX51_PAD_NANDF_D12__SD3_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D11__FEC_RX_DV           (_MX51_PAD_NANDF_D11__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D11__GPIO3_29            (_MX51_PAD_NANDF_D11__GPIO3_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_D11__NANDF_D11           (_MX51_PAD_NANDF_D11__NANDF_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D11__PATA_DATA11         (_MX51_PAD_NANDF_D11__PATA_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D11__SD3_DATA3           (_MX51_PAD_NANDF_D11__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D10__GPIO3_30            (_MX51_PAD_NANDF_D10__GPIO3_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_D10__NANDF_D10           (_MX51_PAD_NANDF_D10__NANDF_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D10__PATA_DATA10         (_MX51_PAD_NANDF_D10__PATA_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D10__SD3_DATA2           (_MX51_PAD_NANDF_D10__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D9__FEC_RDATA0           (_MX51_PAD_NANDF_D9__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
-#define MX51_PAD_NANDF_D9__GPIO3_31             (_MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_D9__NANDF_D9             (_MX51_PAD_NANDF_D9__NANDF_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D9__PATA_DATA9           (_MX51_PAD_NANDF_D9__PATA_DATA9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D9__SD3_DATA1            (_MX51_PAD_NANDF_D9__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D8__FEC_TDATA0           (_MX51_PAD_NANDF_D8__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
-#define MX51_PAD_NANDF_D8__GPIO4_0              (_MX51_PAD_NANDF_D8__GPIO4_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_D8__NANDF_D8             (_MX51_PAD_NANDF_D8__NANDF_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D8__PATA_DATA8           (_MX51_PAD_NANDF_D8__PATA_DATA8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D8__SD3_DATA0            (_MX51_PAD_NANDF_D8__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D7__GPIO4_1              (_MX51_PAD_NANDF_D7__GPIO4_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_D7__NANDF_D7             (_MX51_PAD_NANDF_D7__NANDF_D7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D7__PATA_DATA7           (_MX51_PAD_NANDF_D7__PATA_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D7__USBH3_DATA0          (_MX51_PAD_NANDF_D7__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D6__GPIO4_2              (_MX51_PAD_NANDF_D6__GPIO4_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_D6__NANDF_D6             (_MX51_PAD_NANDF_D6__NANDF_D6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D6__PATA_DATA6           (_MX51_PAD_NANDF_D6__PATA_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D6__SD4_LCTL             (_MX51_PAD_NANDF_D6__SD4_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D6__USBH3_DATA1          (_MX51_PAD_NANDF_D6__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D5__GPIO4_3              (_MX51_PAD_NANDF_D5__GPIO4_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_D5__NANDF_D5             (_MX51_PAD_NANDF_D5__NANDF_D5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D5__PATA_DATA5           (_MX51_PAD_NANDF_D5__PATA_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D5__SD4_WP               (_MX51_PAD_NANDF_D5__SD4_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D5__USBH3_DATA2          (_MX51_PAD_NANDF_D5__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D4__GPIO4_4              (_MX51_PAD_NANDF_D4__GPIO4_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_D4__NANDF_D4             (_MX51_PAD_NANDF_D4__NANDF_D4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D4__PATA_DATA4           (_MX51_PAD_NANDF_D4__PATA_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D4__SD4_CD               (_MX51_PAD_NANDF_D4__SD4_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D4__USBH3_DATA3          (_MX51_PAD_NANDF_D4__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D3__GPIO4_5              (_MX51_PAD_NANDF_D3__GPIO4_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_D3__NANDF_D3             (_MX51_PAD_NANDF_D3__NANDF_D3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D3__PATA_DATA3           (_MX51_PAD_NANDF_D3__PATA_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D3__SD4_DAT4             (_MX51_PAD_NANDF_D3__SD4_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D3__USBH3_DATA4          (_MX51_PAD_NANDF_D3__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D2__GPIO4_6              (_MX51_PAD_NANDF_D2__GPIO4_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_D2__NANDF_D2             (_MX51_PAD_NANDF_D2__NANDF_D2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D2__PATA_DATA2           (_MX51_PAD_NANDF_D2__PATA_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D2__SD4_DAT5             (_MX51_PAD_NANDF_D2__SD4_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D2__USBH3_DATA5          (_MX51_PAD_NANDF_D2__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D1__GPIO4_7              (_MX51_PAD_NANDF_D1__GPIO4_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_D1__NANDF_D1             (_MX51_PAD_NANDF_D1__NANDF_D1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D1__PATA_DATA1           (_MX51_PAD_NANDF_D1__PATA_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D1__SD4_DAT6             (_MX51_PAD_NANDF_D1__SD4_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D1__USBH3_DATA6          (_MX51_PAD_NANDF_D1__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D0__GPIO4_8              (_MX51_PAD_NANDF_D0__GPIO4_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_NANDF_D0__NANDF_D0             (_MX51_PAD_NANDF_D0__NANDF_D0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D0__PATA_DATA0           (_MX51_PAD_NANDF_D0__PATA_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D0__SD4_DAT7             (_MX51_PAD_NANDF_D0__SD4_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_D0__USBH3_DATA7          (_MX51_PAD_NANDF_D0__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI1_D8__CSI1_D8               (_MX51_PAD_CSI1_D8__CSI1_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI1_D8__GPIO3_12              (_MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_CSI1_D9__CSI1_D9               (_MX51_PAD_CSI1_D9__CSI1_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI1_D9__GPIO3_13              (_MX51_PAD_CSI1_D9__GPIO3_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_CSI1_D10__CSI1_D10             (_MX51_PAD_CSI1_D10__CSI1_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI1_D11__CSI1_D11             (_MX51_PAD_CSI1_D11__CSI1_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI1_D12__CSI1_D12             (_MX51_PAD_CSI1_D12__CSI1_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI1_D13__CSI1_D13             (_MX51_PAD_CSI1_D13__CSI1_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI1_D14__CSI1_D14             (_MX51_PAD_CSI1_D14__CSI1_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI1_D15__CSI1_D15             (_MX51_PAD_CSI1_D15__CSI1_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI1_D16__CSI1_D16             (_MX51_PAD_CSI1_D16__CSI1_D16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI1_D17__CSI1_D17             (_MX51_PAD_CSI1_D17__CSI1_D17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI1_D18__CSI1_D18             (_MX51_PAD_CSI1_D18__CSI1_D18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI1_D19__CSI1_D19             (_MX51_PAD_CSI1_D19__CSI1_D19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         (_MX51_PAD_CSI1_VSYNC__CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI1_VSYNC__GPIO3_14           (_MX51_PAD_CSI1_VSYNC__GPIO3_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         (_MX51_PAD_CSI1_HSYNC__CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI1_HSYNC__GPIO3_15           (_MX51_PAD_CSI1_HSYNC__GPIO3_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       (_MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           (_MX51_PAD_CSI1_MCLK__CSI1_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI2_D12__CSI2_D12             (_MX51_PAD_CSI2_D12__CSI2_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI2_D12__GPIO4_9              (_MX51_PAD_CSI2_D12__GPIO4_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_CSI2_D13__CSI2_D13             (_MX51_PAD_CSI2_D13__CSI2_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI2_D13__GPIO4_10             (_MX51_PAD_CSI2_D13__GPIO4_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_CSI2_D14__CSI2_D14             (_MX51_PAD_CSI2_D14__CSI2_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI2_D15__CSI2_D15             (_MX51_PAD_CSI2_D15__CSI2_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI2_D16__CSI2_D16             (_MX51_PAD_CSI2_D16__CSI2_D16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI2_D17__CSI2_D17             (_MX51_PAD_CSI2_D17__CSI2_D17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI2_D18__CSI2_D18             (_MX51_PAD_CSI2_D18__CSI2_D18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI2_D18__GPIO4_11             (_MX51_PAD_CSI2_D18__GPIO4_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_CSI2_D19__CSI2_D19             (_MX51_PAD_CSI2_D19__CSI2_D19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI2_D19__GPIO4_12             (_MX51_PAD_CSI2_D19__GPIO4_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC         (_MX51_PAD_CSI2_VSYNC__CSI2_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI2_VSYNC__GPIO4_13           (_MX51_PAD_CSI2_VSYNC__GPIO4_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC         (_MX51_PAD_CSI2_HSYNC__CSI2_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI2_HSYNC__GPIO4_14           (_MX51_PAD_CSI2_HSYNC__GPIO4_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK       (_MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSI2_PIXCLK__GPIO4_15          (_MX51_PAD_CSI2_PIXCLK__GPIO4_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_I2C1_CLK__GPIO4_16             (_MX51_PAD_I2C1_CLK__GPIO4_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_I2C1_CLK__I2C1_CLK             (_MX51_PAD_I2C1_CLK__I2C1_CLK | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
-#define MX51_PAD_I2C1_DAT__GPIO4_17             (_MX51_PAD_I2C1_DAT__GPIO4_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_I2C1_DAT__I2C1_DAT             (_MX51_PAD_I2C1_DAT__I2C1_DAT | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
-#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD          (_MX51_PAD_AUD3_BB_TXD__AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_AUD3_BB_TXD__GPIO4_18          (_MX51_PAD_AUD3_BB_TXD__GPIO4_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD          (_MX51_PAD_AUD3_BB_RXD__AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_AUD3_BB_RXD__GPIO4_19          (_MX51_PAD_AUD3_BB_RXD__GPIO4_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_AUD3_BB_RXD__UART3_RXD         (_MX51_PAD_AUD3_BB_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_AUD3_BB_CK__AUD3_TXC           (_MX51_PAD_AUD3_BB_CK__AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_AUD3_BB_CK__GPIO4_20           (_MX51_PAD_AUD3_BB_CK__GPIO4_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS          (_MX51_PAD_AUD3_BB_FS__AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_AUD3_BB_FS__GPIO4_21           (_MX51_PAD_AUD3_BB_FS__GPIO4_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_AUD3_BB_FS__UART3_TXD          (_MX51_PAD_AUD3_BB_FS__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        (_MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_CSPI1_MOSI__GPIO4_22           (_MX51_PAD_CSPI1_MOSI__GPIO4_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_CSPI1_MOSI__I2C1_SDA           (_MX51_PAD_CSPI1_MOSI__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
-#define MX51_PAD_CSPI1_MISO__AUD4_RXD           (_MX51_PAD_CSPI1_MISO__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO        (_MX51_PAD_CSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_CSPI1_MISO__GPIO4_23           (_MX51_PAD_CSPI1_MISO__GPIO4_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_CSPI1_SS0__AUD4_TXC            (_MX51_PAD_CSPI1_SS0__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0          (_MX51_PAD_CSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_CSPI1_SS0__GPIO4_24            (_MX51_PAD_CSPI1_SS0__GPIO4_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_CSPI1_SS1__AUD4_TXD            (_MX51_PAD_CSPI1_SS1__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1          (_MX51_PAD_CSPI1_SS1__ECSPI1_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_CSPI1_SS1__GPIO4_25            (_MX51_PAD_CSPI1_SS1__GPIO4_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_CSPI1_RDY__AUD4_TXFS           (_MX51_PAD_CSPI1_RDY__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY          (_MX51_PAD_CSPI1_RDY__ECSPI1_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_CSPI1_RDY__GPIO4_26            (_MX51_PAD_CSPI1_RDY__GPIO4_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        (_MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_CSPI1_SCLK__GPIO4_27           (_MX51_PAD_CSPI1_SCLK__GPIO4_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_CSPI1_SCLK__I2C1_SCL           (_MX51_PAD_CSPI1_SCLK__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
-#define MX51_PAD_UART1_RXD__GPIO4_28            (_MX51_PAD_UART1_RXD__GPIO4_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_UART1_RXD__UART1_RXD           (_MX51_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_UART1_TXD__GPIO4_29            (_MX51_PAD_UART1_TXD__GPIO4_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_UART1_TXD__PWM2_PWMO           (_MX51_PAD_UART1_TXD__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_UART1_TXD__UART1_TXD           (_MX51_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_UART1_RTS__GPIO4_30            (_MX51_PAD_UART1_RTS__GPIO4_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_UART1_RTS__UART1_RTS           (_MX51_PAD_UART1_RTS__UART1_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_UART1_CTS__GPIO4_31            (_MX51_PAD_UART1_CTS__GPIO4_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_UART1_CTS__UART1_CTS           (_MX51_PAD_UART1_CTS__UART1_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_UART2_RXD__FIRI_TXD            (_MX51_PAD_UART2_RXD__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_UART2_RXD__GPIO1_20            (_MX51_PAD_UART2_RXD__GPIO1_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_UART2_RXD__UART2_RXD           (_MX51_PAD_UART2_RXD__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_UART2_TXD__FIRI_RXD            (_MX51_PAD_UART2_TXD__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_UART2_TXD__GPIO1_21            (_MX51_PAD_UART2_TXD__GPIO1_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_UART2_TXD__UART2_TXD           (_MX51_PAD_UART2_TXD__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_UART3_RXD__CSI1_D0             (_MX51_PAD_UART3_RXD__CSI1_D0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_UART3_RXD__GPIO1_22            (_MX51_PAD_UART3_RXD__GPIO1_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_UART3_RXD__UART1_DTR           (_MX51_PAD_UART3_RXD__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_UART3_RXD__UART3_RXD           (_MX51_PAD_UART3_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_UART3_TXD__CSI1_D1             (_MX51_PAD_UART3_TXD__CSI1_D1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_UART3_TXD__GPIO1_23            (_MX51_PAD_UART3_TXD__GPIO1_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_UART3_TXD__UART1_DSR           (_MX51_PAD_UART3_TXD__UART1_DSR | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_UART3_TXD__UART3_TXD           (_MX51_PAD_UART3_TXD__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_OWIRE_LINE__GPIO1_24           (_MX51_PAD_OWIRE_LINE__GPIO1_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_OWIRE_LINE__OWIRE_LINE         (_MX51_PAD_OWIRE_LINE__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_OWIRE_LINE__SPDIF_OUT          (_MX51_PAD_OWIRE_LINE__SPDIF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_KEY_ROW0__KEY_ROW0             (_MX51_PAD_KEY_ROW0__KEY_ROW0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_KEY_ROW1__KEY_ROW1             (_MX51_PAD_KEY_ROW1__KEY_ROW1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_KEY_ROW2__KEY_ROW2             (_MX51_PAD_KEY_ROW2__KEY_ROW2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_KEY_ROW3__KEY_ROW3             (_MX51_PAD_KEY_ROW3__KEY_ROW3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_KEY_COL0__KEY_COL0             (_MX51_PAD_KEY_COL0__KEY_COL0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_KEY_COL0__PLL1_BYP             (_MX51_PAD_KEY_COL0__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_KEY_COL1__KEY_COL1             (_MX51_PAD_KEY_COL1__KEY_COL1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_KEY_COL1__PLL2_BYP             (_MX51_PAD_KEY_COL1__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_KEY_COL2__KEY_COL2             (_MX51_PAD_KEY_COL2__KEY_COL2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_KEY_COL2__PLL3_BYP             (_MX51_PAD_KEY_COL2__PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_KEY_COL3__KEY_COL3             (_MX51_PAD_KEY_COL3__KEY_COL3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_KEY_COL4__I2C2_SCL             (_MX51_PAD_KEY_COL4__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
-#define MX51_PAD_KEY_COL4__KEY_COL4             (_MX51_PAD_KEY_COL4__KEY_COL4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_KEY_COL4__SPDIF_OUT1           (_MX51_PAD_KEY_COL4__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_KEY_COL4__UART1_RI             (_MX51_PAD_KEY_COL4__UART1_RI | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_KEY_COL4__UART3_RTS            (_MX51_PAD_KEY_COL4__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_KEY_COL5__I2C2_SDA             (_MX51_PAD_KEY_COL5__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
-#define MX51_PAD_KEY_COL5__KEY_COL5             (_MX51_PAD_KEY_COL5__KEY_COL5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_KEY_COL5__UART1_DCD            (_MX51_PAD_KEY_COL5__UART1_DCD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_KEY_COL5__UART3_CTS            (_MX51_PAD_KEY_COL5__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_USBH1_CLK__CSPI_SCLK           (_MX51_PAD_USBH1_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_USBH1_CLK__GPIO1_25            (_MX51_PAD_USBH1_CLK__GPIO1_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_USBH1_CLK__I2C2_SCL            (_MX51_PAD_USBH1_CLK__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
-#define MX51_PAD_USBH1_CLK__USBH1_CLK           (_MX51_PAD_USBH1_CLK__USBH1_CLK | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
-#define MX51_PAD_USBH1_DIR__CSPI_MOSI           (_MX51_PAD_USBH1_DIR__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_USBH1_DIR__GPIO1_26            (_MX51_PAD_USBH1_DIR__GPIO1_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_USBH1_DIR__I2C2_SDA            (_MX51_PAD_USBH1_DIR__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
-#define MX51_PAD_USBH1_DIR__USBH1_DIR           (_MX51_PAD_USBH1_DIR__USBH1_DIR | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
-#define MX51_PAD_USBH1_STP__CSPI_RDY            (_MX51_PAD_USBH1_STP__CSPI_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_USBH1_STP__GPIO1_27            (_MX51_PAD_USBH1_STP__GPIO1_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_USBH1_STP__UART3_RXD           (_MX51_PAD_USBH1_STP__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_USBH1_STP__USBH1_STP           (_MX51_PAD_USBH1_STP__USBH1_STP | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
-#define MX51_PAD_USBH1_NXT__CSPI_MISO           (_MX51_PAD_USBH1_NXT__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_USBH1_NXT__GPIO1_28            (_MX51_PAD_USBH1_NXT__GPIO1_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_USBH1_NXT__UART3_TXD           (_MX51_PAD_USBH1_NXT__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_USBH1_NXT__USBH1_NXT           (_MX51_PAD_USBH1_NXT__USBH1_NXT | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA0__GPIO1_11          (_MX51_PAD_USBH1_DATA0__GPIO1_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA0__UART2_CTS         (_MX51_PAD_USBH1_DATA0__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       (_MX51_PAD_USBH1_DATA0__USBH1_DATA0 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA1__GPIO1_12          (_MX51_PAD_USBH1_DATA1__GPIO1_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA1__UART2_RXD         (_MX51_PAD_USBH1_DATA1__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       (_MX51_PAD_USBH1_DATA1__USBH1_DATA1 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA2__GPIO1_13          (_MX51_PAD_USBH1_DATA2__GPIO1_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA2__UART2_TXD         (_MX51_PAD_USBH1_DATA2__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       (_MX51_PAD_USBH1_DATA2__USBH1_DATA2 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA3__GPIO1_14          (_MX51_PAD_USBH1_DATA3__GPIO1_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA3__UART2_RTS         (_MX51_PAD_USBH1_DATA3__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       (_MX51_PAD_USBH1_DATA3__USBH1_DATA3 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA4__CSPI_SS0          (_MX51_PAD_USBH1_DATA4__CSPI_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA4__GPIO1_15          (_MX51_PAD_USBH1_DATA4__GPIO1_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       (_MX51_PAD_USBH1_DATA4__USBH1_DATA4 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA5__CSPI_SS1          (_MX51_PAD_USBH1_DATA5__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA5__GPIO1_16          (_MX51_PAD_USBH1_DATA5__GPIO1_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       (_MX51_PAD_USBH1_DATA5__USBH1_DATA5 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA6__CSPI_SS3          (_MX51_PAD_USBH1_DATA6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA6__GPIO1_17          (_MX51_PAD_USBH1_DATA6__GPIO1_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       (_MX51_PAD_USBH1_DATA6__USBH1_DATA6 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3        (_MX51_PAD_USBH1_DATA7__ECSPI1_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3        (_MX51_PAD_USBH1_DATA7__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA7__GPIO1_18          (_MX51_PAD_USBH1_DATA7__GPIO1_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       (_MX51_PAD_USBH1_DATA7__USBH1_DATA7 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
-#define MX51_PAD_DI1_PIN11__DI1_PIN11           (_MX51_PAD_DI1_PIN11__DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI1_PIN11__ECSPI1_SS2          (_MX51_PAD_DI1_PIN11__ECSPI1_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_DI1_PIN11__GPIO3_0             (_MX51_PAD_DI1_PIN11__GPIO3_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_DI1_PIN12__DI1_PIN12           (_MX51_PAD_DI1_PIN12__DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI1_PIN12__GPIO3_1             (_MX51_PAD_DI1_PIN12__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_DI1_PIN13__DI1_PIN13           (_MX51_PAD_DI1_PIN13__DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI1_PIN13__GPIO3_2             (_MX51_PAD_DI1_PIN13__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_DI1_D0_CS__DI1_D0_CS           (_MX51_PAD_DI1_D0_CS__DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI1_D0_CS__GPIO3_3             (_MX51_PAD_DI1_D0_CS__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_DI1_D1_CS__DI1_D1_CS           (_MX51_PAD_DI1_D1_CS__DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI1_D1_CS__DISP1_PIN14         (_MX51_PAD_DI1_D1_CS__DISP1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI1_D1_CS__DISP1_PIN5          (_MX51_PAD_DI1_D1_CS__DISP1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI1_D1_CS__GPIO3_4             (_MX51_PAD_DI1_D1_CS__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1     (_MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN (_MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5        (_MX51_PAD_DISPB2_SER_DIN__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6     (_MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO (_MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6        (_MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17    (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7     (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK (_MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7        (_MX51_PAD_DISPB2_SER_CLK__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK   (_MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16     (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8      (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISPB2_SER_RS__GPIO3_8         (_MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         (_MX51_PAD_DISP1_DAT0__DISP1_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         (_MX51_PAD_DISP1_DAT1__DISP1_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         (_MX51_PAD_DISP1_DAT2__DISP1_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         (_MX51_PAD_DISP1_DAT3__DISP1_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         (_MX51_PAD_DISP1_DAT4__DISP1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         (_MX51_PAD_DISP1_DAT5__DISP1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC       (_MX51_PAD_DISP1_DAT6__BOOT_USB_SRC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         (_MX51_PAD_DISP1_DAT6__DISP1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG    (_MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         (_MX51_PAD_DISP1_DAT7__DISP1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT8__BOOT_SRC0          (_MX51_PAD_DISP1_DAT8__BOOT_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         (_MX51_PAD_DISP1_DAT8__DISP1_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT9__BOOT_SRC1          (_MX51_PAD_DISP1_DAT9__BOOT_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         (_MX51_PAD_DISP1_DAT9__DISP1_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE   (_MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       (_MX51_PAD_DISP1_DAT10__DISP1_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2    (_MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       (_MX51_PAD_DISP1_DAT11__DISP1_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL      (_MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       (_MX51_PAD_DISP1_DAT12__DISP1_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0     (_MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       (_MX51_PAD_DISP1_DAT13__DISP1_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1     (_MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       (_MX51_PAD_DISP1_DAT14__DISP1_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH    (_MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       (_MX51_PAD_DISP1_DAT15__DISP1_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0   (_MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       (_MX51_PAD_DISP1_DAT16__DISP1_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1   (_MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       (_MX51_PAD_DISP1_DAT17__DISP1_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0  (_MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       (_MX51_PAD_DISP1_DAT18__DISP1_DAT18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT18__DISP2_PIN11       (_MX51_PAD_DISP1_DAT18__DISP2_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT18__DISP2_PIN5        (_MX51_PAD_DISP1_DAT18__DISP2_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1  (_MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       (_MX51_PAD_DISP1_DAT19__DISP1_DAT19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT19__DISP2_PIN12       (_MX51_PAD_DISP1_DAT19__DISP2_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT19__DISP2_PIN6        (_MX51_PAD_DISP1_DAT19__DISP2_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0    (_MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       (_MX51_PAD_DISP1_DAT20__DISP1_DAT20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT20__DISP2_PIN13       (_MX51_PAD_DISP1_DAT20__DISP2_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT20__DISP2_PIN7        (_MX51_PAD_DISP1_DAT20__DISP2_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1    (_MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       (_MX51_PAD_DISP1_DAT21__DISP1_DAT21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT21__DISP2_PIN14       (_MX51_PAD_DISP1_DAT21__DISP2_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT21__DISP2_PIN8        (_MX51_PAD_DISP1_DAT21__DISP2_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0    (_MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       (_MX51_PAD_DISP1_DAT22__DISP1_DAT22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS       (_MX51_PAD_DISP1_DAT22__DISP2_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT22__DISP2_DAT16       (_MX51_PAD_DISP1_DAT22__DISP2_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1    (_MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       (_MX51_PAD_DISP1_DAT23__DISP1_DAT23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS       (_MX51_PAD_DISP1_DAT23__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT23__DISP2_DAT17       (_MX51_PAD_DISP1_DAT23__DISP2_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS      (_MX51_PAD_DISP1_DAT23__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI1_PIN3__DI1_PIN3             (_MX51_PAD_DI1_PIN3__DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI1_PIN2__DI1_PIN2             (_MX51_PAD_DI1_PIN2__DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI_GP2__DISP1_SER_CLK          (_MX51_PAD_DI_GP2__DISP1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI_GP2__DISP2_WAIT             (_MX51_PAD_DI_GP2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI_GP3__CSI1_DATA_EN           (_MX51_PAD_DI_GP3__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI_GP3__DISP1_SER_DIO          (_MX51_PAD_DI_GP3__DISP1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI_GP3__FEC_TX_ER              (_MX51_PAD_DI_GP3__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
-#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN         (_MX51_PAD_DI2_PIN4__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI2_PIN4__DI2_PIN4             (_MX51_PAD_DI2_PIN4__DI2_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI2_PIN4__FEC_CRS              (_MX51_PAD_DI2_PIN4__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI2_PIN2__DI2_PIN2             (_MX51_PAD_DI2_PIN2__DI2_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI2_PIN2__FEC_MDC              (_MX51_PAD_DI2_PIN2__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
-#define MX51_PAD_DI2_PIN3__DI2_PIN3             (_MX51_PAD_DI2_PIN3__DI2_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI2_PIN3__FEC_MDIO             (_MX51_PAD_DI2_PIN3__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     (_MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1       (_MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI_GP4__DI2_PIN15              (_MX51_PAD_DI_GP4__DI2_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI_GP4__DISP1_SER_DIN          (_MX51_PAD_DI_GP4__DISP1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI_GP4__DISP2_PIN1             (_MX51_PAD_DI_GP4__DISP2_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DI_GP4__FEC_RDATA2             (_MX51_PAD_DI_GP4__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         (_MX51_PAD_DISP2_DAT0__DISP2_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT0__FEC_RDATA3         (_MX51_PAD_DISP2_DAT0__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT0__KEY_COL6           (_MX51_PAD_DISP2_DAT0__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT0__UART3_RXD          (_MX51_PAD_DISP2_DAT0__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT0__USBH3_CLK          (_MX51_PAD_DISP2_DAT0__USBH3_CLK | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         (_MX51_PAD_DISP2_DAT1__DISP2_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT1__FEC_RX_ER          (_MX51_PAD_DISP2_DAT1__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT1__KEY_COL7           (_MX51_PAD_DISP2_DAT1__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT1__UART3_TXD          (_MX51_PAD_DISP2_DAT1__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT1__USBH3_DIR          (_MX51_PAD_DISP2_DAT1__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         (_MX51_PAD_DISP2_DAT2__DISP2_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         (_MX51_PAD_DISP2_DAT3__DISP2_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         (_MX51_PAD_DISP2_DAT4__DISP2_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         (_MX51_PAD_DISP2_DAT5__DISP2_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT6__DISP2_DAT6         (_MX51_PAD_DISP2_DAT6__DISP2_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT6__FEC_TDATA1         (_MX51_PAD_DISP2_DAT6__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
-#define MX51_PAD_DISP2_DAT6__GPIO1_19           (_MX51_PAD_DISP2_DAT6__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT6__KEY_ROW4           (_MX51_PAD_DISP2_DAT6__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT6__USBH3_STP          (_MX51_PAD_DISP2_DAT6__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT7__DISP2_DAT7         (_MX51_PAD_DISP2_DAT7__DISP2_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT7__FEC_TDATA2         (_MX51_PAD_DISP2_DAT7__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
-#define MX51_PAD_DISP2_DAT7__GPIO1_29           (_MX51_PAD_DISP2_DAT7__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT7__KEY_ROW5           (_MX51_PAD_DISP2_DAT7__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT7__USBH3_NXT          (_MX51_PAD_DISP2_DAT7__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT8__DISP2_DAT8         (_MX51_PAD_DISP2_DAT8__DISP2_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT8__FEC_TDATA3         (_MX51_PAD_DISP2_DAT8__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
-#define MX51_PAD_DISP2_DAT8__GPIO1_30           (_MX51_PAD_DISP2_DAT8__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT8__KEY_ROW6           (_MX51_PAD_DISP2_DAT8__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT8__USBH3_DATA0        (_MX51_PAD_DISP2_DAT8__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT9__AUD6_RXC           (_MX51_PAD_DISP2_DAT9__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT9__DISP2_DAT9         (_MX51_PAD_DISP2_DAT9__DISP2_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT9__FEC_TX_EN          (_MX51_PAD_DISP2_DAT9__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
-#define MX51_PAD_DISP2_DAT9__GPIO1_31           (_MX51_PAD_DISP2_DAT9__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT9__USBH3_DATA1        (_MX51_PAD_DISP2_DAT9__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       (_MX51_PAD_DISP2_DAT10__DISP2_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS      (_MX51_PAD_DISP2_DAT10__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT10__FEC_COL           (_MX51_PAD_DISP2_DAT10__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT10__KEY_ROW7          (_MX51_PAD_DISP2_DAT10__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT10__USBH3_DATA2       (_MX51_PAD_DISP2_DAT10__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT11__AUD6_TXD          (_MX51_PAD_DISP2_DAT11__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       (_MX51_PAD_DISP2_DAT11__DISP2_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK        (_MX51_PAD_DISP2_DAT11__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT11__GPIO1_10          (_MX51_PAD_DISP2_DAT11__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT11__USBH3_DATA3       (_MX51_PAD_DISP2_DAT11__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT12__AUD6_RXD          (_MX51_PAD_DISP2_DAT12__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       (_MX51_PAD_DISP2_DAT12__DISP2_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT12__FEC_RX_DV         (_MX51_PAD_DISP2_DAT12__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT12__USBH3_DATA4       (_MX51_PAD_DISP2_DAT12__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT13__AUD6_TXC          (_MX51_PAD_DISP2_DAT13__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       (_MX51_PAD_DISP2_DAT13__DISP2_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK        (_MX51_PAD_DISP2_DAT13__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
-#define MX51_PAD_DISP2_DAT13__USBH3_DATA5       (_MX51_PAD_DISP2_DAT13__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT14__AUD6_TXFS         (_MX51_PAD_DISP2_DAT14__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       (_MX51_PAD_DISP2_DAT14__DISP2_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT14__FEC_RDATA0        (_MX51_PAD_DISP2_DAT14__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
-#define MX51_PAD_DISP2_DAT14__USBH3_DATA6       (_MX51_PAD_DISP2_DAT14__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT15__AUD6_RXFS         (_MX51_PAD_DISP2_DAT15__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS      (_MX51_PAD_DISP2_DAT15__DISP1_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       (_MX51_PAD_DISP2_DAT15__DISP2_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_DISP2_DAT15__FEC_TDATA0        (_MX51_PAD_DISP2_DAT15__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
-#define MX51_PAD_DISP2_DAT15__USBH3_DATA7       (_MX51_PAD_DISP2_DAT15__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD1_CMD__AUD5_RXFS             (_MX51_PAD_SD1_CMD__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD1_CMD__CSPI_MOSI             (_MX51_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD1_CMD__SD1_CMD               (_MX51_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_SD1_CLK__AUD5_RXC              (_MX51_PAD_SD1_CLK__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD1_CLK__CSPI_SCLK             (_MX51_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD1_CLK__SD1_CLK               (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
-#define MX51_PAD_SD1_DATA0__AUD5_TXD            (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD1_DATA0__CSPI_MISO           (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_SD1_DATA0__SD1_DATA0           (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_EIM_DA0__EIM_DA0               (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_DA1__EIM_DA1               (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_DA2__EIM_DA2               (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_DA3__EIM_DA3               (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD1_DATA1__AUD5_RXD            (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD1_DATA1__SD1_DATA1           (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_EIM_DA4__EIM_DA4               (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_DA5__EIM_DA5               (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_DA6__EIM_DA6               (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_DA7__EIM_DA7               (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD1_DATA2__AUD5_TXC            (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD1_DATA2__SD1_DATA2           (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_EIM_DA10__EIM_DA10             (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_DA11__EIM_DA11             (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_DA8__EIM_DA8               (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_DA9__EIM_DA9               (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD1_DATA3__AUD5_TXFS           (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD1_DATA3__CSPI_SS1            (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_SD1_DATA3__SD1_DATA3           (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_GPIO1_0__CSPI_SS2              (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_GPIO1_0__GPIO1_0               (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_0__SD1_CD                (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
-#define MX51_PAD_GPIO1_1__CSPI_MISO             (_MX51_PAD_GPIO1_1__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_GPIO1_1__GPIO1_1               (_MX51_PAD_GPIO1_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_1__SD1_WP                (_MX51_PAD_GPIO1_1__SD1_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
-#define MX51_PAD_EIM_DA12__EIM_DA12             (_MX51_PAD_EIM_DA12__EIM_DA12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_DA13__EIM_DA13             (_MX51_PAD_EIM_DA13__EIM_DA13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_DA14__EIM_DA14             (_MX51_PAD_EIM_DA14__EIM_DA14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_EIM_DA15__EIM_DA15             (_MX51_PAD_EIM_DA15__EIM_DA15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD2_CMD__CSPI_MOSI             (_MX51_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_SD2_CMD__I2C1_SCL              (_MX51_PAD_SD2_CMD__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
-#define MX51_PAD_SD2_CMD__SD2_CMD               (_MX51_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_SD2_CLK__CSPI_SCLK             (_MX51_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_SD2_CLK__I2C1_SDA              (_MX51_PAD_SD2_CLK__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
-#define MX51_PAD_SD2_CLK__SD2_CLK               (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
-#define MX51_PAD_SD2_DATA0__CSPI_MISO           (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_SD2_DATA0__SD1_DAT4            (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD2_DATA0__SD2_DATA0           (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_SD2_DATA1__SD1_DAT5            (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD2_DATA1__SD2_DATA1           (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_SD2_DATA1__USBH3_H2_DP         (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD2_DATA2__SD1_DAT6            (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD2_DATA2__SD2_DATA2           (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_SD2_DATA2__USBH3_H2_DM         (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD2_DATA3__CSPI_SS2            (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_SD2_DATA3__SD1_DAT7            (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD2_DATA3__SD2_DATA3           (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
-#define MX51_PAD_GPIO1_2__CCM_OUT_2             (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_2__GPIO1_2               (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_2__I2C2_SCL              (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
-#define MX51_PAD_GPIO1_2__PLL1_BYP              (_MX51_PAD_GPIO1_2__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_2__PWM1_PWMO             (_MX51_PAD_GPIO1_2__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_3__GPIO1_3               (_MX51_PAD_GPIO1_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_3__I2C2_SDA              (_MX51_PAD_GPIO1_3__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
-#define MX51_PAD_GPIO1_3__PLL2_BYP              (_MX51_PAD_GPIO1_3__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_3__PWM2_PWMO             (_MX51_PAD_GPIO1_3__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ     (_MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B   (_MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK         (_MX51_PAD_GPIO1_4__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_4__EIM_RDY               (_MX51_PAD_GPIO1_4__EIM_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_4__GPIO1_4               (_MX51_PAD_GPIO1_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B          (_MX51_PAD_GPIO1_4__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_5__CSI2_MCLK             (_MX51_PAD_GPIO1_5__CSI2_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_5__DISP2_PIN16           (_MX51_PAD_GPIO1_5__DISP2_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_5__GPIO1_5               (_MX51_PAD_GPIO1_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B          (_MX51_PAD_GPIO1_5__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_6__DISP2_PIN17           (_MX51_PAD_GPIO1_6__DISP2_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_6__GPIO1_6               (_MX51_PAD_GPIO1_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_6__REF_EN_B              (_MX51_PAD_GPIO1_6__REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_7__CCM_OUT_0             (_MX51_PAD_GPIO1_7__CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_7__GPIO1_7               (_MX51_PAD_GPIO1_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_7__SD2_WP                (_MX51_PAD_GPIO1_7__SD2_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
-#define MX51_PAD_GPIO1_7__SPDIF_OUT1            (_MX51_PAD_GPIO1_7__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_8__CSI2_DATA_EN          (_MX51_PAD_GPIO1_8__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_8__GPIO1_8               (_MX51_PAD_GPIO1_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_8__SD2_CD                (_MX51_PAD_GPIO1_8__SD2_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
-#define MX51_PAD_GPIO1_8__USBH3_PWR             (_MX51_PAD_GPIO1_8__USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_9__CCM_OUT_1             (_MX51_PAD_GPIO1_9__CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_9__DISP2_D1_CS           (_MX51_PAD_GPIO1_9__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_9__DISP2_SER_CS          (_MX51_PAD_GPIO1_9__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_9__GPIO1_9               (_MX51_PAD_GPIO1_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_9__SD2_LCTL              (_MX51_PAD_GPIO1_9__SD2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_GPIO1_9__USBH3_OC              (_MX51_PAD_GPIO1_9__USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB2__GPIO2_22              IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__GPT_CMPOUT1           IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__AUD5_RXC              IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__CSI1_D3               IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__EIM_EB3               IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__FEC_RDATA1            IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__GPIO2_23              IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__GPT_CMPOUT2           IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_OE__EIM_OE                 IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_OE__GPIO2_24               IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS0__EIM_CS0               IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS0__GPIO2_25              IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS1__EIM_CS1               IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS1__GPIO2_26              IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__AUD5_TXD              IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__CSI1_D4               IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__EIM_CS2               IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__FEC_RDATA2            IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__GPIO2_27              IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__USBOTG_STP            IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__AUD5_RXD              IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__CSI1_D5               IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__EIM_CS3               IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__FEC_RDATA3            IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__GPIO2_28              IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__USBOTG_NXT            IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__AUD5_TXC              IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__CSI1_D6               IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__EIM_CS4               IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__FEC_RX_ER             IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2)
+#define MX51_PAD_EIM_CS4__GPIO2_29              IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__USBOTG_CLK            IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__AUD5_TXFS             IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__CSI1_D7               IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK         IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__EIM_CS5               IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__FEC_CRS               IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2)
+#define MX51_PAD_EIM_CS5__GPIO2_30              IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__USBOTG_DIR            IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DTACK__EIM_DTACK           IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DTACK__GPIO2_31            IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_LBA__EIM_LBA               IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_LBA__GPIO3_1               IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CRE__EIM_CRE               IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CRE__GPIO3_2               IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DRAM_CS1__DRAM_CS1             IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__GPIO3_3            IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__NANDF_WE_B         IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__PATA_DIOW          IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__SD3_DATA0          IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__GPIO3_4            IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__NANDF_RE_B         IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__PATA_DIOR          IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__SD3_DATA1          IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__GPIO3_5             IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__NANDF_ALE           IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN      IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__GPIO3_6             IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__NANDF_CLE           IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__PATA_RESET_B        IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__GPIO3_7            IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__NANDF_WP_B         IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__PATA_DMACK         IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__SD3_DATA2          IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__ECSPI2_SS1          IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__GPIO3_8             IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__NANDF_RB0           IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__PATA_DMARQ          IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__SD3_DATA3           IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__CSPI_MOSI           IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__ECSPI2_RDY          IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__GPIO3_9             IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__NANDF_RB1           IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__PATA_IORDY          IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__SD4_CMD             IOMUX_PAD(0x4fc, 0x120, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__DISP2_WAIT          IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__FEC_COL             IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2)
+#define MX51_PAD_NANDF_RB2__GPIO3_10            IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__NANDF_RB2           IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__USBH3_H3_DP         IOMUX_PAD(0x500, 0x124, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__USBH3_NXT           IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__DISP1_WAIT          IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__ECSPI2_MISO         IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__FEC_RX_CLK          IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2)
+#define MX51_PAD_NANDF_RB3__GPIO3_11            IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__NANDF_RB3           IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__USBH3_CLK           IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__USBH3_H3_DM         IOMUX_PAD(0x504, 0x128, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_NAND__GPIO_NAND           IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_NAND__PATA_INTRQ          IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS0__GPIO3_16            IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS0__NANDF_CS0           IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS1__GPIO3_17            IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS1__NANDF_CS1           IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__CSPI_SCLK           IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__FEC_TX_ER           IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS2__GPIO3_18            IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__NANDF_CS2           IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__PATA_CS_0           IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__SD4_CLK             IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
+#define MX51_PAD_NANDF_CS2__USBH3_H1_DP         IOMUX_PAD(0x520, 0x138, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__FEC_MDC             IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS3__GPIO3_19            IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__NANDF_CS3           IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__PATA_CS_1           IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__SD4_DAT0            IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__USBH3_H1_DM         IOMUX_PAD(0x524, 0x13c, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__FEC_TDATA1          IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS4__GPIO3_20            IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__NANDF_CS4           IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__PATA_DA_0           IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__SD4_DAT1            IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__USBH3_STP           IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__FEC_TDATA2          IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS5__GPIO3_21            IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__NANDF_CS5           IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__PATA_DA_1           IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__SD4_DAT2            IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__USBH3_DIR           IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__CSPI_SS3            IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__FEC_TDATA3          IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS6__GPIO3_22            IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__NANDF_CS6           IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__PATA_DA_2           IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__SD4_DAT3            IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__FEC_TX_EN           IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS7__GPIO3_23            IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__NANDF_CS7           IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__SD3_CLK             IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
+#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0      IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4)
+#define MX51_PAD_NANDF_RDY_INT__GPIO3_24        IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT   IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__SD3_CMD         IOMUX_PAD(0x538, 0x150, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__ECSPI2_MOSI         IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__GPIO3_25            IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__NANDF_D15           IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__PATA_DATA15         IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__SD3_DAT7            IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__ECSPI2_SS3          IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__GPIO3_26            IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__NANDF_D14           IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__PATA_DATA14         IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__SD3_DAT6            IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__ECSPI2_SS2          IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__GPIO3_27            IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__NANDF_D13           IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__PATA_DATA13         IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__SD3_DAT5            IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__ECSPI2_SS1          IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__GPIO3_28            IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__NANDF_D12           IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__PATA_DATA12         IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__SD3_DAT4            IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__FEC_RX_DV           IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__GPIO3_29            IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__NANDF_D11           IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__PATA_DATA11         IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__SD3_DATA3           IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__GPIO3_30            IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__NANDF_D10           IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__PATA_DATA10         IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__SD3_DATA2           IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__FEC_RDATA0           IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4)
+#define MX51_PAD_NANDF_D9__GPIO3_31             IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__NANDF_D9             IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__PATA_DATA9           IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__SD3_DATA1            IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__FEC_TDATA0           IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_D8__GPIO4_0              IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__NANDF_D8             IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__PATA_DATA8           IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__SD3_DATA0            IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__GPIO4_1              IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__NANDF_D7             IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__PATA_DATA7           IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__USBH3_DATA0          IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__GPIO4_2              IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__NANDF_D6             IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__PATA_DATA6           IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__SD4_LCTL             IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__USBH3_DATA1          IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__GPIO4_3              IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__NANDF_D5             IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__PATA_DATA5           IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__SD4_WP               IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__USBH3_DATA2          IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__GPIO4_4              IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__NANDF_D4             IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__PATA_DATA4           IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__SD4_CD               IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__USBH3_DATA3          IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__GPIO4_5              IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__NANDF_D3             IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__PATA_DATA3           IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__SD4_DAT4             IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__USBH3_DATA4          IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__GPIO4_6              IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__NANDF_D2             IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__PATA_DATA2           IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__SD4_DAT5             IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__USBH3_DATA5          IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__GPIO4_7              IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__NANDF_D1             IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__PATA_DATA1           IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__SD4_DAT6             IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__USBH3_DATA6          IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__GPIO4_8              IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__NANDF_D0             IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__PATA_DATA0           IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__SD4_DAT7             IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__USBH3_DATA7          IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D8__CSI1_D8               IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D8__GPIO3_12              IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI1_D9__CSI1_D9               IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D9__GPIO3_13              IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI1_D10__CSI1_D10             IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D11__CSI1_D11             IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D12__CSI1_D12             IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D13__CSI1_D13             IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D14__CSI1_D14             IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D15__CSI1_D15             IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D16__CSI1_D16             IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D17__CSI1_D17             IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D18__CSI1_D18             IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D19__CSI1_D19             IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_VSYNC__GPIO3_14           IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_HSYNC__GPIO3_15           IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D12__CSI2_D12             IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D12__GPIO4_9              IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_D13__CSI2_D13             IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D13__GPIO4_10             IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_D14__CSI2_D14             IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D15__CSI2_D15             IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D16__CSI2_D16             IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D17__CSI2_D17             IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D18__CSI2_D18             IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D18__GPIO4_11             IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_D19__CSI2_D19             IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D19__GPIO4_12             IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC         IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_VSYNC__GPIO4_13           IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC         IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_HSYNC__GPIO4_14           IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK       IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_PIXCLK__GPIO4_15          IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__GPIO4_16             IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__I2C1_CLK             IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__GPIO4_17             IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__I2C1_DAT             IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD          IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__GPIO4_18          IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD          IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__GPIO4_19          IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__UART3_RXD         IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__AUD3_TXC           IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__GPIO4_20           IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS          IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__GPIO4_21           IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__UART3_TXD          IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__GPIO4_22           IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__I2C1_SDA           IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__AUD4_RXD           IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO        IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__GPIO4_23           IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__AUD4_TXC            IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0          IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__GPIO4_24            IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__AUD4_TXD            IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1          IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__GPIO4_25            IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__AUD4_TXFS           IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY          IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__GPIO4_26            IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__GPIO4_27           IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__I2C1_SCL           IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_UART1_RXD__GPIO4_28            IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART1_RXD__UART1_RXD           IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART1_TXD__GPIO4_29            IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART1_TXD__PWM2_PWMO           IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART1_TXD__UART1_TXD           IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART1_RTS__GPIO4_30            IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART1_RTS__UART1_RTS           IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART1_CTS__GPIO4_31            IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART1_CTS__UART1_CTS           IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__FIRI_TXD            IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__GPIO1_20            IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__UART2_RXD           IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__FIRI_RXD            IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__GPIO1_21            IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__UART2_TXD           IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__CSI1_D0             IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__GPIO1_22            IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__UART1_DTR           IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__UART3_RXD           IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__CSI1_D1             IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__GPIO1_23            IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__UART1_DSR           IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__UART3_TXD           IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__GPIO1_24           IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__OWIRE_LINE         IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__SPDIF_OUT          IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW0__KEY_ROW0             IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW1__KEY_ROW1             IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW2__KEY_ROW2             IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW3__KEY_ROW3             IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL0__KEY_COL0             IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL0__PLL1_BYP             IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL1__KEY_COL1             IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL1__PLL2_BYP             IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL2__KEY_COL2             IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL2__PLL3_BYP             IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL3__KEY_COL3             IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__I2C2_SCL             IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__KEY_COL4             IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__SPDIF_OUT1           IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__UART1_RI             IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__UART3_RTS            IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__I2C2_SDA             IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__KEY_COL5             IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__UART1_DCD            IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__UART3_CTS            IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__CSPI_SCLK           IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__GPIO1_25            IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__I2C2_SCL            IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__USBH1_CLK           IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__CSPI_MOSI           IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__GPIO1_26            IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__I2C2_SDA            IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__USBH1_DIR           IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__CSPI_RDY            IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__GPIO1_27            IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__UART3_RXD           IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__USBH1_STP           IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__CSPI_MISO           IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__GPIO1_28            IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__UART3_TXD           IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__USBH1_NXT           IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__GPIO1_11          IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__UART2_CTS         IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__GPIO1_12          IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__UART2_RXD         IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__GPIO1_13          IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__UART2_TXD         IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__GPIO1_14          IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__UART2_RTS         IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__CSPI_SS0          IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__GPIO1_15          IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__CSPI_SS1          IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__GPIO1_16          IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__CSPI_SS3          IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__GPIO1_17          IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3        IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3        IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__GPIO1_18          IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__DI1_PIN11           IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__ECSPI1_SS2          IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__GPIO3_0             IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__DI1_PIN12           IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__GPIO3_1             IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__DI1_PIN13           IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__GPIO3_2             IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__DI1_D0_CS           IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__GPIO3_3             IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__DI1_D1_CS           IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__DISP1_PIN14         IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__DISP1_PIN5          IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__GPIO3_4             IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1     IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5        IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6     IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6        IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17    IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7     IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7        IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK   IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16     IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8      IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__GPIO3_8         IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC       IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG    IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT8__BOOT_SRC0          IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT9__BOOT_SRC1          IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE   IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2    IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL      IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0     IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1     IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH    IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0   IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1   IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0  IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP2_PIN11       IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP2_PIN5        IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1  IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP2_PIN12       IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP2_PIN6        IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0    IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP2_PIN13       IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP2_PIN7        IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1    IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP2_PIN14       IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP2_PIN8        IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0    IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS       IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP2_DAT16       IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1    IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS       IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP2_DAT17       IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS      IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN3__DI1_PIN3             IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN2__DI1_PIN2             IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP2__DISP1_SER_CLK          IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP2__DISP2_WAIT             IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__CSI1_DATA_EN           IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__DISP1_SER_DIO          IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__FEC_TX_ER              IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN         IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN4__DI2_PIN4             IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN4__FEC_CRS              IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN2__DI2_PIN2             IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN2__FEC_MDC              IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DI2_PIN3__DI2_PIN3             IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN3__FEC_MDIO             IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1       IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DI2_PIN15              IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DISP1_SER_DIN          IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DISP2_PIN1             IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__FEC_RDATA2             IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__FEC_RDATA3         IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__KEY_COL6           IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__UART3_RXD          IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__USBH3_CLK          IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__FEC_RX_ER          IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__KEY_COL7           IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__UART3_TXD          IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__USBH3_DIR          IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__DISP2_DAT6         IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__FEC_TDATA1         IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DISP2_DAT6__GPIO1_19           IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__KEY_ROW4           IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__USBH3_STP          IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__DISP2_DAT7         IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__FEC_TDATA2         IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DISP2_DAT7__GPIO1_29           IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__KEY_ROW5           IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__USBH3_NXT          IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__DISP2_DAT8         IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__FEC_TDATA3         IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DISP2_DAT8__GPIO1_30           IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__KEY_ROW6           IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__USBH3_DATA0        IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__AUD6_RXC           IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__DISP2_DAT9         IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__FEC_TX_EN          IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DISP2_DAT9__GPIO1_31           IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__USBH3_DATA1        IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS      IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__FEC_COL           IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__KEY_ROW7          IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__USBH3_DATA2       IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__AUD6_TXD          IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK        IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__GPIO1_10          IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__USBH3_DATA3       IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__AUD6_RXD          IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__FEC_RX_DV         IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__USBH3_DATA4       IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__AUD6_TXC          IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK        IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4)
+#define MX51_PAD_DISP2_DAT13__USBH3_DATA5       IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__AUD6_TXFS         IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__FEC_RDATA0        IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4)
+#define MX51_PAD_DISP2_DAT14__USBH3_DATA6       IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__AUD6_RXFS         IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS      IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__FEC_TDATA0        IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DISP2_DAT15__USBH3_DATA7       IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__AUD5_RXFS             IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__CSPI_MOSI             IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__AUD5_RXC              IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__CSPI_SCLK             IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
+#define MX51_PAD_SD1_DATA0__AUD5_TXD            IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__CSPI_MISO           IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_EIM_DA0__EIM_DA0               IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA1__EIM_DA1               IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA2__EIM_DA2               IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA3__EIM_DA3               IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__AUD5_RXD            IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_EIM_DA4__EIM_DA4               IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA5__EIM_DA5               IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA6__EIM_DA6               IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA7__EIM_DA7               IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__AUD5_TXC            IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_EIM_DA10__EIM_DA10             IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA11__EIM_DA11             IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA8__EIM_DA8               IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA9__EIM_DA9               IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__AUD5_TXFS           IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__CSPI_SS1            IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_GPIO1_0__CSPI_SS2              IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_GPIO1_0__GPIO1_0               IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_0__SD1_CD                IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
+#define MX51_PAD_GPIO1_1__CSPI_MISO             IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_GPIO1_1__GPIO1_1               IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_1__SD1_WP                IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
+#define MX51_PAD_EIM_DA12__EIM_DA12             IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA13__EIM_DA13             IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA14__EIM_DA14             IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA15__EIM_DA15             IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__CSPI_MOSI             IOMUX_PAD(__NA_, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__I2C1_SCL              IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__CSPI_SCLK             IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__I2C1_SDA              IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__SD2_CLK               IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
+#define MX51_PAD_SD2_DATA0__CSPI_MISO           IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA0__SD1_DAT4            IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD1_DAT5            IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__USBH3_H2_DP         IOMUX_PAD(0x7c8, 0x3c0, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD1_DAT6            IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__USBH3_H2_DM         IOMUX_PAD(0x7cc, 0x3c4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__CSPI_SS2            IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__SD1_DAT7            IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__CCM_OUT_2             IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__GPIO1_2               IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__I2C2_SCL              IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__PLL1_BYP              IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__PWM1_PWMO             IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__GPIO1_3               IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__I2C2_SDA              IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__PLL2_BYP              IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__PWM2_PWMO             IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ     IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B   IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK         IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__EIM_RDY               IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__GPIO1_4               IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B          IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__CSI2_MCLK             IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__DISP2_PIN16           IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__GPIO1_5               IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B          IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__DISP2_PIN17           IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__GPIO1_6               IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__REF_EN_B              IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_7__CCM_OUT_0             IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_7__GPIO1_7               IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_7__SD2_WP                IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
+#define MX51_PAD_GPIO1_7__SPDIF_OUT1            IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__CSI2_DATA_EN          IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__GPIO1_8               IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__SD2_CD                IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__USBH3_PWR             IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__CCM_OUT_1             IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__DISP2_D1_CS           IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__DISP2_SER_CS          IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__GPIO1_9               IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__SD2_LCTL              IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__USBH3_OC              IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL)
 
 #endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
index 5408fd1fc736..527f8fe3e31b 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -23,2359 +23,1197 @@
 
 /* These 2 defines are for pins that may not have a mux register, but could
  * have a pad setting register, and vice-versa. */
-#define NON_PAD_I       0x00
+#define __NA_   0x00
 
 #define MX53_UART_PAD_CTRL              (PAD_CTL_PKE | PAD_CTL_PUE |    \
                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
 #define MX53_SDHC_PAD_CTRL      (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
                                 PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
                                 PAD_CTL_SRE_FAST)
-#define PAD_CTRL_I2C    (PAD_CTL_SRE_FAST | PAD_CTL_ODE | PAD_CTL_PKE | \
-                        PAD_CTL_PUE | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP \
-                        | PAD_CTL_HYS)
 
-#define _MX53_PAD_GPIO_19__KPP_COL_5            IOMUX_PAD(0x348, 0x20, 0, 0x840, 0, 0)
-#define _MX53_PAD_GPIO_19__GPIO4_5              IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_19__CCM_CLKO             IOMUX_PAD(0x348, 0x20, 2, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_19__SPDIF_OUT1   IOMUX_PAD(0x348, 0x20, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x20, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_19__ECSPI1_RDY   IOMUX_PAD(0x348, 0x20, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_19__FEC_TDATA_3  IOMUX_PAD(0x348, 0x20, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x20,7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL0__KPP_COL_0   IOMUX_PAD(0x34C, 0x24, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL0__GPIO4_6             IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC     IOMUX_PAD(0x34C, 0x24, 2, 0x758, 0, 0)
-#define _MX53_PAD_KEY_COL0__UART4_TXD_MUX       IOMUX_PAD(0x34C, 0x24, 4, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x24, 5, 0x79C, 0, 0)
-#define _MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x24, 6, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL0__SRC_ANY_PU_RST      IOMUX_PAD(0x34C, 0x24, 7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW0__KPP_ROW_0   IOMUX_PAD(0x350, 0x28, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW0__GPIO4_7             IOMUX_PAD(0x350, 0x28, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD     IOMUX_PAD(0x350, 0x28, 2, 0x74C, 0, 0)
-#define _MX53_PAD_KEY_ROW0__UART4_RXD_MUX       IOMUX_PAD(0x350, 0x28, 4, 0x890, 1, 0)
-#define _MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x28, 5, 0x7A4, 0, 0)
-#define _MX53_PAD_KEY_ROW0__FEC_TX_ER   IOMUX_PAD(0x350, 0x28, 6, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL1__KPP_COL_1   IOMUX_PAD(0x354, 0x2C, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL1__GPIO4_8             IOMUX_PAD(0x354, 0x2C, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS    IOMUX_PAD(0x354, 0x2C, 2, 0x75C, 0, 0)
-#define _MX53_PAD_KEY_COL1__UART5_TXD_MUX       IOMUX_PAD(0x354, 0x2C, 4, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x2C, 5, 0x7A0, 0, 0)
-#define _MX53_PAD_KEY_COL1__FEC_RX_CLK  IOMUX_PAD(0x354, 0x2C, 6, 0x808, 0, 0)
-#define _MX53_PAD_KEY_COL1__USBPHY1_TXREADY     IOMUX_PAD(0x354, 0x2C, 7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW1__KPP_ROW_1   IOMUX_PAD(0x358, 0x30, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW1__GPIO4_9             IOMUX_PAD(0x358, 0x30, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD     IOMUX_PAD(0x358, 0x30, 2, 0x748, 0, 0)
-#define _MX53_PAD_KEY_ROW1__UART5_RXD_MUX       IOMUX_PAD(0x358, 0x30, 4, 0x898, 1, 0)
-#define _MX53_PAD_KEY_ROW1__ECSPI1_SS0  IOMUX_PAD(0x358, 0x30, 5, 0x7A8, 0, 0)
-#define _MX53_PAD_KEY_ROW1__FEC_COL             IOMUX_PAD(0x358, 0x30, 6, 0x800, 0, 0)
-#define _MX53_PAD_KEY_ROW1__USBPHY1_RXVALID     IOMUX_PAD(0x358, 0x30, 7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL2__KPP_COL_2   IOMUX_PAD(0x35C, 0x34, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL2__GPIO4_10            IOMUX_PAD(0x35C, 0x34, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL2__CAN1_TXCAN  IOMUX_PAD(0x35C, 0x34, 2, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL2__FEC_MDIO            IOMUX_PAD(0x35C, 0x34, 4, 0x804, 0, 0)
-#define _MX53_PAD_KEY_COL2__ECSPI1_SS1  IOMUX_PAD(0x35C, 0x34, 5, 0x7AC, 0, 0)
-#define _MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x34, 6, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE    IOMUX_PAD(0x35C, 0x34, 7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW2__KPP_ROW_2   IOMUX_PAD(0x360, 0x38, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW2__GPIO4_11    IOMUX_PAD(0x360, 0x38, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW2__CAN1_RXCAN  IOMUX_PAD(0x360, 0x38, 2, 0x760, 0, 0)
-#define _MX53_PAD_KEY_ROW2__FEC_MDC             IOMUX_PAD(0x360, 0x38, 4, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW2__ECSPI1_SS2  IOMUX_PAD(0x360, 0x38, 5, 0x7B0, 0, 0)
-#define _MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x38, 6, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW2__USBPHY1_RXERROR     IOMUX_PAD(0x360, 0x38, 7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL3__KPP_COL_3   IOMUX_PAD(0x364, 0x3C, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL3__GPIO4_12            IOMUX_PAD(0x364, 0x3C, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL3__USBOH3_H2_DP        IOMUX_PAD(0x364, 0x3C, 2, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL3__SPDIF_IN1   IOMUX_PAD(0x364, 0x3C, 3, 0x870, 0, 0)
-#define _MX53_PAD_KEY_COL3__I2C2_SCL            IOMUX_PAD(0x364, 0x3C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, 0)
-#define _MX53_PAD_KEY_COL3__ECSPI1_SS3  IOMUX_PAD(0x364, 0x3C, 5, 0x7B4, 0, 0)
-#define _MX53_PAD_KEY_COL3__FEC_CRS             IOMUX_PAD(0x364, 0x3C, 6, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK    IOMUX_PAD(0x364, 0x3C, 7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW3__KPP_ROW_3   IOMUX_PAD(0x368, 0x40, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW3__GPIO4_13    IOMUX_PAD(0x368, 0x40, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW3__USBOH3_H2_DM        IOMUX_PAD(0x368, 0x40, 2, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK    IOMUX_PAD(0x368, 0x40, 3, 0x768, 0, 0)
-#define _MX53_PAD_KEY_ROW3__I2C2_SDA    IOMUX_PAD(0x368, 0x40, 4 | IOMUX_CONFIG_SION, 0x820, 0, 0)
-#define _MX53_PAD_KEY_ROW3__OSC32K_32K_OUT      IOMUX_PAD(0x368, 0x40, 5, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW3__CCM_PLL4_BYP        IOMUX_PAD(0x368, 0x40, 6, 0x77C, 0, 0)
-#define _MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x40, 7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL4__KPP_COL_4   IOMUX_PAD(0x36C, 0x44, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL4__GPIO4_14            IOMUX_PAD(0x36C, 0x44, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL4__CAN2_TXCAN  IOMUX_PAD(0x36C, 0x44, 2, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL4__IPU_SISG_4  IOMUX_PAD(0x36C, 0x44, 3, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL4__UART5_RTS   IOMUX_PAD(0x36C, 0x44, 4, 0x894, 0, 0)
-#define _MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC    IOMUX_PAD(0x36C, 0x44, 5, 0x89C, 0, 0)
-#define _MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x44, 7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW4__KPP_ROW_4   IOMUX_PAD(0x370, 0x48, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW4__GPIO4_15    IOMUX_PAD(0x370, 0x48, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW4__CAN2_RXCAN  IOMUX_PAD(0x370, 0x48, 2, 0x764, 0, 0)
-#define _MX53_PAD_KEY_ROW4__IPU_SISG_5  IOMUX_PAD(0x370, 0x48, 3, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW4__UART5_CTS   IOMUX_PAD(0x370, 0x48, 4, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR   IOMUX_PAD(0x370, 0x48, 5, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID   IOMUX_PAD(0x370, 0x48, 7, 0x0, 0, 0)
-#define _MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK        IOMUX_PAD(0x378, 0x4C, 0, 0x0, 0, 0)
-#define _MX53_PAD_DI0_DISP_CLK__GPIO4_16                IOMUX_PAD(0x378, 0x4C, 1, 0x0, 0, 0)
-#define _MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR        IOMUX_PAD(0x378, 0x4C, 2, 0x0, 0, 0)
-#define _MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x4C, 5, 0x0, 0, 0)
-#define _MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x4C, 6, 0x0, 0, 0)
-#define _MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID  IOMUX_PAD(0x378, 0x4C, 7, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN15__IPU_DI0_PIN15              IOMUX_PAD(0x37C, 0x50, 0, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN15__GPIO4_17           IOMUX_PAD(0x37C, 0x50, 1, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC    IOMUX_PAD(0x37C, 0x50, 2, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1    IOMUX_PAD(0x37C, 0x50, 5, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1    IOMUX_PAD(0x37C, 0x50, 6, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN15__USBPHY1_BVALID             IOMUX_PAD(0x37C, 0x50, 7, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN2__IPU_DI0_PIN2                IOMUX_PAD(0x380, 0x54, 0, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN2__GPIO4_18                    IOMUX_PAD(0x380, 0x54, 1, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD     IOMUX_PAD(0x380, 0x54, 2, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2     IOMUX_PAD(0x380, 0x54, 5, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2             IOMUX_PAD(0x380, 0x54, 6, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION  IOMUX_PAD(0x380, 0x54, 7, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                IOMUX_PAD(0x384, 0x58, 0, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN3__GPIO4_19                    IOMUX_PAD(0x384, 0x58, 1, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS    IOMUX_PAD(0x384, 0x58, 2, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3     IOMUX_PAD(0x384, 0x58, 5, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3             IOMUX_PAD(0x384, 0x58, 6, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN3__USBPHY1_IDDIG               IOMUX_PAD(0x384, 0x58, 7, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN4__IPU_DI0_PIN4                IOMUX_PAD(0x388, 0x5C, 0, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN4__GPIO4_20                    IOMUX_PAD(0x388, 0x5C, 1, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD     IOMUX_PAD(0x388, 0x5C, 2, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN4__ESDHC1_WP           IOMUX_PAD(0x388, 0x5C, 3, 0x7FC, 0, 0)
-#define _MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD    IOMUX_PAD(0x388, 0x5C, 5, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4             IOMUX_PAD(0x388, 0x5C, 6, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT      IOMUX_PAD(0x388, 0x5C, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0   IOMUX_PAD(0x38C, 0x60, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT0__GPIO4_21          IOMUX_PAD(0x38C, 0x60, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT0__CSPI_SCLK         IOMUX_PAD(0x38C, 0x60, 2, 0x780, 0, 0)
-#define _MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0       IOMUX_PAD(0x38C, 0x60, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN       IOMUX_PAD(0x38C, 0x60, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5   IOMUX_PAD(0x38C, 0x60, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY   IOMUX_PAD(0x38C, 0x60, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1   IOMUX_PAD(0x390, 0x64, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT1__GPIO4_22          IOMUX_PAD(0x390, 0x64, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT1__CSPI_MOSI         IOMUX_PAD(0x390, 0x64, 2, 0x788, 0, 0)
-#define _MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1       IOMUX_PAD(0x390, 0x64, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL      IOMUX_PAD(0x390, 0x64, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6   IOMUX_PAD(0x390, 0x64, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID   IOMUX_PAD(0x390, 0x64, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2   IOMUX_PAD(0x394, 0x68, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT2__GPIO4_23          IOMUX_PAD(0x394, 0x68, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT2__CSPI_MISO         IOMUX_PAD(0x394, 0x68, 2, 0x784, 0, 0)
-#define _MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2       IOMUX_PAD(0x394, 0x68, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE   IOMUX_PAD(0x394, 0x68, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7   IOMUX_PAD(0x394, 0x68, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE  IOMUX_PAD(0x394, 0x68, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3   IOMUX_PAD(0x398, 0x6C, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT3__GPIO4_24          IOMUX_PAD(0x398, 0x6C, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT3__CSPI_SS0          IOMUX_PAD(0x398, 0x6C, 2, 0x78C, 0, 0)
-#define _MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3       IOMUX_PAD(0x398, 0x6C, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR      IOMUX_PAD(0x398, 0x6C, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8   IOMUX_PAD(0x398, 0x6C, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR   IOMUX_PAD(0x398, 0x6C, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4   IOMUX_PAD(0x39C, 0x70, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT4__GPIO4_25          IOMUX_PAD(0x39C, 0x70, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT4__CSPI_SS1          IOMUX_PAD(0x39C, 0x70, 2, 0x790, 0, 0)
-#define _MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4       IOMUX_PAD(0x39C, 0x70, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB        IOMUX_PAD(0x39C, 0x70, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9   IOMUX_PAD(0x39C, 0x70, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK  IOMUX_PAD(0x39C, 0x70, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5   IOMUX_PAD(0x3A0, 0x74, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT5__GPIO4_26          IOMUX_PAD(0x3A0, 0x74, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT5__CSPI_SS2          IOMUX_PAD(0x3A0, 0x74, 2, 0x794, 0, 0)
-#define _MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5       IOMUX_PAD(0x3A0, 0x74, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS  IOMUX_PAD(0x3A0, 0x74, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10  IOMUX_PAD(0x3A0, 0x74, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0       IOMUX_PAD(0x3A0, 0x74, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6   IOMUX_PAD(0x3A4, 0x78, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT6__GPIO4_27          IOMUX_PAD(0x3A4, 0x78, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT6__CSPI_SS3          IOMUX_PAD(0x3A4, 0x78, 2, 0x798, 0, 0)
-#define _MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6       IOMUX_PAD(0x3A4, 0x78, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x78, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11  IOMUX_PAD(0x3A4, 0x78, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1       IOMUX_PAD(0x3A4, 0x78, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7   IOMUX_PAD(0x3A8, 0x7C, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT7__GPIO4_28          IOMUX_PAD(0x3A8, 0x7C, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT7__CSPI_RDY          IOMUX_PAD(0x3A8, 0x7C, 2, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7       IOMUX_PAD(0x3A8, 0x7C, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0        IOMUX_PAD(0x3A8, 0x7C, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12  IOMUX_PAD(0x3A8, 0x7C, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x7C, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8   IOMUX_PAD(0x3AC, 0x80, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT8__GPIO4_29          IOMUX_PAD(0x3AC, 0x80, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT8__PWM1_PWMO         IOMUX_PAD(0x3AC, 0x80, 2, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B      IOMUX_PAD(0x3AC, 0x80, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1        IOMUX_PAD(0x3AC, 0x80, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13  IOMUX_PAD(0x3AC, 0x80, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT8__USBPHY2_AVALID    IOMUX_PAD(0x3AC, 0x80, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9   IOMUX_PAD(0x3B0, 0x84, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT9__GPIO4_30          IOMUX_PAD(0x3B0, 0x84, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT9__PWM2_PWMO         IOMUX_PAD(0x3B0, 0x84, 2, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B      IOMUX_PAD(0x3B0, 0x84, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2                IOMUX_PAD(0x3B0, 0x84, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14  IOMUX_PAD(0x3B0, 0x84, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x84, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x88, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT10__GPIO4_31         IOMUX_PAD(0x3B4, 0x88, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x88, 2, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3       IOMUX_PAD(0x3B4, 0x88, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x88, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1        IOMUX_PAD(0x3B4, 0x88, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x8C, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT11__GPIO5_5          IOMUX_PAD(0x3B8, 0x8C, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x8C, 2, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4       IOMUX_PAD(0x3B8, 0x8C, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x8C, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2        IOMUX_PAD(0x3B8, 0x8C, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x90, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT12__GPIO5_6          IOMUX_PAD(0x3BC, 0x90, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x90, 2, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5       IOMUX_PAD(0x3BC, 0x90, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x90, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3        IOMUX_PAD(0x3BC, 0x90, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x94, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT13__GPIO5_7          IOMUX_PAD(0x3C0, 0x94, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x94, 3, 0x754, 0, 0)
-#define _MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0       IOMUX_PAD(0x3C0, 0x94, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x94, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4        IOMUX_PAD(0x3C0, 0x94, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x98, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT14__GPIO5_8          IOMUX_PAD(0x3C4, 0x98, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC  IOMUX_PAD(0x3C4, 0x98, 3, 0x750, 0, 0)
-#define _MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1       IOMUX_PAD(0x3C4, 0x98, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x98, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5        IOMUX_PAD(0x3C4, 0x98, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x9C, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT15__GPIO5_9          IOMUX_PAD(0x3C8, 0x9C, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT15__ECSPI1_SS1               IOMUX_PAD(0x3C8, 0x9C, 2, 0x7AC, 1, 0)
-#define _MX53_PAD_DISP0_DAT15__ECSPI2_SS1               IOMUX_PAD(0x3C8, 0x9C, 3, 0x7C8, 0, 0)
-#define _MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2       IOMUX_PAD(0x3C8, 0x9C, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x9C, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6        IOMUX_PAD(0x3C8, 0x9C, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0xA0, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT16__GPIO5_10         IOMUX_PAD(0x3CC, 0xA0, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT16__ECSPI2_MOSI              IOMUX_PAD(0x3CC, 0xA0, 2, 0x7C0, 0, 0)
-#define _MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC  IOMUX_PAD(0x3CC, 0xA0, 3, 0x758, 1, 0)
-#define _MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0xA0, 4, 0x868, 0, 0)
-#define _MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3       IOMUX_PAD(0x3CC, 0xA0, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0xA0, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7        IOMUX_PAD(0x3CC, 0xA0, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0xA4, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT17__GPIO5_11         IOMUX_PAD(0x3D0, 0xA4, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT17__ECSPI2_MISO              IOMUX_PAD(0x3D0, 0xA4, 2, 0x7BC, 0, 0)
-#define _MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD  IOMUX_PAD(0x3D0, 0xA4, 3, 0x74C, 1, 0)
-#define _MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0xA4, 4, 0x86C, 0, 0)
-#define _MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4       IOMUX_PAD(0x3D0, 0xA4, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0xA4, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0xA8, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT18__GPIO5_12         IOMUX_PAD(0x3D4, 0xA8, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT18__ECSPI2_SS0               IOMUX_PAD(0x3D4, 0xA8, 2, 0x7C4, 0, 0)
-#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0xA8, 3, 0x75C, 1, 0)
-#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0xA8, 4, 0x73C, 0, 0)
-#define _MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5       IOMUX_PAD(0x3D4, 0xA8, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0xA8, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2    IOMUX_PAD(0x3D4, 0xA8, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0xAC, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT19__GPIO5_13         IOMUX_PAD(0x3D8, 0xAC, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT19__ECSPI2_SCLK              IOMUX_PAD(0x3D8, 0xAC, 2, 0x7B8, 0, 0)
-#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD  IOMUX_PAD(0x3D8, 0xAC, 3, 0x748, 1, 0)
-#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC  IOMUX_PAD(0x3D8, 0xAC, 4, 0x738, 0, 0)
-#define _MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6       IOMUX_PAD(0x3D8, 0xAC, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0xAC, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3    IOMUX_PAD(0x3D8, 0xAC, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0xB0, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT20__GPIO5_14         IOMUX_PAD(0x3DC, 0xB0, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT20__ECSPI1_SCLK              IOMUX_PAD(0x3DC, 0xB0, 2, 0x79C, 1, 0)
-#define _MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC  IOMUX_PAD(0x3DC, 0xB0, 3, 0x740, 0, 0)
-#define _MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7       IOMUX_PAD(0x3DC, 0xB0, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0xB0, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT20__SATA_PHY_TDI             IOMUX_PAD(0x3DC, 0xB0, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0xB4, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT21__GPIO5_15         IOMUX_PAD(0x3E0, 0xB4, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT21__ECSPI1_MOSI              IOMUX_PAD(0x3E0, 0xB4, 2, 0x7A4, 1, 0)
-#define _MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD  IOMUX_PAD(0x3E0, 0xB4, 3, 0x734, 0, 0)
-#define _MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0  IOMUX_PAD(0x3E0, 0xB4, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0xB4, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT21__SATA_PHY_TDO     IOMUX_PAD(0x3E0, 0xB4, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0xB8, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT22__GPIO5_16         IOMUX_PAD(0x3E4, 0xB8, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT22__ECSPI1_MISO              IOMUX_PAD(0x3E4, 0xB8, 2, 0x7A0, 1, 0)
-#define _MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0xB8, 3, 0x744, 0, 0)
-#define _MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1  IOMUX_PAD(0x3E4, 0xB8, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0xB8, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT22__SATA_PHY_TCK     IOMUX_PAD(0x3E4, 0xB8, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0xBC, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT23__GPIO5_17         IOMUX_PAD(0x3E8, 0xBC, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT23__ECSPI1_SS0               IOMUX_PAD(0x3E8, 0xBC, 2, 0x7A8, 1, 0)
-#define _MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD  IOMUX_PAD(0x3E8, 0xBC, 3, 0x730, 0, 0)
-#define _MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2  IOMUX_PAD(0x3E8, 0xBC, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0xBC, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT23__SATA_PHY_TMS     IOMUX_PAD(0x3E8, 0xBC, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK  IOMUX_PAD(0x3EC, 0xC0, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_PIXCLK__GPIO5_18         IOMUX_PAD(0x3EC, 0xC0, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0  IOMUX_PAD(0x3EC, 0xC0, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0xC0, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC             IOMUX_PAD(0x3F0, 0xC4, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_MCLK__GPIO5_19           IOMUX_PAD(0x3F0, 0xC4, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK              IOMUX_PAD(0x3F0, 0xC4, 2, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1    IOMUX_PAD(0x3F0, 0xC4, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30   IOMUX_PAD(0x3F0, 0xC4, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_MCLK__TPIU_TRCTL         IOMUX_PAD(0x3F0, 0xC4, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN        IOMUX_PAD(0x3F4, 0xC8, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DATA_EN__GPIO5_20                IOMUX_PAD(0x3F4, 0xC8, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0xC8, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31        IOMUX_PAD(0x3F4, 0xC8, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK              IOMUX_PAD(0x3F4, 0xC8, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC    IOMUX_PAD(0x3F8, 0xCC, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_VSYNC__GPIO5_21          IOMUX_PAD(0x3F8, 0xCC, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3   IOMUX_PAD(0x3F8, 0xCC, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32  IOMUX_PAD(0x3F8, 0xCC, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0              IOMUX_PAD(0x3F8, 0xCC, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4               IOMUX_PAD(0x3FC, 0xD0, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT4__GPIO5_22           IOMUX_PAD(0x3FC, 0xD0, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT4__KPP_COL_5          IOMUX_PAD(0x3FC, 0xD0, 2, 0x840, 1, 0)
-#define _MX53_PAD_CSI0_DAT4__ECSPI1_SCLK                IOMUX_PAD(0x3FC, 0xD0, 3, 0x79C, 2, 0)
-#define _MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP   IOMUX_PAD(0x3FC, 0xD0, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC    IOMUX_PAD(0x3FC, 0xD0, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33   IOMUX_PAD(0x3FC, 0xD0, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT4__TPIU_TRACE_1               IOMUX_PAD(0x3FC, 0xD0, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5               IOMUX_PAD(0x400, 0xD4, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT5__GPIO5_23           IOMUX_PAD(0x400, 0xD4, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT5__KPP_ROW_5          IOMUX_PAD(0x400, 0xD4, 2, 0x84C, 0, 0)
-#define _MX53_PAD_CSI0_DAT5__ECSPI1_MOSI                IOMUX_PAD(0x400, 0xD4, 3, 0x7A4, 2, 0)
-#define _MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT   IOMUX_PAD(0x400, 0xD4, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD    IOMUX_PAD(0x400, 0xD4, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34   IOMUX_PAD(0x400, 0xD4, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT5__TPIU_TRACE_2               IOMUX_PAD(0x400, 0xD4, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6               IOMUX_PAD(0x404, 0xD8, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT6__GPIO5_24           IOMUX_PAD(0x404, 0xD8, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT6__KPP_COL_6          IOMUX_PAD(0x404, 0xD8, 2, 0x844, 0, 0)
-#define _MX53_PAD_CSI0_DAT6__ECSPI1_MISO                IOMUX_PAD(0x404, 0xD8, 3, 0x7A0, 2, 0)
-#define _MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK   IOMUX_PAD(0x404, 0xD8, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS   IOMUX_PAD(0x404, 0xD8, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35   IOMUX_PAD(0x404, 0xD8, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT6__TPIU_TRACE_3               IOMUX_PAD(0x404, 0xD8, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7               IOMUX_PAD(0x408, 0xDC, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT7__GPIO5_25           IOMUX_PAD(0x408, 0xDC, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT7__KPP_ROW_6          IOMUX_PAD(0x408, 0xDC, 2, 0x850, 0, 0)
-#define _MX53_PAD_CSI0_DAT7__ECSPI1_SS0         IOMUX_PAD(0x408, 0xDC, 3, 0x7A8, 2, 0)
-#define _MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR   IOMUX_PAD(0x408, 0xDC, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD    IOMUX_PAD(0x408, 0xDC, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36   IOMUX_PAD(0x408, 0xDC, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT7__TPIU_TRACE_4               IOMUX_PAD(0x408, 0xDC, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8               IOMUX_PAD(0x40C, 0xE0, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT8__GPIO5_26           IOMUX_PAD(0x40C, 0xE0, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT8__KPP_COL_7          IOMUX_PAD(0x40C, 0xE0, 2, 0x848, 0, 0)
-#define _MX53_PAD_CSI0_DAT8__ECSPI2_SCLK                IOMUX_PAD(0x40C, 0xE0, 3, 0x7B8, 1, 0)
-#define _MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC    IOMUX_PAD(0x40C, 0xE0, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT8__I2C1_SDA           IOMUX_PAD(0x40C, 0xE0, 5 | IOMUX_CONFIG_SION, 0x818, 0, 0)
-#define _MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37   IOMUX_PAD(0x40C, 0xE0, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT8__TPIU_TRACE_5               IOMUX_PAD(0x40C, 0xE0, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9               IOMUX_PAD(0x410, 0xE4, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT9__GPIO5_27           IOMUX_PAD(0x410, 0xE4, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT9__KPP_ROW_7          IOMUX_PAD(0x410, 0xE4, 2, 0x854, 0, 0)
-#define _MX53_PAD_CSI0_DAT9__ECSPI2_MOSI                IOMUX_PAD(0x410, 0xE4, 3, 0x7C0, 1, 0)
-#define _MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR   IOMUX_PAD(0x410, 0xE4, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT9__I2C1_SCL           IOMUX_PAD(0x410, 0xE4, 5 | IOMUX_CONFIG_SION, 0x814, 0, 0)
-#define _MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38   IOMUX_PAD(0x410, 0xE4, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT9__TPIU_TRACE_6               IOMUX_PAD(0x410, 0xE4, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10             IOMUX_PAD(0x414, 0xE8, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT10__GPIO5_28          IOMUX_PAD(0x414, 0xE8, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT10__UART1_TXD_MUX     IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT10__ECSPI2_MISO               IOMUX_PAD(0x414, 0xE8, 3, 0x7BC, 1, 0)
-#define _MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC   IOMUX_PAD(0x414, 0xE8, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4   IOMUX_PAD(0x414, 0xE8, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39  IOMUX_PAD(0x414, 0xE8, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT10__TPIU_TRACE_7              IOMUX_PAD(0x414, 0xE8, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11             IOMUX_PAD(0x418, 0xEC, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT11__GPIO5_29          IOMUX_PAD(0x418, 0xEC, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT11__UART1_RXD_MUX     IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, 0)
-#define _MX53_PAD_CSI0_DAT11__ECSPI2_SS0                IOMUX_PAD(0x418, 0xEC, 3, 0x7C4, 1, 0)
-#define _MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS  IOMUX_PAD(0x418, 0xEC, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5   IOMUX_PAD(0x418, 0xEC, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40  IOMUX_PAD(0x418, 0xEC, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT11__TPIU_TRACE_8              IOMUX_PAD(0x418, 0xEC, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12             IOMUX_PAD(0x41C, 0xF0, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT12__GPIO5_30          IOMUX_PAD(0x41C, 0xF0, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT12__UART4_TXD_MUX     IOMUX_PAD(0x41C, 0xF0, 2, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0       IOMUX_PAD(0x41C, 0xF0, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6   IOMUX_PAD(0x41C, 0xF0, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41  IOMUX_PAD(0x41C, 0xF0, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT12__TPIU_TRACE_9              IOMUX_PAD(0x41C, 0xF0, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13             IOMUX_PAD(0x420, 0xF4, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT13__GPIO5_31          IOMUX_PAD(0x420, 0xF4, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT13__UART4_RXD_MUX     IOMUX_PAD(0x420, 0xF4, 2, 0x890, 3, 0)
-#define _MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1       IOMUX_PAD(0x420, 0xF4, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7   IOMUX_PAD(0x420, 0xF4, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42  IOMUX_PAD(0x420, 0xF4, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT13__TPIU_TRACE_10             IOMUX_PAD(0x420, 0xF4, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14             IOMUX_PAD(0x424, 0xF8, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT14__GPIO6_0           IOMUX_PAD(0x424, 0xF8, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT14__UART5_TXD_MUX     IOMUX_PAD(0x424, 0xF8, 2, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2       IOMUX_PAD(0x424, 0xF8, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8   IOMUX_PAD(0x424, 0xF8, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43  IOMUX_PAD(0x424, 0xF8, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT14__TPIU_TRACE_11             IOMUX_PAD(0x424, 0xF8, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15             IOMUX_PAD(0x428, 0xFC, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT15__GPIO6_1           IOMUX_PAD(0x428, 0xFC, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT15__UART5_RXD_MUX     IOMUX_PAD(0x428, 0xFC, 2, 0x898, 3, 0)
-#define _MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3       IOMUX_PAD(0x428, 0xFC, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9   IOMUX_PAD(0x428, 0xFC, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44  IOMUX_PAD(0x428, 0xFC, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT15__TPIU_TRACE_12             IOMUX_PAD(0x428, 0xFC, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16             IOMUX_PAD(0x42C, 0x100, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT16__GPIO6_2           IOMUX_PAD(0x42C, 0x100, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT16__UART4_RTS         IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, 0)
-#define _MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4       IOMUX_PAD(0x42C, 0x100, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10  IOMUX_PAD(0x42C, 0x100, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45  IOMUX_PAD(0x42C, 0x100, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT16__TPIU_TRACE_13             IOMUX_PAD(0x42C, 0x100, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17             IOMUX_PAD(0x430, 0x104, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT17__GPIO6_3           IOMUX_PAD(0x430, 0x104, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT17__UART4_CTS         IOMUX_PAD(0x430, 0x104, 2, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5       IOMUX_PAD(0x430, 0x104, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11  IOMUX_PAD(0x430, 0x104, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46  IOMUX_PAD(0x430, 0x104, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT17__TPIU_TRACE_14             IOMUX_PAD(0x430, 0x104, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18             IOMUX_PAD(0x434, 0x108, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT18__GPIO6_4           IOMUX_PAD(0x434, 0x108, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT18__UART5_RTS         IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, 0)
-#define _MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6       IOMUX_PAD(0x434, 0x108, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12  IOMUX_PAD(0x434, 0x108, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47  IOMUX_PAD(0x434, 0x108, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT18__TPIU_TRACE_15             IOMUX_PAD(0x434, 0x108, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19             IOMUX_PAD(0x438, 0x10C, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT19__GPIO6_5           IOMUX_PAD(0x438, 0x10C, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT19__UART5_CTS         IOMUX_PAD(0x438, 0x10C, 2, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7       IOMUX_PAD(0x438, 0x10C, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13  IOMUX_PAD(0x438, 0x10C, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48  IOMUX_PAD(0x438, 0x10C, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK    IOMUX_PAD(0x438, 0x10C, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A25__EMI_WEIM_A_25                IOMUX_PAD(0x458, 0x110, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A25__GPIO5_2                      IOMUX_PAD(0x458, 0x110, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A25__ECSPI2_RDY           IOMUX_PAD(0x458, 0x110, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A25__IPU_DI1_PIN12                IOMUX_PAD(0x458, 0x110, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A25__CSPI_SS1                     IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, 0)
-#define _MX53_PAD_EIM_A25__IPU_DI0_D1_CS                IOMUX_PAD(0x458, 0x110, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A25__USBPHY1_BISTOK               IOMUX_PAD(0x458, 0x110, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB2__EMI_WEIM_EB_2                IOMUX_PAD(0x45C, 0x114, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB2__GPIO2_30                     IOMUX_PAD(0x45C, 0x114, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK              IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, 0)
-#define _MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS             IOMUX_PAD(0x45C, 0x114, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB2__ECSPI1_SS0           IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, 0)
-#define _MX53_PAD_EIM_EB2__I2C2_SCL                     IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, 0)
-#define _MX53_PAD_EIM_D16__EMI_WEIM_D_16                IOMUX_PAD(0x460, 0x118, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D16__GPIO3_16                     IOMUX_PAD(0x460, 0x118, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D16__IPU_DI0_PIN5         IOMUX_PAD(0x460, 0x118, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK   IOMUX_PAD(0x460, 0x118, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D16__ECSPI1_SCLK          IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, 0)
-#define _MX53_PAD_EIM_D16__I2C2_SDA                     IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, 0)
-#define _MX53_PAD_EIM_D17__EMI_WEIM_D_17                IOMUX_PAD(0x464, 0x11C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D17__GPIO3_17                     IOMUX_PAD(0x464, 0x11C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D17__IPU_DI0_PIN6         IOMUX_PAD(0x464, 0x11C, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN   IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, 0)
-#define _MX53_PAD_EIM_D17__ECSPI1_MISO          IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, 0)
-#define _MX53_PAD_EIM_D17__I2C3_SCL                     IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, 0)
-#define _MX53_PAD_EIM_D18__EMI_WEIM_D_18                IOMUX_PAD(0x468, 0x120, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D18__GPIO3_18                     IOMUX_PAD(0x468, 0x120, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D18__IPU_DI0_PIN7         IOMUX_PAD(0x468, 0x120, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO   IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, 0)
-#define _MX53_PAD_EIM_D18__ECSPI1_MOSI          IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, 0)
-#define _MX53_PAD_EIM_D18__I2C3_SDA                     IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, 0)
-#define _MX53_PAD_EIM_D18__IPU_DI1_D0_CS                IOMUX_PAD(0x468, 0x120, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D19__EMI_WEIM_D_19                IOMUX_PAD(0x46C, 0x124, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D19__GPIO3_19                     IOMUX_PAD(0x46C, 0x124, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D19__IPU_DI0_PIN8         IOMUX_PAD(0x46C, 0x124, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS    IOMUX_PAD(0x46C, 0x124, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D19__ECSPI1_SS1           IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, 0)
-#define _MX53_PAD_EIM_D19__EPIT1_EPITO          IOMUX_PAD(0x46C, 0x124, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D19__UART1_CTS                    IOMUX_PAD(0x46C, 0x124, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D19__USBOH3_USBH2_OC              IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, 0)
-#define _MX53_PAD_EIM_D20__EMI_WEIM_D_20                IOMUX_PAD(0x470, 0x128, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D20__GPIO3_20                     IOMUX_PAD(0x470, 0x128, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D20__IPU_DI0_PIN16                IOMUX_PAD(0x470, 0x128, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D20__IPU_SER_DISP0_CS             IOMUX_PAD(0x470, 0x128, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D20__CSPI_SS0                     IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, 0)
-#define _MX53_PAD_EIM_D20__EPIT2_EPITO          IOMUX_PAD(0x470, 0x128, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D20__UART1_RTS                    IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, 0)
-#define _MX53_PAD_EIM_D20__USBOH3_USBH2_PWR     IOMUX_PAD(0x470, 0x128, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D21__EMI_WEIM_D_21                IOMUX_PAD(0x474, 0x12C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D21__GPIO3_21                     IOMUX_PAD(0x474, 0x12C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D21__IPU_DI0_PIN17                IOMUX_PAD(0x474, 0x12C, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK   IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D21__CSPI_SCLK                    IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, 0)
-#define _MX53_PAD_EIM_D21__I2C1_SCL                     IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, 0)
-#define _MX53_PAD_EIM_D21__USBOH3_USBOTG_OC     IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, 0)
-#define _MX53_PAD_EIM_D22__EMI_WEIM_D_22                IOMUX_PAD(0x478, 0x130, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D22__GPIO3_22                     IOMUX_PAD(0x478, 0x130, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D22__IPU_DI0_PIN1         IOMUX_PAD(0x478, 0x130, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN   IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, 0)
-#define _MX53_PAD_EIM_D22__CSPI_MISO                    IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, 0)
-#define _MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR    IOMUX_PAD(0x478, 0x130, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D23__EMI_WEIM_D_23                IOMUX_PAD(0x47C, 0x134, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D23__GPIO3_23                     IOMUX_PAD(0x47C, 0x134, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D23__UART3_CTS                    IOMUX_PAD(0x47C, 0x134, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D23__UART1_DCD            IOMUX_PAD(0x47C, 0x134, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D23__IPU_DI0_D0_CS                IOMUX_PAD(0x47C, 0x134, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D23__IPU_DI1_PIN2         IOMUX_PAD(0x47C, 0x134, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN             IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, 0)
-#define _MX53_PAD_EIM_D23__IPU_DI1_PIN14                IOMUX_PAD(0x47C, 0x134, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB3__EMI_WEIM_EB_3                IOMUX_PAD(0x480, 0x138, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB3__GPIO2_31                     IOMUX_PAD(0x480, 0x138, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB3__UART3_RTS                    IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, 0)
-#define _MX53_PAD_EIM_EB3__UART1_RI                     IOMUX_PAD(0x480, 0x138, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN3         IOMUX_PAD(0x480, 0x138, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC               IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, 0)
-#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN16                IOMUX_PAD(0x480, 0x138, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D24__EMI_WEIM_D_24                IOMUX_PAD(0x484, 0x13C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D24__GPIO3_24                     IOMUX_PAD(0x484, 0x13C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D24__UART3_TXD_MUX                IOMUX_PAD(0x484, 0x13C, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D24__ECSPI1_SS2           IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, 0)
-#define _MX53_PAD_EIM_D24__CSPI_SS2                     IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, 0)
-#define _MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS     IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, 0)
-#define _MX53_PAD_EIM_D24__ECSPI2_SS2           IOMUX_PAD(0x484, 0x13C, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D24__UART1_DTR            IOMUX_PAD(0x484, 0x13C, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D25__EMI_WEIM_D_25                IOMUX_PAD(0x488, 0x140, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D25__GPIO3_25                     IOMUX_PAD(0x488, 0x140, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D25__UART3_RXD_MUX                IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, 0)
-#define _MX53_PAD_EIM_D25__ECSPI1_SS3           IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, 0)
-#define _MX53_PAD_EIM_D25__CSPI_SS3                     IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, 0)
-#define _MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC              IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, 0)
-#define _MX53_PAD_EIM_D25__ECSPI2_SS3           IOMUX_PAD(0x488, 0x140, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D25__UART1_DSR            IOMUX_PAD(0x488, 0x140, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D26__EMI_WEIM_D_26                IOMUX_PAD(0x48C, 0x144, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D26__GPIO3_26                     IOMUX_PAD(0x48C, 0x144, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D26__UART2_TXD_MUX                IOMUX_PAD(0x48C, 0x144, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D26__FIRI_RXD                     IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, 0)
-#define _MX53_PAD_EIM_D26__IPU_CSI0_D_1         IOMUX_PAD(0x48C, 0x144, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D26__IPU_DI1_PIN11                IOMUX_PAD(0x48C, 0x144, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D26__IPU_SISG_2           IOMUX_PAD(0x48C, 0x144, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D26__IPU_DISP1_DAT_22             IOMUX_PAD(0x48C, 0x144, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D27__EMI_WEIM_D_27                IOMUX_PAD(0x490, 0x148, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D27__GPIO3_27                     IOMUX_PAD(0x490, 0x148, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D27__UART2_RXD_MUX                IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, 0)
-#define _MX53_PAD_EIM_D27__FIRI_TXD                     IOMUX_PAD(0x490, 0x148, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D27__IPU_CSI0_D_0         IOMUX_PAD(0x490, 0x148, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D27__IPU_DI1_PIN13                IOMUX_PAD(0x490, 0x148, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D27__IPU_SISG_3           IOMUX_PAD(0x490, 0x148, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D27__IPU_DISP1_DAT_23             IOMUX_PAD(0x490, 0x148, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D28__EMI_WEIM_D_28                IOMUX_PAD(0x494, 0x14C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D28__GPIO3_28                     IOMUX_PAD(0x494, 0x14C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D28__UART2_CTS                    IOMUX_PAD(0x494, 0x14C, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO   IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, 0)
-#define _MX53_PAD_EIM_D28__CSPI_MOSI                    IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, 0)
-#define _MX53_PAD_EIM_D28__I2C1_SDA                     IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, 0)
-#define _MX53_PAD_EIM_D28__IPU_EXT_TRIG         IOMUX_PAD(0x494, 0x14C, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D28__IPU_DI0_PIN13                IOMUX_PAD(0x494, 0x14C, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D29__EMI_WEIM_D_29                IOMUX_PAD(0x498, 0x150, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D29__GPIO3_29                     IOMUX_PAD(0x498, 0x150, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D29__UART2_RTS                    IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, 0)
-#define _MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS    IOMUX_PAD(0x498, 0x150, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D29__CSPI_SS0                     IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, 0)
-#define _MX53_PAD_EIM_D29__IPU_DI1_PIN15                IOMUX_PAD(0x498, 0x150, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D29__IPU_CSI1_VSYNC               IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, 0)
-#define _MX53_PAD_EIM_D29__IPU_DI0_PIN14                IOMUX_PAD(0x498, 0x150, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D30__EMI_WEIM_D_30                IOMUX_PAD(0x49C, 0x154, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D30__GPIO3_30                     IOMUX_PAD(0x49C, 0x154, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D30__UART3_CTS                    IOMUX_PAD(0x49C, 0x154, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D30__IPU_CSI0_D_3         IOMUX_PAD(0x49C, 0x154, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D30__IPU_DI0_PIN11                IOMUX_PAD(0x49C, 0x154, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D30__IPU_DISP1_DAT_21             IOMUX_PAD(0x49C, 0x154, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D30__USBOH3_USBH1_OC              IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, 0)
-#define _MX53_PAD_EIM_D30__USBOH3_USBH2_OC              IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, 0)
-#define _MX53_PAD_EIM_D31__EMI_WEIM_D_31                IOMUX_PAD(0x4A0, 0x158, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D31__GPIO3_31                     IOMUX_PAD(0x4A0, 0x158, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D31__UART3_RTS                    IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, 0)
-#define _MX53_PAD_EIM_D31__IPU_CSI0_D_2         IOMUX_PAD(0x4A0, 0x158, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D31__IPU_DI0_PIN12                IOMUX_PAD(0x4A0, 0x158, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D31__IPU_DISP1_DAT_20             IOMUX_PAD(0x4A0, 0x158, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D31__USBOH3_USBH1_PWR     IOMUX_PAD(0x4A0, 0x158, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D31__USBOH3_USBH2_PWR     IOMUX_PAD(0x4A0, 0x158, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A24__EMI_WEIM_A_24                IOMUX_PAD(0x4A8, 0x15C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A24__GPIO5_4                      IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A24__IPU_DISP1_DAT_19             IOMUX_PAD(0x4A8, 0x15C, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A24__IPU_CSI1_D_19                IOMUX_PAD(0x4A8, 0x15C, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A24__IPU_SISG_2           IOMUX_PAD(0x4A8, 0x15C, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A24__USBPHY2_BVALID               IOMUX_PAD(0x4A8, 0x15C, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A23__EMI_WEIM_A_23                IOMUX_PAD(0x4AC, 0x160, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A23__GPIO6_6                      IOMUX_PAD(0x4AC, 0x160, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A23__IPU_DISP1_DAT_18             IOMUX_PAD(0x4AC, 0x160, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A23__IPU_CSI1_D_18                IOMUX_PAD(0x4AC, 0x160, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A23__IPU_SISG_3           IOMUX_PAD(0x4AC, 0x160, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A23__USBPHY2_ENDSESSION   IOMUX_PAD(0x4AC, 0x160, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A22__EMI_WEIM_A_22                IOMUX_PAD(0x4B0, 0x164, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A22__GPIO2_16                     IOMUX_PAD(0x4B0, 0x164, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A22__IPU_DISP1_DAT_17             IOMUX_PAD(0x4B0, 0x164, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A22__IPU_CSI1_D_17                IOMUX_PAD(0x4B0, 0x164, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A22__SRC_BT_CFG1_7                IOMUX_PAD(0x4B0, 0x164, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A21__EMI_WEIM_A_21                IOMUX_PAD(0x4B4, 0x168, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A21__GPIO2_17                     IOMUX_PAD(0x4B4, 0x168, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A21__IPU_DISP1_DAT_16             IOMUX_PAD(0x4B4, 0x168, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A21__IPU_CSI1_D_16                IOMUX_PAD(0x4B4, 0x168, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A21__SRC_BT_CFG1_6                IOMUX_PAD(0x4B4, 0x168, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A20__EMI_WEIM_A_20                IOMUX_PAD(0x4B8, 0x16C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A20__GPIO2_18                     IOMUX_PAD(0x4B8, 0x16C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A20__IPU_DISP1_DAT_15             IOMUX_PAD(0x4B8, 0x16C, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A20__IPU_CSI1_D_15                IOMUX_PAD(0x4B8, 0x16C, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A20__SRC_BT_CFG1_5                IOMUX_PAD(0x4B8, 0x16C, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A19__EMI_WEIM_A_19                IOMUX_PAD(0x4BC, 0x170, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A19__GPIO2_19                     IOMUX_PAD(0x4BC, 0x170, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A19__IPU_DISP1_DAT_14             IOMUX_PAD(0x4BC, 0x170, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A19__IPU_CSI1_D_14                IOMUX_PAD(0x4BC, 0x170, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A19__SRC_BT_CFG1_4                IOMUX_PAD(0x4BC, 0x170, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A18__EMI_WEIM_A_18                IOMUX_PAD(0x4C0, 0x174, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A18__GPIO2_20                     IOMUX_PAD(0x4C0, 0x174, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A18__IPU_DISP1_DAT_13             IOMUX_PAD(0x4C0, 0x174, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A18__IPU_CSI1_D_13                IOMUX_PAD(0x4C0, 0x174, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A18__SRC_BT_CFG1_3                IOMUX_PAD(0x4C0, 0x174, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A17__EMI_WEIM_A_17                IOMUX_PAD(0x4C4, 0x178, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A17__GPIO2_21                     IOMUX_PAD(0x4C4, 0x178, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A17__IPU_DISP1_DAT_12             IOMUX_PAD(0x4C4, 0x178, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A17__IPU_CSI1_D_12                IOMUX_PAD(0x4C4, 0x178, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A17__SRC_BT_CFG1_2                IOMUX_PAD(0x4C4, 0x178, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A16__EMI_WEIM_A_16                IOMUX_PAD(0x4C8, 0x17C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A16__GPIO2_22                     IOMUX_PAD(0x4C8, 0x17C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK             IOMUX_PAD(0x4C8, 0x17C, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK              IOMUX_PAD(0x4C8, 0x17C, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A16__SRC_BT_CFG1_1                IOMUX_PAD(0x4C8, 0x17C, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_CS0__EMI_WEIM_CS_0                IOMUX_PAD(0x4CC, 0x180, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_CS0__GPIO2_23                     IOMUX_PAD(0x4CC, 0x180, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_CS0__ECSPI2_SCLK          IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, 0)
-#define _MX53_PAD_EIM_CS0__IPU_DI1_PIN5         IOMUX_PAD(0x4CC, 0x180, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_CS1__EMI_WEIM_CS_1                IOMUX_PAD(0x4D0, 0x184, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_CS1__GPIO2_24                     IOMUX_PAD(0x4D0, 0x184, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_CS1__ECSPI2_MOSI          IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, 0)
-#define _MX53_PAD_EIM_CS1__IPU_DI1_PIN6         IOMUX_PAD(0x4D0, 0x184, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_OE__EMI_WEIM_OE           IOMUX_PAD(0x4D4, 0x188, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_OE__GPIO2_25                      IOMUX_PAD(0x4D4, 0x188, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_OE__ECSPI2_MISO           IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, 0)
-#define _MX53_PAD_EIM_OE__IPU_DI1_PIN7          IOMUX_PAD(0x4D4, 0x188, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_OE__USBPHY2_IDDIG         IOMUX_PAD(0x4D4, 0x188, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_RW__EMI_WEIM_RW           IOMUX_PAD(0x4D8, 0x18C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_RW__GPIO2_26                      IOMUX_PAD(0x4D8, 0x18C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_RW__ECSPI2_SS0                    IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, 0)
-#define _MX53_PAD_EIM_RW__IPU_DI1_PIN8          IOMUX_PAD(0x4D8, 0x18C, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT        IOMUX_PAD(0x4D8, 0x18C, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_LBA__EMI_WEIM_LBA         IOMUX_PAD(0x4DC, 0x190, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_LBA__GPIO2_27                     IOMUX_PAD(0x4DC, 0x190, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_LBA__ECSPI2_SS1           IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, 0)
-#define _MX53_PAD_EIM_LBA__IPU_DI1_PIN17                IOMUX_PAD(0x4DC, 0x190, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_LBA__SRC_BT_CFG1_0                IOMUX_PAD(0x4DC, 0x190, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB0__EMI_WEIM_EB_0                IOMUX_PAD(0x4E4, 0x194, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB0__GPIO2_28                     IOMUX_PAD(0x4E4, 0x194, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11             IOMUX_PAD(0x4E4, 0x194, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB0__IPU_CSI1_D_11                IOMUX_PAD(0x4E4, 0x194, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB0__GPC_PMIC_RDY         IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, 0)
-#define _MX53_PAD_EIM_EB0__SRC_BT_CFG2_7                IOMUX_PAD(0x4E4, 0x194, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB1__EMI_WEIM_EB_1                IOMUX_PAD(0x4E8, 0x198, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB1__GPIO2_29                     IOMUX_PAD(0x4E8, 0x198, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10             IOMUX_PAD(0x4E8, 0x198, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB1__IPU_CSI1_D_10                IOMUX_PAD(0x4E8, 0x198, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB1__SRC_BT_CFG2_6                IOMUX_PAD(0x4E8, 0x198, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0   IOMUX_PAD(0x4EC, 0x19C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA0__GPIO3_0                      IOMUX_PAD(0x4EC, 0x19C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9              IOMUX_PAD(0x4EC, 0x19C, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA0__IPU_CSI1_D_9         IOMUX_PAD(0x4EC, 0x19C, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA0__SRC_BT_CFG2_5                IOMUX_PAD(0x4EC, 0x19C, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1   IOMUX_PAD(0x4F0, 0x1A0, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA1__GPIO3_1                      IOMUX_PAD(0x4F0, 0x1A0, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8              IOMUX_PAD(0x4F0, 0x1A0, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA1__IPU_CSI1_D_8         IOMUX_PAD(0x4F0, 0x1A0, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA1__SRC_BT_CFG2_4                IOMUX_PAD(0x4F0, 0x1A0, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2   IOMUX_PAD(0x4F4, 0x1A4, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA2__GPIO3_2                      IOMUX_PAD(0x4F4, 0x1A4, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7              IOMUX_PAD(0x4F4, 0x1A4, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA2__IPU_CSI1_D_7         IOMUX_PAD(0x4F4, 0x1A4, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA2__SRC_BT_CFG2_3                IOMUX_PAD(0x4F4, 0x1A4, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3   IOMUX_PAD(0x4F8, 0x1A8, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA3__GPIO3_3                      IOMUX_PAD(0x4F8, 0x1A8, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6              IOMUX_PAD(0x4F8, 0x1A8, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA3__IPU_CSI1_D_6         IOMUX_PAD(0x4F8, 0x1A8, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA3__SRC_BT_CFG2_2                IOMUX_PAD(0x4F8, 0x1A8, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4   IOMUX_PAD(0x4FC, 0x1AC, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA4__GPIO3_4                      IOMUX_PAD(0x4FC, 0x1AC, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5              IOMUX_PAD(0x4FC, 0x1AC, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA4__IPU_CSI1_D_5         IOMUX_PAD(0x4FC, 0x1AC, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA4__SRC_BT_CFG3_7                IOMUX_PAD(0x4FC, 0x1AC, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5   IOMUX_PAD(0x500, 0x1B0, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA5__GPIO3_5                      IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4              IOMUX_PAD(0x500, 0x1B0, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA5__IPU_CSI1_D_4         IOMUX_PAD(0x500, 0x1B0, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA5__SRC_BT_CFG3_6                IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6   IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA6__GPIO3_6                      IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3              IOMUX_PAD(0x504, 0x1B4, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA6__IPU_CSI1_D_3         IOMUX_PAD(0x504, 0x1B4, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA6__SRC_BT_CFG3_5                IOMUX_PAD(0x504, 0x1B4, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7   IOMUX_PAD(0x508, 0x1B8, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA7__GPIO3_7                      IOMUX_PAD(0x508, 0x1B8, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2              IOMUX_PAD(0x508, 0x1B8, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA7__IPU_CSI1_D_2         IOMUX_PAD(0x508, 0x1B8, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA7__SRC_BT_CFG3_4                IOMUX_PAD(0x508, 0x1B8, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8   IOMUX_PAD(0x50C, 0x1BC, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA8__GPIO3_8                      IOMUX_PAD(0x50C, 0x1BC, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1              IOMUX_PAD(0x50C, 0x1BC, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA8__IPU_CSI1_D_1         IOMUX_PAD(0x50C, 0x1BC, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA8__SRC_BT_CFG3_3                IOMUX_PAD(0x50C, 0x1BC, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9   IOMUX_PAD(0x510, 0x1C0, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA9__GPIO3_9                      IOMUX_PAD(0x510, 0x1C0, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0              IOMUX_PAD(0x510, 0x1C0, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA9__IPU_CSI1_D_0         IOMUX_PAD(0x510, 0x1C0, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA9__SRC_BT_CFG3_2                IOMUX_PAD(0x510, 0x1C0, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA10__GPIO3_10                    IOMUX_PAD(0x514, 0x1C4, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA10__IPU_DI1_PIN15               IOMUX_PAD(0x514, 0x1C4, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN    IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, 0)
-#define _MX53_PAD_EIM_DA10__SRC_BT_CFG3_1               IOMUX_PAD(0x514, 0x1C4, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA11__GPIO3_11                    IOMUX_PAD(0x518, 0x1C8, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA11__IPU_DI1_PIN2                IOMUX_PAD(0x518, 0x1C8, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC              IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, 0)
-#define _MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA12__GPIO3_12                    IOMUX_PAD(0x51C, 0x1CC, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA12__IPU_DI1_PIN3                IOMUX_PAD(0x51C, 0x1CC, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC              IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, 0)
-#define _MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA13__GPIO3_13                    IOMUX_PAD(0x520, 0x1D0, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA13__IPU_DI1_D0_CS               IOMUX_PAD(0x520, 0x1D0, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK             IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, 0)
-#define _MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA14__GPIO3_14                    IOMUX_PAD(0x524, 0x1D4, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA14__IPU_DI1_D1_CS               IOMUX_PAD(0x524, 0x1D4, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK             IOMUX_PAD(0x524, 0x1D4, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA15__GPIO3_15                    IOMUX_PAD(0x528, 0x1D8, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN1                IOMUX_PAD(0x528, 0x1D8, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN4                IOMUX_PAD(0x528, 0x1D8, 4, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B    IOMUX_PAD(0x52C, 0x1DC, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_WE_B__GPIO6_12          IOMUX_PAD(0x52C, 0x1DC, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B    IOMUX_PAD(0x530, 0x1E0, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_RE_B__GPIO6_13          IOMUX_PAD(0x530, 0x1E0, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT               IOMUX_PAD(0x534, 0x1E4, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_WAIT__GPIO5_0                     IOMUX_PAD(0x534, 0x1E4, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B    IOMUX_PAD(0x534, 0x1E4, 2, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_TX3_P__GPIO6_22         IOMUX_PAD(NON_PAD_I, 0x1EC, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3    IOMUX_PAD(NON_PAD_I, 0x1EC, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_TX2_P__GPIO6_24         IOMUX_PAD(NON_PAD_I, 0x1F0, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2    IOMUX_PAD(NON_PAD_I, 0x1F0, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_CLK_P__GPIO6_26         IOMUX_PAD(NON_PAD_I, 0x1F4, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK    IOMUX_PAD(NON_PAD_I, 0x1F4, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_TX1_P__GPIO6_28         IOMUX_PAD(NON_PAD_I, 0x1F8, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1    IOMUX_PAD(NON_PAD_I, 0x1F8, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_TX0_P__GPIO6_30         IOMUX_PAD(NON_PAD_I, 0x1FC, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0    IOMUX_PAD(NON_PAD_I, 0x1FC, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_TX3_P__GPIO7_22         IOMUX_PAD(NON_PAD_I, 0x200, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3    IOMUX_PAD(NON_PAD_I, 0x200, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_CLK_P__GPIO7_24         IOMUX_PAD(NON_PAD_I, 0x204, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK    IOMUX_PAD(NON_PAD_I, 0x204, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_TX2_P__GPIO7_26         IOMUX_PAD(NON_PAD_I, 0x208, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2    IOMUX_PAD(NON_PAD_I, 0x208, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_TX1_P__GPIO7_28         IOMUX_PAD(NON_PAD_I, 0x20C, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1    IOMUX_PAD(NON_PAD_I, 0x20C, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_TX0_P__GPIO7_30         IOMUX_PAD(NON_PAD_I, 0x210, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0    IOMUX_PAD(NON_PAD_I, 0x210, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_10__GPIO4_0                      IOMUX_PAD(0x540, 0x214, 0, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_10__OSC32k_32K_OUT               IOMUX_PAD(0x540, 0x214, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_11__GPIO4_1                      IOMUX_PAD(0x544, 0x218, 0, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_12__GPIO4_2                      IOMUX_PAD(0x548, 0x21C, 0, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_13__GPIO4_3                      IOMUX_PAD(0x54C, 0x220, 0, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_14__GPIO4_4                      IOMUX_PAD(0x550, 0x224, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CLE__EMI_NANDF_CLE              IOMUX_PAD(0x5A0, 0x228, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CLE__GPIO6_7                    IOMUX_PAD(0x5A0, 0x228, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0  IOMUX_PAD(0x5A0, 0x228, 7, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_ALE__EMI_NANDF_ALE              IOMUX_PAD(0x5A4, 0x22C, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_ALE__GPIO6_8            IOMUX_PAD(0x5A4, 0x22C, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1  IOMUX_PAD(0x5A4, 0x22C, 7, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B    IOMUX_PAD(0x5A8, 0x230, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_WP_B__GPIO6_9           IOMUX_PAD(0x5A8, 0x230, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0     IOMUX_PAD(0x5AC, 0x234, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_RB0__GPIO6_10           IOMUX_PAD(0x5AC, 0x234, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3  IOMUX_PAD(0x5AC, 0x234, 7, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0     IOMUX_PAD(0x5B0, 0x238, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS0__GPIO6_11           IOMUX_PAD(0x5B0, 0x238, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4  IOMUX_PAD(0x5B0, 0x238, 7, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1     IOMUX_PAD(0x5B4, 0x23C, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS1__GPIO6_14           IOMUX_PAD(0x5B4, 0x23C, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS1__MLB_MLBCLK         IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, 0)
-#define _MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5  IOMUX_PAD(0x5B4, 0x23C, 7, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2     IOMUX_PAD(0x5B8, 0x240, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS2__GPIO6_15           IOMUX_PAD(0x5B8, 0x240, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS2__IPU_SISG_0         IOMUX_PAD(0x5B8, 0x240, 2, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS2__ESAI1_TX0          IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, 0)
-#define _MX53_PAD_NANDF_CS2__EMI_WEIM_CRE               IOMUX_PAD(0x5B8, 0x240, 4, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK              IOMUX_PAD(0x5B8, 0x240, 5, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS2__MLB_MLBSIG         IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, 0)
-#define _MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6  IOMUX_PAD(0x5B8, 0x240, 7, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3     IOMUX_PAD(0x5BC, 0x244, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS3__GPIO6_16           IOMUX_PAD(0x5BC, 0x244, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS3__IPU_SISG_1         IOMUX_PAD(0x5BC, 0x244, 2, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS3__ESAI1_TX1          IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, 0)
-#define _MX53_PAD_NANDF_CS3__EMI_WEIM_A_26              IOMUX_PAD(0x5BC, 0x244, 4, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS3__MLB_MLBDAT         IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, 0)
-#define _MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7  IOMUX_PAD(0x5BC, 0x244, 7, 0x0, 0, 0)
-#define _MX53_PAD_FEC_MDIO__FEC_MDIO            IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, 0)
-#define _MX53_PAD_FEC_MDIO__GPIO1_22                    IOMUX_PAD(0x5C4, 0x248, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_MDIO__ESAI1_SCKR          IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, 0)
-#define _MX53_PAD_FEC_MDIO__FEC_COL                     IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, 0)
-#define _MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2              IOMUX_PAD(0x5C4, 0x248, 4, 0x0, 0, 0)
-#define _MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3     IOMUX_PAD(0x5C4, 0x248, 5, 0x0, 0, 0)
-#define _MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49    IOMUX_PAD(0x5C4, 0x248, 6, 0x0, 0, 0)
-#define _MX53_PAD_FEC_REF_CLK__FEC_TX_CLK               IOMUX_PAD(0x5C8, 0x24C, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_REF_CLK__GPIO1_23         IOMUX_PAD(0x5C8, 0x24C, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_REF_CLK__ESAI1_FSR                IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, 0)
-#define _MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4  IOMUX_PAD(0x5C8, 0x24C, 5, 0x0, 0, 0)
-#define _MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, 0x0, 0, 0)
-#define _MX53_PAD_FEC_RX_ER__FEC_RX_ER          IOMUX_PAD(0x5CC, 0x250, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_RX_ER__GPIO1_24           IOMUX_PAD(0x5CC, 0x250, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_RX_ER__ESAI1_HCKR         IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, 0)
-#define _MX53_PAD_FEC_RX_ER__FEC_RX_CLK         IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, 0)
-#define _MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3             IOMUX_PAD(0x5CC, 0x250, 4, 0x0, 0, 0)
-#define _MX53_PAD_FEC_CRS_DV__FEC_RX_DV         IOMUX_PAD(0x5D0, 0x254, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_CRS_DV__GPIO1_25          IOMUX_PAD(0x5D0, 0x254, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_CRS_DV__ESAI1_SCKT                IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, 0)
-#define _MX53_PAD_FEC_RXD1__FEC_RDATA_1         IOMUX_PAD(0x5D4, 0x258, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_RXD1__GPIO1_26                    IOMUX_PAD(0x5D4, 0x258, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_RXD1__ESAI1_FST           IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, 0)
-#define _MX53_PAD_FEC_RXD1__MLB_MLBSIG          IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, 0)
-#define _MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1              IOMUX_PAD(0x5D4, 0x258, 4, 0x0, 0, 0)
-#define _MX53_PAD_FEC_RXD0__FEC_RDATA_0         IOMUX_PAD(0x5D8, 0x25C, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_RXD0__GPIO1_27                    IOMUX_PAD(0x5D8, 0x25C, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_RXD0__ESAI1_HCKT          IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, 0)
-#define _MX53_PAD_FEC_RXD0__OSC32k_32K_OUT              IOMUX_PAD(0x5D8, 0x25C, 3, 0x0, 0, 0)
-#define _MX53_PAD_FEC_TX_EN__FEC_TX_EN          IOMUX_PAD(0x5DC, 0x260, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_TX_EN__GPIO1_28           IOMUX_PAD(0x5DC, 0x260, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2              IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, 0)
-#define _MX53_PAD_FEC_TXD1__FEC_TDATA_1         IOMUX_PAD(0x5E0, 0x264, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_TXD1__GPIO1_29                    IOMUX_PAD(0x5E0, 0x264, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3               IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, 0)
-#define _MX53_PAD_FEC_TXD1__MLB_MLBCLK          IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, 0)
-#define _MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, 0x0, 0, 0)
-#define _MX53_PAD_FEC_TXD0__FEC_TDATA_0         IOMUX_PAD(0x5E4, 0x268, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_TXD0__GPIO1_30                    IOMUX_PAD(0x5E4, 0x268, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1               IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, 0)
-#define _MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0   IOMUX_PAD(0x5E4, 0x268, 7, 0x0, 0, 0)
-#define _MX53_PAD_FEC_MDC__FEC_MDC                      IOMUX_PAD(0x5E8, 0x26C, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_MDC__GPIO1_31                     IOMUX_PAD(0x5E8, 0x26C, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_MDC__ESAI1_TX5_RX0                IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, 0)
-#define _MX53_PAD_FEC_MDC__MLB_MLBDAT           IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, 0)
-#define _MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG       IOMUX_PAD(0x5E8, 0x26C, 4, 0x0, 0, 0)
-#define _MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1    IOMUX_PAD(0x5E8, 0x26C, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DIOW__PATA_DIOW          IOMUX_PAD(0x5F0, 0x270, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DIOW__GPIO6_17           IOMUX_PAD(0x5F0, 0x270, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DIOW__UART1_TXD_MUX      IOMUX_PAD(0x5F0, 0x270, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2  IOMUX_PAD(0x5F0, 0x270, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMACK__PATA_DMACK                IOMUX_PAD(0x5F4, 0x274, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMACK__GPIO6_18          IOMUX_PAD(0x5F4, 0x274, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMACK__UART1_RXD_MUX     IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, 0)
-#define _MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMARQ__PATA_DMARQ                IOMUX_PAD(0x5F8, 0x278, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMARQ__GPIO7_0           IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0     IOMUX_PAD(0x5F8, 0x278, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN        IOMUX_PAD(0x5FC, 0x27C, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_BUFFER_EN__GPIO7_1               IOMUX_PAD(0x5FC, 0x27C, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, 0)
-#define _MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5     IOMUX_PAD(0x5FC, 0x27C, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_INTRQ__PATA_INTRQ                IOMUX_PAD(0x600, 0x280, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_INTRQ__GPIO7_2           IOMUX_PAD(0x600, 0x280, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_INTRQ__UART2_CTS         IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_INTRQ__CAN1_TXCAN                IOMUX_PAD(0x600, 0x280, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2     IOMUX_PAD(0x600, 0x280, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DIOR__PATA_DIOR          IOMUX_PAD(0x604, 0x284, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DIOR__GPIO7_3                    IOMUX_PAD(0x604, 0x284, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DIOR__UART2_RTS          IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, 0)
-#define _MX53_PAD_PATA_DIOR__CAN1_RXCAN         IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, 0)
-#define _MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7  IOMUX_PAD(0x604, 0x284, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B       IOMUX_PAD(0x608, 0x288, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_RESET_B__GPIO7_4         IOMUX_PAD(0x608, 0x288, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_RESET_B__ESDHC3_CMD              IOMUX_PAD(0x608, 0x288, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_RESET_B__UART1_CTS               IOMUX_PAD(0x608, 0x288, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_RESET_B__CAN2_TXCAN              IOMUX_PAD(0x608, 0x288, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0       IOMUX_PAD(0x608, 0x288, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_IORDY__PATA_IORDY                IOMUX_PAD(0x60C, 0x28C, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_IORDY__GPIO7_5           IOMUX_PAD(0x60C, 0x28C, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_IORDY__ESDHC3_CLK                IOMUX_PAD(0x60C, 0x28C, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_IORDY__UART1_RTS         IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, 0)
-#define _MX53_PAD_PATA_IORDY__CAN2_RXCAN                IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, 0)
-#define _MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_0__PATA_DA_0          IOMUX_PAD(0x610, 0x290, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_0__GPIO7_6            IOMUX_PAD(0x610, 0x290, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_0__ESDHC3_RST         IOMUX_PAD(0x610, 0x290, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_0__OWIRE_LINE         IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, 0)
-#define _MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2  IOMUX_PAD(0x610, 0x290, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_1__PATA_DA_1          IOMUX_PAD(0x614, 0x294, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_1__GPIO7_7            IOMUX_PAD(0x614, 0x294, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_1__ESDHC4_CMD         IOMUX_PAD(0x614, 0x294, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_1__UART3_CTS          IOMUX_PAD(0x614, 0x294, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3  IOMUX_PAD(0x614, 0x294, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_2__PATA_DA_2          IOMUX_PAD(0x618, 0x298, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_2__GPIO7_8            IOMUX_PAD(0x618, 0x298, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_2__ESDHC4_CLK         IOMUX_PAD(0x618, 0x298, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_2__UART3_RTS          IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, 0)
-#define _MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4  IOMUX_PAD(0x618, 0x298, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_CS_0__PATA_CS_0          IOMUX_PAD(0x61C, 0x29C, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_CS_0__GPIO7_9                    IOMUX_PAD(0x61C, 0x29C, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_CS_0__UART3_TXD_MUX              IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5  IOMUX_PAD(0x61C, 0x29C, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_CS_1__PATA_CS_1          IOMUX_PAD(0x620, 0x2A0, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_CS_1__GPIO7_10           IOMUX_PAD(0x620, 0x2A0, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_CS_1__UART3_RXD_MUX              IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, 0)
-#define _MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6  IOMUX_PAD(0x620, 0x2A0, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA0__PATA_DATA_0               IOMUX_PAD(0x628, 0x2A4, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA0__GPIO2_0           IOMUX_PAD(0x628, 0x2A4, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA0__EMI_NANDF_D_0     IOMUX_PAD(0x628, 0x2A4, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA0__ESDHC3_DAT4               IOMUX_PAD(0x628, 0x2A4, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0     IOMUX_PAD(0x628, 0x2A4, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0    IOMUX_PAD(0x628, 0x2A4, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA1__PATA_DATA_1               IOMUX_PAD(0x62C, 0x2A8, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA1__GPIO2_1           IOMUX_PAD(0x62C, 0x2A8, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA1__EMI_NANDF_D_1     IOMUX_PAD(0x62C, 0x2A8, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA1__ESDHC3_DAT5               IOMUX_PAD(0x62C, 0x2A8, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1     IOMUX_PAD(0x62C, 0x2A8, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1    IOMUX_PAD(0x62C, 0x2A8, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA2__PATA_DATA_2               IOMUX_PAD(0x630, 0x2AC, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA2__GPIO2_2           IOMUX_PAD(0x630, 0x2AC, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA2__EMI_NANDF_D_2     IOMUX_PAD(0x630, 0x2AC, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA2__ESDHC3_DAT6               IOMUX_PAD(0x630, 0x2AC, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2     IOMUX_PAD(0x630, 0x2AC, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2    IOMUX_PAD(0x630, 0x2AC, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA3__PATA_DATA_3               IOMUX_PAD(0x634, 0x2B0, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA3__GPIO2_3           IOMUX_PAD(0x634, 0x2B0, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA3__EMI_NANDF_D_3     IOMUX_PAD(0x634, 0x2B0, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA3__ESDHC3_DAT7               IOMUX_PAD(0x634, 0x2B0, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3     IOMUX_PAD(0x634, 0x2B0, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3    IOMUX_PAD(0x634, 0x2B0, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA4__PATA_DATA_4               IOMUX_PAD(0x638, 0x2B4, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA4__GPIO2_4           IOMUX_PAD(0x638, 0x2B4, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA4__EMI_NANDF_D_4     IOMUX_PAD(0x638, 0x2B4, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA4__ESDHC4_DAT4               IOMUX_PAD(0x638, 0x2B4, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4     IOMUX_PAD(0x638, 0x2B4, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4    IOMUX_PAD(0x638, 0x2B4, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA5__PATA_DATA_5       IOMUX_PAD(0x63C, 0x2B8, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA5__GPIO2_5           IOMUX_PAD(0x63C, 0x2B8, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA5__EMI_NANDF_D_5     IOMUX_PAD(0x63C, 0x2B8, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA5__ESDHC4_DAT5               IOMUX_PAD(0x63C, 0x2B8, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5     IOMUX_PAD(0x63C, 0x2B8, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5    IOMUX_PAD(0x63C, 0x2B8, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__PATA_DATA_6       IOMUX_PAD(0x640, 0x2BC, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__GPIO2_6           IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__EMI_NANDF_D_6     IOMUX_PAD(0x640, 0x2BC, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__ESDHC4_DAT6               IOMUX_PAD(0x640, 0x2BC, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6     IOMUX_PAD(0x640, 0x2BC, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6    IOMUX_PAD(0x640, 0x2BC, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA7__PATA_DATA_7               IOMUX_PAD(0x644, 0x2C0, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA7__GPIO2_7           IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA7__EMI_NANDF_D_7     IOMUX_PAD(0x644, 0x2C0, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA7__ESDHC4_DAT7               IOMUX_PAD(0x644, 0x2C0, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7     IOMUX_PAD(0x644, 0x2C0, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7    IOMUX_PAD(0x644, 0x2C0, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA8__PATA_DATA_8               IOMUX_PAD(0x648, 0x2C4, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA8__GPIO2_8           IOMUX_PAD(0x648, 0x2C4, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA8__ESDHC1_DAT4               IOMUX_PAD(0x648, 0x2C4, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA8__EMI_NANDF_D_8     IOMUX_PAD(0x648, 0x2C4, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA8__ESDHC3_DAT0               IOMUX_PAD(0x648, 0x2C4, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8     IOMUX_PAD(0x648, 0x2C4, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8    IOMUX_PAD(0x648, 0x2C4, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA9__PATA_DATA_9               IOMUX_PAD(0x64C, 0x2C8, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA9__GPIO2_9           IOMUX_PAD(0x64C, 0x2C8, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA9__ESDHC1_DAT5               IOMUX_PAD(0x64C, 0x2C8, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA9__EMI_NANDF_D_9     IOMUX_PAD(0x64C, 0x2C8, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA9__ESDHC3_DAT1               IOMUX_PAD(0x64C, 0x2C8, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9     IOMUX_PAD(0x64C, 0x2C8, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9    IOMUX_PAD(0x64C, 0x2C8, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA10__PATA_DATA_10     IOMUX_PAD(0x650, 0x2CC, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA10__GPIO2_10         IOMUX_PAD(0x650, 0x2CC, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA10__ESDHC1_DAT6              IOMUX_PAD(0x650, 0x2CC, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA10__EMI_NANDF_D_10   IOMUX_PAD(0x650, 0x2CC, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA10__ESDHC3_DAT2              IOMUX_PAD(0x650, 0x2CC, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10   IOMUX_PAD(0x650, 0x2CC, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10  IOMUX_PAD(0x650, 0x2CC, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA11__PATA_DATA_11     IOMUX_PAD(0x654, 0x2D0, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA11__GPIO2_11         IOMUX_PAD(0x654, 0x2D0, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA11__ESDHC1_DAT7              IOMUX_PAD(0x654, 0x2D0, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA11__EMI_NANDF_D_11   IOMUX_PAD(0x654, 0x2D0, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA11__ESDHC3_DAT3              IOMUX_PAD(0x654, 0x2D0, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11   IOMUX_PAD(0x654, 0x2D0, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11  IOMUX_PAD(0x654, 0x2D0, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA12__PATA_DATA_12     IOMUX_PAD(0x658, 0x2D4, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA12__GPIO2_12         IOMUX_PAD(0x658, 0x2D4, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA12__ESDHC2_DAT4              IOMUX_PAD(0x658, 0x2D4, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA12__EMI_NANDF_D_12   IOMUX_PAD(0x658, 0x2D4, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA12__ESDHC4_DAT0              IOMUX_PAD(0x658, 0x2D4, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12   IOMUX_PAD(0x658, 0x2D4, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12  IOMUX_PAD(0x658, 0x2D4, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA13__PATA_DATA_13     IOMUX_PAD(0x65C, 0x2D8, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA13__GPIO2_13         IOMUX_PAD(0x65C, 0x2D8, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA13__ESDHC2_DAT5              IOMUX_PAD(0x65C, 0x2D8, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA13__EMI_NANDF_D_13   IOMUX_PAD(0x65C, 0x2D8, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA13__ESDHC4_DAT1              IOMUX_PAD(0x65C, 0x2D8, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13   IOMUX_PAD(0x65C, 0x2D8, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13  IOMUX_PAD(0x65C, 0x2D8, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA14__PATA_DATA_14     IOMUX_PAD(0x660, 0x2DC, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA14__GPIO2_14         IOMUX_PAD(0x660, 0x2DC, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA14__ESDHC2_DAT6              IOMUX_PAD(0x660, 0x2DC, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA14__EMI_NANDF_D_14   IOMUX_PAD(0x660, 0x2DC, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA14__ESDHC4_DAT2              IOMUX_PAD(0x660, 0x2DC, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14   IOMUX_PAD(0x660, 0x2DC, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14  IOMUX_PAD(0x660, 0x2DC, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA15__PATA_DATA_15     IOMUX_PAD(0x664, 0x2E0, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA15__GPIO2_15         IOMUX_PAD(0x664, 0x2E0, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA15__ESDHC2_DAT7              IOMUX_PAD(0x664, 0x2E0, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA15__EMI_NANDF_D_15   IOMUX_PAD(0x664, 0x2E0, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA15__ESDHC4_DAT3              IOMUX_PAD(0x664, 0x2E0, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15   IOMUX_PAD(0x664, 0x2E0, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15  IOMUX_PAD(0x664, 0x2E0, 6, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA0__ESDHC1_DAT0        IOMUX_PAD(0x66C, 0x2E4, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA0__GPIO1_16   IOMUX_PAD(0x66C, 0x2E4, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA0__CSPI_MISO  IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, 0)
-#define _MX53_PAD_SD1_DATA0__CCM_PLL3_BYP       IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, 0)
-#define _MX53_PAD_SD1_DATA1__ESDHC1_DAT1        IOMUX_PAD(0x670, 0x2E8, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA1__GPIO1_17   IOMUX_PAD(0x670, 0x2E8, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA1__CSPI_SS0   IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, 0)
-#define _MX53_PAD_SD1_DATA1__CCM_PLL4_BYP       IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, 0)
-#define _MX53_PAD_SD1_CMD__ESDHC1_CMD   IOMUX_PAD(0x674, 0x2EC, IOMUX_CONFIG_SION, 0x0, 0, 0)
-#define _MX53_PAD_SD1_CMD__GPIO1_18             IOMUX_PAD(0x674, 0x2EC, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD1_CMD__GPT_CMPOUT1  IOMUX_PAD(0x674, 0x2EC, 3, 0x0, 0, 0)
-#define _MX53_PAD_SD1_CMD__CSPI_MOSI            IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, 0)
-#define _MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, 0)
-#define _MX53_PAD_SD1_DATA2__ESDHC1_DAT2                IOMUX_PAD(0x678, 0x2F0, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA2__GPIO1_19           IOMUX_PAD(0x678, 0x2F0, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA2__GPT_CMPOUT2                IOMUX_PAD(0x678, 0x2F0, 2, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA2__PWM2_PWMO          IOMUX_PAD(0x678, 0x2F0, 3, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_B               IOMUX_PAD(0x678, 0x2F0, 4, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA2__CSPI_SS1           IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, 0)
-#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB       IOMUX_PAD(0x678, 0x2F0, 6, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA2__CCM_PLL2_BYP               IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, 0)
-#define _MX53_PAD_SD1_CLK__ESDHC1_CLK   IOMUX_PAD(0x67C, 0x2F4, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD1_CLK__GPIO1_20             IOMUX_PAD(0x67C, 0x2F4, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD1_CLK__OSC32k_32K_OUT       IOMUX_PAD(0x67C, 0x2F4, 2, 0x0, 0, 0)
-#define _MX53_PAD_SD1_CLK__GPT_CLKIN            IOMUX_PAD(0x67C, 0x2F4, 3, 0x0, 0, 0)
-#define _MX53_PAD_SD1_CLK__CSPI_SCLK            IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, 0)
-#define _MX53_PAD_SD1_CLK__SATA_PHY_DTB_0       IOMUX_PAD(0x67C, 0x2F4, 7, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA3__ESDHC1_DAT3        IOMUX_PAD(0x680, 0x2F8, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA3__GPIO1_21   IOMUX_PAD(0x680, 0x2F8, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA3__GPT_CMPOUT3        IOMUX_PAD(0x680, 0x2F8, 2, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA3__PWM1_PWMO  IOMUX_PAD(0x680, 0x2F8, 3, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_B       IOMUX_PAD(0x680, 0x2F8, 4, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA3__CSPI_SS2   IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, 0)
-#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB       IOMUX_PAD(0x680, 0x2F8, 6, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1     IOMUX_PAD(0x680, 0x2F8, 7, 0x0, 0, 0)
-#define _MX53_PAD_SD2_CLK__ESDHC2_CLK   IOMUX_PAD(0x688, 0x2FC, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD2_CLK__GPIO1_10             IOMUX_PAD(0x688, 0x2FC, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD2_CLK__KPP_COL_5            IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, 0)
-#define _MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS     IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, 0)
-#define _MX53_PAD_SD2_CLK__CSPI_SCLK            IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, 0)
-#define _MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, 0x0, 0, 0)
-#define _MX53_PAD_SD2_CMD__ESDHC2_CMD   IOMUX_PAD(0x68C, 0x300, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD2_CMD__GPIO1_11             IOMUX_PAD(0x68C, 0x300, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD2_CMD__KPP_ROW_5    IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, 0)
-#define _MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC      IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, 0)
-#define _MX53_PAD_SD2_CMD__CSPI_MOSI            IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, 0)
-#define _MX53_PAD_SD2_CMD__SCC_RANDOM   IOMUX_PAD(0x68C, 0x300, 7, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA3__ESDHC2_DAT3        IOMUX_PAD(0x690, 0x304, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA3__GPIO1_12   IOMUX_PAD(0x690, 0x304, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA3__KPP_COL_6  IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, 0)
-#define _MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC    IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, 0)
-#define _MX53_PAD_SD2_DATA3__CSPI_SS2   IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, 0)
-#define _MX53_PAD_SD2_DATA3__SJC_DONE   IOMUX_PAD(0x690, 0x304, 7, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA2__ESDHC2_DAT2        IOMUX_PAD(0x694, 0x308, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA2__GPIO1_13   IOMUX_PAD(0x694, 0x308, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA2__KPP_ROW_6  IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, 0)
-#define _MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD    IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, 0)
-#define _MX53_PAD_SD2_DATA2__CSPI_SS1   IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, 0)
-#define _MX53_PAD_SD2_DATA2__SJC_FAIL   IOMUX_PAD(0x694, 0x308, 7, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA1__ESDHC2_DAT1        IOMUX_PAD(0x698, 0x30C, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA1__GPIO1_14   IOMUX_PAD(0x698, 0x30C, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA1__KPP_COL_7  IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, 0)
-#define _MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS   IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, 0)
-#define _MX53_PAD_SD2_DATA1__CSPI_SS0   IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, 0)
-#define _MX53_PAD_SD2_DATA1__RTIC_SEC_VIO       IOMUX_PAD(0x698, 0x30C, 7, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA0__ESDHC2_DAT0        IOMUX_PAD(0x69C, 0x310, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA0__GPIO1_15   IOMUX_PAD(0x69C, 0x310, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA0__KPP_ROW_7  IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, 0)
-#define _MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD    IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, 0)
-#define _MX53_PAD_SD2_DATA0__CSPI_MISO  IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, 0)
-#define _MX53_PAD_SD2_DATA0__RTIC_DONE_INT      IOMUX_PAD(0x69C, 0x310, 7, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_0__CCM_CLKO              IOMUX_PAD(0x6A4, 0x314, 0, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_0__GPIO1_0               IOMUX_PAD(0x6A4, 0x314, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_0__KPP_COL_5             IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, 0)
-#define _MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK      IOMUX_PAD(0x6A4, 0x314, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_0__EPIT1_EPITO   IOMUX_PAD(0x6A4, 0x314, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_0__SRTC_ALARM_DEB        IOMUX_PAD(0x6A4, 0x314, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_0__USBOH3_USBH1_PWR      IOMUX_PAD(0x6A4, 0x314, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_0__CSU_TD                IOMUX_PAD(0x6A4, 0x314, 7, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_1__ESAI1_SCKR            IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, 0)
-#define _MX53_PAD_GPIO_1__GPIO1_1               IOMUX_PAD(0x6A8, 0x318, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_1__KPP_ROW_5             IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, 0)
-#define _MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK      IOMUX_PAD(0x6A8, 0x318, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_1__PWM2_PWMO     IOMUX_PAD(0x6A8, 0x318, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_1__WDOG2_WDOG_B  IOMUX_PAD(0x6A8, 0x318, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_1__ESDHC1_CD             IOMUX_PAD(0x6A8, 0x318, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_1__SRC_TESTER_ACK        IOMUX_PAD(0x6A8, 0x318, 7, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_9__ESAI1_FSR             IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, 0)
-#define _MX53_PAD_GPIO_9__GPIO1_9               IOMUX_PAD(0x6AC, 0x31C, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_9__KPP_COL_6             IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, 0)
-#define _MX53_PAD_GPIO_9__CCM_REF_EN_B  IOMUX_PAD(0x6AC, 0x31C, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_9__PWM1_PWMO     IOMUX_PAD(0x6AC, 0x31C, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_9__WDOG1_WDOG_B  IOMUX_PAD(0x6AC, 0x31C, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_9__ESDHC1_WP             IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, 0)
-#define _MX53_PAD_GPIO_9__SCC_FAIL_STATE        IOMUX_PAD(0x6AC, 0x31C, 7, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_3__ESAI1_HCKR            IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, 0)
-#define _MX53_PAD_GPIO_3__GPIO1_3               IOMUX_PAD(0x6B0, 0x320, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_3__I2C3_SCL              IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, 0)
-#define _MX53_PAD_GPIO_3__DPLLIP1_TOG_EN        IOMUX_PAD(0x6B0, 0x320, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_3__CCM_CLKO2             IOMUX_PAD(0x6B0, 0x320, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0    IOMUX_PAD(0x6B0, 0x320, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_3__USBOH3_USBH1_OC       IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, 0)
-#define _MX53_PAD_GPIO_3__MLB_MLBCLK            IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, 0)
-#define _MX53_PAD_GPIO_6__ESAI1_SCKT            IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, 0)
-#define _MX53_PAD_GPIO_6__GPIO1_6               IOMUX_PAD(0x6B4, 0x324, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_6__I2C3_SDA              IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, 0)
-#define _MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_6__CSU_CSU_INT_DEB       IOMUX_PAD(0x6B4, 0x324, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1    IOMUX_PAD(0x6B4, 0x324, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_6__ESDHC2_LCTL   IOMUX_PAD(0x6B4, 0x324, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_6__MLB_MLBSIG            IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, 0)
-#define _MX53_PAD_GPIO_2__ESAI1_FST             IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, 0)
-#define _MX53_PAD_GPIO_2__GPIO1_2               IOMUX_PAD(0x6B8, 0x328, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_2__KPP_ROW_6             IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, 0)
-#define _MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0   IOMUX_PAD(0x6B8, 0x328, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2    IOMUX_PAD(0x6B8, 0x328, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_2__ESDHC2_WP             IOMUX_PAD(0x6B8, 0x328, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_2__MLB_MLBDAT    IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, 0)
-#define _MX53_PAD_GPIO_4__ESAI1_HCKT            IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, 0)
-#define _MX53_PAD_GPIO_4__GPIO1_4               IOMUX_PAD(0x6BC, 0x32C, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_4__KPP_COL_7             IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, 0)
-#define _MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1   IOMUX_PAD(0x6BC, 0x32C, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3    IOMUX_PAD(0x6BC, 0x32C, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_4__ESDHC2_CD             IOMUX_PAD(0x6BC, 0x32C, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, 0)
-#define _MX53_PAD_GPIO_5__GPIO1_5               IOMUX_PAD(0x6C0, 0x330, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_5__KPP_ROW_7             IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, 0)
-#define _MX53_PAD_GPIO_5__CCM_CLKO              IOMUX_PAD(0x6C0, 0x330, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2   IOMUX_PAD(0x6C0, 0x330, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4    IOMUX_PAD(0x6C0, 0x330, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_5__I2C3_SCL              IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, 0)
-#define _MX53_PAD_GPIO_5__CCM_PLL1_BYP  IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, 0)
-#define _MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, 0)
-#define _MX53_PAD_GPIO_7__GPIO1_7               IOMUX_PAD(0x6C4, 0x334, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_7__EPIT1_EPITO   IOMUX_PAD(0x6C4, 0x334, 2, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_7__CAN1_TXCAN    IOMUX_PAD(0x6C4, 0x334, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_7__FIRI_RXD              IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, 0)
-#define _MX53_PAD_GPIO_7__SPDIF_PLOCK   IOMUX_PAD(0x6C4, 0x334, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_7__CCM_PLL2_BYP  IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, 0)
-#define _MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, 0)
-#define _MX53_PAD_GPIO_8__GPIO1_8               IOMUX_PAD(0x6C8, 0x338, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_8__EPIT2_EPITO   IOMUX_PAD(0x6C8, 0x338, 2, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_8__CAN1_RXCAN    IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, 0)
-#define _MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, 0)
-#define _MX53_PAD_GPIO_8__FIRI_TXD              IOMUX_PAD(0x6C8, 0x338, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_8__SPDIF_SRCLK   IOMUX_PAD(0x6C8, 0x338, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_8__CCM_PLL3_BYP  IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, 0)
-#define _MX53_PAD_GPIO_16__ESAI1_TX3_RX2        IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, 0)
-#define _MX53_PAD_GPIO_16__GPIO7_11             IOMUX_PAD(0x6CC, 0x33C, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT     IOMUX_PAD(0x6CC, 0x33C, 2, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_16__SPDIF_IN1            IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, 0)
-#define _MX53_PAD_GPIO_16__I2C3_SDA             IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, 0)
-#define _MX53_PAD_GPIO_16__SJC_DE_B             IOMUX_PAD(0x6CC, 0x33C, 7, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_17__ESAI1_TX0            IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, 0)
-#define _MX53_PAD_GPIO_17__GPIO7_12             IOMUX_PAD(0x6D0, 0x340, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0     IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, 0)
-#define _MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, 0)
-#define _MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG  IOMUX_PAD(0x6D0, 0x340, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_17__SPDIF_OUT1   IOMUX_PAD(0x6D0, 0x340, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_17__IPU_SNOOP2   IOMUX_PAD(0x6D0, 0x340, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_18__ESAI1_TX1            IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, 0)
-#define _MX53_PAD_GPIO_18__GPIO7_13             IOMUX_PAD(0x6D4, 0x344, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1     IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, 0)
-#define _MX53_PAD_GPIO_18__OWIRE_LINE   IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, 0)
-#define _MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG       IOMUX_PAD(0x6D4, 0x344, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK     IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, 0)
-#define _MX53_PAD_GPIO_18__ESDHC1_LCTL  IOMUX_PAD(0x6D4, 0x344, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_18__SRC_SYSTEM_RST       IOMUX_PAD(0x6D4, 0x344, 7, 0x0, 0, 0)
 
-#define MX53_PAD_GPIO_19__KPP_COL_5             (_MX53_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_19__GPIO4_5               (_MX53_PAD_GPIO_19__GPIO4_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_19__CCM_CLKO              (_MX53_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_19__SPDIF_OUT1            (_MX53_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2          (_MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_19__ECSPI1_RDY            (_MX53_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_19__FEC_TDATA_3           (_MX53_PAD_GPIO_19__FEC_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_19__SRC_INT_BOOT          (_MX53_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL0__KPP_COL_0            (_MX53_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL0__GPIO4_6              (_MX53_PAD_KEY_COL0__GPIO4_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC              (_MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL0__UART4_TXD_MUX                (_MX53_PAD_KEY_COL0__UART4_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_KEY_COL0__ECSPI1_SCLK          (_MX53_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL0__FEC_RDATA_3          (_MX53_PAD_KEY_COL0__FEC_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST               (_MX53_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW0__KPP_ROW_0            (_MX53_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW0__GPIO4_7              (_MX53_PAD_KEY_ROW0__GPIO4_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD              (_MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX                (_MX53_PAD_KEY_ROW0__UART4_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI          (_MX53_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW0__FEC_TX_ER            (_MX53_PAD_KEY_ROW0__FEC_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL1__KPP_COL_1            (_MX53_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL1__GPIO4_8              (_MX53_PAD_KEY_COL1__GPIO4_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS             (_MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL1__UART5_TXD_MUX                (_MX53_PAD_KEY_COL1__UART5_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_KEY_COL1__ECSPI1_MISO          (_MX53_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL1__FEC_RX_CLK           (_MX53_PAD_KEY_COL1__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY              (_MX53_PAD_KEY_COL1__USBPHY1_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW1__KPP_ROW_1            (_MX53_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW1__GPIO4_9              (_MX53_PAD_KEY_ROW1__GPIO4_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD              (_MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX                (_MX53_PAD_KEY_ROW1__UART5_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_KEY_ROW1__ECSPI1_SS0           (_MX53_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW1__FEC_COL              (_MX53_PAD_KEY_ROW1__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID              (_MX53_PAD_KEY_ROW1__USBPHY1_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL2__KPP_COL_2            (_MX53_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL2__GPIO4_10             (_MX53_PAD_KEY_COL2__GPIO4_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL2__CAN1_TXCAN           (_MX53_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL2__FEC_MDIO             (_MX53_PAD_KEY_COL2__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL2__ECSPI1_SS1           (_MX53_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL2__FEC_RDATA_2          (_MX53_PAD_KEY_COL2__FEC_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE             (_MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW2__KPP_ROW_2            (_MX53_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW2__GPIO4_11             (_MX53_PAD_KEY_ROW2__GPIO4_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW2__CAN1_RXCAN           (_MX53_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW2__FEC_MDC              (_MX53_PAD_KEY_ROW2__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW2__ECSPI1_SS2           (_MX53_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW2__FEC_TDATA_2          (_MX53_PAD_KEY_ROW2__FEC_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR              (_MX53_PAD_KEY_ROW2__USBPHY1_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL3__KPP_COL_3            (_MX53_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL3__GPIO4_12             (_MX53_PAD_KEY_COL3__GPIO4_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL3__USBOH3_H2_DP         (_MX53_PAD_KEY_COL3__USBOH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL3__SPDIF_IN1            (_MX53_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL3__I2C2_SCL             (_MX53_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
-#define MX53_PAD_KEY_COL3__ECSPI1_SS3           (_MX53_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL3__FEC_CRS              (_MX53_PAD_KEY_COL3__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK             (_MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW3__KPP_ROW_3            (_MX53_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW3__GPIO4_13             (_MX53_PAD_KEY_ROW3__GPIO4_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM         (_MX53_PAD_KEY_ROW3__USBOH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK             (_MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW3__I2C2_SDA             (_MX53_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
-#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT               (_MX53_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP         (_MX53_PAD_KEY_ROW3__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0          (_MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL4__KPP_COL_4            (_MX53_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL4__GPIO4_14             (_MX53_PAD_KEY_COL4__GPIO4_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL4__CAN2_TXCAN           (_MX53_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL4__IPU_SISG_4           (_MX53_PAD_KEY_COL4__IPU_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL4__UART5_RTS            (_MX53_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC             (_MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1          (_MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW4__KPP_ROW_4            (_MX53_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW4__GPIO4_15             (_MX53_PAD_KEY_ROW4__GPIO4_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW4__CAN2_RXCAN           (_MX53_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW4__IPU_SISG_5           (_MX53_PAD_KEY_ROW4__IPU_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW4__UART5_CTS            (_MX53_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR            (_MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID            (_MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK         (_MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_DISP_CLK__GPIO4_16         (_MX53_PAD_DI0_DISP_CLK__GPIO4_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR         (_MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0          (_MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0          (_MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID           (_MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               (_MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN15__GPIO4_17            (_MX53_PAD_DI0_PIN15__GPIO4_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC             (_MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1             (_MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1             (_MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID              (_MX53_PAD_DI0_PIN15__USBPHY1_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2         (_MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN2__GPIO4_18             (_MX53_PAD_DI0_PIN2__GPIO4_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD              (_MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2              (_MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2              (_MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION           (_MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3         (_MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN3__GPIO4_19             (_MX53_PAD_DI0_PIN3__GPIO4_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS             (_MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3              (_MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3              (_MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG                (_MX53_PAD_DI0_PIN3__USBPHY1_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4         (_MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN4__GPIO4_20             (_MX53_PAD_DI0_PIN4__GPIO4_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD              (_MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN4__ESDHC1_WP            (_MX53_PAD_DI0_PIN4__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD             (_MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4              (_MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT               (_MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            (_MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT0__GPIO4_21           (_MX53_PAD_DISP0_DAT0__GPIO4_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT0__CSPI_SCLK          (_MX53_PAD_DISP0_DAT0__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0                (_MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN                (_MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5            (_MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY            (_MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            (_MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT1__GPIO4_22           (_MX53_PAD_DISP0_DAT1__GPIO4_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT1__CSPI_MOSI          (_MX53_PAD_DISP0_DAT1__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1                (_MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL               (_MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6            (_MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID            (_MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            (_MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT2__GPIO4_23           (_MX53_PAD_DISP0_DAT2__GPIO4_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT2__CSPI_MISO          (_MX53_PAD_DISP0_DAT2__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2                (_MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE            (_MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7            (_MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE           (_MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            (_MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT3__GPIO4_24           (_MX53_PAD_DISP0_DAT3__GPIO4_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT3__CSPI_SS0           (_MX53_PAD_DISP0_DAT3__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3                (_MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR               (_MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8            (_MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR            (_MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            (_MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT4__GPIO4_25           (_MX53_PAD_DISP0_DAT4__GPIO4_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT4__CSPI_SS1           (_MX53_PAD_DISP0_DAT4__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4                (_MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB         (_MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9            (_MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK           (_MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            (_MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT5__GPIO4_26           (_MX53_PAD_DISP0_DAT5__GPIO4_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT5__CSPI_SS2           (_MX53_PAD_DISP0_DAT5__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5                (_MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS           (_MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10           (_MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0                (_MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            (_MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT6__GPIO4_27           (_MX53_PAD_DISP0_DAT6__GPIO4_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT6__CSPI_SS3           (_MX53_PAD_DISP0_DAT6__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6                (_MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE          (_MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11           (_MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1                (_MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            (_MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT7__GPIO4_28           (_MX53_PAD_DISP0_DAT7__GPIO4_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT7__CSPI_RDY           (_MX53_PAD_DISP0_DAT7__CSPI_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7                (_MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0         (_MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12           (_MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID          (_MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            (_MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT8__GPIO4_29           (_MX53_PAD_DISP0_DAT8__GPIO4_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT8__PWM1_PWMO          (_MX53_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B               (_MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1         (_MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13           (_MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID             (_MX53_PAD_DISP0_DAT8__USBPHY2_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            (_MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT9__GPIO4_30           (_MX53_PAD_DISP0_DAT9__GPIO4_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT9__PWM2_PWMO          (_MX53_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B               (_MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2         (_MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14           (_MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0          (_MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          (_MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT10__GPIO4_31          (_MX53_PAD_DISP0_DAT10__GPIO4_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP          (_MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3                (_MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15          (_MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1         (_MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          (_MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT11__GPIO5_5           (_MX53_PAD_DISP0_DAT11__GPIO5_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT          (_MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4                (_MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16          (_MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2         (_MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          (_MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT12__GPIO5_6           (_MX53_PAD_DISP0_DAT12__GPIO5_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK          (_MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5                (_MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17          (_MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3         (_MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          (_MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT13__GPIO5_7           (_MX53_PAD_DISP0_DAT13__GPIO5_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS          (_MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0                (_MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18          (_MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4         (_MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          (_MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT14__GPIO5_8           (_MX53_PAD_DISP0_DAT14__GPIO5_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC           (_MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1                (_MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19          (_MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5         (_MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          (_MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT15__GPIO5_9           (_MX53_PAD_DISP0_DAT15__GPIO5_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1                (_MX53_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1                (_MX53_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2                (_MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20          (_MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6         (_MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          (_MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT16__GPIO5_10          (_MX53_PAD_DISP0_DAT16__GPIO5_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI               (_MX53_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC           (_MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0          (_MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3                (_MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21          (_MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7         (_MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          (_MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT17__GPIO5_11          (_MX53_PAD_DISP0_DAT17__GPIO5_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO               (_MX53_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD           (_MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1          (_MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4                (_MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22          (_MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          (_MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT18__GPIO5_12          (_MX53_PAD_DISP0_DAT18__GPIO5_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0                (_MX53_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS          (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS          (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5                (_MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23          (_MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2             (_MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          (_MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT19__GPIO5_13          (_MX53_PAD_DISP0_DAT19__GPIO5_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK               (_MX53_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD           (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC           (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6                (_MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24          (_MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3             (_MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          (_MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT20__GPIO5_14          (_MX53_PAD_DISP0_DAT20__GPIO5_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK               (_MX53_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC           (_MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7                (_MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25          (_MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI              (_MX53_PAD_DISP0_DAT20__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          (_MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT21__GPIO5_15          (_MX53_PAD_DISP0_DAT21__GPIO5_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI               (_MX53_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD           (_MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0           (_MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26          (_MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO              (_MX53_PAD_DISP0_DAT21__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          (_MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT22__GPIO5_16          (_MX53_PAD_DISP0_DAT22__GPIO5_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO               (_MX53_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS          (_MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1           (_MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27          (_MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK              (_MX53_PAD_DISP0_DAT22__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          (_MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT23__GPIO5_17          (_MX53_PAD_DISP0_DAT23__GPIO5_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0                (_MX53_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD           (_MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2           (_MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28          (_MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS              (_MX53_PAD_DISP0_DAT23__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK           (_MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_PIXCLK__GPIO5_18          (_MX53_PAD_CSI0_PIXCLK__GPIO5_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0           (_MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29          (_MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC              (_MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_MCLK__GPIO5_19            (_MX53_PAD_CSI0_MCLK__GPIO5_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK               (_MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1             (_MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30            (_MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL          (_MX53_PAD_CSI0_MCLK__TPIU_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN         (_MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DATA_EN__GPIO5_20         (_MX53_PAD_CSI0_DATA_EN__GPIO5_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2          (_MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31         (_MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK               (_MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC             (_MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_VSYNC__GPIO5_21           (_MX53_PAD_CSI0_VSYNC__GPIO5_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3            (_MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32           (_MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0               (_MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4                (_MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT4__GPIO5_22            (_MX53_PAD_CSI0_DAT4__GPIO5_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT4__KPP_COL_5           (_MX53_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK         (_MX53_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP            (_MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC             (_MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33            (_MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1                (_MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5                (_MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT5__GPIO5_23            (_MX53_PAD_CSI0_DAT5__GPIO5_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT5__KPP_ROW_5           (_MX53_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI         (_MX53_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT            (_MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD             (_MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34            (_MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2                (_MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6                (_MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT6__GPIO5_24            (_MX53_PAD_CSI0_DAT6__GPIO5_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT6__KPP_COL_6           (_MX53_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO         (_MX53_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK            (_MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS            (_MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35            (_MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3                (_MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7                (_MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT7__GPIO5_25            (_MX53_PAD_CSI0_DAT7__GPIO5_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT7__KPP_ROW_6           (_MX53_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0          (_MX53_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR            (_MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD             (_MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36            (_MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4                (_MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8                (_MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT8__GPIO5_26            (_MX53_PAD_CSI0_DAT8__GPIO5_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT8__KPP_COL_7           (_MX53_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK         (_MX53_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC             (_MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT8__I2C1_SDA            (_MX53_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
-#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37            (_MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5                (_MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9                (_MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT9__GPIO5_27            (_MX53_PAD_CSI0_DAT9__GPIO5_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT9__KPP_ROW_7           (_MX53_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI         (_MX53_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR            (_MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT9__I2C1_SCL            (_MX53_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
-#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38            (_MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6                (_MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10              (_MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT10__GPIO5_28           (_MX53_PAD_CSI0_DAT10__GPIO5_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX              (_MX53_PAD_CSI0_DAT10__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO                (_MX53_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC            (_MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4            (_MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39           (_MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7               (_MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11              (_MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT11__GPIO5_29           (_MX53_PAD_CSI0_DAT11__GPIO5_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX              (_MX53_PAD_CSI0_DAT11__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0         (_MX53_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS           (_MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5            (_MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40           (_MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8               (_MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12              (_MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT12__GPIO5_30           (_MX53_PAD_CSI0_DAT12__GPIO5_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX              (_MX53_PAD_CSI0_DAT12__UART4_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0                (_MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6            (_MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41           (_MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9               (_MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13              (_MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT13__GPIO5_31           (_MX53_PAD_CSI0_DAT13__GPIO5_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX              (_MX53_PAD_CSI0_DAT13__UART4_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1                (_MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7            (_MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42           (_MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10              (_MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14              (_MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT14__GPIO6_0            (_MX53_PAD_CSI0_DAT14__GPIO6_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX              (_MX53_PAD_CSI0_DAT14__UART5_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2                (_MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8            (_MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43           (_MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11              (_MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15              (_MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT15__GPIO6_1            (_MX53_PAD_CSI0_DAT15__GPIO6_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX              (_MX53_PAD_CSI0_DAT15__UART5_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3                (_MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9            (_MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44           (_MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12              (_MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16              (_MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT16__GPIO6_2            (_MX53_PAD_CSI0_DAT16__GPIO6_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT16__UART4_RTS          (_MX53_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4                (_MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10           (_MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45           (_MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13              (_MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17              (_MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT17__GPIO6_3            (_MX53_PAD_CSI0_DAT17__GPIO6_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT17__UART4_CTS          (_MX53_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5                (_MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11           (_MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46           (_MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14              (_MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18              (_MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT18__GPIO6_4            (_MX53_PAD_CSI0_DAT18__GPIO6_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT18__UART5_RTS          (_MX53_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6                (_MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12           (_MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47           (_MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15              (_MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19              (_MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT19__GPIO6_5            (_MX53_PAD_CSI0_DAT19__GPIO6_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT19__UART5_CTS          (_MX53_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7                (_MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13           (_MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48           (_MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK             (_MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A25__EMI_WEIM_A_25         (_MX53_PAD_EIM_A25__EMI_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A25__GPIO5_2               (_MX53_PAD_EIM_A25__GPIO5_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A25__ECSPI2_RDY            (_MX53_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A25__IPU_DI1_PIN12         (_MX53_PAD_EIM_A25__IPU_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A25__CSPI_SS1              (_MX53_PAD_EIM_A25__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS         (_MX53_PAD_EIM_A25__IPU_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A25__USBPHY1_BISTOK                (_MX53_PAD_EIM_A25__USBPHY1_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2         (_MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB2__GPIO2_30              (_MX53_PAD_EIM_EB2__GPIO2_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK               (_MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS              (_MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB2__ECSPI1_SS0            (_MX53_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB2__I2C2_SCL              (_MX53_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
-#define MX53_PAD_EIM_D16__EMI_WEIM_D_16         (_MX53_PAD_EIM_D16__EMI_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D16__GPIO3_16              (_MX53_PAD_EIM_D16__GPIO3_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D16__IPU_DI0_PIN5          (_MX53_PAD_EIM_D16__IPU_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK            (_MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D16__ECSPI1_SCLK           (_MX53_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D16__I2C2_SDA              (_MX53_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
-#define MX53_PAD_EIM_D17__EMI_WEIM_D_17         (_MX53_PAD_EIM_D17__EMI_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D17__GPIO3_17              (_MX53_PAD_EIM_D17__GPIO3_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D17__IPU_DI0_PIN6          (_MX53_PAD_EIM_D17__IPU_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN            (_MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D17__ECSPI1_MISO           (_MX53_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D17__I2C3_SCL              (_MX53_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
-#define MX53_PAD_EIM_D18__EMI_WEIM_D_18         (_MX53_PAD_EIM_D18__EMI_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D18__GPIO3_18              (_MX53_PAD_EIM_D18__GPIO3_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D18__IPU_DI0_PIN7          (_MX53_PAD_EIM_D18__IPU_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO            (_MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D18__ECSPI1_MOSI           (_MX53_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D18__I2C3_SDA              (_MX53_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
-#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS         (_MX53_PAD_EIM_D18__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D19__EMI_WEIM_D_19         (_MX53_PAD_EIM_D19__EMI_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D19__GPIO3_19              (_MX53_PAD_EIM_D19__GPIO3_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D19__IPU_DI0_PIN8          (_MX53_PAD_EIM_D19__IPU_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS             (_MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D19__ECSPI1_SS1            (_MX53_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D19__EPIT1_EPITO           (_MX53_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D19__UART1_CTS             (_MX53_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC               (_MX53_PAD_EIM_D19__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D20__EMI_WEIM_D_20         (_MX53_PAD_EIM_D20__EMI_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D20__GPIO3_20              (_MX53_PAD_EIM_D20__GPIO3_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D20__IPU_DI0_PIN16         (_MX53_PAD_EIM_D20__IPU_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS              (_MX53_PAD_EIM_D20__IPU_SER_DISP0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D20__CSPI_SS0              (_MX53_PAD_EIM_D20__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D20__EPIT2_EPITO           (_MX53_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D20__UART1_RTS             (_MX53_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR              (_MX53_PAD_EIM_D20__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D21__EMI_WEIM_D_21         (_MX53_PAD_EIM_D21__EMI_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D21__GPIO3_21              (_MX53_PAD_EIM_D21__GPIO3_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D21__IPU_DI0_PIN17         (_MX53_PAD_EIM_D21__IPU_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK            (_MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D21__CSPI_SCLK             (_MX53_PAD_EIM_D21__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D21__I2C1_SCL              (_MX53_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
-#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC              (_MX53_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D22__EMI_WEIM_D_22         (_MX53_PAD_EIM_D22__EMI_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D22__GPIO3_22              (_MX53_PAD_EIM_D22__GPIO3_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D22__IPU_DI0_PIN1          (_MX53_PAD_EIM_D22__IPU_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN            (_MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D22__CSPI_MISO             (_MX53_PAD_EIM_D22__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR             (_MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D23__EMI_WEIM_D_23         (_MX53_PAD_EIM_D23__EMI_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D23__GPIO3_23              (_MX53_PAD_EIM_D23__GPIO3_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D23__UART3_CTS             (_MX53_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_EIM_D23__UART1_DCD             (_MX53_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS         (_MX53_PAD_EIM_D23__IPU_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D23__IPU_DI1_PIN2          (_MX53_PAD_EIM_D23__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN              (_MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D23__IPU_DI1_PIN14         (_MX53_PAD_EIM_D23__IPU_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3         (_MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB3__GPIO2_31              (_MX53_PAD_EIM_EB3__GPIO2_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB3__UART3_RTS             (_MX53_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_EIM_EB3__UART1_RI              (_MX53_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3          (_MX53_PAD_EIM_EB3__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC                (_MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16         (_MX53_PAD_EIM_EB3__IPU_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D24__EMI_WEIM_D_24         (_MX53_PAD_EIM_D24__EMI_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D24__GPIO3_24              (_MX53_PAD_EIM_D24__GPIO3_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D24__UART3_TXD_MUX         (_MX53_PAD_EIM_D24__UART3_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_EIM_D24__ECSPI1_SS2            (_MX53_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D24__CSPI_SS2              (_MX53_PAD_EIM_D24__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS              (_MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D24__ECSPI2_SS2            (_MX53_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D24__UART1_DTR             (_MX53_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D25__EMI_WEIM_D_25         (_MX53_PAD_EIM_D25__EMI_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D25__GPIO3_25              (_MX53_PAD_EIM_D25__GPIO3_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D25__UART3_RXD_MUX         (_MX53_PAD_EIM_D25__UART3_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_EIM_D25__ECSPI1_SS3            (_MX53_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D25__CSPI_SS3              (_MX53_PAD_EIM_D25__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC               (_MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D25__ECSPI2_SS3            (_MX53_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D25__UART1_DSR             (_MX53_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D26__EMI_WEIM_D_26         (_MX53_PAD_EIM_D26__EMI_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D26__GPIO3_26              (_MX53_PAD_EIM_D26__GPIO3_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D26__UART2_TXD_MUX         (_MX53_PAD_EIM_D26__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_EIM_D26__FIRI_RXD              (_MX53_PAD_EIM_D26__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D26__IPU_CSI0_D_1          (_MX53_PAD_EIM_D26__IPU_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D26__IPU_DI1_PIN11         (_MX53_PAD_EIM_D26__IPU_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D26__IPU_SISG_2            (_MX53_PAD_EIM_D26__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22              (_MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D27__EMI_WEIM_D_27         (_MX53_PAD_EIM_D27__EMI_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D27__GPIO3_27              (_MX53_PAD_EIM_D27__GPIO3_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D27__UART2_RXD_MUX         (_MX53_PAD_EIM_D27__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_EIM_D27__FIRI_TXD              (_MX53_PAD_EIM_D27__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D27__IPU_CSI0_D_0          (_MX53_PAD_EIM_D27__IPU_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D27__IPU_DI1_PIN13         (_MX53_PAD_EIM_D27__IPU_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D27__IPU_SISG_3            (_MX53_PAD_EIM_D27__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23              (_MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D28__EMI_WEIM_D_28         (_MX53_PAD_EIM_D28__EMI_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D28__GPIO3_28              (_MX53_PAD_EIM_D28__GPIO3_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D28__UART2_CTS             (_MX53_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO            (_MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D28__CSPI_MOSI             (_MX53_PAD_EIM_D28__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D28__I2C1_SDA              (_MX53_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
-#define MX53_PAD_EIM_D28__IPU_EXT_TRIG          (_MX53_PAD_EIM_D28__IPU_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D28__IPU_DI0_PIN13         (_MX53_PAD_EIM_D28__IPU_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D29__EMI_WEIM_D_29         (_MX53_PAD_EIM_D29__EMI_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D29__GPIO3_29              (_MX53_PAD_EIM_D29__GPIO3_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D29__UART2_RTS             (_MX53_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS             (_MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D29__CSPI_SS0              (_MX53_PAD_EIM_D29__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D29__IPU_DI1_PIN15         (_MX53_PAD_EIM_D29__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC                (_MX53_PAD_EIM_D29__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D29__IPU_DI0_PIN14         (_MX53_PAD_EIM_D29__IPU_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D30__EMI_WEIM_D_30         (_MX53_PAD_EIM_D30__EMI_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D30__GPIO3_30              (_MX53_PAD_EIM_D30__GPIO3_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D30__UART3_CTS             (_MX53_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_EIM_D30__IPU_CSI0_D_3          (_MX53_PAD_EIM_D30__IPU_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D30__IPU_DI0_PIN11         (_MX53_PAD_EIM_D30__IPU_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21              (_MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC               (_MX53_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC               (_MX53_PAD_EIM_D30__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D31__EMI_WEIM_D_31         (_MX53_PAD_EIM_D31__EMI_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D31__GPIO3_31              (_MX53_PAD_EIM_D31__GPIO3_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D31__UART3_RTS             (_MX53_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_EIM_D31__IPU_CSI0_D_2          (_MX53_PAD_EIM_D31__IPU_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D31__IPU_DI0_PIN12         (_MX53_PAD_EIM_D31__IPU_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20              (_MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR              (_MX53_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR              (_MX53_PAD_EIM_D31__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A24__EMI_WEIM_A_24         (_MX53_PAD_EIM_A24__EMI_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A24__GPIO5_4               (_MX53_PAD_EIM_A24__GPIO5_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19              (_MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A24__IPU_CSI1_D_19         (_MX53_PAD_EIM_A24__IPU_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A24__IPU_SISG_2            (_MX53_PAD_EIM_A24__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A24__USBPHY2_BVALID                (_MX53_PAD_EIM_A24__USBPHY2_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A23__EMI_WEIM_A_23         (_MX53_PAD_EIM_A23__EMI_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A23__GPIO6_6               (_MX53_PAD_EIM_A23__GPIO6_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18              (_MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A23__IPU_CSI1_D_18         (_MX53_PAD_EIM_A23__IPU_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A23__IPU_SISG_3            (_MX53_PAD_EIM_A23__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION            (_MX53_PAD_EIM_A23__USBPHY2_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A22__EMI_WEIM_A_22         (_MX53_PAD_EIM_A22__EMI_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A22__GPIO2_16              (_MX53_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17              (_MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A22__IPU_CSI1_D_17         (_MX53_PAD_EIM_A22__IPU_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7         (_MX53_PAD_EIM_A22__SRC_BT_CFG1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A21__EMI_WEIM_A_21         (_MX53_PAD_EIM_A21__EMI_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A21__GPIO2_17              (_MX53_PAD_EIM_A21__GPIO2_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16              (_MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A21__IPU_CSI1_D_16         (_MX53_PAD_EIM_A21__IPU_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6         (_MX53_PAD_EIM_A21__SRC_BT_CFG1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A20__EMI_WEIM_A_20         (_MX53_PAD_EIM_A20__EMI_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A20__GPIO2_18              (_MX53_PAD_EIM_A20__GPIO2_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15              (_MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A20__IPU_CSI1_D_15         (_MX53_PAD_EIM_A20__IPU_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5         (_MX53_PAD_EIM_A20__SRC_BT_CFG1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A19__EMI_WEIM_A_19         (_MX53_PAD_EIM_A19__EMI_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A19__GPIO2_19              (_MX53_PAD_EIM_A19__GPIO2_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14              (_MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A19__IPU_CSI1_D_14         (_MX53_PAD_EIM_A19__IPU_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4         (_MX53_PAD_EIM_A19__SRC_BT_CFG1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A18__EMI_WEIM_A_18         (_MX53_PAD_EIM_A18__EMI_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A18__GPIO2_20              (_MX53_PAD_EIM_A18__GPIO2_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13              (_MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A18__IPU_CSI1_D_13         (_MX53_PAD_EIM_A18__IPU_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3         (_MX53_PAD_EIM_A18__SRC_BT_CFG1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A17__EMI_WEIM_A_17         (_MX53_PAD_EIM_A17__EMI_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A17__GPIO2_21              (_MX53_PAD_EIM_A17__GPIO2_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12              (_MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A17__IPU_CSI1_D_12         (_MX53_PAD_EIM_A17__IPU_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2         (_MX53_PAD_EIM_A17__SRC_BT_CFG1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A16__EMI_WEIM_A_16         (_MX53_PAD_EIM_A16__EMI_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A16__GPIO2_22              (_MX53_PAD_EIM_A16__GPIO2_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK              (_MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK               (_MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1         (_MX53_PAD_EIM_A16__SRC_BT_CFG1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0         (_MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_CS0__GPIO2_23              (_MX53_PAD_EIM_CS0__GPIO2_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_CS0__ECSPI2_SCLK           (_MX53_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5          (_MX53_PAD_EIM_CS0__IPU_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1         (_MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_CS1__GPIO2_24              (_MX53_PAD_EIM_CS1__GPIO2_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_CS1__ECSPI2_MOSI           (_MX53_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6          (_MX53_PAD_EIM_CS1__IPU_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_OE__EMI_WEIM_OE            (_MX53_PAD_EIM_OE__EMI_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_OE__GPIO2_25               (_MX53_PAD_EIM_OE__GPIO2_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_OE__ECSPI2_MISO            (_MX53_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_OE__IPU_DI1_PIN7           (_MX53_PAD_EIM_OE__IPU_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_OE__USBPHY2_IDDIG          (_MX53_PAD_EIM_OE__USBPHY2_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_RW__EMI_WEIM_RW            (_MX53_PAD_EIM_RW__EMI_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_RW__GPIO2_26               (_MX53_PAD_EIM_RW__GPIO2_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_RW__ECSPI2_SS0             (_MX53_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_RW__IPU_DI1_PIN8           (_MX53_PAD_EIM_RW__IPU_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT         (_MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA          (_MX53_PAD_EIM_LBA__EMI_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_LBA__GPIO2_27              (_MX53_PAD_EIM_LBA__GPIO2_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_LBA__ECSPI2_SS1            (_MX53_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17         (_MX53_PAD_EIM_LBA__IPU_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0         (_MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0         (_MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB0__GPIO2_28              (_MX53_PAD_EIM_EB0__GPIO2_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11              (_MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11         (_MX53_PAD_EIM_EB0__IPU_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY          (_MX53_PAD_EIM_EB0__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7         (_MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1         (_MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB1__GPIO2_29              (_MX53_PAD_EIM_EB1__GPIO2_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10              (_MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10         (_MX53_PAD_EIM_EB1__IPU_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6         (_MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0            (_MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA0__GPIO3_0               (_MX53_PAD_EIM_DA0__GPIO3_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9               (_MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9          (_MX53_PAD_EIM_DA0__IPU_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5         (_MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1            (_MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA1__GPIO3_1               (_MX53_PAD_EIM_DA1__GPIO3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8               (_MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8          (_MX53_PAD_EIM_DA1__IPU_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4         (_MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2            (_MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA2__GPIO3_2               (_MX53_PAD_EIM_DA2__GPIO3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7               (_MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7          (_MX53_PAD_EIM_DA2__IPU_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3         (_MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3            (_MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA3__GPIO3_3               (_MX53_PAD_EIM_DA3__GPIO3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6               (_MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6          (_MX53_PAD_EIM_DA3__IPU_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2         (_MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4            (_MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA4__GPIO3_4               (_MX53_PAD_EIM_DA4__GPIO3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5               (_MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5          (_MX53_PAD_EIM_DA4__IPU_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7         (_MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5            (_MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA5__GPIO3_5               (_MX53_PAD_EIM_DA5__GPIO3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4               (_MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4          (_MX53_PAD_EIM_DA5__IPU_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6         (_MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6            (_MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA6__GPIO3_6               (_MX53_PAD_EIM_DA6__GPIO3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3               (_MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3          (_MX53_PAD_EIM_DA6__IPU_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5         (_MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7            (_MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA7__GPIO3_7               (_MX53_PAD_EIM_DA7__GPIO3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2               (_MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2          (_MX53_PAD_EIM_DA7__IPU_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4         (_MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8            (_MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA8__GPIO3_8               (_MX53_PAD_EIM_DA8__GPIO3_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1               (_MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1          (_MX53_PAD_EIM_DA8__IPU_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3         (_MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9            (_MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA9__GPIO3_9               (_MX53_PAD_EIM_DA9__GPIO3_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0               (_MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0          (_MX53_PAD_EIM_DA9__IPU_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2         (_MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10          (_MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA10__GPIO3_10             (_MX53_PAD_EIM_DA10__GPIO3_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15                (_MX53_PAD_EIM_DA10__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN             (_MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1                (_MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11          (_MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA11__GPIO3_11             (_MX53_PAD_EIM_DA11__GPIO3_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2         (_MX53_PAD_EIM_DA11__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC               (_MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12          (_MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA12__GPIO3_12             (_MX53_PAD_EIM_DA12__GPIO3_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3         (_MX53_PAD_EIM_DA12__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC               (_MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13          (_MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA13__GPIO3_13             (_MX53_PAD_EIM_DA13__GPIO3_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS                (_MX53_PAD_EIM_DA13__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK              (_MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14          (_MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA14__GPIO3_14             (_MX53_PAD_EIM_DA14__GPIO3_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS                (_MX53_PAD_EIM_DA14__IPU_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK              (_MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15          (_MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA15__GPIO3_15             (_MX53_PAD_EIM_DA15__GPIO3_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1         (_MX53_PAD_EIM_DA15__IPU_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4         (_MX53_PAD_EIM_DA15__IPU_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B             (_MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_WE_B__GPIO6_12           (_MX53_PAD_NANDF_WE_B__GPIO6_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B             (_MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_RE_B__GPIO6_13           (_MX53_PAD_NANDF_RE_B__GPIO6_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT                (_MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_WAIT__GPIO5_0              (_MX53_PAD_EIM_WAIT__GPIO5_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B             (_MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS1_TX3_P__GPIO6_22          (_MX53_PAD_LVDS1_TX3_P__GPIO6_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3             (_MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS1_TX2_P__GPIO6_24          (_MX53_PAD_LVDS1_TX2_P__GPIO6_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2             (_MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS1_CLK_P__GPIO6_26          (_MX53_PAD_LVDS1_CLK_P__GPIO6_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK             (_MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS1_TX1_P__GPIO6_28          (_MX53_PAD_LVDS1_TX1_P__GPIO6_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1             (_MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS1_TX0_P__GPIO6_30          (_MX53_PAD_LVDS1_TX0_P__GPIO6_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0             (_MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS0_TX3_P__GPIO7_22          (_MX53_PAD_LVDS0_TX3_P__GPIO7_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3             (_MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS0_CLK_P__GPIO7_24          (_MX53_PAD_LVDS0_CLK_P__GPIO7_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK             (_MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS0_TX2_P__GPIO7_26          (_MX53_PAD_LVDS0_TX2_P__GPIO7_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2             (_MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS0_TX1_P__GPIO7_28          (_MX53_PAD_LVDS0_TX1_P__GPIO7_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1             (_MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS0_TX0_P__GPIO7_30          (_MX53_PAD_LVDS0_TX0_P__GPIO7_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0             (_MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_10__GPIO4_0               (_MX53_PAD_GPIO_10__GPIO4_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_10__OSC32k_32K_OUT                (_MX53_PAD_GPIO_10__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_11__GPIO4_1               (_MX53_PAD_GPIO_11__GPIO4_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_12__GPIO4_2               (_MX53_PAD_GPIO_12__GPIO4_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_13__GPIO4_3               (_MX53_PAD_GPIO_13__GPIO4_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_14__GPIO4_4               (_MX53_PAD_GPIO_14__GPIO4_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE               (_MX53_PAD_NANDF_CLE__EMI_NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CLE__GPIO6_7             (_MX53_PAD_NANDF_CLE__GPIO6_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0           (_MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE               (_MX53_PAD_NANDF_ALE__EMI_NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_ALE__GPIO6_8             (_MX53_PAD_NANDF_ALE__GPIO6_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1           (_MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B             (_MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_WP_B__GPIO6_9            (_MX53_PAD_NANDF_WP_B__GPIO6_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2          (_MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0              (_MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_RB0__GPIO6_10            (_MX53_PAD_NANDF_RB0__GPIO6_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3           (_MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0              (_MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS0__GPIO6_11            (_MX53_PAD_NANDF_CS0__GPIO6_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4           (_MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1              (_MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS1__GPIO6_14            (_MX53_PAD_NANDF_CS1__GPIO6_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS1__MLB_MLBCLK          (_MX53_PAD_NANDF_CS1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5           (_MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2              (_MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS2__GPIO6_15            (_MX53_PAD_NANDF_CS2__GPIO6_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS2__IPU_SISG_0          (_MX53_PAD_NANDF_CS2__IPU_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS2__ESAI1_TX0           (_MX53_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE                (_MX53_PAD_NANDF_CS2__EMI_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK               (_MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS2__MLB_MLBSIG          (_MX53_PAD_NANDF_CS2__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6           (_MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3              (_MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS3__GPIO6_16            (_MX53_PAD_NANDF_CS3__GPIO6_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS3__IPU_SISG_1          (_MX53_PAD_NANDF_CS3__IPU_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS3__ESAI1_TX1           (_MX53_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26               (_MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS3__MLB_MLBDAT          (_MX53_PAD_NANDF_CS3__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7           (_MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_MDIO__FEC_MDIO             (_MX53_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_MDIO__GPIO1_22             (_MX53_PAD_FEC_MDIO__GPIO1_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_MDIO__ESAI1_SCKR           (_MX53_PAD_FEC_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_MDIO__FEC_COL              (_MX53_PAD_FEC_MDIO__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2               (_MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3              (_MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49             (_MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK                (_MX53_PAD_FEC_REF_CLK__FEC_TX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_REF_CLK__GPIO1_23          (_MX53_PAD_FEC_REF_CLK__GPIO1_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR         (_MX53_PAD_FEC_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4           (_MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50          (_MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RX_ER__FEC_RX_ER           (_MX53_PAD_FEC_RX_ER__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RX_ER__GPIO1_24            (_MX53_PAD_FEC_RX_ER__GPIO1_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR          (_MX53_PAD_FEC_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK          (_MX53_PAD_FEC_RX_ER__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3              (_MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV          (_MX53_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_CRS_DV__GPIO1_25           (_MX53_PAD_FEC_CRS_DV__GPIO1_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT         (_MX53_PAD_FEC_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RXD1__FEC_RDATA_1          (_MX53_PAD_FEC_RXD1__FEC_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RXD1__GPIO1_26             (_MX53_PAD_FEC_RXD1__GPIO1_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RXD1__ESAI1_FST            (_MX53_PAD_FEC_RXD1__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RXD1__MLB_MLBSIG           (_MX53_PAD_FEC_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1               (_MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RXD0__FEC_RDATA_0          (_MX53_PAD_FEC_RXD0__FEC_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RXD0__GPIO1_27             (_MX53_PAD_FEC_RXD0__GPIO1_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RXD0__ESAI1_HCKT           (_MX53_PAD_FEC_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT               (_MX53_PAD_FEC_RXD0__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_TX_EN__FEC_TX_EN           (_MX53_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_TX_EN__GPIO1_28            (_MX53_PAD_FEC_TX_EN__GPIO1_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2               (_MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_TXD1__FEC_TDATA_1          (_MX53_PAD_FEC_TXD1__FEC_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_TXD1__GPIO1_29             (_MX53_PAD_FEC_TXD1__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3                (_MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_TXD1__MLB_MLBCLK           (_MX53_PAD_FEC_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK          (_MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_TXD0__FEC_TDATA_0          (_MX53_PAD_FEC_TXD0__FEC_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_TXD0__GPIO1_30             (_MX53_PAD_FEC_TXD0__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1                (_MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0            (_MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_MDC__FEC_MDC               (_MX53_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_MDC__GPIO1_31              (_MX53_PAD_FEC_MDC__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0         (_MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_MDC__MLB_MLBDAT            (_MX53_PAD_FEC_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG                (_MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1             (_MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DIOW__PATA_DIOW           (_MX53_PAD_PATA_DIOW__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DIOW__GPIO6_17            (_MX53_PAD_PATA_DIOW__GPIO6_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX               (_MX53_PAD_PATA_DIOW__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2           (_MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DMACK__PATA_DMACK         (_MX53_PAD_PATA_DMACK__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DMACK__GPIO6_18           (_MX53_PAD_PATA_DMACK__GPIO6_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX              (_MX53_PAD_PATA_DMACK__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3          (_MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DMARQ__PATA_DMARQ         (_MX53_PAD_PATA_DMARQ__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DMARQ__GPIO7_0            (_MX53_PAD_PATA_DMARQ__GPIO7_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX              (_MX53_PAD_PATA_DMARQ__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0              (_MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4          (_MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN         (_MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1                (_MX53_PAD_PATA_BUFFER_EN__GPIO7_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX          (_MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1          (_MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5              (_MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_INTRQ__PATA_INTRQ         (_MX53_PAD_PATA_INTRQ__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_INTRQ__GPIO7_2            (_MX53_PAD_PATA_INTRQ__GPIO7_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_INTRQ__UART2_CTS          (_MX53_PAD_PATA_INTRQ__UART2_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN         (_MX53_PAD_PATA_INTRQ__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2              (_MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6          (_MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DIOR__PATA_DIOR           (_MX53_PAD_PATA_DIOR__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DIOR__GPIO7_3             (_MX53_PAD_PATA_DIOR__GPIO7_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DIOR__UART2_RTS           (_MX53_PAD_PATA_DIOR__UART2_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_PATA_DIOR__CAN1_RXCAN          (_MX53_PAD_PATA_DIOR__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7           (_MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B                (_MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_RESET_B__GPIO7_4          (_MX53_PAD_PATA_RESET_B__GPIO7_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD               (_MX53_PAD_PATA_RESET_B__ESDHC3_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_RESET_B__UART1_CTS                (_MX53_PAD_PATA_RESET_B__UART1_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN               (_MX53_PAD_PATA_RESET_B__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0                (_MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_IORDY__PATA_IORDY         (_MX53_PAD_PATA_IORDY__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_IORDY__GPIO7_5            (_MX53_PAD_PATA_IORDY__GPIO7_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_IORDY__ESDHC3_CLK         (_MX53_PAD_PATA_IORDY__ESDHC3_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_IORDY__UART1_RTS          (_MX53_PAD_PATA_IORDY__UART1_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_PATA_IORDY__CAN2_RXCAN         (_MX53_PAD_PATA_IORDY__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1          (_MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DA_0__PATA_DA_0           (_MX53_PAD_PATA_DA_0__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DA_0__GPIO7_6             (_MX53_PAD_PATA_DA_0__GPIO7_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DA_0__ESDHC3_RST          (_MX53_PAD_PATA_DA_0__ESDHC3_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DA_0__OWIRE_LINE          (_MX53_PAD_PATA_DA_0__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2           (_MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DA_1__PATA_DA_1           (_MX53_PAD_PATA_DA_1__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DA_1__GPIO7_7             (_MX53_PAD_PATA_DA_1__GPIO7_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DA_1__ESDHC4_CMD          (_MX53_PAD_PATA_DA_1__ESDHC4_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DA_1__UART3_CTS           (_MX53_PAD_PATA_DA_1__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3           (_MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DA_2__PATA_DA_2           (_MX53_PAD_PATA_DA_2__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DA_2__GPIO7_8             (_MX53_PAD_PATA_DA_2__GPIO7_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DA_2__ESDHC4_CLK          (_MX53_PAD_PATA_DA_2__ESDHC4_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DA_2__UART3_RTS           (_MX53_PAD_PATA_DA_2__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4           (_MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_CS_0__PATA_CS_0           (_MX53_PAD_PATA_CS_0__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_CS_0__GPIO7_9             (_MX53_PAD_PATA_CS_0__GPIO7_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX               (_MX53_PAD_PATA_CS_0__UART3_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5           (_MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_CS_1__PATA_CS_1           (_MX53_PAD_PATA_CS_1__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_CS_1__GPIO7_10            (_MX53_PAD_PATA_CS_1__GPIO7_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX               (_MX53_PAD_PATA_CS_1__UART3_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6           (_MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA0__PATA_DATA_0                (_MX53_PAD_PATA_DATA0__PATA_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA0__GPIO2_0            (_MX53_PAD_PATA_DATA0__GPIO2_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0              (_MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4                (_MX53_PAD_PATA_DATA0__ESDHC3_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0              (_MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0             (_MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7          (_MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA1__PATA_DATA_1                (_MX53_PAD_PATA_DATA1__PATA_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA1__GPIO2_1            (_MX53_PAD_PATA_DATA1__GPIO2_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1              (_MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5                (_MX53_PAD_PATA_DATA1__ESDHC3_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1              (_MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1             (_MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA2__PATA_DATA_2                (_MX53_PAD_PATA_DATA2__PATA_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA2__GPIO2_2            (_MX53_PAD_PATA_DATA2__GPIO2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2              (_MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6                (_MX53_PAD_PATA_DATA2__ESDHC3_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2              (_MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2             (_MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA3__PATA_DATA_3                (_MX53_PAD_PATA_DATA3__PATA_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA3__GPIO2_3            (_MX53_PAD_PATA_DATA3__GPIO2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3              (_MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7                (_MX53_PAD_PATA_DATA3__ESDHC3_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3              (_MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3             (_MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA4__PATA_DATA_4                (_MX53_PAD_PATA_DATA4__PATA_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA4__GPIO2_4            (_MX53_PAD_PATA_DATA4__GPIO2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4              (_MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4                (_MX53_PAD_PATA_DATA4__ESDHC4_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4              (_MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4             (_MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA5__PATA_DATA_5                (_MX53_PAD_PATA_DATA5__PATA_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA5__GPIO2_5            (_MX53_PAD_PATA_DATA5__GPIO2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5              (_MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5                (_MX53_PAD_PATA_DATA5__ESDHC4_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5              (_MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5             (_MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA6__PATA_DATA_6                (_MX53_PAD_PATA_DATA6__PATA_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA6__GPIO2_6            (_MX53_PAD_PATA_DATA6__GPIO2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6              (_MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6                (_MX53_PAD_PATA_DATA6__ESDHC4_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6              (_MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6             (_MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA7__PATA_DATA_7                (_MX53_PAD_PATA_DATA7__PATA_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA7__GPIO2_7            (_MX53_PAD_PATA_DATA7__GPIO2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7              (_MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7                (_MX53_PAD_PATA_DATA7__ESDHC4_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7              (_MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7             (_MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA8__PATA_DATA_8                (_MX53_PAD_PATA_DATA8__PATA_DATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA8__GPIO2_8            (_MX53_PAD_PATA_DATA8__GPIO2_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4                (_MX53_PAD_PATA_DATA8__ESDHC1_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8              (_MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0                (_MX53_PAD_PATA_DATA8__ESDHC3_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8              (_MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8             (_MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA9__PATA_DATA_9                (_MX53_PAD_PATA_DATA9__PATA_DATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA9__GPIO2_9            (_MX53_PAD_PATA_DATA9__GPIO2_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5                (_MX53_PAD_PATA_DATA9__ESDHC1_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9              (_MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1                (_MX53_PAD_PATA_DATA9__ESDHC3_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9              (_MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9             (_MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA10__PATA_DATA_10              (_MX53_PAD_PATA_DATA10__PATA_DATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA10__GPIO2_10          (_MX53_PAD_PATA_DATA10__GPIO2_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6               (_MX53_PAD_PATA_DATA10__ESDHC1_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10            (_MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2               (_MX53_PAD_PATA_DATA10__ESDHC3_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10            (_MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10           (_MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA11__PATA_DATA_11              (_MX53_PAD_PATA_DATA11__PATA_DATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA11__GPIO2_11          (_MX53_PAD_PATA_DATA11__GPIO2_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7               (_MX53_PAD_PATA_DATA11__ESDHC1_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11            (_MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3               (_MX53_PAD_PATA_DATA11__ESDHC3_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11            (_MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11           (_MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA12__PATA_DATA_12              (_MX53_PAD_PATA_DATA12__PATA_DATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA12__GPIO2_12          (_MX53_PAD_PATA_DATA12__GPIO2_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4               (_MX53_PAD_PATA_DATA12__ESDHC2_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12            (_MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0               (_MX53_PAD_PATA_DATA12__ESDHC4_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12            (_MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12           (_MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA13__PATA_DATA_13              (_MX53_PAD_PATA_DATA13__PATA_DATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA13__GPIO2_13          (_MX53_PAD_PATA_DATA13__GPIO2_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5               (_MX53_PAD_PATA_DATA13__ESDHC2_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13            (_MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1               (_MX53_PAD_PATA_DATA13__ESDHC4_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13            (_MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13           (_MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA14__PATA_DATA_14              (_MX53_PAD_PATA_DATA14__PATA_DATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA14__GPIO2_14          (_MX53_PAD_PATA_DATA14__GPIO2_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6               (_MX53_PAD_PATA_DATA14__ESDHC2_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14            (_MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2               (_MX53_PAD_PATA_DATA14__ESDHC4_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14            (_MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14           (_MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA15__PATA_DATA_15              (_MX53_PAD_PATA_DATA15__PATA_DATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA15__GPIO2_15          (_MX53_PAD_PATA_DATA15__GPIO2_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7               (_MX53_PAD_PATA_DATA15__ESDHC2_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15            (_MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3               (_MX53_PAD_PATA_DATA15__ESDHC4_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15            (_MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15           (_MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0         (_MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_SD1_DATA0__GPIO1_16            (_MX53_PAD_SD1_DATA0__GPIO1_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA0__GPT_CAPIN1          (_MX53_PAD_SD1_DATA0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA0__CSPI_MISO           (_MX53_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP                (_MX53_PAD_SD1_DATA0__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1         (_MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_SD1_DATA1__GPIO1_17            (_MX53_PAD_SD1_DATA1__GPIO1_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA1__GPT_CAPIN2          (_MX53_PAD_SD1_DATA1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA1__CSPI_SS0            (_MX53_PAD_SD1_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP                (_MX53_PAD_SD1_DATA1__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_CMD__ESDHC1_CMD            (_MX53_PAD_SD1_CMD__ESDHC1_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_SD1_CMD__GPIO1_18              (_MX53_PAD_SD1_CMD__GPIO1_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_CMD__GPT_CMPOUT1           (_MX53_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_CMD__CSPI_MOSI             (_MX53_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP          (_MX53_PAD_SD1_CMD__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2         (_MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_SD1_DATA2__GPIO1_19            (_MX53_PAD_SD1_DATA2__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2         (_MX53_PAD_SD1_DATA2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA2__PWM2_PWMO           (_MX53_PAD_SD1_DATA2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B                (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA2__CSPI_SS1            (_MX53_PAD_SD1_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB                (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP                (_MX53_PAD_SD1_DATA2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_CLK__ESDHC1_CLK            (_MX53_PAD_SD1_CLK__ESDHC1_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_SD1_CLK__GPIO1_20              (_MX53_PAD_SD1_CLK__GPIO1_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT                (_MX53_PAD_SD1_CLK__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_CLK__GPT_CLKIN             (_MX53_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_CLK__CSPI_SCLK             (_MX53_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0                (_MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3         (_MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_SD1_DATA3__GPIO1_21            (_MX53_PAD_SD1_DATA3__GPIO1_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3         (_MX53_PAD_SD1_DATA3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA3__PWM1_PWMO           (_MX53_PAD_SD1_DATA3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B                (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA3__CSPI_SS2            (_MX53_PAD_SD1_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB                (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1              (_MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_CLK__ESDHC2_CLK            (_MX53_PAD_SD2_CLK__ESDHC2_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_SD2_CLK__GPIO1_10              (_MX53_PAD_SD2_CLK__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_CLK__KPP_COL_5             (_MX53_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS              (_MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_CLK__CSPI_SCLK             (_MX53_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_CLK__SCC_RANDOM_V          (_MX53_PAD_SD2_CLK__SCC_RANDOM_V | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_CMD__ESDHC2_CMD            (_MX53_PAD_SD2_CMD__ESDHC2_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_SD2_CMD__GPIO1_11              (_MX53_PAD_SD2_CMD__GPIO1_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_CMD__KPP_ROW_5             (_MX53_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC               (_MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_CMD__CSPI_MOSI             (_MX53_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_CMD__SCC_RANDOM            (_MX53_PAD_SD2_CMD__SCC_RANDOM | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3         (_MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_SD2_DATA3__GPIO1_12            (_MX53_PAD_SD2_DATA3__GPIO1_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA3__KPP_COL_6           (_MX53_PAD_SD2_DATA3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC             (_MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA3__CSPI_SS2            (_MX53_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA3__SJC_DONE            (_MX53_PAD_SD2_DATA3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2         (_MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_SD2_DATA2__GPIO1_13            (_MX53_PAD_SD2_DATA2__GPIO1_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA2__KPP_ROW_6           (_MX53_PAD_SD2_DATA2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD             (_MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA2__CSPI_SS1            (_MX53_PAD_SD2_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA2__SJC_FAIL            (_MX53_PAD_SD2_DATA2__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1         (_MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_SD2_DATA1__GPIO1_14            (_MX53_PAD_SD2_DATA1__GPIO1_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA1__KPP_COL_7           (_MX53_PAD_SD2_DATA1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS            (_MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA1__CSPI_SS0            (_MX53_PAD_SD2_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO                (_MX53_PAD_SD2_DATA1__RTIC_SEC_VIO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0         (_MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_SD2_DATA0__GPIO1_15            (_MX53_PAD_SD2_DATA0__GPIO1_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA0__KPP_ROW_7           (_MX53_PAD_SD2_DATA0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD             (_MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA0__CSPI_MISO           (_MX53_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT               (_MX53_PAD_SD2_DATA0__RTIC_DONE_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_0__CCM_CLKO               (_MX53_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_0__GPIO1_0                (_MX53_PAD_GPIO_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_0__KPP_COL_5              (_MX53_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK               (_MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_0__EPIT1_EPITO            (_MX53_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB         (_MX53_PAD_GPIO_0__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR               (_MX53_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_0__CSU_TD         (_MX53_PAD_GPIO_0__CSU_TD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_1__ESAI1_SCKR             (_MX53_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_1__GPIO1_1                (_MX53_PAD_GPIO_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_1__KPP_ROW_5              (_MX53_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK               (_MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_1__PWM2_PWMO              (_MX53_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_1__WDOG2_WDOG_B           (_MX53_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_1__ESDHC1_CD              (_MX53_PAD_GPIO_1__ESDHC1_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_1__SRC_TESTER_ACK         (_MX53_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_9__ESAI1_FSR              (_MX53_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_9__GPIO1_9                (_MX53_PAD_GPIO_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_9__KPP_COL_6              (_MX53_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_9__CCM_REF_EN_B           (_MX53_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_9__PWM1_PWMO              (_MX53_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_9__WDOG1_WDOG_B           (_MX53_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_9__ESDHC1_WP              (_MX53_PAD_GPIO_9__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_9__SCC_FAIL_STATE         (_MX53_PAD_GPIO_9__SCC_FAIL_STATE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_3__ESAI1_HCKR             (_MX53_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_3__GPIO1_3                (_MX53_PAD_GPIO_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_3__I2C3_SCL               (_MX53_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
-#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN         (_MX53_PAD_GPIO_3__DPLLIP1_TOG_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_3__CCM_CLKO2              (_MX53_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0             (_MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC                (_MX53_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_3__MLB_MLBCLK             (_MX53_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_6__ESAI1_SCKT             (_MX53_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_6__GPIO1_6                (_MX53_PAD_GPIO_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_6__I2C3_SDA               (_MX53_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
-#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0          (_MX53_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB                (_MX53_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1             (_MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_6__ESDHC2_LCTL            (_MX53_PAD_GPIO_6__ESDHC2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_6__MLB_MLBSIG             (_MX53_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_2__ESAI1_FST              (_MX53_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_2__GPIO1_2                (_MX53_PAD_GPIO_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_2__KPP_ROW_6              (_MX53_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1          (_MX53_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0            (_MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2             (_MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_2__ESDHC2_WP              (_MX53_PAD_GPIO_2__ESDHC2_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_2__MLB_MLBDAT             (_MX53_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_4__ESAI1_HCKT             (_MX53_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_4__GPIO1_4                (_MX53_PAD_GPIO_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_4__KPP_COL_7              (_MX53_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2          (_MX53_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1            (_MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3             (_MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_4__ESDHC2_CD              (_MX53_PAD_GPIO_4__ESDHC2_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_4__SCC_SEC_STATE          (_MX53_PAD_GPIO_4__SCC_SEC_STATE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3          (_MX53_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_5__GPIO1_5                (_MX53_PAD_GPIO_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_5__KPP_ROW_7              (_MX53_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_5__CCM_CLKO               (_MX53_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2            (_MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4             (_MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_5__I2C3_SCL               (_MX53_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
-#define MX53_PAD_GPIO_5__CCM_PLL1_BYP           (_MX53_PAD_GPIO_5__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1          (_MX53_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_7__GPIO1_7                (_MX53_PAD_GPIO_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_7__EPIT1_EPITO            (_MX53_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_7__CAN1_TXCAN             (_MX53_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_7__UART2_TXD_MUX          (_MX53_PAD_GPIO_7__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_GPIO_7__FIRI_RXD               (_MX53_PAD_GPIO_7__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_7__SPDIF_PLOCK            (_MX53_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_7__CCM_PLL2_BYP           (_MX53_PAD_GPIO_7__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0          (_MX53_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_8__GPIO1_8                (_MX53_PAD_GPIO_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_8__EPIT2_EPITO            (_MX53_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_8__CAN1_RXCAN             (_MX53_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_8__UART2_RXD_MUX          (_MX53_PAD_GPIO_8__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
-#define MX53_PAD_GPIO_8__FIRI_TXD               (_MX53_PAD_GPIO_8__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_8__SPDIF_SRCLK            (_MX53_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_8__CCM_PLL3_BYP           (_MX53_PAD_GPIO_8__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2         (_MX53_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_16__GPIO7_11              (_MX53_PAD_GPIO_16__GPIO7_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT              (_MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1          (_MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_16__SPDIF_IN1             (_MX53_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_16__I2C3_SDA              (_MX53_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
-#define MX53_PAD_GPIO_16__SJC_DE_B              (_MX53_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_17__ESAI1_TX0             (_MX53_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_17__GPIO7_12              (_MX53_PAD_GPIO_17__GPIO7_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0              (_MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_17__GPC_PMIC_RDY          (_MX53_PAD_GPIO_17__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG           (_MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_17__SPDIF_OUT1            (_MX53_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_17__IPU_SNOOP2            (_MX53_PAD_GPIO_17__IPU_SNOOP2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_17__SJC_JTAG_ACT          (_MX53_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_18__ESAI1_TX1             (_MX53_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_18__GPIO7_13              (_MX53_PAD_GPIO_18__GPIO7_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1              (_MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_18__OWIRE_LINE            (_MX53_PAD_GPIO_18__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG                (_MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK              (_MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_18__ESDHC1_LCTL           (_MX53_PAD_GPIO_18__ESDHC1_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST                (_MX53_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_19__KPP_COL_5                     IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__GPIO4_5                       IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__CCM_CLKO                      IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__SPDIF_OUT1                    IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2          IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__ECSPI1_RDY                    IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__FEC_TDATA_3                   IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__SRC_INT_BOOT                  IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__KPP_COL_0                    IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__GPIO4_6                      IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC              IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__UART4_TXD_MUX                IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__ECSPI1_SCLK                  IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__FEC_RDATA_3                  IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST               IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__KPP_ROW_0                    IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__GPIO4_7                      IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD              IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX                IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI                  IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__FEC_TX_ER                    IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__KPP_COL_1                    IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__GPIO4_8                      IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS             IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__UART5_TXD_MUX                IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__ECSPI1_MISO                  IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__FEC_RX_CLK                   IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY              IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__KPP_ROW_1                    IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__GPIO4_9                      IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD              IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX                IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__ECSPI1_SS0                   IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__FEC_COL                      IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID              IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__KPP_COL_2                    IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__GPIO4_10                     IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__CAN1_TXCAN                   IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__FEC_MDIO                     IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__ECSPI1_SS1                   IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__FEC_RDATA_2                  IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE             IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__KPP_ROW_2                    IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__GPIO4_11                     IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__CAN1_RXCAN                   IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__FEC_MDC                      IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__ECSPI1_SS2                   IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__FEC_TDATA_2                  IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR              IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__KPP_COL_3                    IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__GPIO4_12                     IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__USBOH3_H2_DP                 IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__SPDIF_IN1                    IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__I2C2_SCL                     IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__ECSPI1_SS3                   IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__FEC_CRS                      IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK             IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__KPP_ROW_3                    IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__GPIO4_13                     IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM                 IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK             IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__I2C2_SDA                     IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT               IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP                 IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0          IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__KPP_COL_4                    IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__GPIO4_14                     IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__CAN2_TXCAN                   IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__IPU_SISG_4                   IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__UART5_RTS                    IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC             IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1          IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__KPP_ROW_4                    IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__GPIO4_15                     IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__CAN2_RXCAN                   IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__IPU_SISG_5                   IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__UART5_CTS                    IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR            IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID            IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK         IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__GPIO4_16                 IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR         IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0  IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0          IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID           IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__GPIO4_17                    IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC             IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1     IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1             IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID              IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2                 IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__GPIO4_18                     IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD              IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2      IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2              IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION           IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                 IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__GPIO4_19                     IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS             IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3      IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3              IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG                IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4                 IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__GPIO4_20                     IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD              IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__ESDHC1_WP                    IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD             IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4              IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT       IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__GPIO4_21                   IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__CSPI_SCLK                  IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0        IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN        IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5            IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY            IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__GPIO4_22                   IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__CSPI_MOSI                  IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1        IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL       \
+                                                        IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6            IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID            IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__GPIO4_23                   IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__CSPI_MISO                  IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2        IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE            IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7            IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE           IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__GPIO4_24                   IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__CSPI_SS0                   IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3        IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR       IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8            IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR            IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__GPIO4_25                   IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__CSPI_SS1                   IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4        IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB         IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9            IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK           IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__GPIO4_26                   IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__CSPI_SS2                   IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5        IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS   IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10           IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0        IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__GPIO4_27                   IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__CSPI_SS3                   IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6        IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE  IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11           IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1        IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__GPIO4_28                   IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__CSPI_RDY                   IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7        IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12           IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID          IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__GPIO4_29                   IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__PWM1_PWMO                  IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B               IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13           IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID             IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__GPIO4_30                   IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__PWM2_PWMO                  IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B               IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14           IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0          IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__GPIO4_31                  IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP          IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3        \
+                                                        IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15          IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1         IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__GPIO5_5                   IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT          IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4        \
+                                                        IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16          IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2         IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__GPIO5_6                   IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK          IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5        \
+                                                        IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17          IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3         IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__GPIO5_7                   IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS          IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0        \
+                                                        IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18          IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4         IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__GPIO5_8                   IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC           IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1        \
+                                                        IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19          IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5         IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__GPIO5_9                   IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1                IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1                IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2        \
+                                                        IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20          IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6         IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__GPIO5_10                  IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI               IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC           IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0          IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3        \
+                                                        IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21          IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7         IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__GPIO5_11                  IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO               IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD           IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1          IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4        \
+                                                        IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22          IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__GPIO5_12                  IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0                IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS          IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS          IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5        \
+                                                        IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23          IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2             IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__GPIO5_13                  IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK               IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD           IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC           IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6        \
+                                                        IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24          IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3             IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__GPIO5_14                  IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK               IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC           IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7        \
+                                                        IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25          IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI              IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__GPIO5_15                  IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI               IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD           IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0   IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26          IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO              IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__GPIO5_16                  IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO               IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS          IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1   IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27          IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK              IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__GPIO5_17                  IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0                IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD           IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2   IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28          IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS              IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK           IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_PIXCLK__GPIO5_18                  IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0           IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29          IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC              IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__GPIO5_19                    IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK               IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1             IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30            IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL                  IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN         IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__GPIO5_20                 IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2          IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31         IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK               IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC             IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_VSYNC__GPIO5_21                   IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3            IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32           IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0               IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4                IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__GPIO5_22                    IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__KPP_COL_5                   IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK                 IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP            IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC             IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33            IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1                IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5                IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__GPIO5_23                    IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__KPP_ROW_5                   IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI                 IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT            IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD             IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34            IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2                IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6                IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__GPIO5_24                    IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__KPP_COL_6                   IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO                 IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK            IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS            IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35            IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3                IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7                IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__GPIO5_25                    IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__KPP_ROW_6                   IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0                  IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR            IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD             IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36            IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4                IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8                IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__GPIO5_26                    IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__KPP_COL_7                   IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK                 IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC             IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__I2C1_SDA                    IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37            IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5                IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9                IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__GPIO5_27                    IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__KPP_ROW_7                   IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI                 IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR            IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__I2C1_SCL                    IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38            IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6                IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10              IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__GPIO5_28                   IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX              IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO                IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC            IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4            IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39           IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7               IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11              IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__GPIO5_29                   IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX              IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0                 IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS           IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5            IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40           IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8               IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12              IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__GPIO5_30                   IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX              IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0        IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6            IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41           IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9               IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13              IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__GPIO5_31                   IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX              IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1        IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7            IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42           IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10              IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14              IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__GPIO6_0                    IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX              IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2        IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8            IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43           IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11              IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15              IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__GPIO6_1                    IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX              IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3        IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9            IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44           IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12              IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16              IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__GPIO6_2                    IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__UART4_RTS                  IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4        IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10           IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45           IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13              IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17              IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__GPIO6_3                    IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__UART4_CTS                  IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5        IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11           IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46           IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14              IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18              IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__GPIO6_4                    IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__UART5_RTS                  IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6        IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12           IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47           IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15              IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19              IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__GPIO6_5                    IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__UART5_CTS                  IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7        IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13           IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48           IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK             IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__EMI_WEIM_A_25                 IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__GPIO5_2                       IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__ECSPI2_RDY                    IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__IPU_DI1_PIN12                 IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__CSPI_SS1                      IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS                 IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__USBPHY1_BISTOK                IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2                 IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__GPIO2_30                      IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK               IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS              IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__ECSPI1_SS0                    IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__I2C2_SCL                      IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__EMI_WEIM_D_16                 IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__GPIO3_16                      IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__IPU_DI0_PIN5                  IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK            IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__ECSPI1_SCLK                   IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__I2C2_SDA                      IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__EMI_WEIM_D_17                 IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__GPIO3_17                      IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__IPU_DI0_PIN6                  IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN            IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__ECSPI1_MISO                   IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__I2C3_SCL                      IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__EMI_WEIM_D_18                 IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__GPIO3_18                      IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__IPU_DI0_PIN7                  IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO            IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__ECSPI1_MOSI                   IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__I2C3_SDA                      IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS                 IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__EMI_WEIM_D_19                 IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__GPIO3_19                      IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__IPU_DI0_PIN8                  IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS             IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__ECSPI1_SS1                    IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__EPIT1_EPITO                   IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__UART1_CTS                     IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC               IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__EMI_WEIM_D_20                 IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__GPIO3_20                      IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__IPU_DI0_PIN16                 IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS              IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__CSPI_SS0                      IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__EPIT2_EPITO                   IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__UART1_RTS                     IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR              IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__EMI_WEIM_D_21                 IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__GPIO3_21                      IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__IPU_DI0_PIN17                 IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK            IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__CSPI_SCLK                     IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__I2C1_SCL                      IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC              IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__EMI_WEIM_D_22                 IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__GPIO3_22                      IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__IPU_DI0_PIN1                  IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN            IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__CSPI_MISO                     IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR             IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__EMI_WEIM_D_23                 IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__GPIO3_23                      IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__UART3_CTS                     IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D23__UART1_DCD                     IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS                 IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN2                  IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN              IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN14                 IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3                 IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__GPIO2_31                      IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__UART3_RTS                     IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__UART1_RI                      IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3                  IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC                IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16                 IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__EMI_WEIM_D_24                 IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__GPIO3_24                      IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__UART3_TXD_MUX                 IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D24__ECSPI1_SS2                    IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__CSPI_SS2                      IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS              IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__ECSPI2_SS2                    IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__UART1_DTR                     IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__EMI_WEIM_D_25                 IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__GPIO3_25                      IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__UART3_RXD_MUX                 IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D25__ECSPI1_SS3                    IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__CSPI_SS3                      IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC               IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__ECSPI2_SS3                    IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__UART1_DSR                     IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__EMI_WEIM_D_26                 IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__GPIO3_26                      IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__UART2_TXD_MUX                 IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D26__FIRI_RXD                      IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__IPU_CSI0_D_1                  IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__IPU_DI1_PIN11                 IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__IPU_SISG_2                    IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22              IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__EMI_WEIM_D_27                 IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__GPIO3_27                      IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__UART2_RXD_MUX                 IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D27__FIRI_TXD                      IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__IPU_CSI0_D_0                  IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__IPU_DI1_PIN13                 IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__IPU_SISG_3                    IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23              IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__EMI_WEIM_D_28                 IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__GPIO3_28                      IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__UART2_CTS                     IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO            IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__CSPI_MOSI                     IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__I2C1_SDA                      IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, PAD_CTRL_I2C)
+#define MX53_PAD_EIM_D28__IPU_EXT_TRIG                  IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__IPU_DI0_PIN13                 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__EMI_WEIM_D_29                 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__GPIO3_29                      IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__UART2_RTS                     IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS             IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__CSPI_SS0                      IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__IPU_DI1_PIN15                 IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC                IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__IPU_DI0_PIN14                 IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__EMI_WEIM_D_30                 IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__GPIO3_30                      IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__UART3_CTS                     IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D30__IPU_CSI0_D_3                  IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__IPU_DI0_PIN11                 IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21              IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC               IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC               IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__EMI_WEIM_D_31                 IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__GPIO3_31                      IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__UART3_RTS                     IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D31__IPU_CSI0_D_2                  IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__IPU_DI0_PIN12                 IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20              IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR              IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR              IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__EMI_WEIM_A_24                 IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__GPIO5_4                       IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19              IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__IPU_CSI1_D_19                 IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__IPU_SISG_2                    IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__USBPHY2_BVALID                IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__EMI_WEIM_A_23                 IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__GPIO6_6                       IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18              IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__IPU_CSI1_D_18                 IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__IPU_SISG_3                    IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION            IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A22__EMI_WEIM_A_22                 IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A22__GPIO2_16                      IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17              IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A22__IPU_CSI1_D_17                 IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7                 IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__EMI_WEIM_A_21                 IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__GPIO2_17                      IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16              IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__IPU_CSI1_D_16                 IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6                 IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__EMI_WEIM_A_20                 IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__GPIO2_18                      IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15              IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__IPU_CSI1_D_15                 IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5                 IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__EMI_WEIM_A_19                 IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__GPIO2_19                      IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14              IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__IPU_CSI1_D_14                 IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4                 IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__EMI_WEIM_A_18                 IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__GPIO2_20                      IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13              IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__IPU_CSI1_D_13                 IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3                 IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__EMI_WEIM_A_17                 IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__GPIO2_21                      IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12              IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__IPU_CSI1_D_12                 IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2                 IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__EMI_WEIM_A_16                 IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__GPIO2_22                      IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK              IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK               IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1                 IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0                 IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS0__GPIO2_23                      IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS0__ECSPI2_SCLK                   IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5                  IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1                 IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS1__GPIO2_24                      IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS1__ECSPI2_MOSI                   IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6                  IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__EMI_WEIM_OE                    IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__GPIO2_25                       IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__ECSPI2_MISO                    IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__IPU_DI1_PIN7                   IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__USBPHY2_IDDIG                  IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__EMI_WEIM_RW                    IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__GPIO2_26                       IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__ECSPI2_SS0                     IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__IPU_DI1_PIN8                   IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT         IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA                  IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__GPIO2_27                      IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__ECSPI2_SS1                    IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17                 IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0                 IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0                 IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__GPIO2_28                      IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11              IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11                 IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY                  IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7                 IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1                 IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__GPIO2_29                      IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10              IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10                 IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6                 IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0            IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__GPIO3_0                       IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9               IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9                  IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5                 IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1            IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__GPIO3_1                       IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8               IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8                  IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4                 IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2            IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__GPIO3_2                       IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7               IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7                  IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3                 IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3            IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__GPIO3_3                       IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6               IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6                  IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2                 IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4            IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__GPIO3_4                       IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5               IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5                  IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7                 IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5            IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__GPIO3_5                       IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4               IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4                  IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6                 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6            IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__GPIO3_6                       IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3               IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3                  IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5                 IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7            IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__GPIO3_7                       IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2               IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2                  IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4                 IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8            IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__GPIO3_8                       IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1               IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1                  IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3                 IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9            IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__GPIO3_9                       IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0               IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0                  IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2                 IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10          IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__GPIO3_10                     IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15                IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN             IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1                IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11          IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA11__GPIO3_11                     IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2                 IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC               IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12          IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA12__GPIO3_12                     IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3                 IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC               IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13          IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA13__GPIO3_13                     IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS                IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK              IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14          IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA14__GPIO3_14                     IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS                IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK              IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15          IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA15__GPIO3_15                     IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1                 IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4                 IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B             IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WE_B__GPIO6_12                   IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B             IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RE_B__GPIO6_13                   IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT                IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_WAIT__GPIO5_0                      IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B             IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX3_P__GPIO6_22                  IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3             IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX2_P__GPIO6_24                  IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2             IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_CLK_P__GPIO6_26                  IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK             IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX1_P__GPIO6_28                  IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1             IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX0_P__GPIO6_30                  IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0             IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX3_P__GPIO7_22                  IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3             IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_CLK_P__GPIO7_24                  IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK             IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX2_P__GPIO7_26                  IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2             IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX1_P__GPIO7_28                  IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1             IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX0_P__GPIO7_30                  IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0             IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_10__GPIO4_0                       IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_10__OSC32k_32K_OUT                IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_11__GPIO4_1                       IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_12__GPIO4_2                       IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_13__GPIO4_3                       IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_14__GPIO4_4                       IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE               IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CLE__GPIO6_7                     IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0           IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE               IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_ALE__GPIO6_8                     IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1           IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B             IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WP_B__GPIO6_9                    IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2          IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0              IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RB0__GPIO6_10                    IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3           IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0              IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS0__GPIO6_11                    IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4           IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1              IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS1__GPIO6_14                    IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS1__MLB_MLBCLK                  IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5           IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2              IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__GPIO6_15                    IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__IPU_SISG_0                  IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__ESAI1_TX0                   IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE                IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK               IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__MLB_MLBSIG                  IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6           IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3              IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__GPIO6_16                    IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__IPU_SISG_1                  IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__ESAI1_TX1                   IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26               IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__MLB_MLBDAT                  IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7           IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__FEC_MDIO                     IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__GPIO1_22                     IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__ESAI1_SCKR                   IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__FEC_COL                      IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2               IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3      IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49             IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK                IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__GPIO1_23                  IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR                 IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4   IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50          IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__FEC_RX_ER                   IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__GPIO1_24                    IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR                  IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK                  IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3              IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV                  IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_CRS_DV__GPIO1_25                   IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT                 IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__FEC_RDATA_1                  IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__GPIO1_26                     IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__ESAI1_FST                    IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__MLB_MLBSIG                   IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1               IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD0__FEC_RDATA_0                  IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD0__GPIO1_27                     IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD0__ESAI1_HCKT                   IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT               IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TX_EN__FEC_TX_EN                   IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TX_EN__GPIO1_28                    IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2               IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__FEC_TDATA_1                  IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__GPIO1_29                     IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3                IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__MLB_MLBCLK                   IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK          IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD0__FEC_TDATA_0                  IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD0__GPIO1_30                     IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1                IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0            IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__FEC_MDC                       IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__GPIO1_31                      IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0                 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__MLB_MLBDAT                    IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG        IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1             IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOW__PATA_DIOW                   IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOW__GPIO6_17                    IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX               IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2           IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMACK__PATA_DMACK                 IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMACK__GPIO6_18                   IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX              IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3          IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMARQ__PATA_DMARQ                 IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMARQ__GPIO7_0                    IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX              IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0              IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4          IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN         IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1                IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX          IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1          IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5      IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__PATA_INTRQ                 IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__GPIO7_2                    IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__UART2_CTS                  IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN                 IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2              IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6          IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOR__PATA_DIOR                   IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOR__GPIO7_3                     IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOR__UART2_RTS                   IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DIOR__CAN1_RXCAN                  IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7           IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B        IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__GPIO7_4                  IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD               IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__UART1_CTS                IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN               IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0        IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__PATA_IORDY                 IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__GPIO7_5                    IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__ESDHC3_CLK                 IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__UART1_RTS                  IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__CAN2_RXCAN                 IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1          IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_0__PATA_DA_0                   IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_0__GPIO7_6                     IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_0__ESDHC3_RST                  IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_0__OWIRE_LINE                  IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2           IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__PATA_DA_1                   IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__GPIO7_7                     IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__ESDHC4_CMD                  IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__UART3_CTS                   IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3           IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__PATA_DA_2                   IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__GPIO7_8                     IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__ESDHC4_CLK                  IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__UART3_RTS                   IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4           IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_0__PATA_CS_0                   IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_0__GPIO7_9                     IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX               IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5           IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_1__PATA_CS_1                   IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_1__GPIO7_10                    IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX               IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6           IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__PATA_DATA_0                IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__GPIO2_0                    IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0              IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4                IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0      IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0             IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7          IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__PATA_DATA_1                IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__GPIO2_1                    IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1              IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5                IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1      IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1             IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__PATA_DATA_2                IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__GPIO2_2                    IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2              IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6                IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2      IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2             IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__PATA_DATA_3                IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__GPIO2_3                    IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3              IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7                IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3      IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3             IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__PATA_DATA_4                IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__GPIO2_4                    IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4              IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4                IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4      IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4             IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__PATA_DATA_5                IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__GPIO2_5                    IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5              IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5                IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5      IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5             IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__PATA_DATA_6                IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__GPIO2_6                    IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6              IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6                IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6      IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6             IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__PATA_DATA_7                IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__GPIO2_7                    IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7              IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7                IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7      IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7             IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__PATA_DATA_8                IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__GPIO2_8                    IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4                IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8              IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0                IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8      IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8             IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__PATA_DATA_9                IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__GPIO2_9                    IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5                IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9              IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1                IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9      IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9             IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__PATA_DATA_10              IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__GPIO2_10                  IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6               IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10            IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2               IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10    IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10           IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__PATA_DATA_11              IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__GPIO2_11                  IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7               IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11            IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3               IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11    IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11           IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__PATA_DATA_12              IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__GPIO2_12                  IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4               IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12            IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0               IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12    IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12           IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__PATA_DATA_13              IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__GPIO2_13                  IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5               IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13            IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1               IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13    IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13           IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__PATA_DATA_14              IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__GPIO2_14                  IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6               IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14            IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2               IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14    IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14           IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__PATA_DATA_15              IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__GPIO2_15                  IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7               IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15            IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3               IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15    IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15           IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0                 IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__GPIO1_16                    IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__GPT_CAPIN1                  IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__CSPI_MISO                   IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP                IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1                 IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__GPIO1_17                    IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__GPT_CAPIN2                  IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__CSPI_SS0                    IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP                IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__ESDHC1_CMD                    IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__GPIO1_18                      IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__GPT_CMPOUT1                   IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__CSPI_MOSI                     IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP                  IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2                 IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__GPIO1_19                    IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2                 IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__PWM2_PWMO                   IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B                IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__CSPI_SS1                    IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB        IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP                IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__ESDHC1_CLK                    IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__GPIO1_20                      IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT                IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__GPT_CLKIN                     IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__CSPI_SCLK                     IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0                IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3                 IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__GPIO1_21                    IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3                 IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__PWM1_PWMO                   IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B                IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__CSPI_SS2                    IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB        IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1              IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__ESDHC2_CLK                    IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__GPIO1_10                      IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__KPP_COL_5                     IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS              IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__CSPI_SCLK                     IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__SCC_RANDOM_V                  IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__ESDHC2_CMD                    IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__GPIO1_11                      IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__KPP_ROW_5                     IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC               IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__CSPI_MOSI                     IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__SCC_RANDOM                    IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3                 IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__GPIO1_12                    IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__KPP_COL_6                   IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC             IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__CSPI_SS2                    IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__SJC_DONE                    IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2                 IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__GPIO1_13                    IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__KPP_ROW_6                   IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD             IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__CSPI_SS1                    IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__SJC_FAIL                    IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1                 IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__GPIO1_14                    IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__KPP_COL_7                   IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS            IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__CSPI_SS0                    IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO                IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0                 IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__GPIO1_15                    IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__KPP_ROW_7                   IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD             IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__CSPI_MISO                   IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT               IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__CCM_CLKO                       IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__GPIO1_0                        IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__KPP_COL_5                      IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK               IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__EPIT1_EPITO                    IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB                 IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR               IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__CSU_TD                         IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__ESAI1_SCKR                     IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__GPIO1_1                        IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__KPP_ROW_5                      IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK               IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__PWM2_PWMO                      IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__WDOG2_WDOG_B                   IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__ESDHC1_CD                      IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__SRC_TESTER_ACK                 IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__ESAI1_FSR                      IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__GPIO1_9                        IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__KPP_COL_6                      IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__CCM_REF_EN_B                   IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__PWM1_PWMO                      IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__WDOG1_WDOG_B                   IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__ESDHC1_WP                      IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__SCC_FAIL_STATE                 IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__ESAI1_HCKR                     IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__GPIO1_3                        IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__I2C3_SCL                       IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN                 IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__CCM_CLKO2                      IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0     IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC                IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__MLB_MLBCLK                     IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__ESAI1_SCKT                     IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__GPIO1_6                        IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__I2C3_SDA                       IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0                  IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB                IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1     IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__ESDHC2_LCTL                    IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__MLB_MLBSIG                     IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__ESAI1_FST                      IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__GPIO1_2                        IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__KPP_ROW_6                      IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1                  IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0            IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2     IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__ESDHC2_WP                      IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__MLB_MLBDAT                     IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__ESAI1_HCKT                     IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__GPIO1_4                        IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__KPP_COL_7                      IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2                  IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1            IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3     IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__ESDHC2_CD                      IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__SCC_SEC_STATE                  IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3                  IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__GPIO1_5                        IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__KPP_ROW_7                      IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__CCM_CLKO                       IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2            IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4     IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__I2C3_SCL                       IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__CCM_PLL1_BYP                   IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1                  IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__GPIO1_7                        IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__EPIT1_EPITO                    IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__CAN1_TXCAN                     IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__UART2_TXD_MUX                  IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_GPIO_7__FIRI_RXD                       IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__SPDIF_PLOCK                    IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__CCM_PLL2_BYP                   IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0                  IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__GPIO1_8                        IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__EPIT2_EPITO                    IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__CAN1_RXCAN                     IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__UART2_RXD_MUX                  IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL)
+#define MX53_PAD_GPIO_8__FIRI_TXD                       IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__SPDIF_SRCLK                    IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__CCM_PLL3_BYP                   IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2                 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__GPIO7_11                      IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT              IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1          IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__SPDIF_IN1                     IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__I2C3_SDA                      IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__SJC_DE_B                      IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__ESAI1_TX0                     IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__GPIO7_12                      IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0              IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__GPC_PMIC_RDY                  IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG           IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__SPDIF_OUT1                    IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__IPU_SNOOP2                    IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__SJC_JTAG_ACT                  IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__ESAI1_TX1                     IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__GPIO7_13                      IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1              IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__OWIRE_LINE                    IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG        IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK              IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__ESDHC1_LCTL                   IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST                IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL)
 
 #endif  /* __MACH_IOMUX_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index ebbce33097a7..35e0df224caa 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -80,6 +80,7 @@ typedef u64 iomux_v3_cfg_t;
                 ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
                 ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT))
 
+#define NEW_PAD_CTRL(cfg, pad)  (((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad))
 /*
  * Use to set PAD control
  */
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 11be5cdbdd1a..3ec84b902243 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -40,19 +40,4 @@
 # endif
 #endif
 
-#if defined(CONFIG_MX3_VIDEO)
-/*
- * Increase size of DMA-consistent memory region.
- * This is required for mx3 camera driver to capture at least two QXGA frames.
- */
-#define CONSISTENT_DMA_SIZE SZ_8M
-
-#elif defined(CONFIG_MX1_VIDEO) || defined(CONFIG_VIDEO_MX2_HOSTSUPPORT)
-/*
- * Increase size of DMA-consistent memory region.
- * This is required for i.MX camera driver to capture at least four VGA frames.
- */
-#define CONSISTENT_DMA_SIZE SZ_4M
-#endif /* CONFIG_MX1_VIDEO || CONFIG_VIDEO_MX2_HOSTSUPPORT */
-
 #endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index dede19a766ff..cdf07c65ec1e 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -18,18 +18,6 @@
 #define MX51_GPU_CTRL_BASE_ADDR         0x30000000
 #define MX51_IPU_CTRL_BASE_ADDR         0x40000000
 
-#define MX51_DEBUG_BASE_ADDR            0x60000000
-#define MX51_DEBUG_SIZE                 SZ_1M
-
-#define MX51_ETB_BASE_ADDR              (MX51_DEBUG_BASE_ADDR + 0x01000)
-#define MX51_ETM_BASE_ADDR              (MX51_DEBUG_BASE_ADDR + 0x02000)
-#define MX51_TPIU_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x03000)
-#define MX51_CTI0_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x04000)
-#define MX51_CTI1_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x05000)
-#define MX51_CTI2_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x06000)
-#define MX51_CTI3_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x07000)
-#define MX51_CORTEX_DBG_BASE_ADDR       (MX51_DEBUG_BASE_ADDR + 0x08000)
-
 /*
  * SPBA global module enabled #0
  */
@@ -55,7 +43,10 @@
 #define MX51_AIPS1_BASE_ADDR            0x73f00000
 #define MX51_AIPS1_SIZE                 SZ_1M
 
-#define MX51_OTG_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x80000)
+#define MX51_USB_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x80000)
+#define MX51_USB_OTG_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0000)
+#define MX51_USB_HS1_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0200)
+#define MX51_USB_HS2_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0400)
 #define MX51_GPIO1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x84000)
 #define MX51_GPIO2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x88000)
 #define MX51_GPIO3_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x8c000)
@@ -132,6 +123,7 @@
 
 #define MX51_GPU2D_BASE_ADDR            0xd0000000
 #define MX51_TZIC_BASE_ADDR             0xe0000000
+#define MX51_TZIC_SIZE                  SZ_16K
 
 #define MX51_IO_P2V(x)                  IMX_IO_P2V(x)
 #define MX51_IO_ADDRESS(x)              IOMEM(MX51_IO_P2V(x))
@@ -240,117 +232,114 @@
 /*
  * Interrupt numbers
  */
-#define MX51_MXC_INT_BASE               0
-#define MX51_MXC_INT_RESV0              0
+#define MX51_INT_BASE                   0
+#define MX51_INT_RESV0                  0
 #define MX51_INT_ESDHC1                 1
 #define MX51_INT_ESDHC2                 2
 #define MX51_INT_ESDHC3                 3
 #define MX51_INT_ESDHC4                 4
-#define MX51_MXC_INT_RESV5              5
+#define MX51_INT_RESV5                  5
 #define MX51_INT_SDMA                   6
-#define MX51_MXC_INT_IOMUX              7
+#define MX51_INT_IOMUX                  7
 #define MX51_INT_NFC                    8
-#define MX51_MXC_INT_VPU                9
+#define MX51_INT_VPU                    9
 #define MX51_INT_IPU_ERR                10
 #define MX51_INT_IPU_SYN                11
-#define MX51_MXC_INT_GPU                12
-#define MX51_MXC_INT_RESV13             13
-#define MX51_MXC_INT_USB_H1             14
-#define MX51_MXC_INT_EMI                15
-#define MX51_MXC_INT_USB_H2             16
-#define MX51_MXC_INT_USB_H3             17
-#define MX51_MXC_INT_USB_OTG            18
-#define MX51_MXC_INT_SAHARA_H0          19
-#define MX51_MXC_INT_SAHARA_H1          20
-#define MX51_MXC_INT_SCC_SMN            21
-#define MX51_MXC_INT_SCC_STZ            22
-#define MX51_MXC_INT_SCC_SCM            23
-#define MX51_MXC_INT_SRTC_NTZ           24
-#define MX51_MXC_INT_SRTC_TZ            25
-#define MX51_MXC_INT_RTIC               26
-#define MX51_MXC_INT_CSU                27
-#define MX51_MXC_INT_SLIM_B             28
+#define MX51_INT_GPU                    12
+#define MX51_INT_RESV13                 13
+#define MX51_INT_USB_HS1                14
+#define MX51_INT_EMI                    15
+#define MX51_INT_USB_HS2                16
+#define MX51_INT_USB_HS3                17
+#define MX51_INT_USB_OTG                18
+#define MX51_INT_SAHARA_H0              19
+#define MX51_INT_SAHARA_H1              20
+#define MX51_INT_SCC_SMN                21
+#define MX51_INT_SCC_STZ                22
+#define MX51_INT_SCC_SCM                23
+#define MX51_INT_SRTC_NTZ               24
+#define MX51_INT_SRTC_TZ                25
+#define MX51_INT_RTIC                   26
+#define MX51_INT_CSU                    27
+#define MX51_INT_SLIM_B                 28
 #define MX51_INT_SSI1                   29
 #define MX51_INT_SSI2                   30
 #define MX51_INT_UART1                  31
 #define MX51_INT_UART2                  32
 #define MX51_INT_UART3                  33
-#define MX51_MXC_INT_RESV34             34
-#define MX51_MXC_INT_RESV35             35
+#define MX51_INT_RESV34                 34
+#define MX51_INT_RESV35                 35
 #define MX51_INT_ECSPI1                 36
 #define MX51_INT_ECSPI2                 37
 #define MX51_INT_CSPI                   38
-#define MX51_MXC_INT_GPT                39
-#define MX51_MXC_INT_EPIT1              40
-#define MX51_MXC_INT_EPIT2              41
-#define MX51_MXC_INT_GPIO1_INT7         42
-#define MX51_MXC_INT_GPIO1_INT6         43
-#define MX51_MXC_INT_GPIO1_INT5         44
-#define MX51_MXC_INT_GPIO1_INT4         45
-#define MX51_MXC_INT_GPIO1_INT3         46
-#define MX51_MXC_INT_GPIO1_INT2         47
-#define MX51_MXC_INT_GPIO1_INT1         48
-#define MX51_MXC_INT_GPIO1_INT0         49
-#define MX51_MXC_INT_GPIO1_LOW          50
-#define MX51_MXC_INT_GPIO1_HIGH         51
-#define MX51_MXC_INT_GPIO2_LOW          52
-#define MX51_MXC_INT_GPIO2_HIGH         53
-#define MX51_MXC_INT_GPIO3_LOW          54
-#define MX51_MXC_INT_GPIO3_HIGH         55
-#define MX51_MXC_INT_GPIO4_LOW          56
-#define MX51_MXC_INT_GPIO4_HIGH         57
-#define MX51_MXC_INT_WDOG1              58
-#define MX51_MXC_INT_WDOG2              59
+#define MX51_INT_GPT                    39
+#define MX51_INT_EPIT1                  40
+#define MX51_INT_EPIT2                  41
+#define MX51_INT_GPIO1_INT7             42
+#define MX51_INT_GPIO1_INT6             43
+#define MX51_INT_GPIO1_INT5             44
+#define MX51_INT_GPIO1_INT4             45
+#define MX51_INT_GPIO1_INT3             46
+#define MX51_INT_GPIO1_INT2             47
+#define MX51_INT_GPIO1_INT1             48
+#define MX51_INT_GPIO1_INT0             49
+#define MX51_INT_GPIO1_LOW              50
+#define MX51_INT_GPIO1_HIGH             51
+#define MX51_INT_GPIO2_LOW              52
+#define MX51_INT_GPIO2_HIGH             53
+#define MX51_INT_GPIO3_LOW              54
+#define MX51_INT_GPIO3_HIGH             55
+#define MX51_INT_GPIO4_LOW              56
+#define MX51_INT_GPIO4_HIGH             57
+#define MX51_INT_WDOG1                  58
+#define MX51_INT_WDOG2                  59
 #define MX51_INT_KPP                    60
 #define MX51_INT_PWM1                   61
 #define MX51_INT_I2C1                   62
 #define MX51_INT_I2C2                   63
-#define MX51_MXC_INT_HS_I2C             64
-#define MX51_MXC_INT_RESV65             65
-#define MX51_MXC_INT_RESV66             66
-#define MX51_MXC_INT_SIM_IPB            67
-#define MX51_MXC_INT_SIM_DAT            68
-#define MX51_MXC_INT_IIM                69
-#define MX51_MXC_INT_ATA                70
-#define MX51_MXC_INT_CCM1               71
-#define MX51_MXC_INT_CCM2               72
-#define MX51_MXC_INT_GPC1               73
-#define MX51_MXC_INT_GPC2               74
-#define MX51_MXC_INT_SRC                75
-#define MX51_MXC_INT_NM                 76
-#define MX51_MXC_INT_PMU                77
-#define MX51_MXC_INT_CTI_IRQ            78
-#define MX51_MXC_INT_CTI1_TG0           79
-#define MX51_MXC_INT_CTI1_TG1           80
-#define MX51_MXC_INT_MCG_ERR            81
-#define MX51_MXC_INT_MCG_TMR            82
-#define MX51_MXC_INT_MCG_FUNC           83
-#define MX51_MXC_INT_GPU2_IRQ           84
-#define MX51_MXC_INT_GPU2_BUSY          85
-#define MX51_MXC_INT_RESV86             86
+#define MX51_INT_HS_I2C                 64
+#define MX51_INT_RESV65                 65
+#define MX51_INT_RESV66                 66
+#define MX51_INT_SIM_IPB                67
+#define MX51_INT_SIM_DAT                68
+#define MX51_INT_IIM                    69
+#define MX51_INT_ATA                    70
+#define MX51_INT_CCM1                   71
+#define MX51_INT_CCM2                   72
+#define MX51_INT_GPC1                           73
+#define MX51_INT_GPC2                   74
+#define MX51_INT_SRC                    75
+#define MX51_INT_NM                     76
+#define MX51_INT_PMU                    77
+#define MX51_INT_CTI_IRQ                78
+#define MX51_INT_CTI1_TG0               79
+#define MX51_INT_CTI1_TG1               80
+#define MX51_INT_MCG_ERR                81
+#define MX51_INT_MCG_TMR                82
+#define MX51_INT_MCG_FUNC               83
+#define MX51_INT_GPU2_IRQ               84
+#define MX51_INT_GPU2_BUSY              85
+#define MX51_INT_RESV86                 86
 #define MX51_INT_FEC                    87
-#define MX51_MXC_INT_OWIRE              88
-#define MX51_MXC_INT_CTI1_TG2           89
-#define MX51_MXC_INT_SJC                90
-#define MX51_MXC_INT_SPDIF              91
-#define MX51_MXC_INT_TVE                92
-#define MX51_MXC_INT_FIRI               93
+#define MX51_INT_OWIRE                  88
+#define MX51_INT_CTI1_TG2               89
+#define MX51_INT_SJC                    90
+#define MX51_INT_SPDIF                  91
+#define MX51_INT_TVE                    92
+#define MX51_INT_FIRI                   93
 #define MX51_INT_PWM2                   94
-#define MX51_MXC_INT_SLIM_EXP           95
+#define MX51_INT_SLIM_EXP               95
 #define MX51_INT_SSI3                   96
-#define MX51_MXC_INT_EMI_BOOT           97
-#define MX51_MXC_INT_CTI1_TG3           98
-#define MX51_MXC_INT_SMC_RX             99
-#define MX51_MXC_INT_VPU_IDLE           100
-#define MX51_MXC_INT_EMI_NFC            101
-#define MX51_MXC_INT_GPU_IDLE           102
+#define MX51_INT_EMI_BOOT               97
+#define MX51_INT_CTI1_TG3               98
+#define MX51_INT_SMC_RX                 99
+#define MX51_INT_VPU_IDLE               100
+#define MX51_INT_EMI_NFC                101
+#define MX51_INT_GPU_IDLE               102
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 extern int mx51_revision(void);
 extern void mx51_display_revision(void);
 #endif
 
-/* tape-out 1 defines */
-#define MX51_TZIC_BASE_ADDR_TO1         0x8fffc000
-
 #endif  /* ifndef __MACH_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index 5e3c3236ebf3..a37e8c353994 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -9,6 +9,7 @@
 
 /* TZIC */
 #define MX53_TZIC_BASE_ADDR             0x0FFFC000
+#define MX53_TZIC_SIZE                  SZ_16K
 
 /*
  * AHCI SATA
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 09879235a9f5..00a78193c681 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -183,13 +183,6 @@ struct cpu_op {
 };
 
 int tzic_enable_wake(int is_idle);
-enum mxc_cpu_pwr_mode {
-        WAIT_CLOCKED,           /* wfi only */
-        WAIT_UNCLOCKED,         /* WAIT */
-        WAIT_UNCLOCKED_POWER_OFF,       /* WAIT + SRPG */
-        STOP_POWER_ON,          /* just STOP */
-        STOP_POWER_OFF,         /* STOP + SRPG */
-};
 
 extern struct cpu_op *(*get_cpu_op)(int *op);
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 51f02a9d41a3..cf88b3593fba 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -17,41 +17,12 @@
 #ifndef __ASM_ARCH_MXC_SYSTEM_H__
 #define __ASM_ARCH_MXC_SYSTEM_H__
 
-#include <mach/hardware.h>
-#include <mach/common.h>
-
-extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
+extern void (*imx_idle)(void);
 
 static inline void arch_idle(void)
 {
-        /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
-        if (cpu_is_mx31() || cpu_is_mx35()) {
-                unsigned long reg = 0;
-                __asm__ __volatile__(
-                        /* disable I and D cache */
-                        "mrc p15, 0, %0, c1, c0, 0\n"
-                        "bic %0, %0, #0x00001000\n"
-                        "bic %0, %0, #0x00000004\n"
-                        "mcr p15, 0, %0, c1, c0, 0\n"
-                        /* invalidate I cache */
-                        "mov %0, #0\n"
-                        "mcr p15, 0, %0, c7, c5, 0\n"
-                        /* clear and invalidate D cache */
-                        "mov %0, #0\n"
-                        "mcr p15, 0, %0, c7, c14, 0\n"
-                        /* WFI */
-                        "mov %0, #0\n"
-                        "mcr p15, 0, %0, c7, c0, 4\n"
-                        "nop\n" "nop\n" "nop\n" "nop\n"
-                        "nop\n" "nop\n" "nop\n"
-                        /* enable I and D cache */
-                        "mrc p15, 0, %0, c1, c0, 0\n"
-                        "orr %0, %0, #0x00001000\n"
-                        "orr %0, %0, #0x00000004\n"
-                        "mcr p15, 0, %0, c1, c0, 0\n"
-                        : "=r" (reg));
-        } else if (cpu_is_mx51())
-                mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+        if (imx_idle != NULL)
+                (imx_idle)();
         else
                 cpu_do_idle();
 }
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 8024f2ac177c..9dad8dcc2ea9 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -28,6 +28,9 @@
 #include <asm/system.h>
 #include <asm/mach-types.h>
 
+void (*imx_idle)(void) = NULL;
+void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
+
 static void __iomem *wdog_base;
 
 /*
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
index 05a3936ae6d1..22cb97d2d8ad 100644
--- a/arch/arm/plat-nomadik/include/plat/pincfg.h
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -37,7 +37,6 @@
  *                   SLPM value = same as normal
  *
  * PIN_CFG         - default config with alternate function
- * PIN_CFG_PULL    - default config with alternate function and pull up/down
  */
 
 typedef unsigned long pin_cfg_t;
@@ -133,10 +132,6 @@ typedef unsigned long pin_cfg_t;
         (PIN_CFG_DEFAULT |\
          (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
 
-#define PIN_CFG_PULL(num, alt, pull)    \
-        ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\
-         (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull))
-
 extern int nmk_config_pin(pin_cfg_t cfg, bool sleep);
 extern int nmk_config_pins(pin_cfg_t *cfgs, int num);
 extern int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num);
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index ea28f98d5d6a..bd9a06b3ee89 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -26,54 +26,8 @@
 #include <plat/mmc.h>
 #include <mach/gpio.h>
 #include <plat/menelaus.h>
-#include <plat/mcbsp.h>
 #include <plat/omap44xx.h>
 
-/*-------------------------------------------------------------------------*/
-
-#if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE)
-
-static struct platform_device **omap_mcbsp_devices;
-
-void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
-                        struct omap_mcbsp_platform_data *config, int size)
-{
-        int i;
-
-        omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *),
-                                     GFP_KERNEL);
-        if (!omap_mcbsp_devices) {
-                printk(KERN_ERR "Could not register McBSP devices\n");
-                return;
-        }
-
-        for (i = 0; i < size; i++) {
-                struct platform_device *new_mcbsp;
-                int ret;
-
-                new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
-                if (!new_mcbsp)
-                        continue;
-                platform_device_add_resources(new_mcbsp, &res[i * res_count],
-                                        res_count);
-                new_mcbsp->dev.platform_data = &config[i];
-                ret = platform_device_add(new_mcbsp);
-                if (ret) {
-                        platform_device_put(new_mcbsp);
-                        continue;
-                }
-                omap_mcbsp_devices[i] = new_mcbsp;
-        }
-}
-
-#else
-void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
-                        struct omap_mcbsp_platform_data *config, int size)
-{  }
-#endif
-
-/*-------------------------------------------------------------------------*/
-
 #if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
                 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
 
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 3341ca4703e9..0c7caf2458b4 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -135,7 +135,7 @@ static inline int omap2_i2c_add_bus(int bus_id)
 {
         int l;
         struct omap_hwmod *oh;
-        struct omap_device *od;
+        struct platform_device *pdev;
         char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
         struct omap_i2c_bus_platform_data *pdata;
 
@@ -160,12 +160,12 @@ static inline int omap2_i2c_add_bus(int bus_id)
          */
         if (cpu_is_omap34xx())
                 pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
-        od = omap_device_build(name, bus_id, oh, pdata,
+        pdev = omap_device_build(name, bus_id, oh, pdata,
                         sizeof(struct omap_i2c_bus_platform_data),
                         omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0);
-        WARN(IS_ERR(od), "Could not build omap_device for %s\n", name);
+        WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
 
-        return PTR_ERR(od);
+        return PTR_ERR(pdev);
 }
 #else
 static inline int omap2_i2c_add_bus(int bus_id)
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index df4b9683f17f..197ca03c3f7d 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -80,8 +80,6 @@ struct clkops {
  *
  * @div is the divisor that should be applied to the parent clock's rate
  * to produce the current clock's rate.
- *
- * XXX @flags probably should be replaced with an struct omap_chip.
  */
 struct clksel_rate {
         u32                     val;
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 4564cc697d7f..abda2c7e499b 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -45,6 +45,15 @@ extern unsigned long long notrace omap_32k_sched_clock(void);
 
 extern void omap_reserve(void);
 
+void omap2420_init_early(void);
+void omap2430_init_early(void);
+void omap3430_init_early(void);
+void omap35xx_init_early(void);
+void omap3630_init_early(void);
+void am35xx_init_early(void);
+void ti816x_init_early(void);
+void omap4430_init_early(void);
+
 /*
  * IO bases for various OMAP processors
  * Except the tap base, rest all the io bases
@@ -74,7 +83,11 @@ void omap2_set_globals_sdrc(struct omap_globals *);
 void omap2_set_globals_control(struct omap_globals *);
 void omap2_set_globals_prcm(struct omap_globals *);
 
+void omap242x_map_io(void);
+void omap243x_map_io(void);
 void omap3_map_io(void);
+void omap4_map_io(void);
+
 
 /**
  * omap_test_timeout - busy-loop, testing a condition
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 67b3d75884cd..2f9026942229 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -44,13 +44,6 @@
 
 int omap_type(void);
 
-struct omap_chip_id {
-        u16 oc;
-        u8 type;
-};
-
-#define OMAP_CHIP_INIT(x)       { .oc = x }
-
 /*
  * omap_rev bits:
  * CPU id bits  (0730, 1510, 1710, 2422...)     [31:16]
@@ -60,19 +53,6 @@ struct omap_chip_id {
 unsigned int omap_rev(void);
 
 /*
- * Define CPU revision bits
- *
- * Verbose meaning of the revision bits may be different for a silicon
- * family. This difference can be handled separately.
- */
-#define OMAP_REVBITS_00         0x00
-#define OMAP_REVBITS_01         0x01
-#define OMAP_REVBITS_02         0x02
-#define OMAP_REVBITS_03         0x03
-#define OMAP_REVBITS_04         0x04
-#define OMAP_REVBITS_05         0x05
-
-/*
  * Get the CPU revision for OMAP devices
  */
 #define GET_OMAP_REVISION()     ((omap_rev() >> 8) & 0xff)
@@ -262,7 +242,7 @@ IS_OMAP_TYPE(2422, 0x2422)
 IS_OMAP_TYPE(2423, 0x2423)
 IS_OMAP_TYPE(2430, 0x2430)
 IS_OMAP_TYPE(3430, 0x3430)
-IS_OMAP_TYPE(3505, 0x3505)
+IS_OMAP_TYPE(3505, 0x3517)
 IS_OMAP_TYPE(3517, 0x3517)
 
 #define cpu_is_omap310()                0
@@ -354,8 +334,9 @@ IS_OMAP_TYPE(3517, 0x3517)
                                                 (!omap3_has_sgx()) &&   \
                                                 (omap3_has_iva()))
 # define cpu_is_omap3530()              (cpu_is_omap3430())
-# define cpu_is_omap3505()              is_omap3505()
 # define cpu_is_omap3517()              is_omap3517()
+# define cpu_is_omap3505()              (cpu_is_omap3517() &&           \
+                                                !omap3_has_sgx())
 # undef cpu_is_omap3630
 # define cpu_is_omap3630()              is_omap363x()
 # define cpu_is_ti816x()                is_ti816x()
@@ -379,35 +360,31 @@ IS_OMAP_TYPE(3517, 0x3517)
 /* Various silicon revisions for omap2 */
 #define OMAP242X_CLASS          0x24200024
 #define OMAP2420_REV_ES1_0      OMAP242X_CLASS
-#define OMAP2420_REV_ES2_0      (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8))
+#define OMAP2420_REV_ES2_0      (OMAP242X_CLASS | (0x1 << 8))
 
 #define OMAP243X_CLASS          0x24300024
 #define OMAP2430_REV_ES1_0      OMAP243X_CLASS
 
 #define OMAP343X_CLASS          0x34300034
 #define OMAP3430_REV_ES1_0      OMAP343X_CLASS
-#define OMAP3430_REV_ES2_0      (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8))
-#define OMAP3430_REV_ES2_1      (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8))
-#define OMAP3430_REV_ES3_0      (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8))
-#define OMAP3430_REV_ES3_1      (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8))
-#define OMAP3430_REV_ES3_1_2    (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8))
+#define OMAP3430_REV_ES2_0      (OMAP343X_CLASS | (0x1 << 8))
+#define OMAP3430_REV_ES2_1      (OMAP343X_CLASS | (0x2 << 8))
+#define OMAP3430_REV_ES3_0      (OMAP343X_CLASS | (0x3 << 8))
+#define OMAP3430_REV_ES3_1      (OMAP343X_CLASS | (0x4 << 8))
+#define OMAP3430_REV_ES3_1_2    (OMAP343X_CLASS | (0x5 << 8))
 
 #define OMAP363X_CLASS          0x36300034
 #define OMAP3630_REV_ES1_0      OMAP363X_CLASS
-#define OMAP3630_REV_ES1_1      (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8))
-#define OMAP3630_REV_ES1_2      (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8))
+#define OMAP3630_REV_ES1_1      (OMAP363X_CLASS | (0x1 << 8))
+#define OMAP3630_REV_ES1_2      (OMAP363X_CLASS | (0x2 << 8))
 
-#define OMAP35XX_CLASS          0x35000034
-#define OMAP3503_REV(v)         (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
-#define OMAP3515_REV(v)         (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
-#define OMAP3525_REV(v)         (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
-#define OMAP3530_REV(v)         (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
-#define OMAP3505_REV(v)         (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
-#define OMAP3517_REV(v)         (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
+#define OMAP3517_CLASS          0x35170034
+#define OMAP3517_REV_ES1_0      OMAP3517_CLASS
+#define OMAP3517_REV_ES1_1      (OMAP3517_CLASS | (0x1 << 8))
 
 #define TI816X_CLASS            0x81600034
 #define TI8168_REV_ES1_0        TI816X_CLASS
-#define TI8168_REV_ES1_1        (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
+#define TI8168_REV_ES1_1        (TI816X_CLASS | (0x1 << 8))
 
 #define OMAP443X_CLASS          0x44300044
 #define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
@@ -418,61 +395,6 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP446X_CLASS          0x44600044
 #define OMAP4460_REV_ES1_0      (OMAP446X_CLASS | (0x10 << 8))
 
-/*
- * omap_chip bits
- *
- * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
- * valid on all chips of that type.  CHIP_IS_OMAP3430ES{1,2} indicates
- * something that is only valid on that particular ES revision.
- *
- * These bits may be ORed together to indicate structures that are
- * available on multiple chip types.
- *
- * To test whether a particular structure matches the current OMAP chip type,
- * use omap_chip_is().
- *
- */
-#define CHIP_IS_OMAP2420                (1 << 0)
-#define CHIP_IS_OMAP2430                (1 << 1)
-#define CHIP_IS_OMAP3430                (1 << 2)
-#define CHIP_IS_OMAP3430ES1             (1 << 3)
-#define CHIP_IS_OMAP3430ES2             (1 << 4)
-#define CHIP_IS_OMAP3430ES3_0           (1 << 5)
-#define CHIP_IS_OMAP3430ES3_1           (1 << 6)
-#define CHIP_IS_OMAP3630ES1             (1 << 7)
-#define CHIP_IS_OMAP4430ES1             (1 << 8)
-#define CHIP_IS_OMAP3630ES1_1           (1 << 9)
-#define CHIP_IS_OMAP3630ES1_2           (1 << 10)
-#define CHIP_IS_OMAP4430ES2             (1 << 11)
-#define CHIP_IS_OMAP4430ES2_1           (1 << 12)
-#define CHIP_IS_OMAP4430ES2_2           (1 << 13)
-#define CHIP_IS_TI816X                  (1 << 14)
-#define CHIP_IS_OMAP4460ES1_0           (1 << 15)
-
-#define CHIP_IS_OMAP24XX                (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
-
-#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1 |          \
-                                         CHIP_IS_OMAP4430ES2 |          \
-                                         CHIP_IS_OMAP4430ES2_1 |        \
-                                         CHIP_IS_OMAP4430ES2_2 |        \
-                                         CHIP_IS_OMAP4460ES1_0)
-
-/*
- * "GE" here represents "greater than or equal to" in terms of ES
- * levels.  So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
- * chips at ES2 and beyond, but not, for example, any OMAP lines after
- * OMAP3.
- */
-#define CHIP_GE_OMAP3430ES2             (CHIP_IS_OMAP3430ES2 | \
-                                         CHIP_IS_OMAP3430ES3_0 | \
-                                         CHIP_GE_OMAP3430ES3_1)
-#define CHIP_GE_OMAP3430ES3_1           (CHIP_IS_OMAP3430ES3_1 | \
-                                         CHIP_IS_OMAP3630ES1 | \
-                                         CHIP_GE_OMAP3630ES1_1)
-#define CHIP_GE_OMAP3630ES1_1           (CHIP_IS_OMAP3630ES1_1 | \
-                                         CHIP_IS_OMAP3630ES1_2)
-
-int omap_chip_is(struct omap_chip_id oci);
 void omap2_check_revision(void);
 
 /*
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index d72ec85c97e6..a93a00db93da 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -300,7 +300,7 @@ static inline void omap44xx_map_common_io(void)
 #endif
 
 extern void omap2_init_common_infrastructure(void);
-extern void omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
+extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                                       struct omap_sdrc_params *sdrc_cs1);
 
 #define __arch_ioremap  omap_ioremap
@@ -309,6 +309,8 @@ extern void omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
 void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
 void omap_iounmap(volatile void __iomem *addr);
 
+extern void __init omap_init_consistent_dma_size(void);
+
 #endif
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 9882c657b2d4..8fa74e2c9d6e 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -25,9 +25,7 @@
 #define __ASM_ARCH_OMAP_MCBSP_H
 
 #include <linux/spinlock.h>
-
-#include <mach/hardware.h>
-#include <plat/clock.h>
+#include <linux/clk.h>
 
 /* macro for building platform_device for McBSP ports */
 #define OMAP_MCBSP_PLATFORM_DEVICE(port_nr)             \
@@ -40,104 +38,60 @@ static struct platform_device omap_mcbsp##port_nr = {	\
 #define MCBSP_CONFIG_TYPE3      0x3
 #define MCBSP_CONFIG_TYPE4      0x4
 
-#define OMAP7XX_MCBSP1_BASE     0xfffb1000
-#define OMAP7XX_MCBSP2_BASE     0xfffb1800
-
-#define OMAP1510_MCBSP1_BASE    0xe1011800
-#define OMAP1510_MCBSP2_BASE    0xfffb1000
-#define OMAP1510_MCBSP3_BASE    0xe1017000
-
-#define OMAP1610_MCBSP1_BASE    0xe1011800
-#define OMAP1610_MCBSP2_BASE    0xfffb1000
-#define OMAP1610_MCBSP3_BASE    0xe1017000
-
-#ifdef CONFIG_ARCH_OMAP1
-
-#define OMAP_MCBSP_REG_DRR2     0x00
-#define OMAP_MCBSP_REG_DRR1     0x02
-#define OMAP_MCBSP_REG_DXR2     0x04
-#define OMAP_MCBSP_REG_DXR1     0x06
-#define OMAP_MCBSP_REG_DRR      0x02
-#define OMAP_MCBSP_REG_DXR      0x06
-#define OMAP_MCBSP_REG_SPCR2    0x08
-#define OMAP_MCBSP_REG_SPCR1    0x0a
-#define OMAP_MCBSP_REG_RCR2     0x0c
-#define OMAP_MCBSP_REG_RCR1     0x0e
-#define OMAP_MCBSP_REG_XCR2     0x10
-#define OMAP_MCBSP_REG_XCR1     0x12
-#define OMAP_MCBSP_REG_SRGR2    0x14
-#define OMAP_MCBSP_REG_SRGR1    0x16
-#define OMAP_MCBSP_REG_MCR2     0x18
-#define OMAP_MCBSP_REG_MCR1     0x1a
-#define OMAP_MCBSP_REG_RCERA    0x1c
-#define OMAP_MCBSP_REG_RCERB    0x1e
-#define OMAP_MCBSP_REG_XCERA    0x20
-#define OMAP_MCBSP_REG_XCERB    0x22
-#define OMAP_MCBSP_REG_PCR0     0x24
-#define OMAP_MCBSP_REG_RCERC    0x26
-#define OMAP_MCBSP_REG_RCERD    0x28
-#define OMAP_MCBSP_REG_XCERC    0x2A
-#define OMAP_MCBSP_REG_XCERD    0x2C
-#define OMAP_MCBSP_REG_RCERE    0x2E
-#define OMAP_MCBSP_REG_RCERF    0x30
-#define OMAP_MCBSP_REG_XCERE    0x32
-#define OMAP_MCBSP_REG_XCERF    0x34
-#define OMAP_MCBSP_REG_RCERG    0x36
-#define OMAP_MCBSP_REG_RCERH    0x38
-#define OMAP_MCBSP_REG_XCERG    0x3A
-#define OMAP_MCBSP_REG_XCERH    0x3C
-
-/* Dummy defines, these are not available on omap1 */
-#define OMAP_MCBSP_REG_XCCR     0x00
-#define OMAP_MCBSP_REG_RCCR     0x00
-
-#else
-
-#define OMAP_MCBSP_REG_DRR2     0x00
-#define OMAP_MCBSP_REG_DRR1     0x04
-#define OMAP_MCBSP_REG_DXR2     0x08
-#define OMAP_MCBSP_REG_DXR1     0x0C
-#define OMAP_MCBSP_REG_DRR      0x00
-#define OMAP_MCBSP_REG_DXR      0x08
-#define OMAP_MCBSP_REG_SPCR2    0x10
-#define OMAP_MCBSP_REG_SPCR1    0x14
-#define OMAP_MCBSP_REG_RCR2     0x18
-#define OMAP_MCBSP_REG_RCR1     0x1C
-#define OMAP_MCBSP_REG_XCR2     0x20
-#define OMAP_MCBSP_REG_XCR1     0x24
-#define OMAP_MCBSP_REG_SRGR2    0x28
-#define OMAP_MCBSP_REG_SRGR1    0x2C
-#define OMAP_MCBSP_REG_MCR2     0x30
-#define OMAP_MCBSP_REG_MCR1     0x34
-#define OMAP_MCBSP_REG_RCERA    0x38
-#define OMAP_MCBSP_REG_RCERB    0x3C
-#define OMAP_MCBSP_REG_XCERA    0x40
-#define OMAP_MCBSP_REG_XCERB    0x44
-#define OMAP_MCBSP_REG_PCR0     0x48
-#define OMAP_MCBSP_REG_RCERC    0x4C
-#define OMAP_MCBSP_REG_RCERD    0x50
-#define OMAP_MCBSP_REG_XCERC    0x54
-#define OMAP_MCBSP_REG_XCERD    0x58
-#define OMAP_MCBSP_REG_RCERE    0x5C
-#define OMAP_MCBSP_REG_RCERF    0x60
-#define OMAP_MCBSP_REG_XCERE    0x64
-#define OMAP_MCBSP_REG_XCERF    0x68
-#define OMAP_MCBSP_REG_RCERG    0x6C
-#define OMAP_MCBSP_REG_RCERH    0x70
-#define OMAP_MCBSP_REG_XCERG    0x74
-#define OMAP_MCBSP_REG_XCERH    0x78
-#define OMAP_MCBSP_REG_SYSCON   0x8C
-#define OMAP_MCBSP_REG_THRSH2   0x90
-#define OMAP_MCBSP_REG_THRSH1   0x94
-#define OMAP_MCBSP_REG_IRQST    0xA0
-#define OMAP_MCBSP_REG_IRQEN    0xA4
-#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
-#define OMAP_MCBSP_REG_XCCR     0xAC
-#define OMAP_MCBSP_REG_RCCR     0xB0
-#define OMAP_MCBSP_REG_XBUFFSTAT        0xB4
-#define OMAP_MCBSP_REG_RBUFFSTAT        0xB8
-#define OMAP_MCBSP_REG_SSELCR   0xBC
+/* McBSP register numbers. Register address offset = num * reg_step */
+enum {
+        /* Common registers */
+        OMAP_MCBSP_REG_SPCR2 = 4,
+        OMAP_MCBSP_REG_SPCR1,
+        OMAP_MCBSP_REG_RCR2,
+        OMAP_MCBSP_REG_RCR1,
+        OMAP_MCBSP_REG_XCR2,
+        OMAP_MCBSP_REG_XCR1,
+        OMAP_MCBSP_REG_SRGR2,
+        OMAP_MCBSP_REG_SRGR1,
+        OMAP_MCBSP_REG_MCR2,
+        OMAP_MCBSP_REG_MCR1,
+        OMAP_MCBSP_REG_RCERA,
+        OMAP_MCBSP_REG_RCERB,
+        OMAP_MCBSP_REG_XCERA,
+        OMAP_MCBSP_REG_XCERB,
+        OMAP_MCBSP_REG_PCR0,
+        OMAP_MCBSP_REG_RCERC,
+        OMAP_MCBSP_REG_RCERD,
+        OMAP_MCBSP_REG_XCERC,
+        OMAP_MCBSP_REG_XCERD,
+        OMAP_MCBSP_REG_RCERE,
+        OMAP_MCBSP_REG_RCERF,
+        OMAP_MCBSP_REG_XCERE,
+        OMAP_MCBSP_REG_XCERF,
+        OMAP_MCBSP_REG_RCERG,
+        OMAP_MCBSP_REG_RCERH,
+        OMAP_MCBSP_REG_XCERG,
+        OMAP_MCBSP_REG_XCERH,
+
+        /* OMAP1-OMAP2420 registers */
+        OMAP_MCBSP_REG_DRR2 = 0,
+        OMAP_MCBSP_REG_DRR1,
+        OMAP_MCBSP_REG_DXR2,
+        OMAP_MCBSP_REG_DXR1,
+
+        /* OMAP2430 and onwards */
+        OMAP_MCBSP_REG_DRR = 0,
+        OMAP_MCBSP_REG_DXR = 2,
+        OMAP_MCBSP_REG_SYSCON = 35,
+        OMAP_MCBSP_REG_THRSH2,
+        OMAP_MCBSP_REG_THRSH1,
+        OMAP_MCBSP_REG_IRQST = 40,
+        OMAP_MCBSP_REG_IRQEN,
+        OMAP_MCBSP_REG_WAKEUPEN,
+        OMAP_MCBSP_REG_XCCR,
+        OMAP_MCBSP_REG_RCCR,
+        OMAP_MCBSP_REG_XBUFFSTAT,
+        OMAP_MCBSP_REG_RBUFFSTAT,
+        OMAP_MCBSP_REG_SSELCR,
+};
 
+/* OMAP3 sidetone control registers */
 #define OMAP_ST_REG_REV         0x00
 #define OMAP_ST_REG_SYSCONFIG   0x10
 #define OMAP_ST_REG_IRQSTATUS   0x18
@@ -146,8 +100,6 @@ static struct platform_device omap_mcbsp##port_nr = {	\
 #define OMAP_ST_REG_SFIRCR      0x28
 #define OMAP_ST_REG_SSELCR      0x2C
 
-#endif
-
 /************************** McBSP SPCR1 bit definitions ***********************/
 #define RRST                    0x0001
 #define RRDY                    0x0002
@@ -344,20 +296,20 @@ typedef enum {
 struct omap_mcbsp_ops {
         void (*request)(unsigned int);
         void (*free)(unsigned int);
-        int (*set_clks_src)(u8, u8);
 };
 
 struct omap_mcbsp_platform_data {
-        unsigned long phys_base;
-        u8 dma_rx_sync, dma_tx_sync;
-        u16 rx_irq, tx_irq;
         struct omap_mcbsp_ops *ops;
-#ifdef CONFIG_ARCH_OMAP3
-        /* Sidetone block for McBSP 2 and 3 */
-        unsigned long phys_base_st;
-#endif
         u16 buffer_size;
-        unsigned int mcbsp_config_type;
+        u8 reg_size;
+        u8 reg_step;
+
+        /* McBSP platform and instance specific features */
+        bool has_wakeup; /* Wakeup capability */
+        bool has_ccr; /* Transceiver has configuration control registers */
+        int (*enable_st_clock)(unsigned int, bool);
+        int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src);
+        int (*mux_signal)(struct device *dev, const char *signal, const char *src);
 };
 
 struct omap_mcbsp_st_data {
@@ -389,14 +341,12 @@ struct omap_mcbsp {
         spinlock_t lock;
         struct omap_mcbsp_platform_data *pdata;
         struct clk *fclk;
-#ifdef CONFIG_ARCH_OMAP3
         struct omap_mcbsp_st_data *st_data;
         int dma_op_mode;
         u16 max_tx_thres;
         u16 max_rx_thres;
-#endif
         void *reg_cache;
-        unsigned int mcbsp_config_type;
+        int reg_cache_size;
 };
 
 /**
@@ -408,16 +358,10 @@ struct omap_mcbsp_dev_attr {
 };
 
 extern struct omap_mcbsp **mcbsp_ptr;
-extern int omap_mcbsp_count, omap_mcbsp_cache_size;
-
-#define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
-#define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
+extern int omap_mcbsp_count;
 
 int omap_mcbsp_init(void);
-void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
-                        struct omap_mcbsp_platform_data *config, int size);
 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
-#ifdef CONFIG_ARCH_OMAP3
 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
@@ -426,18 +370,6 @@ u16 omap_mcbsp_get_fifo_size(unsigned int id);
 u16 omap_mcbsp_get_tx_delay(unsigned int id);
 u16 omap_mcbsp_get_rx_delay(unsigned int id);
 int omap_mcbsp_get_dma_op_mode(unsigned int id);
-#else
-static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
-{ }
-static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
-{ }
-static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
-static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
-static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; }
-static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
-static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
-static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
-#endif
 int omap_mcbsp_request(unsigned int id);
 void omap_mcbsp_free(unsigned int id);
 void omap_mcbsp_start(unsigned int id, int tx, int rx);
@@ -453,21 +385,11 @@ void omap2_mcbsp1_mux_fsr_src(u8 mux);
 int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
 int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
 
-#ifdef CONFIG_ARCH_OMAP3
 /* Sidetone specific API */
 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
 int omap_st_enable(unsigned int id);
 int omap_st_disable(unsigned int id);
 int omap_st_is_enabled(unsigned int id);
-#else
-static inline int omap_st_set_chgain(unsigned int id, int channel,
-                                     s16 chgain) { return 0; }
-static inline int omap_st_get_chgain(unsigned int id, int channel,
-                                     s16 *chgain) { return 0; }
-static inline int omap_st_enable(unsigned int id) { return 0; }
-static inline int omap_st_disable(unsigned int id) { return 0; }
-static inline int omap_st_is_enabled(unsigned int id) {  return 0; }
-#endif
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h
index e6720aa2d553..7f9df6f1e113 100644
--- a/arch/arm/plat-omap/include/plat/memory.h
+++ b/arch/arm/plat-omap/include/plat/memory.h
@@ -85,18 +85,5 @@
 
 #endif  /* CONFIG_ARCH_OMAP15XX */
 
-/* Override the ARM default */
-#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
-
-#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0)
-#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
-#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2
-#endif
-
-#define CONSISTENT_DMA_SIZE \
-        (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024)
-
-#endif
-
 #endif
 
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index ee405b36df4b..d4d9b96f961e 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -68,7 +68,7 @@ extern struct device omap_device_parent;
  *
  */
 struct omap_device {
-        struct platform_device          pdev;
+        struct platform_device          *pdev;
         struct omap_hwmod               **hwmods;
         struct omap_device_pm_latency   *pm_lats;
         u32                             dev_wakeup_lat;
@@ -88,24 +88,18 @@ int omap_device_shutdown(struct platform_device *pdev);
 
 /* Core code interface */
 
-int omap_device_count_resources(struct omap_device *od);
-int omap_device_fill_resources(struct omap_device *od, struct resource *res);
-
-struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
+struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
                                       struct omap_hwmod *oh, void *pdata,
                                       int pdata_len,
                                       struct omap_device_pm_latency *pm_lats,
                                       int pm_lats_cnt, int is_early_device);
 
-struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
+struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
                                          struct omap_hwmod **oh, int oh_cnt,
                                          void *pdata, int pdata_len,
                                          struct omap_device_pm_latency *pm_lats,
                                          int pm_lats_cnt, int is_early_device);
 
-int omap_device_register(struct omap_device *od);
-int omap_early_device_register(struct omap_device *od);
-
 void __iomem *omap_device_get_rt_va(struct omap_device *od);
 
 /* OMAP PM interface */
@@ -122,11 +116,6 @@ int omap_device_enable_hwmods(struct omap_device *od);
 int omap_device_disable_clocks(struct omap_device *od);
 int omap_device_enable_clocks(struct omap_device *od);
 
-static inline void omap_device_disable_idle_on_suspend(struct omap_device *od)
-{
-        od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
-}
-
 /*
  * Entries should be kept in latency order ascending
  *
@@ -157,6 +146,17 @@ struct omap_device_pm_latency {
 #define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1)
 
 /* Get omap_device pointer from platform_device pointer */
-#define to_omap_device(x) container_of((x), struct omap_device, pdev)
+static inline struct omap_device *to_omap_device(struct platform_device *pdev)
+{
+        return pdev ? pdev->archdata.od : NULL;
+}
+
+static inline
+void omap_device_disable_idle_on_suspend(struct platform_device *pdev)
+{
+        struct omap_device *od = to_omap_device(pdev);
+
+        od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
+}
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 0e329ca88a70..9115aedd2124 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -496,7 +496,6 @@ struct omap_hwmod_class {
  * @_state: internal-use hwmod state
  * @_postsetup_state: internal-use state to leave the hwmod in after _setup()
  * @flags: hwmod flags (documented below)
- * @omap_chip: OMAP chips this hwmod is present on
  * @_lock: spinlock serializing operations on this hwmod
  * @node: list node for hwmod list (internal use)
  *
@@ -545,7 +544,6 @@ struct omap_hwmod {
         u8                              _int_flags;
         u8                              _state;
         u8                              _postsetup_state;
-        const struct omap_chip_id       omap_chip;
 };
 
 int omap_hwmod_register(struct omap_hwmod **ohs);
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index f1ecfa9fc61d..e9b0e23edd0a 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -12,6 +12,7 @@
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/mm.h>
+#include <linux/dma-mapping.h>
 
 #include <plat/omap7xx.h>
 #include <plat/omap1510.h>
@@ -139,3 +140,10 @@ void omap_iounmap(volatile void __iomem *addr)
                 __iounmap(addr);
 }
 EXPORT_SYMBOL(omap_iounmap);
+
+void __init omap_init_consistent_dma_size(void)
+{
+#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
+        init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
+#endif
+}
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 6c62af108710..4b15cd7926d7 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -24,45 +24,40 @@
 #include <linux/slab.h>
 
 #include <plat/mcbsp.h>
-#include <plat/omap_device.h>
 #include <linux/pm_runtime.h>
 
-/* XXX These "sideways" includes are a sign that something is wrong */
-#include "../mach-omap2/cm2xxx_3xxx.h"
-#include "../mach-omap2/cm-regbits-34xx.h"
-
 struct omap_mcbsp **mcbsp_ptr;
-int omap_mcbsp_count, omap_mcbsp_cache_size;
+int omap_mcbsp_count;
+
+#define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
+#define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
 
 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
 {
-        if (cpu_class_is_omap1()) {
-                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
-                __raw_writew((u16)val, mcbsp->io_base + reg);
-        } else if (cpu_is_omap2420()) {
-                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
-                __raw_writew((u16)val, mcbsp->io_base + reg);
+        void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
+
+        if (mcbsp->pdata->reg_size == 2) {
+                ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
+                __raw_writew((u16)val, addr);
         } else {
-                ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
-                __raw_writel(val, mcbsp->io_base + reg);
+                ((u32 *)mcbsp->reg_cache)[reg] = val;
+                __raw_writel(val, addr);
         }
 }
 
 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
 {
-        if (cpu_class_is_omap1()) {
-                return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
-                                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
-        } else if (cpu_is_omap2420()) {
-                return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
-                                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
+        void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
+
+        if (mcbsp->pdata->reg_size == 2) {
+                return !from_cache ? __raw_readw(addr) :
+                                     ((u16 *)mcbsp->reg_cache)[reg];
         } else {
-                return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
-                                ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
+                return !from_cache ? __raw_readl(addr) :
+                                     ((u32 *)mcbsp->reg_cache)[reg];
         }
 }
 
-#ifdef CONFIG_ARCH_OMAP3
 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
 {
         __raw_writel(val, mcbsp->st_data->io_base_st + reg);
@@ -72,7 +67,6 @@ static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
 {
         return __raw_readl(mcbsp->st_data->io_base_st + reg);
 }
-#endif
 
 #define MCBSP_READ(mcbsp, reg) \
                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
@@ -187,7 +181,7 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
         MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
         MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
         MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
-        if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
+        if (mcbsp->pdata->has_ccr) {
                 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
                 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
         }
@@ -239,46 +233,28 @@ int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
         }
         mcbsp = id_to_mcbsp_ptr(id);
 
-        data_reg = mcbsp->phys_dma_base;
-
-        if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) {
+        if (mcbsp->pdata->reg_size == 2) {
                 if (stream)
-                        data_reg += OMAP_MCBSP_REG_DRR1;
+                        data_reg = OMAP_MCBSP_REG_DRR1;
                 else
-                        data_reg += OMAP_MCBSP_REG_DXR1;
+                        data_reg = OMAP_MCBSP_REG_DXR1;
         } else {
                 if (stream)
-                        data_reg += OMAP_MCBSP_REG_DRR;
+                        data_reg = OMAP_MCBSP_REG_DRR;
                 else
-                        data_reg += OMAP_MCBSP_REG_DXR;
+                        data_reg = OMAP_MCBSP_REG_DXR;
         }
 
-        return data_reg;
+        return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
 }
 EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
 
-#ifdef CONFIG_ARCH_OMAP3
-static struct omap_device *find_omap_device_by_dev(struct device *dev)
-{
-        struct platform_device *pdev = container_of(dev,
-                                        struct platform_device, dev);
-        return container_of(pdev, struct omap_device, pdev);
-}
-
 static void omap_st_on(struct omap_mcbsp *mcbsp)
 {
         unsigned int w;
-        struct omap_device *od;
 
-        od = find_omap_device_by_dev(mcbsp->dev);
-
-        /*
-         * Sidetone uses McBSP ICLK - which must not idle when sidetones
-         * are enabled or sidetones start sounding ugly.
-         */
-        w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
-        w &= ~(1 << (mcbsp->id - 2));
-        omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
+        if (mcbsp->pdata->enable_st_clock)
+                mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
 
         /* Enable McBSP Sidetone */
         w = MCBSP_READ(mcbsp, SSELCR);
@@ -292,9 +268,6 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
 static void omap_st_off(struct omap_mcbsp *mcbsp)
 {
         unsigned int w;
-        struct omap_device *od;
-
-        od = find_omap_device_by_dev(mcbsp->dev);
 
         w = MCBSP_ST_READ(mcbsp, SSELCR);
         MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
@@ -302,17 +275,13 @@ static void omap_st_off(struct omap_mcbsp *mcbsp)
         w = MCBSP_READ(mcbsp, SSELCR);
         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 
-        w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
-        w |= 1 << (mcbsp->id - 2);
-        omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
+        if (mcbsp->pdata->enable_st_clock)
+                mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
 }
 
 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 {
         u16 val, i;
-        struct omap_device *od;
-
-        od = find_omap_device_by_dev(mcbsp->dev);
 
         val = MCBSP_ST_READ(mcbsp, SSELCR);
 
@@ -340,9 +309,6 @@ static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 {
         u16 w;
         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
-        struct omap_device *od;
-
-        od = find_omap_device_by_dev(mcbsp->dev);
 
         w = MCBSP_ST_READ(mcbsp, SSELCR);
 
@@ -525,14 +491,13 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 {
         struct omap_mcbsp *mcbsp;
 
-        if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
-                return;
-
         if (!omap_mcbsp_check_valid_id(id)) {
                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
                 return;
         }
         mcbsp = id_to_mcbsp_ptr(id);
+        if (mcbsp->pdata->buffer_size == 0)
+                return;
 
         if (threshold && threshold <= mcbsp->max_tx_thres)
                 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
@@ -548,14 +513,13 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 {
         struct omap_mcbsp *mcbsp;
 
-        if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
-                return;
-
         if (!omap_mcbsp_check_valid_id(id)) {
                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
                 return;
         }
         mcbsp = id_to_mcbsp_ptr(id);
+        if (mcbsp->pdata->buffer_size == 0)
+                return;
 
         if (threshold && threshold <= mcbsp->max_rx_thres)
                 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
@@ -625,6 +589,8 @@ u16 omap_mcbsp_get_tx_delay(unsigned int id)
                 return -ENODEV;
         }
         mcbsp = id_to_mcbsp_ptr(id);
+        if (mcbsp->pdata->buffer_size == 0)
+                return 0;
 
         /* Returns the number of free locations in the buffer */
         buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
@@ -648,6 +614,8 @@ u16 omap_mcbsp_get_rx_delay(unsigned int id)
                 return -ENODEV;
         }
         mcbsp = id_to_mcbsp_ptr(id);
+        if (mcbsp->pdata->buffer_size == 0)
+                return 0;
 
         /* Returns the number of used locations in the buffer */
         buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
@@ -683,46 +651,6 @@ int omap_mcbsp_get_dma_op_mode(unsigned int id)
 }
 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 
-static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
-{
-        struct omap_device *od;
-
-        od = find_omap_device_by_dev(mcbsp->dev);
-        /*
-         * Enable wakup behavior, smart idle and all wakeups
-         * REVISIT: some wakeups may be unnecessary
-         */
-        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
-        }
-}
-
-static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
-{
-        struct omap_device *od;
-
-        od = find_omap_device_by_dev(mcbsp->dev);
-
-        /*
-         * Disable wakup behavior, smart idle and all wakeups
-         */
-        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                /*
-                 * HW bug workaround - If no_idle mode is taken, we need to
-                 * go to smart_idle before going to always_idle, or the
-                 * device will not hit retention anymore.
-                 */
-
-                MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
-        }
-}
-#else
-static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
-static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
-static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
-static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
-#endif
-
 int omap_mcbsp_request(unsigned int id)
 {
         struct omap_mcbsp *mcbsp;
@@ -735,7 +663,7 @@ int omap_mcbsp_request(unsigned int id)
         }
         mcbsp = id_to_mcbsp_ptr(id);
 
-        reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
+        reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
         if (!reg_cache) {
                 return -ENOMEM;
         }
@@ -757,8 +685,9 @@ int omap_mcbsp_request(unsigned int id)
 
         pm_runtime_get_sync(mcbsp->dev);
 
-        /* Do procedure specific to omap34xx arch, if applicable */
-        omap34xx_mcbsp_request(mcbsp);
+        /* Enable wakeup behavior */
+        if (mcbsp->pdata->has_wakeup)
+                MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
 
         /*
          * Make sure that transmitter, receiver and sample-rate generator are
@@ -795,8 +724,9 @@ err_clk_disable:
         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
                 mcbsp->pdata->ops->free(id);
 
-        /* Do procedure specific to omap34xx arch, if applicable */
-        omap34xx_mcbsp_free(mcbsp);
+        /* Disable wakeup behavior */
+        if (mcbsp->pdata->has_wakeup)
+                MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 
         pm_runtime_put_sync(mcbsp->dev);
 
@@ -825,8 +755,9 @@ void omap_mcbsp_free(unsigned int id)
         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
                 mcbsp->pdata->ops->free(id);
 
-        /* Do procedure specific to omap34xx arch, if applicable */
-        omap34xx_mcbsp_free(mcbsp);
+        /* Disable wakeup behavior */
+        if (mcbsp->pdata->has_wakeup)
+                MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 
         pm_runtime_put_sync(mcbsp->dev);
 
@@ -866,7 +797,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
         }
         mcbsp = id_to_mcbsp_ptr(id);
 
-        if (cpu_is_omap34xx())
+        if (mcbsp->st_data)
                 omap_st_start(mcbsp);
 
         /* Only enable SRG, if McBSP is master */
@@ -904,7 +835,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
         }
 
-        if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
+        if (mcbsp->pdata->has_ccr) {
                 /* Release the transmitter and receiver */
                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
                 w &= ~(tx ? XDISABLE : 0);
@@ -934,7 +865,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 
         /* Reset transmitter */
         tx &= 1;
-        if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
+        if (mcbsp->pdata->has_ccr) {
                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
                 w |= (tx ? XDISABLE : 0);
                 MCBSP_WRITE(mcbsp, XCCR, w);
@@ -944,7 +875,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 
         /* Reset receiver */
         rx &= 1;
-        if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
+        if (mcbsp->pdata->has_ccr) {
                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
                 w |= (rx ? RDISABLE : 0);
                 MCBSP_WRITE(mcbsp, RCCR, w);
@@ -961,39 +892,72 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
                 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
         }
 
-        if (cpu_is_omap34xx())
+        if (mcbsp->st_data)
                 omap_st_stop(mcbsp);
 }
 EXPORT_SYMBOL(omap_mcbsp_stop);
 
-/*
- * The following functions are only required on an OMAP1-only build.
- * mach-omap2/mcbsp.c contains the real functions
- */
-#ifndef CONFIG_ARCH_OMAP2PLUS
 int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
 {
-        WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
-             __func__);
-        return -EINVAL;
+        struct omap_mcbsp *mcbsp;
+        const char *src;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
+                return -EINVAL;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+
+        if (fck_src_id == MCBSP_CLKS_PAD_SRC)
+                src = "clks_ext";
+        else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
+                src = "clks_fclk";
+        else
+                return -EINVAL;
+
+        if (mcbsp->pdata->set_clk_src)
+                return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
+        else
+                return -EINVAL;
 }
+EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
 
 void omap2_mcbsp1_mux_clkr_src(u8 mux)
 {
-        WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
-             __func__);
-        return;
+        struct omap_mcbsp *mcbsp;
+        const char *src;
+
+        if (mux == CLKR_SRC_CLKR)
+                src = "clkr";
+        else if (mux == CLKR_SRC_CLKX)
+                src = "clkx";
+        else
+                return;
+
+        mcbsp = id_to_mcbsp_ptr(0);
+        if (mcbsp->pdata->mux_signal)
+                mcbsp->pdata->mux_signal(mcbsp->dev, "clkr", src);
 }
+EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src);
 
 void omap2_mcbsp1_mux_fsr_src(u8 mux)
 {
-        WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
-             __func__);
-        return;
+        struct omap_mcbsp *mcbsp;
+        const char *src;
+
+        if (mux == FSR_SRC_FSR)
+                src = "fsr";
+        else if (mux == FSR_SRC_FSX)
+                src = "fsx";
+        else
+                return;
+
+        mcbsp = id_to_mcbsp_ptr(0);
+        if (mcbsp->pdata->mux_signal)
+                mcbsp->pdata->mux_signal(mcbsp->dev, "fsr", src);
 }
-#endif
+EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
 
-#ifdef CONFIG_ARCH_OMAP3
 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
 #define valid_threshold(m, val)         ((val) <= max_thres(m))
 #define THRESHOLD_PROP_BUILDER(prop)                                    \
@@ -1084,6 +1048,17 @@ unlock:
 
 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
 
+static const struct attribute *additional_attrs[] = {
+        &dev_attr_max_tx_thres.attr,
+        &dev_attr_max_rx_thres.attr,
+        &dev_attr_dma_op_mode.attr,
+        NULL,
+};
+
+static const struct attribute_group additional_attr_group = {
+        .attrs = (struct attribute **)additional_attrs,
+};
+
 static ssize_t st_taps_show(struct device *dev,
                             struct device_attribute *attr, char *buf)
 {
@@ -1142,27 +1117,6 @@ out:
 
 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
 
-static const struct attribute *additional_attrs[] = {
-        &dev_attr_max_tx_thres.attr,
-        &dev_attr_max_rx_thres.attr,
-        &dev_attr_dma_op_mode.attr,
-        NULL,
-};
-
-static const struct attribute_group additional_attr_group = {
-        .attrs = (struct attribute **)additional_attrs,
-};
-
-static inline int __devinit omap_additional_add(struct device *dev)
-{
-        return sysfs_create_group(&dev->kobj, &additional_attr_group);
-}
-
-static inline void __devexit omap_additional_remove(struct device *dev)
-{
-        sysfs_remove_group(&dev->kobj, &additional_attr_group);
-}
-
 static const struct attribute *sidetone_attrs[] = {
         &dev_attr_st_taps.attr,
         NULL,
@@ -1172,10 +1126,9 @@ static const struct attribute_group sidetone_attr_group = {
         .attrs = (struct attribute **)sidetone_attrs,
 };
 
-static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
+static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
+                                 struct resource *res)
 {
-        struct platform_device *pdev;
-        struct resource *res;
         struct omap_mcbsp_st_data *st_data;
         int err;
 
@@ -1185,9 +1138,6 @@ static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
                 goto err1;
         }
 
-        pdev = container_of(mcbsp->dev, struct platform_device, dev);
-
-        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
         st_data->io_base_st = ioremap(res->start, resource_size(res));
         if (!st_data->io_base_st) {
                 err = -ENOMEM;
@@ -1214,59 +1164,10 @@ static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
 {
         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 
-        if (st_data) {
-                sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
-                iounmap(st_data->io_base_st);
-                kfree(st_data);
-        }
-}
-
-static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
-{
-        mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
-        if (cpu_is_omap34xx()) {
-                /*
-                 * Initially configure the maximum thresholds to a safe value.
-                 * The McBSP FIFO usage with these values should not go under
-                 * 16 locations.
-                 * If the whole FIFO without safety buffer is used, than there
-                 * is a possibility that the DMA will be not able to push the
-                 * new data on time, causing channel shifts in runtime.
-                 */
-                mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
-                mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
-                /*
-                 * REVISIT: Set dmap_op_mode to THRESHOLD as default
-                 * for mcbsp2 instances.
-                 */
-                if (omap_additional_add(mcbsp->dev))
-                        dev_warn(mcbsp->dev,
-                                "Unable to create additional controls\n");
-
-                if (mcbsp->id == 2 || mcbsp->id == 3)
-                        if (omap_st_add(mcbsp))
-                                dev_warn(mcbsp->dev,
-                                 "Unable to create sidetone controls\n");
-
-        } else {
-                mcbsp->max_tx_thres = -EINVAL;
-                mcbsp->max_rx_thres = -EINVAL;
-        }
-}
-
-static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
-{
-        if (cpu_is_omap34xx()) {
-                omap_additional_remove(mcbsp->dev);
-
-                if (mcbsp->id == 2 || mcbsp->id == 3)
-                        omap_st_remove(mcbsp);
-        }
+        sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
+        iounmap(st_data->io_base_st);
+        kfree(st_data);
 }
-#else
-static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
-static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
-#endif /* CONFIG_ARCH_OMAP3 */
 
 /*
  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
@@ -1316,7 +1217,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
                 }
         }
         mcbsp->phys_base = res->start;
-        omap_mcbsp_cache_size = resource_size(res);
+        mcbsp->reg_cache_size = resource_size(res);
         mcbsp->io_base = ioremap(res->start, resource_size(res));
         if (!mcbsp->io_base) {
                 ret = -ENOMEM;
@@ -1364,15 +1265,52 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
         mcbsp->pdata = pdata;
         mcbsp->dev = &pdev->dev;
         mcbsp_ptr[id] = mcbsp;
-        mcbsp->mcbsp_config_type = pdata->mcbsp_config_type;
         platform_set_drvdata(pdev, mcbsp);
         pm_runtime_enable(mcbsp->dev);
 
-        /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
-        omap34xx_device_init(mcbsp);
+        mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
+        if (mcbsp->pdata->buffer_size) {
+                /*
+                 * Initially configure the maximum thresholds to a safe value.
+                 * The McBSP FIFO usage with these values should not go under
+                 * 16 locations.
+                 * If the whole FIFO without safety buffer is used, than there
+                 * is a possibility that the DMA will be not able to push the
+                 * new data on time, causing channel shifts in runtime.
+                 */
+                mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
+                mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
+
+                ret = sysfs_create_group(&mcbsp->dev->kobj,
+                                         &additional_attr_group);
+                if (ret) {
+                        dev_err(mcbsp->dev,
+                                "Unable to create additional controls\n");
+                        goto err_thres;
+                }
+        } else {
+                mcbsp->max_tx_thres = -EINVAL;
+                mcbsp->max_rx_thres = -EINVAL;
+        }
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
+        if (res) {
+                ret = omap_st_add(mcbsp, res);
+                if (ret) {
+                        dev_err(mcbsp->dev,
+                                "Unable to create sidetone controls\n");
+                        goto err_st;
+                }
+        }
 
         return 0;
 
+err_st:
+        if (mcbsp->pdata->buffer_size)
+                sysfs_remove_group(&mcbsp->dev->kobj,
+                                   &additional_attr_group);
+err_thres:
+        clk_put(mcbsp->fclk);
 err_res:
         iounmap(mcbsp->io_base);
 err_ioremap:
@@ -1392,7 +1330,12 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
                                 mcbsp->pdata->ops->free)
                         mcbsp->pdata->ops->free(mcbsp->id);
 
-                omap34xx_device_exit(mcbsp);
+                if (mcbsp->pdata->buffer_size)
+                        sysfs_remove_group(&mcbsp->dev->kobj,
+                                           &additional_attr_group);
+
+                if (mcbsp->st_data)
+                        omap_st_remove(mcbsp);
 
                 clk_put(mcbsp->fclk);
 
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 02609eee0562..26aee5cc1fc1 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -94,6 +94,9 @@
 #define USE_WAKEUP_LAT                  0
 #define IGNORE_WAKEUP_LAT               1
 
+static int omap_device_register(struct platform_device *pdev);
+static int omap_early_device_register(struct platform_device *pdev);
+
 /* Private functions */
 
 /**
@@ -114,7 +117,7 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
 {
         struct timespec a, b, c;
 
-        pr_debug("omap_device: %s: activating\n", od->pdev.name);
+        dev_dbg(&od->pdev->dev, "omap_device: activating\n");
 
         while (od->pm_lat_level > 0) {
                 struct omap_device_pm_latency *odpl;
@@ -138,25 +141,24 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
                 c = timespec_sub(b, a);
                 act_lat = timespec_to_ns(&c);
 
-                pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time "
-                         "%llu nsec\n", od->pdev.name, od->pm_lat_level,
-                         act_lat);
+                dev_dbg(&od->pdev->dev,
+                        "omap_device: pm_lat %d: activate: elapsed time "
+                        "%llu nsec\n", od->pm_lat_level, act_lat);
 
                 if (act_lat > odpl->activate_lat) {
                         odpl->activate_lat_worst = act_lat;
                         if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
                                 odpl->activate_lat = act_lat;
-                                pr_warning("omap_device: %s.%d: new worst case "
-                                           "activate latency %d: %llu\n",
-                                           od->pdev.name, od->pdev.id,
-                                           od->pm_lat_level, act_lat);
+                                dev_dbg(&od->pdev->dev,
+                                        "new worst case activate latency "
+                                        "%d: %llu\n",
+                                        od->pm_lat_level, act_lat);
                         } else
-                                pr_warning("omap_device: %s.%d: activate "
-                                           "latency %d higher than exptected. "
-                                           "(%llu > %d)\n",
-                                           od->pdev.name, od->pdev.id,
-                                           od->pm_lat_level, act_lat,
-                                           odpl->activate_lat);
+                                dev_warn(&od->pdev->dev,
+                                         "activate latency %d "
+                                         "higher than exptected. (%llu > %d)\n",
+                                         od->pm_lat_level, act_lat,
+                                         odpl->activate_lat);
                 }
 
                 od->dev_wakeup_lat -= odpl->activate_lat;
@@ -183,7 +185,7 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
 {
         struct timespec a, b, c;
 
-        pr_debug("omap_device: %s: deactivating\n", od->pdev.name);
+        dev_dbg(&od->pdev->dev, "omap_device: deactivating\n");
 
         while (od->pm_lat_level < od->pm_lats_cnt) {
                 struct omap_device_pm_latency *odpl;
@@ -206,28 +208,26 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
                 c = timespec_sub(b, a);
                 deact_lat = timespec_to_ns(&c);
 
-                pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time "
-                         "%llu nsec\n", od->pdev.name, od->pm_lat_level,
-                         deact_lat);
+                dev_dbg(&od->pdev->dev,
+                        "omap_device: pm_lat %d: deactivate: elapsed time "
+                        "%llu nsec\n", od->pm_lat_level, deact_lat);
 
                 if (deact_lat > odpl->deactivate_lat) {
                         odpl->deactivate_lat_worst = deact_lat;
                         if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
                                 odpl->deactivate_lat = deact_lat;
-                                pr_warning("omap_device: %s.%d: new worst case "
-                                           "deactivate latency %d: %llu\n",
-                                           od->pdev.name, od->pdev.id,
-                                           od->pm_lat_level, deact_lat);
+                                dev_dbg(&od->pdev->dev,
+                                        "new worst case deactivate latency "
+                                        "%d: %llu\n",
+                                        od->pm_lat_level, deact_lat);
                         } else
-                                pr_warning("omap_device: %s.%d: deactivate "
-                                           "latency %d higher than exptected. "
-                                           "(%llu > %d)\n",
-                                           od->pdev.name, od->pdev.id,
-                                           od->pm_lat_level, deact_lat,
-                                           odpl->deactivate_lat);
+                                dev_warn(&od->pdev->dev,
+                                         "deactivate latency %d "
+                                         "higher than exptected. (%llu > %d)\n",
+                                         od->pm_lat_level, deact_lat,
+                                         odpl->deactivate_lat);
                 }
 
-
                 od->dev_wakeup_lat += odpl->activate_lat;
 
                 od->pm_lat_level++;
@@ -245,28 +245,27 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
         if (!clk_alias || !clk_name)
                 return;
 
-        pr_debug("omap_device: %s: Creating %s -> %s\n",
-                 dev_name(&od->pdev.dev), clk_alias, clk_name);
+        dev_dbg(&od->pdev->dev, "Creating %s -> %s\n", clk_alias, clk_name);
 
-        r = clk_get_sys(dev_name(&od->pdev.dev), clk_alias);
+        r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
         if (!IS_ERR(r)) {
-                pr_warning("omap_device: %s: alias %s already exists\n",
-                           dev_name(&od->pdev.dev), clk_alias);
+                dev_warn(&od->pdev->dev,
+                         "alias %s already exists\n", clk_alias);
                 clk_put(r);
                 return;
         }
 
         r = omap_clk_get_by_name(clk_name);
         if (IS_ERR(r)) {
-                pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
-                       dev_name(&od->pdev.dev), clk_name);
+                dev_err(&od->pdev->dev,
+                        "omap_clk_get_by_name for %s failed\n", clk_name);
                 return;
         }
 
-        l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev.dev));
+        l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev->dev));
         if (!l) {
-                pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
-                       dev_name(&od->pdev.dev), clk_alias);
+                dev_err(&od->pdev->dev,
+                        "clkdev_alloc for %s failed\n", clk_alias);
                 return;
         }
 
@@ -343,7 +342,7 @@ u32 omap_device_get_context_loss_count(struct platform_device *pdev)
  * much memory to allocate before calling
  * omap_device_fill_resources().  Returns the count.
  */
-int omap_device_count_resources(struct omap_device *od)
+static int omap_device_count_resources(struct omap_device *od)
 {
         int c = 0;
         int i;
@@ -352,7 +351,7 @@ int omap_device_count_resources(struct omap_device *od)
                 c += omap_hwmod_count_resources(od->hwmods[i]);
 
         pr_debug("omap_device: %s: counted %d total resources across %d "
-                 "hwmods\n", od->pdev.name, c, od->hwmods_cnt);
+                 "hwmods\n", od->pdev->name, c, od->hwmods_cnt);
 
         return c;
 }
@@ -374,7 +373,8 @@ int omap_device_count_resources(struct omap_device *od)
  * functions to get device resources.  Hacking around the existing
  * platform_device code wastes memory.  Returns 0.
  */
-int omap_device_fill_resources(struct omap_device *od, struct resource *res)
+static int omap_device_fill_resources(struct omap_device *od,
+                                      struct resource *res)
 {
         int c = 0;
         int i, r;
@@ -405,7 +405,7 @@ int omap_device_fill_resources(struct omap_device *od, struct resource *res)
  * information.  Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
  * passes along the return value of omap_device_build_ss().
  */
-struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
+struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
                                       struct omap_hwmod *oh, void *pdata,
                                       int pdata_len,
                                       struct omap_device_pm_latency *pm_lats,
@@ -438,15 +438,15 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
  * platform_device record.  Returns an ERR_PTR() on error, or passes
  * along the return value of omap_device_register().
  */
-struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
+struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
                                          struct omap_hwmod **ohs, int oh_cnt,
                                          void *pdata, int pdata_len,
                                          struct omap_device_pm_latency *pm_lats,
                                          int pm_lats_cnt, int is_early_device)
 {
         int ret = -ENOMEM;
+        struct platform_device *pdev;
         struct omap_device *od;
-        char *pdev_name2;
         struct resource *res = NULL;
         int i, res_count;
         struct omap_hwmod **hwmods;
@@ -457,72 +457,76 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
         if (!pdata && pdata_len > 0)
                 return ERR_PTR(-EINVAL);
 
+        pdev = platform_device_alloc(pdev_name, pdev_id);
+        if (!pdev) {
+                ret = -ENOMEM;
+                goto odbs_exit;
+        }
+
         pr_debug("omap_device: %s: building with %d hwmods\n", pdev_name,
                  oh_cnt);
 
         od = kzalloc(sizeof(struct omap_device), GFP_KERNEL);
-        if (!od)
-                return ERR_PTR(-ENOMEM);
-
+        if (!od) {
+                ret = -ENOMEM;
+                goto odbs_exit1;
+        }
         od->hwmods_cnt = oh_cnt;
 
         hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt,
                          GFP_KERNEL);
         if (!hwmods)
-                goto odbs_exit1;
+                goto odbs_exit2;
 
         memcpy(hwmods, ohs, sizeof(struct omap_hwmod *) * oh_cnt);
         od->hwmods = hwmods;
-
-        pdev_name2 = kzalloc(strlen(pdev_name) + 1, GFP_KERNEL);
-        if (!pdev_name2)
-                goto odbs_exit2;
-        strcpy(pdev_name2, pdev_name);
-
-        od->pdev.name = pdev_name2;
-        od->pdev.id = pdev_id;
+        od->pdev = pdev;
 
         res_count = omap_device_count_resources(od);
         if (res_count > 0) {
                 res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
                 if (!res)
                         goto odbs_exit3;
-        }
-        omap_device_fill_resources(od, res);
 
-        od->pdev.num_resources = res_count;
-        od->pdev.resource = res;
+                omap_device_fill_resources(od, res);
+
+                ret = platform_device_add_resources(pdev, res, res_count);
+                kfree(res);
 
-        ret = platform_device_add_data(&od->pdev, pdata, pdata_len);
+                if (ret)
+                        goto odbs_exit3;
+        }
+
+        ret = platform_device_add_data(pdev, pdata, pdata_len);
         if (ret)
-                goto odbs_exit4;
+                goto odbs_exit3;
 
-        od->pm_lats = pm_lats;
-        od->pm_lats_cnt = pm_lats_cnt;
+        pdev->archdata.od = od;
 
         if (is_early_device)
-                ret = omap_early_device_register(od);
+                ret = omap_early_device_register(pdev);
         else
-                ret = omap_device_register(od);
+                ret = omap_device_register(pdev);
+        if (ret)
+                goto odbs_exit3;
+
+        od->pm_lats = pm_lats;
+        od->pm_lats_cnt = pm_lats_cnt;
 
         for (i = 0; i < oh_cnt; i++) {
                 hwmods[i]->od = od;
                 _add_hwmod_clocks_clkdev(od, hwmods[i]);
         }
 
-        if (ret)
-                goto odbs_exit4;
-
-        return od;
+        return pdev;
 
-odbs_exit4:
-        kfree(res);
 odbs_exit3:
-        kfree(pdev_name2);
-odbs_exit2:
         kfree(hwmods);
-odbs_exit1:
+odbs_exit2:
         kfree(od);
+odbs_exit1:
+        platform_device_put(pdev);
+odbs_exit:
 
         pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret);
 
@@ -538,11 +542,11 @@ odbs_exit1:
  * platform_early_add_device() on the underlying platform_device.
  * Returns 0 by default.
  */
-int omap_early_device_register(struct omap_device *od)
+static int omap_early_device_register(struct platform_device *pdev)
 {
         struct platform_device *devices[1];
 
-        devices[0] = &(od->pdev);
+        devices[0] = pdev;
         early_platform_add_devices(devices, 1);
         return 0;
 }
@@ -638,13 +642,13 @@ static struct dev_pm_domain omap_device_pm_domain = {
  * platform_device_register() on the underlying platform_device.
  * Returns the return value of platform_device_register().
  */
-int omap_device_register(struct omap_device *od)
+static int omap_device_register(struct platform_device *pdev)
 {
-        pr_debug("omap_device: %s: registering\n", od->pdev.name);
+        pr_debug("omap_device: %s: registering\n", pdev->name);
 
-        od->pdev.dev.parent = &omap_device_parent;
-        od->pdev.dev.pm_domain = &omap_device_pm_domain;
-        return platform_device_register(&od->pdev);
+        pdev->dev.parent = &omap_device_parent;
+        pdev->dev.pm_domain = &omap_device_pm_domain;
+        return platform_device_add(pdev);
 }
 
 
@@ -671,8 +675,9 @@ int omap_device_enable(struct platform_device *pdev)
         od = to_omap_device(pdev);
 
         if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
-                WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
-                     od->pdev.name, od->pdev.id, __func__, od->_state);
+                dev_warn(&pdev->dev,
+                         "omap_device: %s() called from invalid state %d\n",
+                         __func__, od->_state);
                 return -EINVAL;
         }
 
@@ -710,8 +715,9 @@ int omap_device_idle(struct platform_device *pdev)
         od = to_omap_device(pdev);
 
         if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
-                WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
-                     od->pdev.name, od->pdev.id, __func__, od->_state);
+                dev_warn(&pdev->dev,
+                         "omap_device: %s() called from invalid state %d\n",
+                         __func__, od->_state);
                 return -EINVAL;
         }
 
@@ -742,8 +748,9 @@ int omap_device_shutdown(struct platform_device *pdev)
 
         if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
             od->_state != OMAP_DEVICE_STATE_IDLE) {
-                WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
-                     od->pdev.name, od->pdev.id, __func__, od->_state);
+                dev_warn(&pdev->dev,
+                         "omap_device: %s() called from invalid state %d\n",
+                         __func__, od->_state);
                 return -EINVAL;
         }
 
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h
deleted file mode 100644
index bd534d32b993..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/map.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/map.h
- *
- * Copyright (c) 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_S3C24XX_MAP_H
-#define __ASM_PLAT_S3C24XX_MAP_H
-
-/* interrupt controller is the first thing we put in, to make
- * the assembly code for the irq detection easier
- */
-#define S3C24XX_VA_IRQ     S3C_VA_IRQ
-#define S3C2410_PA_IRQ     (0x4A000000)
-#define S3C24XX_SZ_IRQ     SZ_1M
-
-/* memory controller registers */
-#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
-#define S3C2410_PA_MEMCTRL (0x48000000)
-#define S3C24XX_SZ_MEMCTRL SZ_1M
-
-/* UARTs */
-#define S3C24XX_VA_UART    S3C_VA_UART
-#define S3C2410_PA_UART    (0x50000000)
-#define S3C24XX_SZ_UART    SZ_1M
-#define S3C_UART_OFFSET    (0x4000)
-
-#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
-
-/* Timers */
-#define S3C24XX_VA_TIMER   S3C_VA_TIMER
-#define S3C2410_PA_TIMER   (0x51000000)
-#define S3C24XX_SZ_TIMER   SZ_1M
-
-/* Clock and Power management */
-#define S3C24XX_VA_CLKPWR  S3C_VA_SYS
-#define S3C24XX_SZ_CLKPWR  SZ_1M
-
-/* USB Device port */
-#define S3C2410_PA_USBDEV  (0x52000000)
-#define S3C24XX_SZ_USBDEV  SZ_1M
-
-/* Watchdog */
-#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
-#define S3C2410_PA_WATCHDOG (0x53000000)
-#define S3C24XX_SZ_WATCHDOG SZ_1M
-
-/* Standard size definitions for peripheral blocks. */
-
-#define S3C24XX_SZ_IIS          SZ_1M
-#define S3C24XX_SZ_ADC          SZ_1M
-#define S3C24XX_SZ_SPI          SZ_1M
-#define S3C24XX_SZ_SDI          SZ_1M
-#define S3C24XX_SZ_NAND         SZ_1M
-
-/* GPIO ports */
-
-/* the calculation for the VA of this must ensure that
- * it is the same distance apart from the UART in the
- * phsyical address space, as the initial mapping for the IO
- * is done as a 1:1 mapping. This puts it (currently) at
- * 0xFA800000, which is not in the way of any current mapping
- * by the base system.
-*/
-
-#define S3C2410_PA_GPIO    (0x56000000)
-#define S3C24XX_VA_GPIO    ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
-#define S3C24XX_SZ_GPIO    SZ_1M
-
-
-/* ISA style IO, for each machine to sort out mappings for, if it
- * implements it. We reserve two 16M regions for ISA.
- */
-
-#define S3C24XX_VA_ISA_WORD  S3C2410_ADDR(0x02000000)
-#define S3C24XX_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)
-
-/* deal with the registers that move under the 2412/2413 */
-
-#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
-#ifndef __ASSEMBLY__
-extern void __iomem *s3c24xx_va_gpio2;
-#endif
-#ifdef CONFIG_CPU_S3C2412_ONLY
-#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
-#else
-#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
-#endif
-#else
-#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
-#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
-#endif
-
-#endif /* __ASM_PLAT_S3C24XX_MAP_H */
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h
index bf28fadee7ae..ebc142c5c84c 100644
--- a/arch/arm/plat-s5p/include/plat/pll.h
+++ b/arch/arm/plat-s5p/include/plat/pll.h
@@ -72,7 +72,6 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
         mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
         pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
         sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
-        kdiv = pll_con1 & PLL46XX_KDIV_MASK;
 
         if (pll_type == pll_4650c)
                 kdiv = pll_con1 & PLL4650C_KDIV_MASK;
diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c
index db7a65c7f127..06825c4276de 100644
--- a/arch/arm/plat-samsung/dev-hsmmc.c
+++ b/arch/arm/plat-samsung/dev-hsmmc.c
@@ -58,22 +58,5 @@ struct platform_device s3c_device_hsmmc0 = {
 
 void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
 {
-        struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
-
-        set->cd_type = pd->cd_type;
-        set->ext_cd_init = pd->ext_cd_init;
-        set->ext_cd_cleanup = pd->ext_cd_cleanup;
-        set->ext_cd_gpio = pd->ext_cd_gpio;
-        set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
-
-        if (pd->max_width)
-                set->max_width = pd->max_width;
-        if (pd->cfg_gpio)
-                set->cfg_gpio = pd->cfg_gpio;
-        if (pd->cfg_card)
-                set->cfg_card = pd->cfg_card;
-        if (pd->host_caps)
-                set->host_caps |= pd->host_caps;
-        if (pd->clk_type)
-                set->clk_type = pd->clk_type;
+        s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c
index 2497321f08d7..4524ef440010 100644
--- a/arch/arm/plat-samsung/dev-hsmmc1.c
+++ b/arch/arm/plat-samsung/dev-hsmmc1.c
@@ -58,22 +58,5 @@ struct platform_device s3c_device_hsmmc1 = {
 
 void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
 {
-        struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
-
-        set->cd_type = pd->cd_type;
-        set->ext_cd_init = pd->ext_cd_init;
-        set->ext_cd_cleanup = pd->ext_cd_cleanup;
-        set->ext_cd_gpio = pd->ext_cd_gpio;
-        set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
-
-        if (pd->max_width)
-                set->max_width = pd->max_width;
-        if (pd->cfg_gpio)
-                set->cfg_gpio = pd->cfg_gpio;
-        if (pd->cfg_card)
-                set->cfg_card = pd->cfg_card;
-        if (pd->host_caps)
-                set->host_caps |= pd->host_caps;
-        if (pd->clk_type)
-                set->clk_type = pd->clk_type;
+        s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c
index f60aedba417c..9cede9615e48 100644
--- a/arch/arm/plat-samsung/dev-hsmmc2.c
+++ b/arch/arm/plat-samsung/dev-hsmmc2.c
@@ -59,22 +59,5 @@ struct platform_device s3c_device_hsmmc2 = {
 
 void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
 {
-        struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata;
-
-        set->cd_type = pd->cd_type;
-        set->ext_cd_init = pd->ext_cd_init;
-        set->ext_cd_cleanup = pd->ext_cd_cleanup;
-        set->ext_cd_gpio = pd->ext_cd_gpio;
-        set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
-
-        if (pd->max_width)
-                set->max_width = pd->max_width;
-        if (pd->cfg_gpio)
-                set->cfg_gpio = pd->cfg_gpio;
-        if (pd->cfg_card)
-                set->cfg_card = pd->cfg_card;
-        if (pd->host_caps)
-                set->host_caps |= pd->host_caps;
-        if (pd->clk_type)
-                set->clk_type = pd->clk_type;
+        s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c
index ede776f20e62..0358ef4a8f66 100644
--- a/arch/arm/plat-samsung/dev-hsmmc3.c
+++ b/arch/arm/plat-samsung/dev-hsmmc3.c
@@ -62,22 +62,5 @@ struct platform_device s3c_device_hsmmc3 = {
 
 void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
 {
-        struct s3c_sdhci_platdata *set = &s3c_hsmmc3_def_platdata;
-
-        set->cd_type = pd->cd_type;
-        set->ext_cd_init = pd->ext_cd_init;
-        set->ext_cd_cleanup = pd->ext_cd_cleanup;
-        set->ext_cd_gpio = pd->ext_cd_gpio;
-        set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
-
-        if (pd->max_width)
-                set->max_width = pd->max_width;
-        if (pd->cfg_gpio)
-                set->cfg_gpio = pd->cfg_gpio;
-        if (pd->cfg_card)
-                set->cfg_card = pd->cfg_card;
-        if (pd->host_caps)
-                set->host_caps |= pd->host_caps;
-        if (pd->clk_type)
-                set->clk_type = pd->clk_type;
+        s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
 }
diff --git a/arch/arm/plat-samsung/dev-ts.c b/arch/arm/plat-samsung/dev-ts.c
index 82543f0248ac..5f3d46a9bd88 100644
--- a/arch/arm/plat-samsung/dev-ts.c
+++ b/arch/arm/plat-samsung/dev-ts.c
@@ -43,8 +43,17 @@ struct platform_device s3c_device_ts = {
         .resource       = s3c_ts_resource,
 };
 
+static struct s3c2410_ts_mach_info default_ts_data __initdata = {
+        .delay                  = 10000,
+        .presc                  = 49,
+        .oversampling_shift     = 2,
+};
+
 void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
 {
+        if (!pd)
+                pd = &default_ts_data;
+
         s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
                          &s3c_device_ts);
 }
diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
index 336d5ac02035..ab9bce637cbd 100644
--- a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
+++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
@@ -18,11 +18,6 @@ extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
 #define DMA_CH_VALID            (1<<31)
 #define DMA_CH_NEVER            (1<<30)
 
-struct s3c24xx_dma_addr {
-        unsigned long           from;
-        unsigned long           to;
-};
-
 /* struct s3c24xx_dma_map
  *
  * this holds the mapping information for the channel selected
@@ -31,7 +26,6 @@ struct s3c24xx_dma_addr {
 
 struct s3c24xx_dma_map {
         const char              *name;
-        struct s3c24xx_dma_addr  hw_addr;
 
         unsigned long            channels[S3C_DMA_CHANNELS];
         unsigned long            channels_rx[S3C_DMA_CHANNELS];
diff --git a/arch/arm/plat-samsung/include/plat/map-s3c.h b/arch/arm/plat-samsung/include/plat/map-s3c.h
new file mode 100644
index 000000000000..7d048759b772
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/map-s3c.h
@@ -0,0 +1,84 @@
+/* linux/arch/arm/plat-samsung/include/plat/map-s3c.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_MAP_S3C_H
+#define __ASM_PLAT_MAP_S3C_H __FILE__
+
+#define S3C24XX_VA_IRQ          S3C_VA_IRQ
+#define S3C24XX_VA_MEMCTRL      S3C_VA_MEM
+#define S3C24XX_VA_UART         S3C_VA_UART
+
+#define S3C24XX_VA_TIMER        S3C_VA_TIMER
+#define S3C24XX_VA_CLKPWR       S3C_VA_SYS
+#define S3C24XX_VA_WATCHDOG     S3C_VA_WATCHDOG
+
+#define S3C2412_VA_SSMC         S3C_ADDR_CPU(0x00000000)
+#define S3C2412_VA_EBI          S3C_ADDR_CPU(0x00010000)
+
+#define S3C2410_PA_UART         (0x50000000)
+#define S3C24XX_PA_UART         S3C2410_PA_UART
+
+#ifndef S3C_UART_OFFSET
+#define S3C_UART_OFFSET         (0x400)
+#endif
+
+/*
+ * GPIO ports
+ *
+ * the calculation for the VA of this must ensure that
+ * it is the same distance apart from the UART in the
+ * phsyical address space, as the initial mapping for the IO
+ * is done as a 1:1 mapping. This puts it (currently) at
+ * 0xFA800000, which is not in the way of any current mapping
+ * by the base system.
+*/
+
+#define S3C2410_PA_GPIO         (0x56000000)
+#define S3C24XX_PA_GPIO         S3C2410_PA_GPIO
+
+#define S3C24XX_VA_GPIO         ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
+#define S3C64XX_VA_GPIO         S3C_ADDR_CPU(0x00000000)
+
+#define S3C64XX_VA_MODEM        S3C_ADDR_CPU(0x00100000)
+#define S3C64XX_VA_USB_HSPHY    S3C_ADDR_CPU(0x00200000)
+
+#define S3C_VA_USB_HSPHY        S3C64XX_VA_USB_HSPHY
+
+/*
+ * ISA style IO, for each machine to sort out mappings for,
+ * if it implements it. We reserve two 16M regions for ISA.
+ */
+
+#define S3C2410_ADDR(x)         S3C_ADDR(x)
+
+#define S3C24XX_VA_ISA_WORD     S3C2410_ADDR(0x02000000)
+#define S3C24XX_VA_ISA_BYTE     S3C2410_ADDR(0x03000000)
+
+/* deal with the registers that move under the 2412/2413 */
+
+#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+#ifndef __ASSEMBLY__
+extern void __iomem *s3c24xx_va_gpio2;
+#endif
+#ifdef CONFIG_CPU_S3C2412_ONLY
+#define S3C24XX_VA_GPIO2        (S3C24XX_VA_GPIO + 0x10)
+#else
+#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
+#endif
+#else
+#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
+#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
+#endif
+
+#include <plat/map-s5p.h>
+
+#endif /* __ASM_PLAT_MAP_S3C_H */
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index 36d3551173b2..c2d7bdae5891 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5p/include/plat/map-s5p.h
+/* linux/arch/arm/plat-samsung/include/plat/map-s5p.h
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
@@ -40,8 +40,6 @@
 #define S5P_VA_GIC_CPU          S3C_ADDR(0x02810000)
 #define S5P_VA_GIC_DIST         S3C_ADDR(0x02820000)
 
-#define S3C_VA_USB_HSPHY        S3C_ADDR(0x02900000)
-
 #define VA_VIC(x)               (S3C_VA_IRQ + ((x) * 0x10000))
 #define VA_VIC0                 VA_VIC(0)
 #define VA_VIC1                 VA_VIC(1)
@@ -58,4 +56,6 @@
 #define S3C_UART_OFFSET         (0x400)
 #endif
 
+#include <plat/map-s3c.h>
+
 #endif /* __ASM_PLAT_MAP_S5P_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 058e09654fe8..4a6552066c7e 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -86,6 +86,13 @@ struct s3c_sdhci_platdata {
                             struct mmc_card *card);
 };
 
+/* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data
+ * @pd: The default platform data for this device.
+ * @set: Pointer to the platform data to fill in.
+ */
+extern void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd,
+                                    struct s3c_sdhci_platdata *set);
+
 /**
  * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device.
  * @pd: Platform data to register to device.
diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/plat-samsung/platformdata.c
index 7cf2e1e3b20f..6de1a3825927 100644
--- a/arch/arm/plat-samsung/platformdata.c
+++ b/arch/arm/plat-samsung/platformdata.c
@@ -14,6 +14,7 @@
 #include <linux/platform_device.h>
 
 #include <plat/devs.h>
+#include <plat/sdhci.h>
 
 void __init *s3c_set_platdata(void *pd, size_t pdsize,
                               struct platform_device *pdev)
@@ -35,3 +36,24 @@ void __init *s3c_set_platdata(void *pd, size_t pdsize,
         pdev->dev.platform_data = npd;
         return npd;
 }
+
+void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd,
+                             struct s3c_sdhci_platdata *set)
+{
+        set->cd_type = pd->cd_type;
+        set->ext_cd_init = pd->ext_cd_init;
+        set->ext_cd_cleanup = pd->ext_cd_cleanup;
+        set->ext_cd_gpio = pd->ext_cd_gpio;
+        set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
+
+        if (pd->max_width)
+                set->max_width = pd->max_width;
+        if (pd->cfg_gpio)
+                set->cfg_gpio = pd->cfg_gpio;
+        if (pd->cfg_card)
+                set->cfg_card = pd->cfg_card;
+        if (pd->host_caps)
+                set->host_caps |= pd->host_caps;
+        if (pd->clk_type)
+                set->clk_type = pd->clk_type;
+}
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 79bcb4316930..0cbd5a0a9332 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -11,6 +11,7 @@
 #include <linux/module.h>
 #include <linux/types.h>
 #include <linux/cpu.h>
+#include <linux/cpu_pm.h>
 #include <linux/kernel.h>
 #include <linux/notifier.h>
 #include <linux/signal.h>
@@ -68,7 +69,7 @@ static bool vfp_state_in_hw(unsigned int cpu, struct thread_info *thread)
 /*
  * Force a reload of the VFP context from the thread structure.  We do
  * this by ensuring that access to the VFP hardware is disabled, and
- * clear last_VFP_context.  Must be called from non-preemptible context.
+ * clear vfp_current_hw_state.  Must be called from non-preemptible context.
  */
 static void vfp_force_reload(unsigned int cpu, struct thread_info *thread)
 {
@@ -436,9 +437,7 @@ static void vfp_enable(void *unused)
         set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
 }
 
-#ifdef CONFIG_PM
-#include <linux/syscore_ops.h>
-
+#ifdef CONFIG_CPU_PM
 static int vfp_pm_suspend(void)
 {
         struct thread_info *ti = current_thread_info();
@@ -468,19 +467,33 @@ static void vfp_pm_resume(void)
         fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
 }
 
-static struct syscore_ops vfp_pm_syscore_ops = {
-        .suspend        = vfp_pm_suspend,
-        .resume         = vfp_pm_resume,
+static int vfp_cpu_pm_notifier(struct notifier_block *self, unsigned long cmd,
+        void *v)
+{
+        switch (cmd) {
+        case CPU_PM_ENTER:
+                vfp_pm_suspend();
+                break;
+        case CPU_PM_ENTER_FAILED:
+        case CPU_PM_EXIT:
+                vfp_pm_resume();
+                break;
+        }
+        return NOTIFY_OK;
+}
+
+static struct notifier_block vfp_cpu_pm_notifier_block = {
+        .notifier_call = vfp_cpu_pm_notifier,
 };
 
 static void vfp_pm_init(void)
 {
-        register_syscore_ops(&vfp_pm_syscore_ops);
+        cpu_pm_register_notifier(&vfp_cpu_pm_notifier_block);
 }
 
 #else
 static inline void vfp_pm_init(void) { }
-#endif /* CONFIG_PM */
+#endif /* CONFIG_CPU_PM */
 
 /*
  * Ensure that the VFP state stored in 'thread->vfpstate' is up to date